1/*
2 * Toshiba RBTX4939 setup routines.
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 *	    and RBTX49xx patch from CELF patch archive.
5 *
6 * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/slab.h>
16#include <linux/export.h>
17#include <linux/platform_device.h>
18#include <linux/leds.h>
19#include <linux/interrupt.h>
20#include <linux/smc91x.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/partitions.h>
23#include <linux/mtd/map.h>
24#include <asm/reboot.h>
25#include <asm/txx9/generic.h>
26#include <asm/txx9/pci.h>
27#include <asm/txx9/rbtx4939.h>
28
29static void rbtx4939_machine_restart(char *command)
30{
31	local_irq_disable();
32	writeb(1, rbtx4939_reseten_addr);
33	writeb(1, rbtx4939_softreset_addr);
34	while (1)
35		;
36}
37
38static void __init rbtx4939_time_init(void)
39{
40	tx4939_time_init(0);
41}
42
43#if defined(__BIG_ENDIAN) && IS_ENABLED(CONFIG_SMC91X)
44#define HAVE_RBTX4939_IOSWAB
45#define IS_CE1_ADDR(addr) \
46	((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
47static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x)
48{
49	return IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
50}
51static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x)
52{
53	return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
54}
55#endif /* __BIG_ENDIAN && CONFIG_SMC91X */
56
57static void __init rbtx4939_pci_setup(void)
58{
59#ifdef CONFIG_PCI
60	int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
61	struct pci_controller *c = &txx9_primary_pcic;
62
63	register_pci_controller(c);
64
65	tx4939_report_pciclk();
66	tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
67	if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
68	    (__raw_readq(&tx4939_ccfgptr->pcfg) &
69	     (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
70		tx4939_report_pci1clk();
71
72		/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
73		c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
74		register_pci_controller(c);
75		tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
76	}
77
78	tx4939_setup_pcierr_irq();
79#endif /* CONFIG_PCI */
80}
81
82static unsigned long long default_ebccr[] __initdata = {
83	0x01c0000000007608ULL, /* 64M ROM */
84	0x017f000000007049ULL, /* 1M IOC */
85	0x0180000000408608ULL, /* ISA */
86	0,
87};
88
89static void __init rbtx4939_ebusc_setup(void)
90{
91	int i;
92	unsigned int sp;
93
94	/* use user-configured speed */
95	sp = TX4939_EBUSC_CR(0) & 0x30;
96	default_ebccr[0] |= sp;
97	default_ebccr[1] |= sp;
98	default_ebccr[2] |= sp;
99	/* initialise by myself */
100	for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
101		if (default_ebccr[i])
102			____raw_writeq(default_ebccr[i],
103				       &tx4939_ebuscptr->cr[i]);
104		else
105			____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
106				       & ~8,
107				       &tx4939_ebuscptr->cr[i]);
108	}
109}
110
111static void __init rbtx4939_update_ioc_pen(void)
112{
113	__u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
114	__u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
115	__u8 pe1 = readb(rbtx4939_pe1_addr);
116	__u8 pe2 = readb(rbtx4939_pe2_addr);
117	__u8 pe3 = readb(rbtx4939_pe3_addr);
118	if (pcfg & TX4939_PCFG_ATA0MODE)
119		pe1 |= RBTX4939_PE1_ATA(0);
120	else
121		pe1 &= ~RBTX4939_PE1_ATA(0);
122	if (pcfg & TX4939_PCFG_ATA1MODE) {
123		pe1 |= RBTX4939_PE1_ATA(1);
124		pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
125	} else {
126		pe1 &= ~RBTX4939_PE1_ATA(1);
127		if (pcfg & TX4939_PCFG_ET0MODE)
128			pe1 |= RBTX4939_PE1_RMII(0);
129		else
130			pe1 &= ~RBTX4939_PE1_RMII(0);
131		if (pcfg & TX4939_PCFG_ET1MODE)
132			pe1 |= RBTX4939_PE1_RMII(1);
133		else
134			pe1 &= ~RBTX4939_PE1_RMII(1);
135	}
136	if (ccfg & TX4939_CCFG_PTSEL)
137		pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
138			 RBTX4939_PE3_VP_S);
139	else {
140		__u64 vmode = pcfg &
141			(TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
142		if (vmode == 0)
143			pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
144				 RBTX4939_PE3_VP_S);
145		else if (vmode == TX4939_PCFG_VPSMODE) {
146			pe3 |= RBTX4939_PE3_VP_P;
147			pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
148		} else if (vmode == TX4939_PCFG_VSSMODE) {
149			pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
150			pe3 &= ~RBTX4939_PE3_VP_P;
151		} else {
152			pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
153			pe3 &= ~RBTX4939_PE3_VP_S;
154		}
155	}
156	if (pcfg & TX4939_PCFG_SPIMODE) {
157		if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
158			pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
159		else {
160			if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
161				pe2 |= RBTX4939_PE2_SIO2;
162				pe2 &= ~RBTX4939_PE2_SIO0;
163			} else {
164				pe2 |= RBTX4939_PE2_SIO0;
165				pe2 &= ~RBTX4939_PE2_SIO2;
166			}
167		}
168		if (pcfg & TX4939_PCFG_SIO3MODE)
169			pe2 |= RBTX4939_PE2_SIO3;
170		else
171			pe2 &= ~RBTX4939_PE2_SIO3;
172		pe2 &= ~RBTX4939_PE2_SPI;
173	} else {
174		pe2 |= RBTX4939_PE2_SPI;
175		pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
176			 RBTX4939_PE2_SIO0);
177	}
178	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
179		pe2 |= RBTX4939_PE2_GPIO;
180	else
181		pe2 &= ~RBTX4939_PE2_GPIO;
182	writeb(pe1, rbtx4939_pe1_addr);
183	writeb(pe2, rbtx4939_pe2_addr);
184	writeb(pe3, rbtx4939_pe3_addr);
185}
186
187#define RBTX4939_MAX_7SEGLEDS	8
188
189#if IS_ENABLED(CONFIG_LEDS_CLASS)
190static u8 led_val[RBTX4939_MAX_7SEGLEDS];
191struct rbtx4939_led_data {
192	struct led_classdev cdev;
193	char name[32];
194	unsigned int num;
195};
196
197/* Use "dot" in 7seg LEDs */
198static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
199					enum led_brightness value)
200{
201	struct rbtx4939_led_data *led_dat =
202		container_of(led_cdev, struct rbtx4939_led_data, cdev);
203	unsigned int num = led_dat->num;
204	unsigned long flags;
205
206	local_irq_save(flags);
207	led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
208	writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
209	local_irq_restore(flags);
210}
211
212static int __init rbtx4939_led_probe(struct platform_device *pdev)
213{
214	struct rbtx4939_led_data *leds_data;
215	int i;
216	static char *default_triggers[] __initdata = {
217		"heartbeat",
218		"ide-disk",
219		"nand-disk",
220	};
221
222	leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS,
223			    GFP_KERNEL);
224	if (!leds_data)
225		return -ENOMEM;
226	for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
227		int rc;
228		struct rbtx4939_led_data *led_dat = &leds_data[i];
229
230		led_dat->num = i;
231		led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
232		sprintf(led_dat->name, "rbtx4939:amber:%u", i);
233		led_dat->cdev.name = led_dat->name;
234		if (i < ARRAY_SIZE(default_triggers))
235			led_dat->cdev.default_trigger = default_triggers[i];
236		rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
237		if (rc < 0)
238			return rc;
239		led_dat->cdev.brightness_set(&led_dat->cdev, 0);
240	}
241	return 0;
242
243}
244
245static struct platform_driver rbtx4939_led_driver = {
246	.driver	 = {
247		.name = "rbtx4939-led",
248		.owner = THIS_MODULE,
249	},
250};
251
252static void __init rbtx4939_led_setup(void)
253{
254	platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
255	platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
256}
257#else
258static inline void rbtx4939_led_setup(void)
259{
260}
261#endif
262
263static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
264{
265#if IS_ENABLED(CONFIG_LEDS_CLASS)
266	unsigned long flags;
267	local_irq_save(flags);
268	/* bit7: reserved for LED class */
269	led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f);
270	val = led_val[pos];
271	local_irq_restore(flags);
272#endif
273	writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4));
274}
275
276static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
277{
278	/* convert from map_to_seg7() notation */
279	val = (val & 0x88) |
280		((val & 0x40) >> 6) |
281		((val & 0x20) >> 4) |
282		((val & 0x10) >> 2) |
283		((val & 0x04) << 2) |
284		((val & 0x02) << 4) |
285		((val & 0x01) << 6);
286	__rbtx4939_7segled_putc(pos, val);
287}
288
289#if IS_ENABLED(CONFIG_MTD_RBTX4939)
290/* special mapping for boot rom */
291static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs)
292{
293	u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
294	unsigned char shift;
295
296	if (bdipsw & 8) {
297		/* BOOT Mode: USER ROM1 / USER ROM2 */
298		shift = bdipsw & 3;
299		/* rotate A[23:22] */
300		return (ofs & ~0xc00000) | ((((ofs >> 22) + shift) & 3) << 22);
301	}
302#ifdef __BIG_ENDIAN
303	if (bdipsw == 0)
304		/* BOOT Mode: Monitor ROM */
305		ofs ^= 0x400000;	/* swap A[22] */
306#endif
307	return ofs;
308}
309
310static map_word rbtx4939_flash_read16(struct map_info *map, unsigned long ofs)
311{
312	map_word r;
313
314	ofs = rbtx4939_flash_fixup_ofs(ofs);
315	r.x[0] = __raw_readw(map->virt + ofs);
316	return r;
317}
318
319static void rbtx4939_flash_write16(struct map_info *map, const map_word datum,
320				   unsigned long ofs)
321{
322	ofs = rbtx4939_flash_fixup_ofs(ofs);
323	__raw_writew(datum.x[0], map->virt + ofs);
324	mb();	/* see inline_map_write() in mtd/map.h */
325}
326
327static void rbtx4939_flash_copy_from(struct map_info *map, void *to,
328				     unsigned long from, ssize_t len)
329{
330	u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
331	unsigned char shift;
332	ssize_t curlen;
333
334	from += (unsigned long)map->virt;
335	if (bdipsw & 8) {
336		/* BOOT Mode: USER ROM1 / USER ROM2 */
337		shift = bdipsw & 3;
338		while (len) {
339			curlen = min_t(unsigned long, len,
340				     0x400000 - (from & (0x400000 - 1)));
341			memcpy(to,
342			       (void *)((from & ~0xc00000) |
343					((((from >> 22) + shift) & 3) << 22)),
344			       curlen);
345			len -= curlen;
346			from += curlen;
347			to += curlen;
348		}
349		return;
350	}
351#ifdef __BIG_ENDIAN
352	if (bdipsw == 0) {
353		/* BOOT Mode: Monitor ROM */
354		while (len) {
355			curlen = min_t(unsigned long, len,
356				     0x400000 - (from & (0x400000 - 1)));
357			memcpy(to, (void *)(from ^ 0x400000), curlen);
358			len -= curlen;
359			from += curlen;
360			to += curlen;
361		}
362		return;
363	}
364#endif
365	memcpy(to, (void *)from, len);
366}
367
368static void rbtx4939_flash_map_init(struct map_info *map)
369{
370	map->read = rbtx4939_flash_read16;
371	map->write = rbtx4939_flash_write16;
372	map->copy_from = rbtx4939_flash_copy_from;
373}
374
375static void __init rbtx4939_mtd_init(void)
376{
377	static struct {
378		struct platform_device dev;
379		struct resource res;
380		struct rbtx4939_flash_data data;
381	} pdevs[4];
382	int i;
383	static char names[4][8];
384	static struct mtd_partition parts[4];
385	struct rbtx4939_flash_data *boot_pdata = &pdevs[0].data;
386	u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
387
388	if (bdipsw & 8) {
389		/* BOOT Mode: USER ROM1 / USER ROM2 */
390		boot_pdata->nr_parts = 4;
391		for (i = 0; i < boot_pdata->nr_parts; i++) {
392			sprintf(names[i], "img%d", 4 - i);
393			parts[i].name = names[i];
394			parts[i].size = 0x400000;
395			parts[i].offset = MTDPART_OFS_NXTBLK;
396		}
397	} else if (bdipsw == 0) {
398		/* BOOT Mode: Monitor ROM */
399		boot_pdata->nr_parts = 2;
400		strcpy(names[0], "big");
401		strcpy(names[1], "little");
402		for (i = 0; i < boot_pdata->nr_parts; i++) {
403			parts[i].name = names[i];
404			parts[i].size = 0x400000;
405			parts[i].offset = MTDPART_OFS_NXTBLK;
406		}
407	} else {
408		/* BOOT Mode: ROM Emulator */
409		boot_pdata->nr_parts = 2;
410		parts[0].name = "boot";
411		parts[0].offset = 0xc00000;
412		parts[0].size = 0x400000;
413		parts[1].name = "user";
414		parts[1].offset = 0;
415		parts[1].size = 0xc00000;
416	}
417	boot_pdata->parts = parts;
418	boot_pdata->map_init = rbtx4939_flash_map_init;
419
420	for (i = 0; i < ARRAY_SIZE(pdevs); i++) {
421		struct resource *r = &pdevs[i].res;
422		struct platform_device *dev = &pdevs[i].dev;
423
424		r->start = 0x1f000000 - i * 0x1000000;
425		r->end = r->start + 0x1000000 - 1;
426		r->flags = IORESOURCE_MEM;
427		pdevs[i].data.width = 2;
428		dev->num_resources = 1;
429		dev->resource = r;
430		dev->id = i;
431		dev->name = "rbtx4939-flash";
432		dev->dev.platform_data = &pdevs[i].data;
433		platform_device_register(dev);
434	}
435}
436#else
437static void __init rbtx4939_mtd_init(void)
438{
439}
440#endif
441
442static void __init rbtx4939_arch_init(void)
443{
444	rbtx4939_pci_setup();
445}
446
447static void __init rbtx4939_device_init(void)
448{
449	unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
450	struct resource smc_res[] = {
451		{
452			.start	= smc_addr,
453			.end	= smc_addr + 0x10 - 1,
454			.flags	= IORESOURCE_MEM,
455		}, {
456			.start	= RBTX4939_IRQ_ETHER,
457			/* override default irq flag defined in smc91x.h */
458			.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
459		},
460	};
461	struct smc91x_platdata smc_pdata = {
462		.flags = SMC91X_USE_16BIT,
463	};
464	struct platform_device *pdev;
465#if IS_ENABLED(CONFIG_TC35815)
466	int i, j;
467	unsigned char ethaddr[2][6];
468	u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
469
470	for (i = 0; i < 2; i++) {
471		unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
472		if (bdipsw == 0)
473			memcpy(ethaddr[i], (void *)area, 6);
474		else {
475			u16 buf[3];
476			if (bdipsw & 8)
477				area -= 0x03000000;
478			else
479				area -= 0x01000000;
480			for (j = 0; j < 3; j++)
481				buf[j] = le16_to_cpup((u16 *)(area + j * 2));
482			memcpy(ethaddr[i], buf, 6);
483		}
484	}
485	tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
486#endif
487	pdev = platform_device_alloc("smc91x", -1);
488	if (!pdev ||
489	    platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) ||
490	    platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) ||
491	    platform_device_add(pdev))
492		platform_device_put(pdev);
493	rbtx4939_mtd_init();
494	/* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
495	tx4939_ndfmc_init(10, 35,
496			  (1 << 1) | (1 << 2),
497			  (1 << 2)); /* ch1:8bit, ch2:16bit */
498	rbtx4939_led_setup();
499	tx4939_wdt_init();
500	tx4939_ata_init();
501	tx4939_rtc_init();
502	tx4939_dmac_init(0, 2);
503	tx4939_aclc_init();
504	platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
505	tx4939_sramc_init();
506	tx4939_rng_init();
507}
508
509static void __init rbtx4939_setup(void)
510{
511	int i;
512
513	rbtx4939_ebusc_setup();
514	/* always enable ATA0 */
515	txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
516	if (txx9_master_clock == 0)
517		txx9_master_clock = 20000000;
518	tx4939_setup();
519	rbtx4939_update_ioc_pen();
520#ifdef HAVE_RBTX4939_IOSWAB
521	ioswabw = rbtx4939_ioswabw;
522	__mem_ioswabw = rbtx4939_mem_ioswabw;
523#endif
524
525	_machine_restart = rbtx4939_machine_restart;
526
527	txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc);
528	for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++)
529		txx9_7segled_putc(i, '-');
530	pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
531		readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
532		readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
533
534#ifdef CONFIG_PCI
535	txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
536	txx9_board_pcibios_setup = tx4927_pcibios_setup;
537#else
538	set_io_port_base(RBTX4939_ETHER_BASE);
539#endif
540
541	tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
542}
543
544struct txx9_board_vec rbtx4939_vec __initdata = {
545	.system = "Toshiba RBTX4939",
546	.prom_init = rbtx4939_prom_init,
547	.mem_setup = rbtx4939_setup,
548	.irq_setup = rbtx4939_irq_setup,
549	.time_init = rbtx4939_time_init,
550	.device_init = rbtx4939_device_init,
551	.arch_init = rbtx4939_arch_init,
552#ifdef CONFIG_PCI
553	.pci_map_irq = tx4939_pci_map_irq,
554#endif
555};
556