1/* 2 * Port for PPC64 David Engebretsen, IBM Corp. 3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 4 * 5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 6 * Rework, based on alpha PCI code. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14#undef DEBUG 15 16#include <linux/kernel.h> 17#include <linux/pci.h> 18#include <linux/string.h> 19#include <linux/init.h> 20#include <linux/bootmem.h> 21#include <linux/export.h> 22#include <linux/mm.h> 23#include <linux/list.h> 24#include <linux/syscalls.h> 25#include <linux/irq.h> 26#include <linux/vmalloc.h> 27 28#include <asm/processor.h> 29#include <asm/io.h> 30#include <asm/prom.h> 31#include <asm/pci-bridge.h> 32#include <asm/byteorder.h> 33#include <asm/machdep.h> 34#include <asm/ppc-pci.h> 35 36/* pci_io_base -- the base address from which io bars are offsets. 37 * This is the lowest I/O base address (so bar values are always positive), 38 * and it *must* be the start of ISA space if an ISA bus exists because 39 * ISA drivers use hard coded offsets. If no ISA bus exists nothing 40 * is mapped on the first 64K of IO space 41 */ 42unsigned long pci_io_base = ISA_IO_BASE; 43EXPORT_SYMBOL(pci_io_base); 44 45static int __init pcibios_init(void) 46{ 47 struct pci_controller *hose, *tmp; 48 49 printk(KERN_INFO "PCI: Probing PCI hardware\n"); 50 51 /* For now, override phys_mem_access_prot. If we need it,g 52 * later, we may move that initialization to each ppc_md 53 */ 54 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 55 56 /* On ppc64, we always enable PCI domains and we keep domain 0 57 * backward compatible in /proc for video cards 58 */ 59 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); 60 61 /* Scan all of the recorded PCI controllers. */ 62 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 63 pcibios_scan_phb(hose); 64 pci_bus_add_devices(hose->bus); 65 } 66 67 /* Call common code to handle resource allocation */ 68 pcibios_resource_survey(); 69 70 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); 71 72 return 0; 73} 74 75subsys_initcall(pcibios_init); 76 77int pcibios_unmap_io_space(struct pci_bus *bus) 78{ 79 struct pci_controller *hose; 80 81 WARN_ON(bus == NULL); 82 83 /* If this is not a PHB, we only flush the hash table over 84 * the area mapped by this bridge. We don't play with the PTE 85 * mappings since we might have to deal with sub-page alignemnts 86 * so flushing the hash table is the only sane way to make sure 87 * that no hash entries are covering that removed bridge area 88 * while still allowing other busses overlapping those pages 89 * 90 * Note: If we ever support P2P hotplug on Book3E, we'll have 91 * to do an appropriate TLB flush here too 92 */ 93 if (bus->self) { 94#ifdef CONFIG_PPC_STD_MMU_64 95 struct resource *res = bus->resource[0]; 96#endif 97 98 pr_debug("IO unmapping for PCI-PCI bridge %s\n", 99 pci_name(bus->self)); 100 101#ifdef CONFIG_PPC_STD_MMU_64 102 __flush_hash_table_range(&init_mm, res->start + _IO_BASE, 103 res->end + _IO_BASE + 1); 104#endif 105 return 0; 106 } 107 108 /* Get the host bridge */ 109 hose = pci_bus_to_host(bus); 110 111 /* Check if we have IOs allocated */ 112 if (hose->io_base_alloc == NULL) 113 return 0; 114 115 pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name); 116 pr_debug(" alloc=0x%p\n", hose->io_base_alloc); 117 118 /* This is a PHB, we fully unmap the IO area */ 119 vunmap(hose->io_base_alloc); 120 121 return 0; 122} 123EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); 124 125static int pcibios_map_phb_io_space(struct pci_controller *hose) 126{ 127 struct vm_struct *area; 128 unsigned long phys_page; 129 unsigned long size_page; 130 unsigned long io_virt_offset; 131 132 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); 133 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); 134 135 /* Make sure IO area address is clear */ 136 hose->io_base_alloc = NULL; 137 138 /* If there's no IO to map on that bus, get away too */ 139 if (hose->pci_io_size == 0 || hose->io_base_phys == 0) 140 return 0; 141 142 /* Let's allocate some IO space for that guy. We don't pass 143 * VM_IOREMAP because we don't care about alignment tricks that 144 * the core does in that case. Maybe we should due to stupid card 145 * with incomplete address decoding but I'd rather not deal with 146 * those outside of the reserved 64K legacy region. 147 */ 148 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END); 149 if (area == NULL) 150 return -ENOMEM; 151 hose->io_base_alloc = area->addr; 152 hose->io_base_virt = (void __iomem *)(area->addr + 153 hose->io_base_phys - phys_page); 154 155 pr_debug("IO mapping for PHB %s\n", hose->dn->full_name); 156 pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", 157 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); 158 pr_debug(" size=0x%016llx (alloc=0x%016lx)\n", 159 hose->pci_io_size, size_page); 160 161 /* Establish the mapping */ 162 if (__ioremap_at(phys_page, area->addr, size_page, 163 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL) 164 return -ENOMEM; 165 166 /* Fixup hose IO resource */ 167 io_virt_offset = pcibios_io_space_offset(hose); 168 hose->io_resource.start += io_virt_offset; 169 hose->io_resource.end += io_virt_offset; 170 171 pr_debug(" hose->io_resource=%pR\n", &hose->io_resource); 172 173 return 0; 174} 175 176int pcibios_map_io_space(struct pci_bus *bus) 177{ 178 WARN_ON(bus == NULL); 179 180 /* If this not a PHB, nothing to do, page tables still exist and 181 * thus HPTEs will be faulted in when needed 182 */ 183 if (bus->self) { 184 pr_debug("IO mapping for PCI-PCI bridge %s\n", 185 pci_name(bus->self)); 186 pr_debug(" virt=0x%016llx...0x%016llx\n", 187 bus->resource[0]->start + _IO_BASE, 188 bus->resource[0]->end + _IO_BASE); 189 return 0; 190 } 191 192 return pcibios_map_phb_io_space(pci_bus_to_host(bus)); 193} 194EXPORT_SYMBOL_GPL(pcibios_map_io_space); 195 196void pcibios_setup_phb_io_space(struct pci_controller *hose) 197{ 198 pcibios_map_phb_io_space(hose); 199} 200 201#define IOBASE_BRIDGE_NUMBER 0 202#define IOBASE_MEMORY 1 203#define IOBASE_IO 2 204#define IOBASE_ISA_IO 3 205#define IOBASE_ISA_MEM 4 206 207long sys_pciconfig_iobase(long which, unsigned long in_bus, 208 unsigned long in_devfn) 209{ 210 struct pci_controller* hose; 211 struct pci_bus *tmp_bus, *bus = NULL; 212 struct device_node *hose_node; 213 214 /* Argh ! Please forgive me for that hack, but that's the 215 * simplest way to get existing XFree to not lockup on some 216 * G5 machines... So when something asks for bus 0 io base 217 * (bus 0 is HT root), we return the AGP one instead. 218 */ 219 if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) { 220 struct device_node *agp; 221 222 agp = of_find_compatible_node(NULL, NULL, "u3-agp"); 223 if (agp) 224 in_bus = 0xf0; 225 of_node_put(agp); 226 } 227 228 /* That syscall isn't quite compatible with PCI domains, but it's 229 * used on pre-domains setup. We return the first match 230 */ 231 232 list_for_each_entry(tmp_bus, &pci_root_buses, node) { 233 if (in_bus >= tmp_bus->number && 234 in_bus <= tmp_bus->busn_res.end) { 235 bus = tmp_bus; 236 break; 237 } 238 } 239 if (bus == NULL || bus->dev.of_node == NULL) 240 return -ENODEV; 241 242 hose_node = bus->dev.of_node; 243 hose = PCI_DN(hose_node)->phb; 244 245 switch (which) { 246 case IOBASE_BRIDGE_NUMBER: 247 return (long)hose->first_busno; 248 case IOBASE_MEMORY: 249 return (long)hose->mem_offset[0]; 250 case IOBASE_IO: 251 return (long)hose->io_base_phys; 252 case IOBASE_ISA_IO: 253 return (long)isa_io_base; 254 case IOBASE_ISA_MEM: 255 return -EINVAL; 256 } 257 258 return -EOPNOTSUPP; 259} 260 261#ifdef CONFIG_NUMA 262int pcibus_to_node(struct pci_bus *bus) 263{ 264 struct pci_controller *phb = pci_bus_to_host(bus); 265 return phb->node; 266} 267EXPORT_SYMBOL(pcibus_to_node); 268#endif 269