1/* 2 * S390 version 3 * Copyright IBM Corp. 1999, 2000 4 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) 5 */ 6 7#ifndef _UAPI_S390_PTRACE_H 8#define _UAPI_S390_PTRACE_H 9 10/* 11 * Offsets in the user_regs_struct. They are used for the ptrace 12 * system call and in entry.S 13 */ 14#ifndef __s390x__ 15 16#define PT_PSWMASK 0x00 17#define PT_PSWADDR 0x04 18#define PT_GPR0 0x08 19#define PT_GPR1 0x0C 20#define PT_GPR2 0x10 21#define PT_GPR3 0x14 22#define PT_GPR4 0x18 23#define PT_GPR5 0x1C 24#define PT_GPR6 0x20 25#define PT_GPR7 0x24 26#define PT_GPR8 0x28 27#define PT_GPR9 0x2C 28#define PT_GPR10 0x30 29#define PT_GPR11 0x34 30#define PT_GPR12 0x38 31#define PT_GPR13 0x3C 32#define PT_GPR14 0x40 33#define PT_GPR15 0x44 34#define PT_ACR0 0x48 35#define PT_ACR1 0x4C 36#define PT_ACR2 0x50 37#define PT_ACR3 0x54 38#define PT_ACR4 0x58 39#define PT_ACR5 0x5C 40#define PT_ACR6 0x60 41#define PT_ACR7 0x64 42#define PT_ACR8 0x68 43#define PT_ACR9 0x6C 44#define PT_ACR10 0x70 45#define PT_ACR11 0x74 46#define PT_ACR12 0x78 47#define PT_ACR13 0x7C 48#define PT_ACR14 0x80 49#define PT_ACR15 0x84 50#define PT_ORIGGPR2 0x88 51#define PT_FPC 0x90 52/* 53 * A nasty fact of life that the ptrace api 54 * only supports passing of longs. 55 */ 56#define PT_FPR0_HI 0x98 57#define PT_FPR0_LO 0x9C 58#define PT_FPR1_HI 0xA0 59#define PT_FPR1_LO 0xA4 60#define PT_FPR2_HI 0xA8 61#define PT_FPR2_LO 0xAC 62#define PT_FPR3_HI 0xB0 63#define PT_FPR3_LO 0xB4 64#define PT_FPR4_HI 0xB8 65#define PT_FPR4_LO 0xBC 66#define PT_FPR5_HI 0xC0 67#define PT_FPR5_LO 0xC4 68#define PT_FPR6_HI 0xC8 69#define PT_FPR6_LO 0xCC 70#define PT_FPR7_HI 0xD0 71#define PT_FPR7_LO 0xD4 72#define PT_FPR8_HI 0xD8 73#define PT_FPR8_LO 0XDC 74#define PT_FPR9_HI 0xE0 75#define PT_FPR9_LO 0xE4 76#define PT_FPR10_HI 0xE8 77#define PT_FPR10_LO 0xEC 78#define PT_FPR11_HI 0xF0 79#define PT_FPR11_LO 0xF4 80#define PT_FPR12_HI 0xF8 81#define PT_FPR12_LO 0xFC 82#define PT_FPR13_HI 0x100 83#define PT_FPR13_LO 0x104 84#define PT_FPR14_HI 0x108 85#define PT_FPR14_LO 0x10C 86#define PT_FPR15_HI 0x110 87#define PT_FPR15_LO 0x114 88#define PT_CR_9 0x118 89#define PT_CR_10 0x11C 90#define PT_CR_11 0x120 91#define PT_IEEE_IP 0x13C 92#define PT_LASTOFF PT_IEEE_IP 93#define PT_ENDREGS 0x140-1 94 95#define GPR_SIZE 4 96#define CR_SIZE 4 97 98#define STACK_FRAME_OVERHEAD 96 /* size of minimum stack frame */ 99 100#else /* __s390x__ */ 101 102#define PT_PSWMASK 0x00 103#define PT_PSWADDR 0x08 104#define PT_GPR0 0x10 105#define PT_GPR1 0x18 106#define PT_GPR2 0x20 107#define PT_GPR3 0x28 108#define PT_GPR4 0x30 109#define PT_GPR5 0x38 110#define PT_GPR6 0x40 111#define PT_GPR7 0x48 112#define PT_GPR8 0x50 113#define PT_GPR9 0x58 114#define PT_GPR10 0x60 115#define PT_GPR11 0x68 116#define PT_GPR12 0x70 117#define PT_GPR13 0x78 118#define PT_GPR14 0x80 119#define PT_GPR15 0x88 120#define PT_ACR0 0x90 121#define PT_ACR1 0x94 122#define PT_ACR2 0x98 123#define PT_ACR3 0x9C 124#define PT_ACR4 0xA0 125#define PT_ACR5 0xA4 126#define PT_ACR6 0xA8 127#define PT_ACR7 0xAC 128#define PT_ACR8 0xB0 129#define PT_ACR9 0xB4 130#define PT_ACR10 0xB8 131#define PT_ACR11 0xBC 132#define PT_ACR12 0xC0 133#define PT_ACR13 0xC4 134#define PT_ACR14 0xC8 135#define PT_ACR15 0xCC 136#define PT_ORIGGPR2 0xD0 137#define PT_FPC 0xD8 138#define PT_FPR0 0xE0 139#define PT_FPR1 0xE8 140#define PT_FPR2 0xF0 141#define PT_FPR3 0xF8 142#define PT_FPR4 0x100 143#define PT_FPR5 0x108 144#define PT_FPR6 0x110 145#define PT_FPR7 0x118 146#define PT_FPR8 0x120 147#define PT_FPR9 0x128 148#define PT_FPR10 0x130 149#define PT_FPR11 0x138 150#define PT_FPR12 0x140 151#define PT_FPR13 0x148 152#define PT_FPR14 0x150 153#define PT_FPR15 0x158 154#define PT_CR_9 0x160 155#define PT_CR_10 0x168 156#define PT_CR_11 0x170 157#define PT_IEEE_IP 0x1A8 158#define PT_LASTOFF PT_IEEE_IP 159#define PT_ENDREGS 0x1B0-1 160 161#define GPR_SIZE 8 162#define CR_SIZE 8 163 164#define STACK_FRAME_OVERHEAD 160 /* size of minimum stack frame */ 165 166#endif /* __s390x__ */ 167 168#define NUM_GPRS 16 169#define NUM_FPRS 16 170#define NUM_CRS 16 171#define NUM_ACRS 16 172 173#define NUM_CR_WORDS 3 174 175#define FPR_SIZE 8 176#define FPC_SIZE 4 177#define FPC_PAD_SIZE 4 /* gcc insists on aligning the fpregs */ 178#define ACR_SIZE 4 179 180 181#define PTRACE_OLDSETOPTIONS 21 182 183#ifndef __ASSEMBLY__ 184#include <linux/stddef.h> 185#include <linux/types.h> 186 187typedef union 188{ 189 float f; 190 double d; 191 __u64 ui; 192 struct 193 { 194 __u32 hi; 195 __u32 lo; 196 } fp; 197} freg_t; 198 199typedef struct 200{ 201 __u32 fpc; 202 __u32 pad; 203 freg_t fprs[NUM_FPRS]; 204} s390_fp_regs; 205 206#define FPC_EXCEPTION_MASK 0xF8000000 207#define FPC_FLAGS_MASK 0x00F80000 208#define FPC_DXC_MASK 0x0000FF00 209#define FPC_RM_MASK 0x00000003 210 211/* this typedef defines how a Program Status Word looks like */ 212typedef struct 213{ 214 unsigned long mask; 215 unsigned long addr; 216} __attribute__ ((aligned(8))) psw_t; 217 218#ifndef __s390x__ 219 220#define PSW_MASK_PER 0x40000000UL 221#define PSW_MASK_DAT 0x04000000UL 222#define PSW_MASK_IO 0x02000000UL 223#define PSW_MASK_EXT 0x01000000UL 224#define PSW_MASK_KEY 0x00F00000UL 225#define PSW_MASK_BASE 0x00080000UL /* always one */ 226#define PSW_MASK_MCHECK 0x00040000UL 227#define PSW_MASK_WAIT 0x00020000UL 228#define PSW_MASK_PSTATE 0x00010000UL 229#define PSW_MASK_ASC 0x0000C000UL 230#define PSW_MASK_CC 0x00003000UL 231#define PSW_MASK_PM 0x00000F00UL 232#define PSW_MASK_RI 0x00000000UL 233#define PSW_MASK_EA 0x00000000UL 234#define PSW_MASK_BA 0x00000000UL 235 236#define PSW_MASK_USER 0x0000FF00UL 237 238#define PSW_ADDR_AMODE 0x80000000UL 239#define PSW_ADDR_INSN 0x7FFFFFFFUL 240 241#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 20) 242 243#define PSW_ASC_PRIMARY 0x00000000UL 244#define PSW_ASC_ACCREG 0x00004000UL 245#define PSW_ASC_SECONDARY 0x00008000UL 246#define PSW_ASC_HOME 0x0000C000UL 247 248#else /* __s390x__ */ 249 250#define PSW_MASK_PER 0x4000000000000000UL 251#define PSW_MASK_DAT 0x0400000000000000UL 252#define PSW_MASK_IO 0x0200000000000000UL 253#define PSW_MASK_EXT 0x0100000000000000UL 254#define PSW_MASK_BASE 0x0000000000000000UL 255#define PSW_MASK_KEY 0x00F0000000000000UL 256#define PSW_MASK_MCHECK 0x0004000000000000UL 257#define PSW_MASK_WAIT 0x0002000000000000UL 258#define PSW_MASK_PSTATE 0x0001000000000000UL 259#define PSW_MASK_ASC 0x0000C00000000000UL 260#define PSW_MASK_CC 0x0000300000000000UL 261#define PSW_MASK_PM 0x00000F0000000000UL 262#define PSW_MASK_RI 0x0000008000000000UL 263#define PSW_MASK_EA 0x0000000100000000UL 264#define PSW_MASK_BA 0x0000000080000000UL 265 266#define PSW_MASK_USER 0x0000FF0180000000UL 267 268#define PSW_ADDR_AMODE 0x0000000000000000UL 269#define PSW_ADDR_INSN 0xFFFFFFFFFFFFFFFFUL 270 271#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 52) 272 273#define PSW_ASC_PRIMARY 0x0000000000000000UL 274#define PSW_ASC_ACCREG 0x0000400000000000UL 275#define PSW_ASC_SECONDARY 0x0000800000000000UL 276#define PSW_ASC_HOME 0x0000C00000000000UL 277 278#endif /* __s390x__ */ 279 280 281/* 282 * The s390_regs structure is used to define the elf_gregset_t. 283 */ 284typedef struct 285{ 286 psw_t psw; 287 unsigned long gprs[NUM_GPRS]; 288 unsigned int acrs[NUM_ACRS]; 289 unsigned long orig_gpr2; 290} s390_regs; 291 292/* 293 * Now for the user space program event recording (trace) definitions. 294 * The following structures are used only for the ptrace interface, don't 295 * touch or even look at it if you don't want to modify the user-space 296 * ptrace interface. In particular stay away from it for in-kernel PER. 297 */ 298typedef struct 299{ 300 unsigned long cr[NUM_CR_WORDS]; 301} per_cr_words; 302 303#define PER_EM_MASK 0xE8000000UL 304 305typedef struct 306{ 307#ifdef __s390x__ 308 unsigned : 32; 309#endif /* __s390x__ */ 310 unsigned em_branching : 1; 311 unsigned em_instruction_fetch : 1; 312 /* 313 * Switching on storage alteration automatically fixes 314 * the storage alteration event bit in the users std. 315 */ 316 unsigned em_storage_alteration : 1; 317 unsigned em_gpr_alt_unused : 1; 318 unsigned em_store_real_address : 1; 319 unsigned : 3; 320 unsigned branch_addr_ctl : 1; 321 unsigned : 1; 322 unsigned storage_alt_space_ctl : 1; 323 unsigned : 21; 324 unsigned long starting_addr; 325 unsigned long ending_addr; 326} per_cr_bits; 327 328typedef struct 329{ 330 unsigned short perc_atmid; 331 unsigned long address; 332 unsigned char access_id; 333} per_lowcore_words; 334 335typedef struct 336{ 337 unsigned perc_branching : 1; 338 unsigned perc_instruction_fetch : 1; 339 unsigned perc_storage_alteration : 1; 340 unsigned perc_gpr_alt_unused : 1; 341 unsigned perc_store_real_address : 1; 342 unsigned : 3; 343 unsigned atmid_psw_bit_31 : 1; 344 unsigned atmid_validity_bit : 1; 345 unsigned atmid_psw_bit_32 : 1; 346 unsigned atmid_psw_bit_5 : 1; 347 unsigned atmid_psw_bit_16 : 1; 348 unsigned atmid_psw_bit_17 : 1; 349 unsigned si : 2; 350 unsigned long address; 351 unsigned : 4; 352 unsigned access_id : 4; 353} per_lowcore_bits; 354 355typedef struct 356{ 357 union { 358 per_cr_words words; 359 per_cr_bits bits; 360 } control_regs; 361 /* 362 * Use these flags instead of setting em_instruction_fetch 363 * directly they are used so that single stepping can be 364 * switched on & off while not affecting other tracing 365 */ 366 unsigned single_step : 1; 367 unsigned instruction_fetch : 1; 368 unsigned : 30; 369 /* 370 * These addresses are copied into cr10 & cr11 if single 371 * stepping is switched off 372 */ 373 unsigned long starting_addr; 374 unsigned long ending_addr; 375 union { 376 per_lowcore_words words; 377 per_lowcore_bits bits; 378 } lowcore; 379} per_struct; 380 381typedef struct 382{ 383 unsigned int len; 384 unsigned long kernel_addr; 385 unsigned long process_addr; 386} ptrace_area; 387 388/* 389 * S/390 specific non posix ptrace requests. I chose unusual values so 390 * they are unlikely to clash with future ptrace definitions. 391 */ 392#define PTRACE_PEEKUSR_AREA 0x5000 393#define PTRACE_POKEUSR_AREA 0x5001 394#define PTRACE_PEEKTEXT_AREA 0x5002 395#define PTRACE_PEEKDATA_AREA 0x5003 396#define PTRACE_POKETEXT_AREA 0x5004 397#define PTRACE_POKEDATA_AREA 0x5005 398#define PTRACE_GET_LAST_BREAK 0x5006 399#define PTRACE_PEEK_SYSTEM_CALL 0x5007 400#define PTRACE_POKE_SYSTEM_CALL 0x5008 401#define PTRACE_ENABLE_TE 0x5009 402#define PTRACE_DISABLE_TE 0x5010 403#define PTRACE_TE_ABORT_RAND 0x5011 404 405/* 406 * The numbers chosen here are somewhat arbitrary but absolutely MUST 407 * not overlap with any of the number assigned in <linux/ptrace.h>. 408 */ 409#define PTRACE_SINGLEBLOCK 12 /* resume execution until next branch */ 410 411/* 412 * PT_PROT definition is loosely based on hppa bsd definition in 413 * gdb/hppab-nat.c 414 */ 415#define PTRACE_PROT 21 416 417typedef enum 418{ 419 ptprot_set_access_watchpoint, 420 ptprot_set_write_watchpoint, 421 ptprot_disable_watchpoint 422} ptprot_flags; 423 424typedef struct 425{ 426 unsigned long lowaddr; 427 unsigned long hiaddr; 428 ptprot_flags prot; 429} ptprot_area; 430 431/* Sequence of bytes for breakpoint illegal instruction. */ 432#define S390_BREAKPOINT {0x0,0x1} 433#define S390_BREAKPOINT_U16 ((__u16)0x0001) 434#define S390_SYSCALL_OPCODE ((__u16)0x0a00) 435#define S390_SYSCALL_SIZE 2 436 437/* 438 * The user_regs_struct defines the way the user registers are 439 * store on the stack for signal handling. 440 */ 441struct user_regs_struct 442{ 443 psw_t psw; 444 unsigned long gprs[NUM_GPRS]; 445 unsigned int acrs[NUM_ACRS]; 446 unsigned long orig_gpr2; 447 s390_fp_regs fp_regs; 448 /* 449 * These per registers are in here so that gdb can modify them 450 * itself as there is no "official" ptrace interface for hardware 451 * watchpoints. This is the way intel does it. 452 */ 453 per_struct per_info; 454 unsigned long ieee_instruction_pointer; /* obsolete, always 0 */ 455}; 456 457#endif /* __ASSEMBLY__ */ 458 459#endif /* _UAPI_S390_PTRACE_H */ 460