1/* 2 * Disassemble s390 instructions. 3 * 4 * Copyright IBM Corp. 2007 5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), 6 */ 7 8#include <linux/sched.h> 9#include <linux/kernel.h> 10#include <linux/string.h> 11#include <linux/errno.h> 12#include <linux/ptrace.h> 13#include <linux/timer.h> 14#include <linux/mm.h> 15#include <linux/smp.h> 16#include <linux/init.h> 17#include <linux/interrupt.h> 18#include <linux/delay.h> 19#include <linux/module.h> 20#include <linux/kallsyms.h> 21#include <linux/reboot.h> 22#include <linux/kprobes.h> 23#include <linux/kdebug.h> 24 25#include <asm/uaccess.h> 26#include <asm/dis.h> 27#include <asm/io.h> 28#include <linux/atomic.h> 29#include <asm/mathemu.h> 30#include <asm/cpcmd.h> 31#include <asm/lowcore.h> 32#include <asm/debug.h> 33#include <asm/irq.h> 34 35#ifndef CONFIG_64BIT 36#define ONELONG "%08lx: " 37#else /* CONFIG_64BIT */ 38#define ONELONG "%016lx: " 39#endif /* CONFIG_64BIT */ 40 41enum { 42 UNUSED, /* Indicates the end of the operand list */ 43 R_8, /* GPR starting at position 8 */ 44 R_12, /* GPR starting at position 12 */ 45 R_16, /* GPR starting at position 16 */ 46 R_20, /* GPR starting at position 20 */ 47 R_24, /* GPR starting at position 24 */ 48 R_28, /* GPR starting at position 28 */ 49 R_32, /* GPR starting at position 32 */ 50 F_8, /* FPR starting at position 8 */ 51 F_12, /* FPR starting at position 12 */ 52 F_16, /* FPR starting at position 16 */ 53 F_20, /* FPR starting at position 16 */ 54 F_24, /* FPR starting at position 24 */ 55 F_28, /* FPR starting at position 28 */ 56 F_32, /* FPR starting at position 32 */ 57 A_8, /* Access reg. starting at position 8 */ 58 A_12, /* Access reg. starting at position 12 */ 59 A_24, /* Access reg. starting at position 24 */ 60 A_28, /* Access reg. starting at position 28 */ 61 C_8, /* Control reg. starting at position 8 */ 62 C_12, /* Control reg. starting at position 12 */ 63 V_8, /* Vector reg. starting at position 8, extension bit at 36 */ 64 V_12, /* Vector reg. starting at position 12, extension bit at 37 */ 65 V_16, /* Vector reg. starting at position 16, extension bit at 38 */ 66 V_32, /* Vector reg. starting at position 32, extension bit at 39 */ 67 W_12, /* Vector reg. at bit 12, extension at bit 37, used as index */ 68 B_16, /* Base register starting at position 16 */ 69 B_32, /* Base register starting at position 32 */ 70 X_12, /* Index register starting at position 12 */ 71 D_20, /* Displacement starting at position 20 */ 72 D_36, /* Displacement starting at position 36 */ 73 D20_20, /* 20 bit displacement starting at 20 */ 74 L4_8, /* 4 bit length starting at position 8 */ 75 L4_12, /* 4 bit length starting at position 12 */ 76 L8_8, /* 8 bit length starting at position 8 */ 77 U4_8, /* 4 bit unsigned value starting at 8 */ 78 U4_12, /* 4 bit unsigned value starting at 12 */ 79 U4_16, /* 4 bit unsigned value starting at 16 */ 80 U4_20, /* 4 bit unsigned value starting at 20 */ 81 U4_24, /* 4 bit unsigned value starting at 24 */ 82 U4_28, /* 4 bit unsigned value starting at 28 */ 83 U4_32, /* 4 bit unsigned value starting at 32 */ 84 U4_36, /* 4 bit unsigned value starting at 36 */ 85 U8_8, /* 8 bit unsigned value starting at 8 */ 86 U8_16, /* 8 bit unsigned value starting at 16 */ 87 U8_24, /* 8 bit unsigned value starting at 24 */ 88 U8_32, /* 8 bit unsigned value starting at 32 */ 89 I8_8, /* 8 bit signed value starting at 8 */ 90 I8_16, /* 8 bit signed value starting at 16 */ 91 I8_24, /* 8 bit signed value starting at 24 */ 92 I8_32, /* 8 bit signed value starting at 32 */ 93 J12_12, /* PC relative offset at 12 */ 94 I16_16, /* 16 bit signed value starting at 16 */ 95 I16_32, /* 32 bit signed value starting at 16 */ 96 U16_16, /* 16 bit unsigned value starting at 16 */ 97 U16_32, /* 32 bit unsigned value starting at 16 */ 98 J16_16, /* PC relative jump offset at 16 */ 99 J16_32, /* PC relative offset at 16 */ 100 I24_24, /* 24 bit signed value starting at 24 */ 101 J32_16, /* PC relative long offset at 16 */ 102 I32_16, /* 32 bit signed value starting at 16 */ 103 U32_16, /* 32 bit unsigned value starting at 16 */ 104 M_16, /* 4 bit optional mask starting at 16 */ 105 M_20, /* 4 bit optional mask starting at 20 */ 106 M_24, /* 4 bit optional mask starting at 24 */ 107 M_28, /* 4 bit optional mask starting at 28 */ 108 M_32, /* 4 bit optional mask starting at 32 */ 109 RO_28, /* optional GPR starting at position 28 */ 110}; 111 112/* 113 * Enumeration of the different instruction formats. 114 * For details consult the principles of operation. 115 */ 116enum { 117 INSTR_INVALID, 118 INSTR_E, 119 INSTR_IE_UU, 120 INSTR_MII_UPI, 121 INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU, 122 INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0, 123 INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP, 124 INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU, 125 INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP, 126 INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0, 127 INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, 128 INSTR_RRE_RR, INSTR_RRE_RR_OPT, 129 INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, 130 INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_FUFF2, INSTR_RRF_M0RR, 131 INSTR_RRF_R0RR, INSTR_RRF_R0RR2, INSTR_RRF_RMRR, INSTR_RRF_RURR, 132 INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR, INSTR_RRF_UUFF, 133 INSTR_RRF_UUFR, INSTR_RRF_UURF, 134 INSTR_RRR_F0FF, INSTR_RRS_RRRDU, 135 INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR, 136 INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, 137 INSTR_RSI_RRP, 138 INSTR_RSL_LRDFU, INSTR_RSL_R0RD, 139 INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD, 140 INSTR_RSY_RDRM, 141 INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD, 142 INSTR_RS_RURD, 143 INSTR_RXE_FRRD, INSTR_RXE_RRRD, INSTR_RXE_RRRDM, 144 INSTR_RXF_FRRDF, 145 INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD, 146 INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD, 147 INSTR_SIL_RDI, INSTR_SIL_RDU, 148 INSTR_SIY_IRD, INSTR_SIY_URD, 149 INSTR_SI_URD, 150 INSTR_SMI_U0RDP, 151 INSTR_SSE_RDRD, 152 INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2, 153 INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, 154 INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3, 155 INSTR_S_00, INSTR_S_RD, 156 INSTR_VRI_V0IM, INSTR_VRI_V0I0, INSTR_VRI_V0IIM, INSTR_VRI_VVIM, 157 INSTR_VRI_VVV0IM, INSTR_VRI_VVV0I0, INSTR_VRI_VVIMM, 158 INSTR_VRR_VV00MMM, INSTR_VRR_VV000MM, INSTR_VRR_VV0000M, 159 INSTR_VRR_VV00000, INSTR_VRR_VVV0M0M, INSTR_VRR_VV00M0M, 160 INSTR_VRR_VVV000M, INSTR_VRR_VVV000V, INSTR_VRR_VVV0000, 161 INSTR_VRR_VVV0MMM, INSTR_VRR_VVV00MM, INSTR_VRR_VVVMM0V, 162 INSTR_VRR_VVVM0MV, INSTR_VRR_VVVM00V, INSTR_VRR_VRR0000, 163 INSTR_VRS_VVRDM, INSTR_VRS_VVRD0, INSTR_VRS_VRRDM, INSTR_VRS_VRRD0, 164 INSTR_VRS_RVRDM, 165 INSTR_VRV_VVRDM, INSTR_VRV_VWRDM, 166 INSTR_VRX_VRRDM, INSTR_VRX_VRRD0, 167}; 168 169static const struct s390_operand operands[] = 170{ 171 [UNUSED] = { 0, 0, 0 }, 172 [R_8] = { 4, 8, OPERAND_GPR }, 173 [R_12] = { 4, 12, OPERAND_GPR }, 174 [R_16] = { 4, 16, OPERAND_GPR }, 175 [R_20] = { 4, 20, OPERAND_GPR }, 176 [R_24] = { 4, 24, OPERAND_GPR }, 177 [R_28] = { 4, 28, OPERAND_GPR }, 178 [R_32] = { 4, 32, OPERAND_GPR }, 179 [F_8] = { 4, 8, OPERAND_FPR }, 180 [F_12] = { 4, 12, OPERAND_FPR }, 181 [F_16] = { 4, 16, OPERAND_FPR }, 182 [F_20] = { 4, 16, OPERAND_FPR }, 183 [F_24] = { 4, 24, OPERAND_FPR }, 184 [F_28] = { 4, 28, OPERAND_FPR }, 185 [F_32] = { 4, 32, OPERAND_FPR }, 186 [A_8] = { 4, 8, OPERAND_AR }, 187 [A_12] = { 4, 12, OPERAND_AR }, 188 [A_24] = { 4, 24, OPERAND_AR }, 189 [A_28] = { 4, 28, OPERAND_AR }, 190 [C_8] = { 4, 8, OPERAND_CR }, 191 [C_12] = { 4, 12, OPERAND_CR }, 192 [V_8] = { 4, 8, OPERAND_VR }, 193 [V_12] = { 4, 12, OPERAND_VR }, 194 [V_16] = { 4, 16, OPERAND_VR }, 195 [V_32] = { 4, 32, OPERAND_VR }, 196 [W_12] = { 4, 12, OPERAND_INDEX | OPERAND_VR }, 197 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 198 [B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR }, 199 [X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR }, 200 [D_20] = { 12, 20, OPERAND_DISP }, 201 [D_36] = { 12, 36, OPERAND_DISP }, 202 [D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED }, 203 [L4_8] = { 4, 8, OPERAND_LENGTH }, 204 [L4_12] = { 4, 12, OPERAND_LENGTH }, 205 [L8_8] = { 8, 8, OPERAND_LENGTH }, 206 [U4_8] = { 4, 8, 0 }, 207 [U4_12] = { 4, 12, 0 }, 208 [U4_16] = { 4, 16, 0 }, 209 [U4_20] = { 4, 20, 0 }, 210 [U4_24] = { 4, 24, 0 }, 211 [U4_28] = { 4, 28, 0 }, 212 [U4_32] = { 4, 32, 0 }, 213 [U4_36] = { 4, 36, 0 }, 214 [U8_8] = { 8, 8, 0 }, 215 [U8_16] = { 8, 16, 0 }, 216 [U8_24] = { 8, 24, 0 }, 217 [U8_32] = { 8, 32, 0 }, 218 [J12_12] = { 12, 12, OPERAND_PCREL }, 219 [I8_8] = { 8, 8, OPERAND_SIGNED }, 220 [I8_16] = { 8, 16, OPERAND_SIGNED }, 221 [I8_24] = { 8, 24, OPERAND_SIGNED }, 222 [I8_32] = { 8, 32, OPERAND_SIGNED }, 223 [I16_32] = { 16, 32, OPERAND_SIGNED }, 224 [I16_16] = { 16, 16, OPERAND_SIGNED }, 225 [U16_16] = { 16, 16, 0 }, 226 [U16_32] = { 16, 32, 0 }, 227 [J16_16] = { 16, 16, OPERAND_PCREL }, 228 [J16_32] = { 16, 32, OPERAND_PCREL }, 229 [I16_32] = { 16, 32, OPERAND_SIGNED }, 230 [I24_24] = { 24, 24, OPERAND_SIGNED }, 231 [J32_16] = { 32, 16, OPERAND_PCREL }, 232 [I32_16] = { 32, 16, OPERAND_SIGNED }, 233 [U32_16] = { 32, 16, 0 }, 234 [M_16] = { 4, 16, 0 }, 235 [M_20] = { 4, 20, 0 }, 236 [M_24] = { 4, 24, 0 }, 237 [M_28] = { 4, 28, 0 }, 238 [M_32] = { 4, 32, 0 }, 239 [RO_28] = { 4, 28, OPERAND_GPR } 240}; 241 242static const unsigned char formats[][7] = { 243 [INSTR_E] = { 0xff, 0,0,0,0,0,0 }, 244 [INSTR_IE_UU] = { 0xff, U4_24,U4_28,0,0,0,0 }, 245 [INSTR_MII_UPI] = { 0xff, U4_8,J12_12,I24_24 }, 246 [INSTR_RIE_R0IU] = { 0xff, R_8,I16_16,U4_32,0,0,0 }, 247 [INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 }, 248 [INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 }, 249 [INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 }, 250 [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 251 [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 }, 252 [INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 }, 253 [INSTR_RIE_RUPU] = { 0xff, R_8,U8_32,U4_12,J16_16,0,0 }, 254 [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 }, 255 [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 }, 256 [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 }, 257 [INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 }, 258 [INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 }, 259 [INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 }, 260 [INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 }, 261 [INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 }, 262 [INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 }, 263 [INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 }, 264 [INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 }, 265 [INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 }, 266 [INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 }, 267 [INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 }, 268 [INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 }, 269 [INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 }, 270 [INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 }, 271 [INSTR_RRE_FR] = { 0xff, F_24,R_28,0,0,0,0 }, 272 [INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 }, 273 [INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 }, 274 [INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 }, 275 [INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 }, 276 [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 }, 277 [INSTR_RRF_0UFF] = { 0xff, F_24,F_28,U4_20,0,0,0 }, 278 [INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 }, 279 [INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 }, 280 [INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 }, 281 [INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 }, 282 [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 }, 283 [INSTR_RRF_FUFF2] = { 0xff, F_24,F_28,F_16,U4_20,0,0 }, 284 [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 }, 285 [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 }, 286 [INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 }, 287 [INSTR_RRF_RMRR] = { 0xff, R_24,R_16,R_28,M_20,0,0 }, 288 [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 }, 289 [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 }, 290 [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 }, 291 [INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 }, 292 [INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 }, 293 [INSTR_RRF_UUFR] = { 0xff, F_24,U4_16,R_28,U4_20,0,0 }, 294 [INSTR_RRF_UURF] = { 0xff, R_24,U4_16,F_28,U4_20,0,0 }, 295 [INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 }, 296 [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 }, 297 [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 }, 298 [INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 }, 299 [INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 }, 300 [INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 }, 301 [INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 }, 302 [INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 303 [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 304 [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 305 [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 306 [INSTR_RSL_LRDFU] = { 0xff, F_32,D_20,L4_8,B_16,U4_36,0 }, 307 [INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 }, 308 [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 }, 309 [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 }, 310 [INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 }, 311 [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 }, 312 [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, 313 [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 }, 314 [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 315 [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, 316 [INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 317 [INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 318 [INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 319 [INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 320 [INSTR_RXE_RRRDM] = { 0xff, R_8,D_20,X_12,B_16,M_32,0 }, 321 [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 }, 322 [INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 }, 323 [INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 }, 324 [INSTR_RXY_URRD] = { 0xff, U4_8,D20_20,X_12,B_16,0,0 }, 325 [INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 326 [INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 327 [INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 }, 328 [INSTR_SIL_RDI] = { 0xff, D_20,B_16,I16_32,0,0,0 }, 329 [INSTR_SIL_RDU] = { 0xff, D_20,B_16,U16_32,0,0,0 }, 330 [INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 }, 331 [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 }, 332 [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 }, 333 [INSTR_SMI_U0RDP] = { 0xff, U4_8,J16_32,D_20,B_16,0,0 }, 334 [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 }, 335 [INSTR_SSF_RRDRD] = { 0x0f, D_20,B_16,D_36,B_32,R_8,0 }, 336 [INSTR_SSF_RRDRD2]= { 0x0f, R_8,D_20,B_16,D_36,B_32,0 }, 337 [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 }, 338 [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 }, 339 [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 }, 340 [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 }, 341 [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 }, 342 [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 }, 343 [INSTR_S_00] = { 0xff, 0,0,0,0,0,0 }, 344 [INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 }, 345 [INSTR_VRI_V0IM] = { 0xff, V_8,I16_16,M_32,0,0,0 }, 346 [INSTR_VRI_V0I0] = { 0xff, V_8,I16_16,0,0,0,0 }, 347 [INSTR_VRI_V0IIM] = { 0xff, V_8,I8_16,I8_24,M_32,0,0 }, 348 [INSTR_VRI_VVIM] = { 0xff, V_8,I16_16,V_12,M_32,0,0 }, 349 [INSTR_VRI_VVV0IM]= { 0xff, V_8,V_12,V_16,I8_24,M_32,0 }, 350 [INSTR_VRI_VVV0I0]= { 0xff, V_8,V_12,V_16,I8_24,0,0 }, 351 [INSTR_VRI_VVIMM] = { 0xff, V_8,V_12,I16_16,M_32,M_28,0 }, 352 [INSTR_VRR_VV00MMM]={ 0xff, V_8,V_12,M_32,M_28,M_24,0 }, 353 [INSTR_VRR_VV000MM]={ 0xff, V_8,V_12,M_32,M_28,0,0 }, 354 [INSTR_VRR_VV0000M]={ 0xff, V_8,V_12,M_32,0,0,0 }, 355 [INSTR_VRR_VV00000]={ 0xff, V_8,V_12,0,0,0,0 }, 356 [INSTR_VRR_VVV0M0M]={ 0xff, V_8,V_12,V_16,M_32,M_24,0 }, 357 [INSTR_VRR_VV00M0M]={ 0xff, V_8,V_12,M_32,M_24,0,0 }, 358 [INSTR_VRR_VVV000M]={ 0xff, V_8,V_12,V_16,M_32,0,0 }, 359 [INSTR_VRR_VVV000V]={ 0xff, V_8,V_12,V_16,V_32,0,0 }, 360 [INSTR_VRR_VVV0000]={ 0xff, V_8,V_12,V_16,0,0,0 }, 361 [INSTR_VRR_VVV0MMM]={ 0xff, V_8,V_12,V_16,M_32,M_28,M_24 }, 362 [INSTR_VRR_VVV00MM]={ 0xff, V_8,V_12,V_16,M_32,M_28,0 }, 363 [INSTR_VRR_VVVMM0V]={ 0xff, V_8,V_12,V_16,V_32,M_20,M_24 }, 364 [INSTR_VRR_VVVM0MV]={ 0xff, V_8,V_12,V_16,V_32,M_28,M_20 }, 365 [INSTR_VRR_VVVM00V]={ 0xff, V_8,V_12,V_16,V_32,M_20,0 }, 366 [INSTR_VRR_VRR0000]={ 0xff, V_8,R_12,R_16,0,0,0 }, 367 [INSTR_VRS_VVRDM] = { 0xff, V_8,V_12,D_20,B_16,M_32,0 }, 368 [INSTR_VRS_VVRD0] = { 0xff, V_8,V_12,D_20,B_16,0,0 }, 369 [INSTR_VRS_VRRDM] = { 0xff, V_8,R_12,D_20,B_16,M_32,0 }, 370 [INSTR_VRS_VRRD0] = { 0xff, V_8,R_12,D_20,B_16,0,0 }, 371 [INSTR_VRS_RVRDM] = { 0xff, R_8,V_12,D_20,B_16,M_32,0 }, 372 [INSTR_VRV_VVRDM] = { 0xff, V_8,V_12,D_20,B_16,M_32,0 }, 373 [INSTR_VRV_VWRDM] = { 0xff, V_8,D_20,W_12,B_16,M_32,0 }, 374 [INSTR_VRX_VRRDM] = { 0xff, V_8,D_20,X_12,B_16,M_32,0 }, 375 [INSTR_VRX_VRRD0] = { 0xff, V_8,D_20,X_12,B_16,0,0 }, 376}; 377 378enum { 379 LONG_INSN_ALGHSIK, 380 LONG_INSN_ALHHHR, 381 LONG_INSN_ALHHLR, 382 LONG_INSN_ALHSIK, 383 LONG_INSN_ALSIHN, 384 LONG_INSN_CDFBRA, 385 LONG_INSN_CDGBRA, 386 LONG_INSN_CDGTRA, 387 LONG_INSN_CDLFBR, 388 LONG_INSN_CDLFTR, 389 LONG_INSN_CDLGBR, 390 LONG_INSN_CDLGTR, 391 LONG_INSN_CEFBRA, 392 LONG_INSN_CEGBRA, 393 LONG_INSN_CELFBR, 394 LONG_INSN_CELGBR, 395 LONG_INSN_CFDBRA, 396 LONG_INSN_CFEBRA, 397 LONG_INSN_CFXBRA, 398 LONG_INSN_CGDBRA, 399 LONG_INSN_CGDTRA, 400 LONG_INSN_CGEBRA, 401 LONG_INSN_CGXBRA, 402 LONG_INSN_CGXTRA, 403 LONG_INSN_CLFDBR, 404 LONG_INSN_CLFDTR, 405 LONG_INSN_CLFEBR, 406 LONG_INSN_CLFHSI, 407 LONG_INSN_CLFXBR, 408 LONG_INSN_CLFXTR, 409 LONG_INSN_CLGDBR, 410 LONG_INSN_CLGDTR, 411 LONG_INSN_CLGEBR, 412 LONG_INSN_CLGFRL, 413 LONG_INSN_CLGHRL, 414 LONG_INSN_CLGHSI, 415 LONG_INSN_CLGXBR, 416 LONG_INSN_CLGXTR, 417 LONG_INSN_CLHHSI, 418 LONG_INSN_CXFBRA, 419 LONG_INSN_CXGBRA, 420 LONG_INSN_CXGTRA, 421 LONG_INSN_CXLFBR, 422 LONG_INSN_CXLFTR, 423 LONG_INSN_CXLGBR, 424 LONG_INSN_CXLGTR, 425 LONG_INSN_FIDBRA, 426 LONG_INSN_FIEBRA, 427 LONG_INSN_FIXBRA, 428 LONG_INSN_LDXBRA, 429 LONG_INSN_LEDBRA, 430 LONG_INSN_LEXBRA, 431 LONG_INSN_LLGFAT, 432 LONG_INSN_LLGFRL, 433 LONG_INSN_LLGHRL, 434 LONG_INSN_LLGTAT, 435 LONG_INSN_POPCNT, 436 LONG_INSN_RIEMIT, 437 LONG_INSN_RINEXT, 438 LONG_INSN_RISBGN, 439 LONG_INSN_RISBHG, 440 LONG_INSN_RISBLG, 441 LONG_INSN_SLHHHR, 442 LONG_INSN_SLHHLR, 443 LONG_INSN_TABORT, 444 LONG_INSN_TBEGIN, 445 LONG_INSN_TBEGINC, 446 LONG_INSN_PCISTG, 447 LONG_INSN_MPCIFC, 448 LONG_INSN_STPCIFC, 449 LONG_INSN_PCISTB, 450 LONG_INSN_VPOPCT, 451 LONG_INSN_VERLLV, 452 LONG_INSN_VESRAV, 453 LONG_INSN_VESRLV, 454 LONG_INSN_VSBCBI 455}; 456 457static char *long_insn_name[] = { 458 [LONG_INSN_ALGHSIK] = "alghsik", 459 [LONG_INSN_ALHHHR] = "alhhhr", 460 [LONG_INSN_ALHHLR] = "alhhlr", 461 [LONG_INSN_ALHSIK] = "alhsik", 462 [LONG_INSN_ALSIHN] = "alsihn", 463 [LONG_INSN_CDFBRA] = "cdfbra", 464 [LONG_INSN_CDGBRA] = "cdgbra", 465 [LONG_INSN_CDGTRA] = "cdgtra", 466 [LONG_INSN_CDLFBR] = "cdlfbr", 467 [LONG_INSN_CDLFTR] = "cdlftr", 468 [LONG_INSN_CDLGBR] = "cdlgbr", 469 [LONG_INSN_CDLGTR] = "cdlgtr", 470 [LONG_INSN_CEFBRA] = "cefbra", 471 [LONG_INSN_CEGBRA] = "cegbra", 472 [LONG_INSN_CELFBR] = "celfbr", 473 [LONG_INSN_CELGBR] = "celgbr", 474 [LONG_INSN_CFDBRA] = "cfdbra", 475 [LONG_INSN_CFEBRA] = "cfebra", 476 [LONG_INSN_CFXBRA] = "cfxbra", 477 [LONG_INSN_CGDBRA] = "cgdbra", 478 [LONG_INSN_CGDTRA] = "cgdtra", 479 [LONG_INSN_CGEBRA] = "cgebra", 480 [LONG_INSN_CGXBRA] = "cgxbra", 481 [LONG_INSN_CGXTRA] = "cgxtra", 482 [LONG_INSN_CLFDBR] = "clfdbr", 483 [LONG_INSN_CLFDTR] = "clfdtr", 484 [LONG_INSN_CLFEBR] = "clfebr", 485 [LONG_INSN_CLFHSI] = "clfhsi", 486 [LONG_INSN_CLFXBR] = "clfxbr", 487 [LONG_INSN_CLFXTR] = "clfxtr", 488 [LONG_INSN_CLGDBR] = "clgdbr", 489 [LONG_INSN_CLGDTR] = "clgdtr", 490 [LONG_INSN_CLGEBR] = "clgebr", 491 [LONG_INSN_CLGFRL] = "clgfrl", 492 [LONG_INSN_CLGHRL] = "clghrl", 493 [LONG_INSN_CLGHSI] = "clghsi", 494 [LONG_INSN_CLGXBR] = "clgxbr", 495 [LONG_INSN_CLGXTR] = "clgxtr", 496 [LONG_INSN_CLHHSI] = "clhhsi", 497 [LONG_INSN_CXFBRA] = "cxfbra", 498 [LONG_INSN_CXGBRA] = "cxgbra", 499 [LONG_INSN_CXGTRA] = "cxgtra", 500 [LONG_INSN_CXLFBR] = "cxlfbr", 501 [LONG_INSN_CXLFTR] = "cxlftr", 502 [LONG_INSN_CXLGBR] = "cxlgbr", 503 [LONG_INSN_CXLGTR] = "cxlgtr", 504 [LONG_INSN_FIDBRA] = "fidbra", 505 [LONG_INSN_FIEBRA] = "fiebra", 506 [LONG_INSN_FIXBRA] = "fixbra", 507 [LONG_INSN_LDXBRA] = "ldxbra", 508 [LONG_INSN_LEDBRA] = "ledbra", 509 [LONG_INSN_LEXBRA] = "lexbra", 510 [LONG_INSN_LLGFAT] = "llgfat", 511 [LONG_INSN_LLGFRL] = "llgfrl", 512 [LONG_INSN_LLGHRL] = "llghrl", 513 [LONG_INSN_LLGTAT] = "llgtat", 514 [LONG_INSN_POPCNT] = "popcnt", 515 [LONG_INSN_RIEMIT] = "riemit", 516 [LONG_INSN_RINEXT] = "rinext", 517 [LONG_INSN_RISBGN] = "risbgn", 518 [LONG_INSN_RISBHG] = "risbhg", 519 [LONG_INSN_RISBLG] = "risblg", 520 [LONG_INSN_SLHHHR] = "slhhhr", 521 [LONG_INSN_SLHHLR] = "slhhlr", 522 [LONG_INSN_TABORT] = "tabort", 523 [LONG_INSN_TBEGIN] = "tbegin", 524 [LONG_INSN_TBEGINC] = "tbeginc", 525 [LONG_INSN_PCISTG] = "pcistg", 526 [LONG_INSN_MPCIFC] = "mpcifc", 527 [LONG_INSN_STPCIFC] = "stpcifc", 528 [LONG_INSN_PCISTB] = "pcistb", 529 [LONG_INSN_VPOPCT] = "vpopct", 530 [LONG_INSN_VERLLV] = "verllv", 531 [LONG_INSN_VESRAV] = "vesrav", 532 [LONG_INSN_VESRLV] = "vesrlv", 533 [LONG_INSN_VSBCBI] = "vsbcbi", 534}; 535 536static struct s390_insn opcode[] = { 537#ifdef CONFIG_64BIT 538 { "bprp", 0xc5, INSTR_MII_UPI }, 539 { "bpp", 0xc7, INSTR_SMI_U0RDP }, 540 { "trtr", 0xd0, INSTR_SS_L0RDRD }, 541 { "lmd", 0xef, INSTR_SS_RRRDRD3 }, 542#endif 543 { "spm", 0x04, INSTR_RR_R0 }, 544 { "balr", 0x05, INSTR_RR_RR }, 545 { "bctr", 0x06, INSTR_RR_RR }, 546 { "bcr", 0x07, INSTR_RR_UR }, 547 { "svc", 0x0a, INSTR_RR_U0 }, 548 { "bsm", 0x0b, INSTR_RR_RR }, 549 { "bassm", 0x0c, INSTR_RR_RR }, 550 { "basr", 0x0d, INSTR_RR_RR }, 551 { "mvcl", 0x0e, INSTR_RR_RR }, 552 { "clcl", 0x0f, INSTR_RR_RR }, 553 { "lpr", 0x10, INSTR_RR_RR }, 554 { "lnr", 0x11, INSTR_RR_RR }, 555 { "ltr", 0x12, INSTR_RR_RR }, 556 { "lcr", 0x13, INSTR_RR_RR }, 557 { "nr", 0x14, INSTR_RR_RR }, 558 { "clr", 0x15, INSTR_RR_RR }, 559 { "or", 0x16, INSTR_RR_RR }, 560 { "xr", 0x17, INSTR_RR_RR }, 561 { "lr", 0x18, INSTR_RR_RR }, 562 { "cr", 0x19, INSTR_RR_RR }, 563 { "ar", 0x1a, INSTR_RR_RR }, 564 { "sr", 0x1b, INSTR_RR_RR }, 565 { "mr", 0x1c, INSTR_RR_RR }, 566 { "dr", 0x1d, INSTR_RR_RR }, 567 { "alr", 0x1e, INSTR_RR_RR }, 568 { "slr", 0x1f, INSTR_RR_RR }, 569 { "lpdr", 0x20, INSTR_RR_FF }, 570 { "lndr", 0x21, INSTR_RR_FF }, 571 { "ltdr", 0x22, INSTR_RR_FF }, 572 { "lcdr", 0x23, INSTR_RR_FF }, 573 { "hdr", 0x24, INSTR_RR_FF }, 574 { "ldxr", 0x25, INSTR_RR_FF }, 575 { "mxr", 0x26, INSTR_RR_FF }, 576 { "mxdr", 0x27, INSTR_RR_FF }, 577 { "ldr", 0x28, INSTR_RR_FF }, 578 { "cdr", 0x29, INSTR_RR_FF }, 579 { "adr", 0x2a, INSTR_RR_FF }, 580 { "sdr", 0x2b, INSTR_RR_FF }, 581 { "mdr", 0x2c, INSTR_RR_FF }, 582 { "ddr", 0x2d, INSTR_RR_FF }, 583 { "awr", 0x2e, INSTR_RR_FF }, 584 { "swr", 0x2f, INSTR_RR_FF }, 585 { "lper", 0x30, INSTR_RR_FF }, 586 { "lner", 0x31, INSTR_RR_FF }, 587 { "lter", 0x32, INSTR_RR_FF }, 588 { "lcer", 0x33, INSTR_RR_FF }, 589 { "her", 0x34, INSTR_RR_FF }, 590 { "ledr", 0x35, INSTR_RR_FF }, 591 { "axr", 0x36, INSTR_RR_FF }, 592 { "sxr", 0x37, INSTR_RR_FF }, 593 { "ler", 0x38, INSTR_RR_FF }, 594 { "cer", 0x39, INSTR_RR_FF }, 595 { "aer", 0x3a, INSTR_RR_FF }, 596 { "ser", 0x3b, INSTR_RR_FF }, 597 { "mder", 0x3c, INSTR_RR_FF }, 598 { "der", 0x3d, INSTR_RR_FF }, 599 { "aur", 0x3e, INSTR_RR_FF }, 600 { "sur", 0x3f, INSTR_RR_FF }, 601 { "sth", 0x40, INSTR_RX_RRRD }, 602 { "la", 0x41, INSTR_RX_RRRD }, 603 { "stc", 0x42, INSTR_RX_RRRD }, 604 { "ic", 0x43, INSTR_RX_RRRD }, 605 { "ex", 0x44, INSTR_RX_RRRD }, 606 { "bal", 0x45, INSTR_RX_RRRD }, 607 { "bct", 0x46, INSTR_RX_RRRD }, 608 { "bc", 0x47, INSTR_RX_URRD }, 609 { "lh", 0x48, INSTR_RX_RRRD }, 610 { "ch", 0x49, INSTR_RX_RRRD }, 611 { "ah", 0x4a, INSTR_RX_RRRD }, 612 { "sh", 0x4b, INSTR_RX_RRRD }, 613 { "mh", 0x4c, INSTR_RX_RRRD }, 614 { "bas", 0x4d, INSTR_RX_RRRD }, 615 { "cvd", 0x4e, INSTR_RX_RRRD }, 616 { "cvb", 0x4f, INSTR_RX_RRRD }, 617 { "st", 0x50, INSTR_RX_RRRD }, 618 { "lae", 0x51, INSTR_RX_RRRD }, 619 { "n", 0x54, INSTR_RX_RRRD }, 620 { "cl", 0x55, INSTR_RX_RRRD }, 621 { "o", 0x56, INSTR_RX_RRRD }, 622 { "x", 0x57, INSTR_RX_RRRD }, 623 { "l", 0x58, INSTR_RX_RRRD }, 624 { "c", 0x59, INSTR_RX_RRRD }, 625 { "a", 0x5a, INSTR_RX_RRRD }, 626 { "s", 0x5b, INSTR_RX_RRRD }, 627 { "m", 0x5c, INSTR_RX_RRRD }, 628 { "d", 0x5d, INSTR_RX_RRRD }, 629 { "al", 0x5e, INSTR_RX_RRRD }, 630 { "sl", 0x5f, INSTR_RX_RRRD }, 631 { "std", 0x60, INSTR_RX_FRRD }, 632 { "mxd", 0x67, INSTR_RX_FRRD }, 633 { "ld", 0x68, INSTR_RX_FRRD }, 634 { "cd", 0x69, INSTR_RX_FRRD }, 635 { "ad", 0x6a, INSTR_RX_FRRD }, 636 { "sd", 0x6b, INSTR_RX_FRRD }, 637 { "md", 0x6c, INSTR_RX_FRRD }, 638 { "dd", 0x6d, INSTR_RX_FRRD }, 639 { "aw", 0x6e, INSTR_RX_FRRD }, 640 { "sw", 0x6f, INSTR_RX_FRRD }, 641 { "ste", 0x70, INSTR_RX_FRRD }, 642 { "ms", 0x71, INSTR_RX_RRRD }, 643 { "le", 0x78, INSTR_RX_FRRD }, 644 { "ce", 0x79, INSTR_RX_FRRD }, 645 { "ae", 0x7a, INSTR_RX_FRRD }, 646 { "se", 0x7b, INSTR_RX_FRRD }, 647 { "mde", 0x7c, INSTR_RX_FRRD }, 648 { "de", 0x7d, INSTR_RX_FRRD }, 649 { "au", 0x7e, INSTR_RX_FRRD }, 650 { "su", 0x7f, INSTR_RX_FRRD }, 651 { "ssm", 0x80, INSTR_S_RD }, 652 { "lpsw", 0x82, INSTR_S_RD }, 653 { "diag", 0x83, INSTR_RS_RRRD }, 654 { "brxh", 0x84, INSTR_RSI_RRP }, 655 { "brxle", 0x85, INSTR_RSI_RRP }, 656 { "bxh", 0x86, INSTR_RS_RRRD }, 657 { "bxle", 0x87, INSTR_RS_RRRD }, 658 { "srl", 0x88, INSTR_RS_R0RD }, 659 { "sll", 0x89, INSTR_RS_R0RD }, 660 { "sra", 0x8a, INSTR_RS_R0RD }, 661 { "sla", 0x8b, INSTR_RS_R0RD }, 662 { "srdl", 0x8c, INSTR_RS_R0RD }, 663 { "sldl", 0x8d, INSTR_RS_R0RD }, 664 { "srda", 0x8e, INSTR_RS_R0RD }, 665 { "slda", 0x8f, INSTR_RS_R0RD }, 666 { "stm", 0x90, INSTR_RS_RRRD }, 667 { "tm", 0x91, INSTR_SI_URD }, 668 { "mvi", 0x92, INSTR_SI_URD }, 669 { "ts", 0x93, INSTR_S_RD }, 670 { "ni", 0x94, INSTR_SI_URD }, 671 { "cli", 0x95, INSTR_SI_URD }, 672 { "oi", 0x96, INSTR_SI_URD }, 673 { "xi", 0x97, INSTR_SI_URD }, 674 { "lm", 0x98, INSTR_RS_RRRD }, 675 { "trace", 0x99, INSTR_RS_RRRD }, 676 { "lam", 0x9a, INSTR_RS_AARD }, 677 { "stam", 0x9b, INSTR_RS_AARD }, 678 { "mvcle", 0xa8, INSTR_RS_RRRD }, 679 { "clcle", 0xa9, INSTR_RS_RRRD }, 680 { "stnsm", 0xac, INSTR_SI_URD }, 681 { "stosm", 0xad, INSTR_SI_URD }, 682 { "sigp", 0xae, INSTR_RS_RRRD }, 683 { "mc", 0xaf, INSTR_SI_URD }, 684 { "lra", 0xb1, INSTR_RX_RRRD }, 685 { "stctl", 0xb6, INSTR_RS_CCRD }, 686 { "lctl", 0xb7, INSTR_RS_CCRD }, 687 { "cs", 0xba, INSTR_RS_RRRD }, 688 { "cds", 0xbb, INSTR_RS_RRRD }, 689 { "clm", 0xbd, INSTR_RS_RURD }, 690 { "stcm", 0xbe, INSTR_RS_RURD }, 691 { "icm", 0xbf, INSTR_RS_RURD }, 692 { "mvn", 0xd1, INSTR_SS_L0RDRD }, 693 { "mvc", 0xd2, INSTR_SS_L0RDRD }, 694 { "mvz", 0xd3, INSTR_SS_L0RDRD }, 695 { "nc", 0xd4, INSTR_SS_L0RDRD }, 696 { "clc", 0xd5, INSTR_SS_L0RDRD }, 697 { "oc", 0xd6, INSTR_SS_L0RDRD }, 698 { "xc", 0xd7, INSTR_SS_L0RDRD }, 699 { "mvck", 0xd9, INSTR_SS_RRRDRD }, 700 { "mvcp", 0xda, INSTR_SS_RRRDRD }, 701 { "mvcs", 0xdb, INSTR_SS_RRRDRD }, 702 { "tr", 0xdc, INSTR_SS_L0RDRD }, 703 { "trt", 0xdd, INSTR_SS_L0RDRD }, 704 { "ed", 0xde, INSTR_SS_L0RDRD }, 705 { "edmk", 0xdf, INSTR_SS_L0RDRD }, 706 { "pku", 0xe1, INSTR_SS_L0RDRD }, 707 { "unpku", 0xe2, INSTR_SS_L0RDRD }, 708 { "mvcin", 0xe8, INSTR_SS_L0RDRD }, 709 { "pka", 0xe9, INSTR_SS_L0RDRD }, 710 { "unpka", 0xea, INSTR_SS_L0RDRD }, 711 { "plo", 0xee, INSTR_SS_RRRDRD2 }, 712 { "srp", 0xf0, INSTR_SS_LIRDRD }, 713 { "mvo", 0xf1, INSTR_SS_LLRDRD }, 714 { "pack", 0xf2, INSTR_SS_LLRDRD }, 715 { "unpk", 0xf3, INSTR_SS_LLRDRD }, 716 { "zap", 0xf8, INSTR_SS_LLRDRD }, 717 { "cp", 0xf9, INSTR_SS_LLRDRD }, 718 { "ap", 0xfa, INSTR_SS_LLRDRD }, 719 { "sp", 0xfb, INSTR_SS_LLRDRD }, 720 { "mp", 0xfc, INSTR_SS_LLRDRD }, 721 { "dp", 0xfd, INSTR_SS_LLRDRD }, 722 { "", 0, INSTR_INVALID } 723}; 724 725static struct s390_insn opcode_01[] = { 726#ifdef CONFIG_64BIT 727 { "ptff", 0x04, INSTR_E }, 728 { "pfpo", 0x0a, INSTR_E }, 729 { "sam64", 0x0e, INSTR_E }, 730#endif 731 { "pr", 0x01, INSTR_E }, 732 { "upt", 0x02, INSTR_E }, 733 { "sckpf", 0x07, INSTR_E }, 734 { "tam", 0x0b, INSTR_E }, 735 { "sam24", 0x0c, INSTR_E }, 736 { "sam31", 0x0d, INSTR_E }, 737 { "trap2", 0xff, INSTR_E }, 738 { "", 0, INSTR_INVALID } 739}; 740 741static struct s390_insn opcode_a5[] = { 742#ifdef CONFIG_64BIT 743 { "iihh", 0x00, INSTR_RI_RU }, 744 { "iihl", 0x01, INSTR_RI_RU }, 745 { "iilh", 0x02, INSTR_RI_RU }, 746 { "iill", 0x03, INSTR_RI_RU }, 747 { "nihh", 0x04, INSTR_RI_RU }, 748 { "nihl", 0x05, INSTR_RI_RU }, 749 { "nilh", 0x06, INSTR_RI_RU }, 750 { "nill", 0x07, INSTR_RI_RU }, 751 { "oihh", 0x08, INSTR_RI_RU }, 752 { "oihl", 0x09, INSTR_RI_RU }, 753 { "oilh", 0x0a, INSTR_RI_RU }, 754 { "oill", 0x0b, INSTR_RI_RU }, 755 { "llihh", 0x0c, INSTR_RI_RU }, 756 { "llihl", 0x0d, INSTR_RI_RU }, 757 { "llilh", 0x0e, INSTR_RI_RU }, 758 { "llill", 0x0f, INSTR_RI_RU }, 759#endif 760 { "", 0, INSTR_INVALID } 761}; 762 763static struct s390_insn opcode_a7[] = { 764#ifdef CONFIG_64BIT 765 { "tmhh", 0x02, INSTR_RI_RU }, 766 { "tmhl", 0x03, INSTR_RI_RU }, 767 { "brctg", 0x07, INSTR_RI_RP }, 768 { "lghi", 0x09, INSTR_RI_RI }, 769 { "aghi", 0x0b, INSTR_RI_RI }, 770 { "mghi", 0x0d, INSTR_RI_RI }, 771 { "cghi", 0x0f, INSTR_RI_RI }, 772#endif 773 { "tmlh", 0x00, INSTR_RI_RU }, 774 { "tmll", 0x01, INSTR_RI_RU }, 775 { "brc", 0x04, INSTR_RI_UP }, 776 { "bras", 0x05, INSTR_RI_RP }, 777 { "brct", 0x06, INSTR_RI_RP }, 778 { "lhi", 0x08, INSTR_RI_RI }, 779 { "ahi", 0x0a, INSTR_RI_RI }, 780 { "mhi", 0x0c, INSTR_RI_RI }, 781 { "chi", 0x0e, INSTR_RI_RI }, 782 { "", 0, INSTR_INVALID } 783}; 784 785static struct s390_insn opcode_aa[] = { 786#ifdef CONFIG_64BIT 787 { { 0, LONG_INSN_RINEXT }, 0x00, INSTR_RI_RI }, 788 { "rion", 0x01, INSTR_RI_RI }, 789 { "tric", 0x02, INSTR_RI_RI }, 790 { "rioff", 0x03, INSTR_RI_RI }, 791 { { 0, LONG_INSN_RIEMIT }, 0x04, INSTR_RI_RI }, 792#endif 793 { "", 0, INSTR_INVALID } 794}; 795 796static struct s390_insn opcode_b2[] = { 797#ifdef CONFIG_64BIT 798 { "stckf", 0x7c, INSTR_S_RD }, 799 { "lpp", 0x80, INSTR_S_RD }, 800 { "lcctl", 0x84, INSTR_S_RD }, 801 { "lpctl", 0x85, INSTR_S_RD }, 802 { "qsi", 0x86, INSTR_S_RD }, 803 { "lsctl", 0x87, INSTR_S_RD }, 804 { "qctri", 0x8e, INSTR_S_RD }, 805 { "stfle", 0xb0, INSTR_S_RD }, 806 { "lpswe", 0xb2, INSTR_S_RD }, 807 { "srnmb", 0xb8, INSTR_S_RD }, 808 { "srnmt", 0xb9, INSTR_S_RD }, 809 { "lfas", 0xbd, INSTR_S_RD }, 810 { "scctr", 0xe0, INSTR_RRE_RR }, 811 { "spctr", 0xe1, INSTR_RRE_RR }, 812 { "ecctr", 0xe4, INSTR_RRE_RR }, 813 { "epctr", 0xe5, INSTR_RRE_RR }, 814 { "ppa", 0xe8, INSTR_RRF_U0RR }, 815 { "etnd", 0xec, INSTR_RRE_R0 }, 816 { "ecpga", 0xed, INSTR_RRE_RR }, 817 { "tend", 0xf8, INSTR_S_00 }, 818 { "niai", 0xfa, INSTR_IE_UU }, 819 { { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD }, 820#endif 821 { "stidp", 0x02, INSTR_S_RD }, 822 { "sck", 0x04, INSTR_S_RD }, 823 { "stck", 0x05, INSTR_S_RD }, 824 { "sckc", 0x06, INSTR_S_RD }, 825 { "stckc", 0x07, INSTR_S_RD }, 826 { "spt", 0x08, INSTR_S_RD }, 827 { "stpt", 0x09, INSTR_S_RD }, 828 { "spka", 0x0a, INSTR_S_RD }, 829 { "ipk", 0x0b, INSTR_S_00 }, 830 { "ptlb", 0x0d, INSTR_S_00 }, 831 { "spx", 0x10, INSTR_S_RD }, 832 { "stpx", 0x11, INSTR_S_RD }, 833 { "stap", 0x12, INSTR_S_RD }, 834 { "sie", 0x14, INSTR_S_RD }, 835 { "pc", 0x18, INSTR_S_RD }, 836 { "sac", 0x19, INSTR_S_RD }, 837 { "cfc", 0x1a, INSTR_S_RD }, 838 { "servc", 0x20, INSTR_RRE_RR }, 839 { "ipte", 0x21, INSTR_RRE_RR }, 840 { "ipm", 0x22, INSTR_RRE_R0 }, 841 { "ivsk", 0x23, INSTR_RRE_RR }, 842 { "iac", 0x24, INSTR_RRE_R0 }, 843 { "ssar", 0x25, INSTR_RRE_R0 }, 844 { "epar", 0x26, INSTR_RRE_R0 }, 845 { "esar", 0x27, INSTR_RRE_R0 }, 846 { "pt", 0x28, INSTR_RRE_RR }, 847 { "iske", 0x29, INSTR_RRE_RR }, 848 { "rrbe", 0x2a, INSTR_RRE_RR }, 849 { "sske", 0x2b, INSTR_RRF_M0RR }, 850 { "tb", 0x2c, INSTR_RRE_0R }, 851 { "dxr", 0x2d, INSTR_RRE_FF }, 852 { "pgin", 0x2e, INSTR_RRE_RR }, 853 { "pgout", 0x2f, INSTR_RRE_RR }, 854 { "csch", 0x30, INSTR_S_00 }, 855 { "hsch", 0x31, INSTR_S_00 }, 856 { "msch", 0x32, INSTR_S_RD }, 857 { "ssch", 0x33, INSTR_S_RD }, 858 { "stsch", 0x34, INSTR_S_RD }, 859 { "tsch", 0x35, INSTR_S_RD }, 860 { "tpi", 0x36, INSTR_S_RD }, 861 { "sal", 0x37, INSTR_S_00 }, 862 { "rsch", 0x38, INSTR_S_00 }, 863 { "stcrw", 0x39, INSTR_S_RD }, 864 { "stcps", 0x3a, INSTR_S_RD }, 865 { "rchp", 0x3b, INSTR_S_00 }, 866 { "schm", 0x3c, INSTR_S_00 }, 867 { "bakr", 0x40, INSTR_RRE_RR }, 868 { "cksm", 0x41, INSTR_RRE_RR }, 869 { "sqdr", 0x44, INSTR_RRE_FF }, 870 { "sqer", 0x45, INSTR_RRE_FF }, 871 { "stura", 0x46, INSTR_RRE_RR }, 872 { "msta", 0x47, INSTR_RRE_R0 }, 873 { "palb", 0x48, INSTR_RRE_00 }, 874 { "ereg", 0x49, INSTR_RRE_RR }, 875 { "esta", 0x4a, INSTR_RRE_RR }, 876 { "lura", 0x4b, INSTR_RRE_RR }, 877 { "tar", 0x4c, INSTR_RRE_AR }, 878 { "cpya", 0x4d, INSTR_RRE_AA }, 879 { "sar", 0x4e, INSTR_RRE_AR }, 880 { "ear", 0x4f, INSTR_RRE_RA }, 881 { "csp", 0x50, INSTR_RRE_RR }, 882 { "msr", 0x52, INSTR_RRE_RR }, 883 { "mvpg", 0x54, INSTR_RRE_RR }, 884 { "mvst", 0x55, INSTR_RRE_RR }, 885 { "cuse", 0x57, INSTR_RRE_RR }, 886 { "bsg", 0x58, INSTR_RRE_RR }, 887 { "bsa", 0x5a, INSTR_RRE_RR }, 888 { "clst", 0x5d, INSTR_RRE_RR }, 889 { "srst", 0x5e, INSTR_RRE_RR }, 890 { "cmpsc", 0x63, INSTR_RRE_RR }, 891 { "siga", 0x74, INSTR_S_RD }, 892 { "xsch", 0x76, INSTR_S_00 }, 893 { "rp", 0x77, INSTR_S_RD }, 894 { "stcke", 0x78, INSTR_S_RD }, 895 { "sacf", 0x79, INSTR_S_RD }, 896 { "stsi", 0x7d, INSTR_S_RD }, 897 { "srnm", 0x99, INSTR_S_RD }, 898 { "stfpc", 0x9c, INSTR_S_RD }, 899 { "lfpc", 0x9d, INSTR_S_RD }, 900 { "tre", 0xa5, INSTR_RRE_RR }, 901 { "cuutf", 0xa6, INSTR_RRF_M0RR }, 902 { "cutfu", 0xa7, INSTR_RRF_M0RR }, 903 { "stfl", 0xb1, INSTR_S_RD }, 904 { "trap4", 0xff, INSTR_S_RD }, 905 { "", 0, INSTR_INVALID } 906}; 907 908static struct s390_insn opcode_b3[] = { 909#ifdef CONFIG_64BIT 910 { "maylr", 0x38, INSTR_RRF_F0FF }, 911 { "mylr", 0x39, INSTR_RRF_F0FF }, 912 { "mayr", 0x3a, INSTR_RRF_F0FF }, 913 { "myr", 0x3b, INSTR_RRF_F0FF }, 914 { "mayhr", 0x3c, INSTR_RRF_F0FF }, 915 { "myhr", 0x3d, INSTR_RRF_F0FF }, 916 { "lpdfr", 0x70, INSTR_RRE_FF }, 917 { "lndfr", 0x71, INSTR_RRE_FF }, 918 { "cpsdr", 0x72, INSTR_RRF_F0FF2 }, 919 { "lcdfr", 0x73, INSTR_RRE_FF }, 920 { "sfasr", 0x85, INSTR_RRE_R0 }, 921 { { 0, LONG_INSN_CELFBR }, 0x90, INSTR_RRF_UUFR }, 922 { { 0, LONG_INSN_CDLFBR }, 0x91, INSTR_RRF_UUFR }, 923 { { 0, LONG_INSN_CXLFBR }, 0x92, INSTR_RRF_UURF }, 924 { { 0, LONG_INSN_CEFBRA }, 0x94, INSTR_RRF_UUFR }, 925 { { 0, LONG_INSN_CDFBRA }, 0x95, INSTR_RRF_UUFR }, 926 { { 0, LONG_INSN_CXFBRA }, 0x96, INSTR_RRF_UURF }, 927 { { 0, LONG_INSN_CFEBRA }, 0x98, INSTR_RRF_UURF }, 928 { { 0, LONG_INSN_CFDBRA }, 0x99, INSTR_RRF_UURF }, 929 { { 0, LONG_INSN_CFXBRA }, 0x9a, INSTR_RRF_UUFR }, 930 { { 0, LONG_INSN_CLFEBR }, 0x9c, INSTR_RRF_UURF }, 931 { { 0, LONG_INSN_CLFDBR }, 0x9d, INSTR_RRF_UURF }, 932 { { 0, LONG_INSN_CLFXBR }, 0x9e, INSTR_RRF_UUFR }, 933 { { 0, LONG_INSN_CELGBR }, 0xa0, INSTR_RRF_UUFR }, 934 { { 0, LONG_INSN_CDLGBR }, 0xa1, INSTR_RRF_UUFR }, 935 { { 0, LONG_INSN_CXLGBR }, 0xa2, INSTR_RRF_UURF }, 936 { { 0, LONG_INSN_CEGBRA }, 0xa4, INSTR_RRF_UUFR }, 937 { { 0, LONG_INSN_CDGBRA }, 0xa5, INSTR_RRF_UUFR }, 938 { { 0, LONG_INSN_CXGBRA }, 0xa6, INSTR_RRF_UURF }, 939 { { 0, LONG_INSN_CGEBRA }, 0xa8, INSTR_RRF_UURF }, 940 { { 0, LONG_INSN_CGDBRA }, 0xa9, INSTR_RRF_UURF }, 941 { { 0, LONG_INSN_CGXBRA }, 0xaa, INSTR_RRF_UUFR }, 942 { { 0, LONG_INSN_CLGEBR }, 0xac, INSTR_RRF_UURF }, 943 { { 0, LONG_INSN_CLGDBR }, 0xad, INSTR_RRF_UURF }, 944 { { 0, LONG_INSN_CLGXBR }, 0xae, INSTR_RRF_UUFR }, 945 { "ldgr", 0xc1, INSTR_RRE_FR }, 946 { "cegr", 0xc4, INSTR_RRE_FR }, 947 { "cdgr", 0xc5, INSTR_RRE_FR }, 948 { "cxgr", 0xc6, INSTR_RRE_FR }, 949 { "cger", 0xc8, INSTR_RRF_U0RF }, 950 { "cgdr", 0xc9, INSTR_RRF_U0RF }, 951 { "cgxr", 0xca, INSTR_RRF_U0RF }, 952 { "lgdr", 0xcd, INSTR_RRE_RF }, 953 { "mdtra", 0xd0, INSTR_RRF_FUFF2 }, 954 { "ddtra", 0xd1, INSTR_RRF_FUFF2 }, 955 { "adtra", 0xd2, INSTR_RRF_FUFF2 }, 956 { "sdtra", 0xd3, INSTR_RRF_FUFF2 }, 957 { "ldetr", 0xd4, INSTR_RRF_0UFF }, 958 { "ledtr", 0xd5, INSTR_RRF_UUFF }, 959 { "ltdtr", 0xd6, INSTR_RRE_FF }, 960 { "fidtr", 0xd7, INSTR_RRF_UUFF }, 961 { "mxtra", 0xd8, INSTR_RRF_FUFF2 }, 962 { "dxtra", 0xd9, INSTR_RRF_FUFF2 }, 963 { "axtra", 0xda, INSTR_RRF_FUFF2 }, 964 { "sxtra", 0xdb, INSTR_RRF_FUFF2 }, 965 { "lxdtr", 0xdc, INSTR_RRF_0UFF }, 966 { "ldxtr", 0xdd, INSTR_RRF_UUFF }, 967 { "ltxtr", 0xde, INSTR_RRE_FF }, 968 { "fixtr", 0xdf, INSTR_RRF_UUFF }, 969 { "kdtr", 0xe0, INSTR_RRE_FF }, 970 { { 0, LONG_INSN_CGDTRA }, 0xe1, INSTR_RRF_UURF }, 971 { "cudtr", 0xe2, INSTR_RRE_RF }, 972 { "csdtr", 0xe3, INSTR_RRE_RF }, 973 { "cdtr", 0xe4, INSTR_RRE_FF }, 974 { "eedtr", 0xe5, INSTR_RRE_RF }, 975 { "esdtr", 0xe7, INSTR_RRE_RF }, 976 { "kxtr", 0xe8, INSTR_RRE_FF }, 977 { { 0, LONG_INSN_CGXTRA }, 0xe9, INSTR_RRF_UUFR }, 978 { "cuxtr", 0xea, INSTR_RRE_RF }, 979 { "csxtr", 0xeb, INSTR_RRE_RF }, 980 { "cxtr", 0xec, INSTR_RRE_FF }, 981 { "eextr", 0xed, INSTR_RRE_RF }, 982 { "esxtr", 0xef, INSTR_RRE_RF }, 983 { { 0, LONG_INSN_CDGTRA }, 0xf1, INSTR_RRF_UUFR }, 984 { "cdutr", 0xf2, INSTR_RRE_FR }, 985 { "cdstr", 0xf3, INSTR_RRE_FR }, 986 { "cedtr", 0xf4, INSTR_RRE_FF }, 987 { "qadtr", 0xf5, INSTR_RRF_FUFF }, 988 { "iedtr", 0xf6, INSTR_RRF_F0FR }, 989 { "rrdtr", 0xf7, INSTR_RRF_FFRU }, 990 { { 0, LONG_INSN_CXGTRA }, 0xf9, INSTR_RRF_UURF }, 991 { "cxutr", 0xfa, INSTR_RRE_FR }, 992 { "cxstr", 0xfb, INSTR_RRE_FR }, 993 { "cextr", 0xfc, INSTR_RRE_FF }, 994 { "qaxtr", 0xfd, INSTR_RRF_FUFF }, 995 { "iextr", 0xfe, INSTR_RRF_F0FR }, 996 { "rrxtr", 0xff, INSTR_RRF_FFRU }, 997#endif 998 { "lpebr", 0x00, INSTR_RRE_FF }, 999 { "lnebr", 0x01, INSTR_RRE_FF }, 1000 { "ltebr", 0x02, INSTR_RRE_FF }, 1001 { "lcebr", 0x03, INSTR_RRE_FF }, 1002 { "ldebr", 0x04, INSTR_RRE_FF }, 1003 { "lxdbr", 0x05, INSTR_RRE_FF }, 1004 { "lxebr", 0x06, INSTR_RRE_FF }, 1005 { "mxdbr", 0x07, INSTR_RRE_FF }, 1006 { "kebr", 0x08, INSTR_RRE_FF }, 1007 { "cebr", 0x09, INSTR_RRE_FF }, 1008 { "aebr", 0x0a, INSTR_RRE_FF }, 1009 { "sebr", 0x0b, INSTR_RRE_FF }, 1010 { "mdebr", 0x0c, INSTR_RRE_FF }, 1011 { "debr", 0x0d, INSTR_RRE_FF }, 1012 { "maebr", 0x0e, INSTR_RRF_F0FF }, 1013 { "msebr", 0x0f, INSTR_RRF_F0FF }, 1014 { "lpdbr", 0x10, INSTR_RRE_FF }, 1015 { "lndbr", 0x11, INSTR_RRE_FF }, 1016 { "ltdbr", 0x12, INSTR_RRE_FF }, 1017 { "lcdbr", 0x13, INSTR_RRE_FF }, 1018 { "sqebr", 0x14, INSTR_RRE_FF }, 1019 { "sqdbr", 0x15, INSTR_RRE_FF }, 1020 { "sqxbr", 0x16, INSTR_RRE_FF }, 1021 { "meebr", 0x17, INSTR_RRE_FF }, 1022 { "kdbr", 0x18, INSTR_RRE_FF }, 1023 { "cdbr", 0x19, INSTR_RRE_FF }, 1024 { "adbr", 0x1a, INSTR_RRE_FF }, 1025 { "sdbr", 0x1b, INSTR_RRE_FF }, 1026 { "mdbr", 0x1c, INSTR_RRE_FF }, 1027 { "ddbr", 0x1d, INSTR_RRE_FF }, 1028 { "madbr", 0x1e, INSTR_RRF_F0FF }, 1029 { "msdbr", 0x1f, INSTR_RRF_F0FF }, 1030 { "lder", 0x24, INSTR_RRE_FF }, 1031 { "lxdr", 0x25, INSTR_RRE_FF }, 1032 { "lxer", 0x26, INSTR_RRE_FF }, 1033 { "maer", 0x2e, INSTR_RRF_F0FF }, 1034 { "mser", 0x2f, INSTR_RRF_F0FF }, 1035 { "sqxr", 0x36, INSTR_RRE_FF }, 1036 { "meer", 0x37, INSTR_RRE_FF }, 1037 { "madr", 0x3e, INSTR_RRF_F0FF }, 1038 { "msdr", 0x3f, INSTR_RRF_F0FF }, 1039 { "lpxbr", 0x40, INSTR_RRE_FF }, 1040 { "lnxbr", 0x41, INSTR_RRE_FF }, 1041 { "ltxbr", 0x42, INSTR_RRE_FF }, 1042 { "lcxbr", 0x43, INSTR_RRE_FF }, 1043 { { 0, LONG_INSN_LEDBRA }, 0x44, INSTR_RRF_UUFF }, 1044 { { 0, LONG_INSN_LDXBRA }, 0x45, INSTR_RRF_UUFF }, 1045 { { 0, LONG_INSN_LEXBRA }, 0x46, INSTR_RRF_UUFF }, 1046 { { 0, LONG_INSN_FIXBRA }, 0x47, INSTR_RRF_UUFF }, 1047 { "kxbr", 0x48, INSTR_RRE_FF }, 1048 { "cxbr", 0x49, INSTR_RRE_FF }, 1049 { "axbr", 0x4a, INSTR_RRE_FF }, 1050 { "sxbr", 0x4b, INSTR_RRE_FF }, 1051 { "mxbr", 0x4c, INSTR_RRE_FF }, 1052 { "dxbr", 0x4d, INSTR_RRE_FF }, 1053 { "tbedr", 0x50, INSTR_RRF_U0FF }, 1054 { "tbdr", 0x51, INSTR_RRF_U0FF }, 1055 { "diebr", 0x53, INSTR_RRF_FUFF }, 1056 { { 0, LONG_INSN_FIEBRA }, 0x57, INSTR_RRF_UUFF }, 1057 { "thder", 0x58, INSTR_RRE_FF }, 1058 { "thdr", 0x59, INSTR_RRE_FF }, 1059 { "didbr", 0x5b, INSTR_RRF_FUFF }, 1060 { { 0, LONG_INSN_FIDBRA }, 0x5f, INSTR_RRF_UUFF }, 1061 { "lpxr", 0x60, INSTR_RRE_FF }, 1062 { "lnxr", 0x61, INSTR_RRE_FF }, 1063 { "ltxr", 0x62, INSTR_RRE_FF }, 1064 { "lcxr", 0x63, INSTR_RRE_FF }, 1065 { "lxr", 0x65, INSTR_RRE_FF }, 1066 { "lexr", 0x66, INSTR_RRE_FF }, 1067 { "fixr", 0x67, INSTR_RRE_FF }, 1068 { "cxr", 0x69, INSTR_RRE_FF }, 1069 { "lzer", 0x74, INSTR_RRE_F0 }, 1070 { "lzdr", 0x75, INSTR_RRE_F0 }, 1071 { "lzxr", 0x76, INSTR_RRE_F0 }, 1072 { "fier", 0x77, INSTR_RRE_FF }, 1073 { "fidr", 0x7f, INSTR_RRE_FF }, 1074 { "sfpc", 0x84, INSTR_RRE_RR_OPT }, 1075 { "efpc", 0x8c, INSTR_RRE_RR_OPT }, 1076 { "cefbr", 0x94, INSTR_RRE_RF }, 1077 { "cdfbr", 0x95, INSTR_RRE_RF }, 1078 { "cxfbr", 0x96, INSTR_RRE_RF }, 1079 { "cfebr", 0x98, INSTR_RRF_U0RF }, 1080 { "cfdbr", 0x99, INSTR_RRF_U0RF }, 1081 { "cfxbr", 0x9a, INSTR_RRF_U0RF }, 1082 { "cefr", 0xb4, INSTR_RRE_FR }, 1083 { "cdfr", 0xb5, INSTR_RRE_FR }, 1084 { "cxfr", 0xb6, INSTR_RRE_FR }, 1085 { "cfer", 0xb8, INSTR_RRF_U0RF }, 1086 { "cfdr", 0xb9, INSTR_RRF_U0RF }, 1087 { "cfxr", 0xba, INSTR_RRF_U0RF }, 1088 { "", 0, INSTR_INVALID } 1089}; 1090 1091static struct s390_insn opcode_b9[] = { 1092#ifdef CONFIG_64BIT 1093 { "lpgr", 0x00, INSTR_RRE_RR }, 1094 { "lngr", 0x01, INSTR_RRE_RR }, 1095 { "ltgr", 0x02, INSTR_RRE_RR }, 1096 { "lcgr", 0x03, INSTR_RRE_RR }, 1097 { "lgr", 0x04, INSTR_RRE_RR }, 1098 { "lurag", 0x05, INSTR_RRE_RR }, 1099 { "lgbr", 0x06, INSTR_RRE_RR }, 1100 { "lghr", 0x07, INSTR_RRE_RR }, 1101 { "agr", 0x08, INSTR_RRE_RR }, 1102 { "sgr", 0x09, INSTR_RRE_RR }, 1103 { "algr", 0x0a, INSTR_RRE_RR }, 1104 { "slgr", 0x0b, INSTR_RRE_RR }, 1105 { "msgr", 0x0c, INSTR_RRE_RR }, 1106 { "dsgr", 0x0d, INSTR_RRE_RR }, 1107 { "eregg", 0x0e, INSTR_RRE_RR }, 1108 { "lrvgr", 0x0f, INSTR_RRE_RR }, 1109 { "lpgfr", 0x10, INSTR_RRE_RR }, 1110 { "lngfr", 0x11, INSTR_RRE_RR }, 1111 { "ltgfr", 0x12, INSTR_RRE_RR }, 1112 { "lcgfr", 0x13, INSTR_RRE_RR }, 1113 { "lgfr", 0x14, INSTR_RRE_RR }, 1114 { "llgfr", 0x16, INSTR_RRE_RR }, 1115 { "llgtr", 0x17, INSTR_RRE_RR }, 1116 { "agfr", 0x18, INSTR_RRE_RR }, 1117 { "sgfr", 0x19, INSTR_RRE_RR }, 1118 { "algfr", 0x1a, INSTR_RRE_RR }, 1119 { "slgfr", 0x1b, INSTR_RRE_RR }, 1120 { "msgfr", 0x1c, INSTR_RRE_RR }, 1121 { "dsgfr", 0x1d, INSTR_RRE_RR }, 1122 { "cgr", 0x20, INSTR_RRE_RR }, 1123 { "clgr", 0x21, INSTR_RRE_RR }, 1124 { "sturg", 0x25, INSTR_RRE_RR }, 1125 { "lbr", 0x26, INSTR_RRE_RR }, 1126 { "lhr", 0x27, INSTR_RRE_RR }, 1127 { "cgfr", 0x30, INSTR_RRE_RR }, 1128 { "clgfr", 0x31, INSTR_RRE_RR }, 1129 { "cfdtr", 0x41, INSTR_RRF_UURF }, 1130 { { 0, LONG_INSN_CLGDTR }, 0x42, INSTR_RRF_UURF }, 1131 { { 0, LONG_INSN_CLFDTR }, 0x43, INSTR_RRF_UURF }, 1132 { "bctgr", 0x46, INSTR_RRE_RR }, 1133 { "cfxtr", 0x49, INSTR_RRF_UURF }, 1134 { { 0, LONG_INSN_CLGXTR }, 0x4a, INSTR_RRF_UUFR }, 1135 { { 0, LONG_INSN_CLFXTR }, 0x4b, INSTR_RRF_UUFR }, 1136 { "cdftr", 0x51, INSTR_RRF_UUFR }, 1137 { { 0, LONG_INSN_CDLGTR }, 0x52, INSTR_RRF_UUFR }, 1138 { { 0, LONG_INSN_CDLFTR }, 0x53, INSTR_RRF_UUFR }, 1139 { "cxftr", 0x59, INSTR_RRF_UURF }, 1140 { { 0, LONG_INSN_CXLGTR }, 0x5a, INSTR_RRF_UURF }, 1141 { { 0, LONG_INSN_CXLFTR }, 0x5b, INSTR_RRF_UUFR }, 1142 { "cgrt", 0x60, INSTR_RRF_U0RR }, 1143 { "clgrt", 0x61, INSTR_RRF_U0RR }, 1144 { "crt", 0x72, INSTR_RRF_U0RR }, 1145 { "clrt", 0x73, INSTR_RRF_U0RR }, 1146 { "ngr", 0x80, INSTR_RRE_RR }, 1147 { "ogr", 0x81, INSTR_RRE_RR }, 1148 { "xgr", 0x82, INSTR_RRE_RR }, 1149 { "flogr", 0x83, INSTR_RRE_RR }, 1150 { "llgcr", 0x84, INSTR_RRE_RR }, 1151 { "llghr", 0x85, INSTR_RRE_RR }, 1152 { "mlgr", 0x86, INSTR_RRE_RR }, 1153 { "dlgr", 0x87, INSTR_RRE_RR }, 1154 { "alcgr", 0x88, INSTR_RRE_RR }, 1155 { "slbgr", 0x89, INSTR_RRE_RR }, 1156 { "cspg", 0x8a, INSTR_RRE_RR }, 1157 { "idte", 0x8e, INSTR_RRF_R0RR }, 1158 { "crdte", 0x8f, INSTR_RRF_RMRR }, 1159 { "llcr", 0x94, INSTR_RRE_RR }, 1160 { "llhr", 0x95, INSTR_RRE_RR }, 1161 { "esea", 0x9d, INSTR_RRE_R0 }, 1162 { "ptf", 0xa2, INSTR_RRE_R0 }, 1163 { "lptea", 0xaa, INSTR_RRF_RURR }, 1164 { "rrbm", 0xae, INSTR_RRE_RR }, 1165 { "pfmf", 0xaf, INSTR_RRE_RR }, 1166 { "cu14", 0xb0, INSTR_RRF_M0RR }, 1167 { "cu24", 0xb1, INSTR_RRF_M0RR }, 1168 { "cu41", 0xb2, INSTR_RRE_RR }, 1169 { "cu42", 0xb3, INSTR_RRE_RR }, 1170 { "trtre", 0xbd, INSTR_RRF_M0RR }, 1171 { "srstu", 0xbe, INSTR_RRE_RR }, 1172 { "trte", 0xbf, INSTR_RRF_M0RR }, 1173 { "ahhhr", 0xc8, INSTR_RRF_R0RR2 }, 1174 { "shhhr", 0xc9, INSTR_RRF_R0RR2 }, 1175 { { 0, LONG_INSN_ALHHHR }, 0xca, INSTR_RRF_R0RR2 }, 1176 { { 0, LONG_INSN_SLHHHR }, 0xcb, INSTR_RRF_R0RR2 }, 1177 { "chhr", 0xcd, INSTR_RRE_RR }, 1178 { "clhhr", 0xcf, INSTR_RRE_RR }, 1179 { { 0, LONG_INSN_PCISTG }, 0xd0, INSTR_RRE_RR }, 1180 { "pcilg", 0xd2, INSTR_RRE_RR }, 1181 { "rpcit", 0xd3, INSTR_RRE_RR }, 1182 { "ahhlr", 0xd8, INSTR_RRF_R0RR2 }, 1183 { "shhlr", 0xd9, INSTR_RRF_R0RR2 }, 1184 { { 0, LONG_INSN_ALHHLR }, 0xda, INSTR_RRF_R0RR2 }, 1185 { { 0, LONG_INSN_SLHHLR }, 0xdb, INSTR_RRF_R0RR2 }, 1186 { "chlr", 0xdd, INSTR_RRE_RR }, 1187 { "clhlr", 0xdf, INSTR_RRE_RR }, 1188 { { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR }, 1189 { "locgr", 0xe2, INSTR_RRF_M0RR }, 1190 { "ngrk", 0xe4, INSTR_RRF_R0RR2 }, 1191 { "ogrk", 0xe6, INSTR_RRF_R0RR2 }, 1192 { "xgrk", 0xe7, INSTR_RRF_R0RR2 }, 1193 { "agrk", 0xe8, INSTR_RRF_R0RR2 }, 1194 { "sgrk", 0xe9, INSTR_RRF_R0RR2 }, 1195 { "algrk", 0xea, INSTR_RRF_R0RR2 }, 1196 { "slgrk", 0xeb, INSTR_RRF_R0RR2 }, 1197 { "locr", 0xf2, INSTR_RRF_M0RR }, 1198 { "nrk", 0xf4, INSTR_RRF_R0RR2 }, 1199 { "ork", 0xf6, INSTR_RRF_R0RR2 }, 1200 { "xrk", 0xf7, INSTR_RRF_R0RR2 }, 1201 { "ark", 0xf8, INSTR_RRF_R0RR2 }, 1202 { "srk", 0xf9, INSTR_RRF_R0RR2 }, 1203 { "alrk", 0xfa, INSTR_RRF_R0RR2 }, 1204 { "slrk", 0xfb, INSTR_RRF_R0RR2 }, 1205#endif 1206 { "kmac", 0x1e, INSTR_RRE_RR }, 1207 { "lrvr", 0x1f, INSTR_RRE_RR }, 1208 { "km", 0x2e, INSTR_RRE_RR }, 1209 { "kmc", 0x2f, INSTR_RRE_RR }, 1210 { "kimd", 0x3e, INSTR_RRE_RR }, 1211 { "klmd", 0x3f, INSTR_RRE_RR }, 1212 { "epsw", 0x8d, INSTR_RRE_RR }, 1213 { "trtt", 0x90, INSTR_RRF_M0RR }, 1214 { "trto", 0x91, INSTR_RRF_M0RR }, 1215 { "trot", 0x92, INSTR_RRF_M0RR }, 1216 { "troo", 0x93, INSTR_RRF_M0RR }, 1217 { "mlr", 0x96, INSTR_RRE_RR }, 1218 { "dlr", 0x97, INSTR_RRE_RR }, 1219 { "alcr", 0x98, INSTR_RRE_RR }, 1220 { "slbr", 0x99, INSTR_RRE_RR }, 1221 { "", 0, INSTR_INVALID } 1222}; 1223 1224static struct s390_insn opcode_c0[] = { 1225#ifdef CONFIG_64BIT 1226 { "lgfi", 0x01, INSTR_RIL_RI }, 1227 { "xihf", 0x06, INSTR_RIL_RU }, 1228 { "xilf", 0x07, INSTR_RIL_RU }, 1229 { "iihf", 0x08, INSTR_RIL_RU }, 1230 { "iilf", 0x09, INSTR_RIL_RU }, 1231 { "nihf", 0x0a, INSTR_RIL_RU }, 1232 { "nilf", 0x0b, INSTR_RIL_RU }, 1233 { "oihf", 0x0c, INSTR_RIL_RU }, 1234 { "oilf", 0x0d, INSTR_RIL_RU }, 1235 { "llihf", 0x0e, INSTR_RIL_RU }, 1236 { "llilf", 0x0f, INSTR_RIL_RU }, 1237#endif 1238 { "larl", 0x00, INSTR_RIL_RP }, 1239 { "brcl", 0x04, INSTR_RIL_UP }, 1240 { "brasl", 0x05, INSTR_RIL_RP }, 1241 { "", 0, INSTR_INVALID } 1242}; 1243 1244static struct s390_insn opcode_c2[] = { 1245#ifdef CONFIG_64BIT 1246 { "msgfi", 0x00, INSTR_RIL_RI }, 1247 { "msfi", 0x01, INSTR_RIL_RI }, 1248 { "slgfi", 0x04, INSTR_RIL_RU }, 1249 { "slfi", 0x05, INSTR_RIL_RU }, 1250 { "agfi", 0x08, INSTR_RIL_RI }, 1251 { "afi", 0x09, INSTR_RIL_RI }, 1252 { "algfi", 0x0a, INSTR_RIL_RU }, 1253 { "alfi", 0x0b, INSTR_RIL_RU }, 1254 { "cgfi", 0x0c, INSTR_RIL_RI }, 1255 { "cfi", 0x0d, INSTR_RIL_RI }, 1256 { "clgfi", 0x0e, INSTR_RIL_RU }, 1257 { "clfi", 0x0f, INSTR_RIL_RU }, 1258#endif 1259 { "", 0, INSTR_INVALID } 1260}; 1261 1262static struct s390_insn opcode_c4[] = { 1263#ifdef CONFIG_64BIT 1264 { "llhrl", 0x02, INSTR_RIL_RP }, 1265 { "lghrl", 0x04, INSTR_RIL_RP }, 1266 { "lhrl", 0x05, INSTR_RIL_RP }, 1267 { { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP }, 1268 { "sthrl", 0x07, INSTR_RIL_RP }, 1269 { "lgrl", 0x08, INSTR_RIL_RP }, 1270 { "stgrl", 0x0b, INSTR_RIL_RP }, 1271 { "lgfrl", 0x0c, INSTR_RIL_RP }, 1272 { "lrl", 0x0d, INSTR_RIL_RP }, 1273 { { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP }, 1274 { "strl", 0x0f, INSTR_RIL_RP }, 1275#endif 1276 { "", 0, INSTR_INVALID } 1277}; 1278 1279static struct s390_insn opcode_c6[] = { 1280#ifdef CONFIG_64BIT 1281 { "exrl", 0x00, INSTR_RIL_RP }, 1282 { "pfdrl", 0x02, INSTR_RIL_UP }, 1283 { "cghrl", 0x04, INSTR_RIL_RP }, 1284 { "chrl", 0x05, INSTR_RIL_RP }, 1285 { { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP }, 1286 { "clhrl", 0x07, INSTR_RIL_RP }, 1287 { "cgrl", 0x08, INSTR_RIL_RP }, 1288 { "clgrl", 0x0a, INSTR_RIL_RP }, 1289 { "cgfrl", 0x0c, INSTR_RIL_RP }, 1290 { "crl", 0x0d, INSTR_RIL_RP }, 1291 { { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP }, 1292 { "clrl", 0x0f, INSTR_RIL_RP }, 1293#endif 1294 { "", 0, INSTR_INVALID } 1295}; 1296 1297static struct s390_insn opcode_c8[] = { 1298#ifdef CONFIG_64BIT 1299 { "mvcos", 0x00, INSTR_SSF_RRDRD }, 1300 { "ectg", 0x01, INSTR_SSF_RRDRD }, 1301 { "csst", 0x02, INSTR_SSF_RRDRD }, 1302 { "lpd", 0x04, INSTR_SSF_RRDRD2 }, 1303 { "lpdg", 0x05, INSTR_SSF_RRDRD2 }, 1304#endif 1305 { "", 0, INSTR_INVALID } 1306}; 1307 1308static struct s390_insn opcode_cc[] = { 1309#ifdef CONFIG_64BIT 1310 { "brcth", 0x06, INSTR_RIL_RP }, 1311 { "aih", 0x08, INSTR_RIL_RI }, 1312 { "alsih", 0x0a, INSTR_RIL_RI }, 1313 { { 0, LONG_INSN_ALSIHN }, 0x0b, INSTR_RIL_RI }, 1314 { "cih", 0x0d, INSTR_RIL_RI }, 1315 { "clih", 0x0f, INSTR_RIL_RI }, 1316#endif 1317 { "", 0, INSTR_INVALID } 1318}; 1319 1320static struct s390_insn opcode_e3[] = { 1321#ifdef CONFIG_64BIT 1322 { "ltg", 0x02, INSTR_RXY_RRRD }, 1323 { "lrag", 0x03, INSTR_RXY_RRRD }, 1324 { "lg", 0x04, INSTR_RXY_RRRD }, 1325 { "cvby", 0x06, INSTR_RXY_RRRD }, 1326 { "ag", 0x08, INSTR_RXY_RRRD }, 1327 { "sg", 0x09, INSTR_RXY_RRRD }, 1328 { "alg", 0x0a, INSTR_RXY_RRRD }, 1329 { "slg", 0x0b, INSTR_RXY_RRRD }, 1330 { "msg", 0x0c, INSTR_RXY_RRRD }, 1331 { "dsg", 0x0d, INSTR_RXY_RRRD }, 1332 { "cvbg", 0x0e, INSTR_RXY_RRRD }, 1333 { "lrvg", 0x0f, INSTR_RXY_RRRD }, 1334 { "lt", 0x12, INSTR_RXY_RRRD }, 1335 { "lray", 0x13, INSTR_RXY_RRRD }, 1336 { "lgf", 0x14, INSTR_RXY_RRRD }, 1337 { "lgh", 0x15, INSTR_RXY_RRRD }, 1338 { "llgf", 0x16, INSTR_RXY_RRRD }, 1339 { "llgt", 0x17, INSTR_RXY_RRRD }, 1340 { "agf", 0x18, INSTR_RXY_RRRD }, 1341 { "sgf", 0x19, INSTR_RXY_RRRD }, 1342 { "algf", 0x1a, INSTR_RXY_RRRD }, 1343 { "slgf", 0x1b, INSTR_RXY_RRRD }, 1344 { "msgf", 0x1c, INSTR_RXY_RRRD }, 1345 { "dsgf", 0x1d, INSTR_RXY_RRRD }, 1346 { "cg", 0x20, INSTR_RXY_RRRD }, 1347 { "clg", 0x21, INSTR_RXY_RRRD }, 1348 { "stg", 0x24, INSTR_RXY_RRRD }, 1349 { "ntstg", 0x25, INSTR_RXY_RRRD }, 1350 { "cvdy", 0x26, INSTR_RXY_RRRD }, 1351 { "cvdg", 0x2e, INSTR_RXY_RRRD }, 1352 { "strvg", 0x2f, INSTR_RXY_RRRD }, 1353 { "cgf", 0x30, INSTR_RXY_RRRD }, 1354 { "clgf", 0x31, INSTR_RXY_RRRD }, 1355 { "ltgf", 0x32, INSTR_RXY_RRRD }, 1356 { "cgh", 0x34, INSTR_RXY_RRRD }, 1357 { "pfd", 0x36, INSTR_RXY_URRD }, 1358 { "strvh", 0x3f, INSTR_RXY_RRRD }, 1359 { "bctg", 0x46, INSTR_RXY_RRRD }, 1360 { "sty", 0x50, INSTR_RXY_RRRD }, 1361 { "msy", 0x51, INSTR_RXY_RRRD }, 1362 { "ny", 0x54, INSTR_RXY_RRRD }, 1363 { "cly", 0x55, INSTR_RXY_RRRD }, 1364 { "oy", 0x56, INSTR_RXY_RRRD }, 1365 { "xy", 0x57, INSTR_RXY_RRRD }, 1366 { "ly", 0x58, INSTR_RXY_RRRD }, 1367 { "cy", 0x59, INSTR_RXY_RRRD }, 1368 { "ay", 0x5a, INSTR_RXY_RRRD }, 1369 { "sy", 0x5b, INSTR_RXY_RRRD }, 1370 { "mfy", 0x5c, INSTR_RXY_RRRD }, 1371 { "aly", 0x5e, INSTR_RXY_RRRD }, 1372 { "sly", 0x5f, INSTR_RXY_RRRD }, 1373 { "sthy", 0x70, INSTR_RXY_RRRD }, 1374 { "lay", 0x71, INSTR_RXY_RRRD }, 1375 { "stcy", 0x72, INSTR_RXY_RRRD }, 1376 { "icy", 0x73, INSTR_RXY_RRRD }, 1377 { "laey", 0x75, INSTR_RXY_RRRD }, 1378 { "lb", 0x76, INSTR_RXY_RRRD }, 1379 { "lgb", 0x77, INSTR_RXY_RRRD }, 1380 { "lhy", 0x78, INSTR_RXY_RRRD }, 1381 { "chy", 0x79, INSTR_RXY_RRRD }, 1382 { "ahy", 0x7a, INSTR_RXY_RRRD }, 1383 { "shy", 0x7b, INSTR_RXY_RRRD }, 1384 { "mhy", 0x7c, INSTR_RXY_RRRD }, 1385 { "ng", 0x80, INSTR_RXY_RRRD }, 1386 { "og", 0x81, INSTR_RXY_RRRD }, 1387 { "xg", 0x82, INSTR_RXY_RRRD }, 1388 { "lgat", 0x85, INSTR_RXY_RRRD }, 1389 { "mlg", 0x86, INSTR_RXY_RRRD }, 1390 { "dlg", 0x87, INSTR_RXY_RRRD }, 1391 { "alcg", 0x88, INSTR_RXY_RRRD }, 1392 { "slbg", 0x89, INSTR_RXY_RRRD }, 1393 { "stpq", 0x8e, INSTR_RXY_RRRD }, 1394 { "lpq", 0x8f, INSTR_RXY_RRRD }, 1395 { "llgc", 0x90, INSTR_RXY_RRRD }, 1396 { "llgh", 0x91, INSTR_RXY_RRRD }, 1397 { "llc", 0x94, INSTR_RXY_RRRD }, 1398 { "llh", 0x95, INSTR_RXY_RRRD }, 1399 { { 0, LONG_INSN_LLGTAT }, 0x9c, INSTR_RXY_RRRD }, 1400 { { 0, LONG_INSN_LLGFAT }, 0x9d, INSTR_RXY_RRRD }, 1401 { "lat", 0x9f, INSTR_RXY_RRRD }, 1402 { "lbh", 0xc0, INSTR_RXY_RRRD }, 1403 { "llch", 0xc2, INSTR_RXY_RRRD }, 1404 { "stch", 0xc3, INSTR_RXY_RRRD }, 1405 { "lhh", 0xc4, INSTR_RXY_RRRD }, 1406 { "llhh", 0xc6, INSTR_RXY_RRRD }, 1407 { "sthh", 0xc7, INSTR_RXY_RRRD }, 1408 { "lfhat", 0xc8, INSTR_RXY_RRRD }, 1409 { "lfh", 0xca, INSTR_RXY_RRRD }, 1410 { "stfh", 0xcb, INSTR_RXY_RRRD }, 1411 { "chf", 0xcd, INSTR_RXY_RRRD }, 1412 { "clhf", 0xcf, INSTR_RXY_RRRD }, 1413 { { 0, LONG_INSN_MPCIFC }, 0xd0, INSTR_RXY_RRRD }, 1414 { { 0, LONG_INSN_STPCIFC }, 0xd4, INSTR_RXY_RRRD }, 1415#endif 1416 { "lrv", 0x1e, INSTR_RXY_RRRD }, 1417 { "lrvh", 0x1f, INSTR_RXY_RRRD }, 1418 { "strv", 0x3e, INSTR_RXY_RRRD }, 1419 { "ml", 0x96, INSTR_RXY_RRRD }, 1420 { "dl", 0x97, INSTR_RXY_RRRD }, 1421 { "alc", 0x98, INSTR_RXY_RRRD }, 1422 { "slb", 0x99, INSTR_RXY_RRRD }, 1423 { "", 0, INSTR_INVALID } 1424}; 1425 1426static struct s390_insn opcode_e5[] = { 1427#ifdef CONFIG_64BIT 1428 { "strag", 0x02, INSTR_SSE_RDRD }, 1429 { "mvhhi", 0x44, INSTR_SIL_RDI }, 1430 { "mvghi", 0x48, INSTR_SIL_RDI }, 1431 { "mvhi", 0x4c, INSTR_SIL_RDI }, 1432 { "chhsi", 0x54, INSTR_SIL_RDI }, 1433 { { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU }, 1434 { "cghsi", 0x58, INSTR_SIL_RDI }, 1435 { { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU }, 1436 { "chsi", 0x5c, INSTR_SIL_RDI }, 1437 { { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU }, 1438 { { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU }, 1439 { { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU }, 1440#endif 1441 { "lasp", 0x00, INSTR_SSE_RDRD }, 1442 { "tprot", 0x01, INSTR_SSE_RDRD }, 1443 { "mvcsk", 0x0e, INSTR_SSE_RDRD }, 1444 { "mvcdk", 0x0f, INSTR_SSE_RDRD }, 1445 { "", 0, INSTR_INVALID } 1446}; 1447 1448static struct s390_insn opcode_e7[] = { 1449#ifdef CONFIG_64BIT 1450 { "lcbb", 0x27, INSTR_RXE_RRRDM }, 1451 { "vgef", 0x13, INSTR_VRV_VVRDM }, 1452 { "vgeg", 0x12, INSTR_VRV_VVRDM }, 1453 { "vgbm", 0x44, INSTR_VRI_V0I0 }, 1454 { "vgm", 0x46, INSTR_VRI_V0IIM }, 1455 { "vl", 0x06, INSTR_VRX_VRRD0 }, 1456 { "vlr", 0x56, INSTR_VRR_VV00000 }, 1457 { "vlrp", 0x05, INSTR_VRX_VRRDM }, 1458 { "vleb", 0x00, INSTR_VRX_VRRDM }, 1459 { "vleh", 0x01, INSTR_VRX_VRRDM }, 1460 { "vlef", 0x03, INSTR_VRX_VRRDM }, 1461 { "vleg", 0x02, INSTR_VRX_VRRDM }, 1462 { "vleib", 0x40, INSTR_VRI_V0IM }, 1463 { "vleih", 0x41, INSTR_VRI_V0IM }, 1464 { "vleif", 0x43, INSTR_VRI_V0IM }, 1465 { "vleig", 0x42, INSTR_VRI_V0IM }, 1466 { "vlgv", 0x21, INSTR_VRS_RVRDM }, 1467 { "vllez", 0x04, INSTR_VRX_VRRDM }, 1468 { "vlm", 0x36, INSTR_VRS_VVRD0 }, 1469 { "vlbb", 0x07, INSTR_VRX_VRRDM }, 1470 { "vlvg", 0x22, INSTR_VRS_VRRDM }, 1471 { "vlvgp", 0x62, INSTR_VRR_VRR0000 }, 1472 { "vll", 0x37, INSTR_VRS_VRRD0 }, 1473 { "vmrh", 0x61, INSTR_VRR_VVV000M }, 1474 { "vmrl", 0x60, INSTR_VRR_VVV000M }, 1475 { "vpk", 0x94, INSTR_VRR_VVV000M }, 1476 { "vpks", 0x97, INSTR_VRR_VVV0M0M }, 1477 { "vpkls", 0x95, INSTR_VRR_VVV0M0M }, 1478 { "vperm", 0x8c, INSTR_VRR_VVV000V }, 1479 { "vpdi", 0x84, INSTR_VRR_VVV000M }, 1480 { "vrep", 0x4d, INSTR_VRI_VVIM }, 1481 { "vrepi", 0x45, INSTR_VRI_V0IM }, 1482 { "vscef", 0x1b, INSTR_VRV_VWRDM }, 1483 { "vsceg", 0x1a, INSTR_VRV_VWRDM }, 1484 { "vsel", 0x8d, INSTR_VRR_VVV000V }, 1485 { "vseg", 0x5f, INSTR_VRR_VV0000M }, 1486 { "vst", 0x0e, INSTR_VRX_VRRD0 }, 1487 { "vsteb", 0x08, INSTR_VRX_VRRDM }, 1488 { "vsteh", 0x09, INSTR_VRX_VRRDM }, 1489 { "vstef", 0x0b, INSTR_VRX_VRRDM }, 1490 { "vsteg", 0x0a, INSTR_VRX_VRRDM }, 1491 { "vstm", 0x3e, INSTR_VRS_VVRD0 }, 1492 { "vstl", 0x3f, INSTR_VRS_VRRD0 }, 1493 { "vuph", 0xd7, INSTR_VRR_VV0000M }, 1494 { "vuplh", 0xd5, INSTR_VRR_VV0000M }, 1495 { "vupl", 0xd6, INSTR_VRR_VV0000M }, 1496 { "vupll", 0xd4, INSTR_VRR_VV0000M }, 1497 { "va", 0xf3, INSTR_VRR_VVV000M }, 1498 { "vacc", 0xf1, INSTR_VRR_VVV000M }, 1499 { "vac", 0xbb, INSTR_VRR_VVVM00V }, 1500 { "vaccc", 0xb9, INSTR_VRR_VVVM00V }, 1501 { "vn", 0x68, INSTR_VRR_VVV0000 }, 1502 { "vnc", 0x69, INSTR_VRR_VVV0000 }, 1503 { "vavg", 0xf2, INSTR_VRR_VVV000M }, 1504 { "vavgl", 0xf0, INSTR_VRR_VVV000M }, 1505 { "vcksm", 0x66, INSTR_VRR_VVV0000 }, 1506 { "vec", 0xdb, INSTR_VRR_VV0000M }, 1507 { "vecl", 0xd9, INSTR_VRR_VV0000M }, 1508 { "vceq", 0xf8, INSTR_VRR_VVV0M0M }, 1509 { "vch", 0xfb, INSTR_VRR_VVV0M0M }, 1510 { "vchl", 0xf9, INSTR_VRR_VVV0M0M }, 1511 { "vclz", 0x53, INSTR_VRR_VV0000M }, 1512 { "vctz", 0x52, INSTR_VRR_VV0000M }, 1513 { "vx", 0x6d, INSTR_VRR_VVV0000 }, 1514 { "vgfm", 0xb4, INSTR_VRR_VVV000M }, 1515 { "vgfma", 0xbc, INSTR_VRR_VVVM00V }, 1516 { "vlc", 0xde, INSTR_VRR_VV0000M }, 1517 { "vlp", 0xdf, INSTR_VRR_VV0000M }, 1518 { "vmx", 0xff, INSTR_VRR_VVV000M }, 1519 { "vmxl", 0xfd, INSTR_VRR_VVV000M }, 1520 { "vmn", 0xfe, INSTR_VRR_VVV000M }, 1521 { "vmnl", 0xfc, INSTR_VRR_VVV000M }, 1522 { "vmal", 0xaa, INSTR_VRR_VVVM00V }, 1523 { "vmae", 0xae, INSTR_VRR_VVVM00V }, 1524 { "vmale", 0xac, INSTR_VRR_VVVM00V }, 1525 { "vmah", 0xab, INSTR_VRR_VVVM00V }, 1526 { "vmalh", 0xa9, INSTR_VRR_VVVM00V }, 1527 { "vmao", 0xaf, INSTR_VRR_VVVM00V }, 1528 { "vmalo", 0xad, INSTR_VRR_VVVM00V }, 1529 { "vmh", 0xa3, INSTR_VRR_VVV000M }, 1530 { "vmlh", 0xa1, INSTR_VRR_VVV000M }, 1531 { "vml", 0xa2, INSTR_VRR_VVV000M }, 1532 { "vme", 0xa6, INSTR_VRR_VVV000M }, 1533 { "vmle", 0xa4, INSTR_VRR_VVV000M }, 1534 { "vmo", 0xa7, INSTR_VRR_VVV000M }, 1535 { "vmlo", 0xa5, INSTR_VRR_VVV000M }, 1536 { "vno", 0x6b, INSTR_VRR_VVV0000 }, 1537 { "vo", 0x6a, INSTR_VRR_VVV0000 }, 1538 { { 0, LONG_INSN_VPOPCT }, 0x50, INSTR_VRR_VV0000M }, 1539 { { 0, LONG_INSN_VERLLV }, 0x73, INSTR_VRR_VVV000M }, 1540 { "verll", 0x33, INSTR_VRS_VVRDM }, 1541 { "verim", 0x72, INSTR_VRI_VVV0IM }, 1542 { "veslv", 0x70, INSTR_VRR_VVV000M }, 1543 { "vesl", 0x30, INSTR_VRS_VVRDM }, 1544 { { 0, LONG_INSN_VESRAV }, 0x7a, INSTR_VRR_VVV000M }, 1545 { "vesra", 0x3a, INSTR_VRS_VVRDM }, 1546 { { 0, LONG_INSN_VESRLV }, 0x78, INSTR_VRR_VVV000M }, 1547 { "vesrl", 0x38, INSTR_VRS_VVRDM }, 1548 { "vsl", 0x74, INSTR_VRR_VVV0000 }, 1549 { "vslb", 0x75, INSTR_VRR_VVV0000 }, 1550 { "vsldb", 0x77, INSTR_VRI_VVV0I0 }, 1551 { "vsra", 0x7e, INSTR_VRR_VVV0000 }, 1552 { "vsrab", 0x7f, INSTR_VRR_VVV0000 }, 1553 { "vsrl", 0x7c, INSTR_VRR_VVV0000 }, 1554 { "vsrlb", 0x7d, INSTR_VRR_VVV0000 }, 1555 { "vs", 0xf7, INSTR_VRR_VVV000M }, 1556 { "vscb", 0xf5, INSTR_VRR_VVV000M }, 1557 { "vsb", 0xbf, INSTR_VRR_VVVM00V }, 1558 { { 0, LONG_INSN_VSBCBI }, 0xbd, INSTR_VRR_VVVM00V }, 1559 { "vsumg", 0x65, INSTR_VRR_VVV000M }, 1560 { "vsumq", 0x67, INSTR_VRR_VVV000M }, 1561 { "vsum", 0x64, INSTR_VRR_VVV000M }, 1562 { "vtm", 0xd8, INSTR_VRR_VV00000 }, 1563 { "vfae", 0x82, INSTR_VRR_VVV0M0M }, 1564 { "vfee", 0x80, INSTR_VRR_VVV0M0M }, 1565 { "vfene", 0x81, INSTR_VRR_VVV0M0M }, 1566 { "vistr", 0x5c, INSTR_VRR_VV00M0M }, 1567 { "vstrc", 0x8a, INSTR_VRR_VVVMM0V }, 1568 { "vfa", 0xe3, INSTR_VRR_VVV00MM }, 1569 { "wfc", 0xcb, INSTR_VRR_VV000MM }, 1570 { "wfk", 0xca, INSTR_VRR_VV000MM }, 1571 { "vfce", 0xe8, INSTR_VRR_VVV0MMM }, 1572 { "vfch", 0xeb, INSTR_VRR_VVV0MMM }, 1573 { "vfche", 0xea, INSTR_VRR_VVV0MMM }, 1574 { "vcdg", 0xc3, INSTR_VRR_VV00MMM }, 1575 { "vcdlg", 0xc1, INSTR_VRR_VV00MMM }, 1576 { "vcgd", 0xc2, INSTR_VRR_VV00MMM }, 1577 { "vclgd", 0xc0, INSTR_VRR_VV00MMM }, 1578 { "vfd", 0xe5, INSTR_VRR_VVV00MM }, 1579 { "vfi", 0xc7, INSTR_VRR_VV00MMM }, 1580 { "vlde", 0xc4, INSTR_VRR_VV000MM }, 1581 { "vled", 0xc5, INSTR_VRR_VV00MMM }, 1582 { "vfm", 0xe7, INSTR_VRR_VVV00MM }, 1583 { "vfma", 0x8f, INSTR_VRR_VVVM0MV }, 1584 { "vfms", 0x8e, INSTR_VRR_VVVM0MV }, 1585 { "vfpso", 0xcc, INSTR_VRR_VV00MMM }, 1586 { "vfsq", 0xce, INSTR_VRR_VV000MM }, 1587 { "vfs", 0xe2, INSTR_VRR_VVV00MM }, 1588 { "vftci", 0x4a, INSTR_VRI_VVIMM }, 1589#endif 1590}; 1591 1592static struct s390_insn opcode_eb[] = { 1593#ifdef CONFIG_64BIT 1594 { "lmg", 0x04, INSTR_RSY_RRRD }, 1595 { "srag", 0x0a, INSTR_RSY_RRRD }, 1596 { "slag", 0x0b, INSTR_RSY_RRRD }, 1597 { "srlg", 0x0c, INSTR_RSY_RRRD }, 1598 { "sllg", 0x0d, INSTR_RSY_RRRD }, 1599 { "tracg", 0x0f, INSTR_RSY_RRRD }, 1600 { "csy", 0x14, INSTR_RSY_RRRD }, 1601 { "rllg", 0x1c, INSTR_RSY_RRRD }, 1602 { "clmh", 0x20, INSTR_RSY_RURD }, 1603 { "clmy", 0x21, INSTR_RSY_RURD }, 1604 { "clt", 0x23, INSTR_RSY_RURD }, 1605 { "stmg", 0x24, INSTR_RSY_RRRD }, 1606 { "stctg", 0x25, INSTR_RSY_CCRD }, 1607 { "stmh", 0x26, INSTR_RSY_RRRD }, 1608 { "clgt", 0x2b, INSTR_RSY_RURD }, 1609 { "stcmh", 0x2c, INSTR_RSY_RURD }, 1610 { "stcmy", 0x2d, INSTR_RSY_RURD }, 1611 { "lctlg", 0x2f, INSTR_RSY_CCRD }, 1612 { "csg", 0x30, INSTR_RSY_RRRD }, 1613 { "cdsy", 0x31, INSTR_RSY_RRRD }, 1614 { "cdsg", 0x3e, INSTR_RSY_RRRD }, 1615 { "bxhg", 0x44, INSTR_RSY_RRRD }, 1616 { "bxleg", 0x45, INSTR_RSY_RRRD }, 1617 { "ecag", 0x4c, INSTR_RSY_RRRD }, 1618 { "tmy", 0x51, INSTR_SIY_URD }, 1619 { "mviy", 0x52, INSTR_SIY_URD }, 1620 { "niy", 0x54, INSTR_SIY_URD }, 1621 { "cliy", 0x55, INSTR_SIY_URD }, 1622 { "oiy", 0x56, INSTR_SIY_URD }, 1623 { "xiy", 0x57, INSTR_SIY_URD }, 1624 { "asi", 0x6a, INSTR_SIY_IRD }, 1625 { "alsi", 0x6e, INSTR_SIY_IRD }, 1626 { "agsi", 0x7a, INSTR_SIY_IRD }, 1627 { "algsi", 0x7e, INSTR_SIY_IRD }, 1628 { "icmh", 0x80, INSTR_RSY_RURD }, 1629 { "icmy", 0x81, INSTR_RSY_RURD }, 1630 { "clclu", 0x8f, INSTR_RSY_RRRD }, 1631 { "stmy", 0x90, INSTR_RSY_RRRD }, 1632 { "lmh", 0x96, INSTR_RSY_RRRD }, 1633 { "lmy", 0x98, INSTR_RSY_RRRD }, 1634 { "lamy", 0x9a, INSTR_RSY_AARD }, 1635 { "stamy", 0x9b, INSTR_RSY_AARD }, 1636 { { 0, LONG_INSN_PCISTB }, 0xd0, INSTR_RSY_RRRD }, 1637 { "sic", 0xd1, INSTR_RSY_RRRD }, 1638 { "srak", 0xdc, INSTR_RSY_RRRD }, 1639 { "slak", 0xdd, INSTR_RSY_RRRD }, 1640 { "srlk", 0xde, INSTR_RSY_RRRD }, 1641 { "sllk", 0xdf, INSTR_RSY_RRRD }, 1642 { "locg", 0xe2, INSTR_RSY_RDRM }, 1643 { "stocg", 0xe3, INSTR_RSY_RDRM }, 1644 { "lang", 0xe4, INSTR_RSY_RRRD }, 1645 { "laog", 0xe6, INSTR_RSY_RRRD }, 1646 { "laxg", 0xe7, INSTR_RSY_RRRD }, 1647 { "laag", 0xe8, INSTR_RSY_RRRD }, 1648 { "laalg", 0xea, INSTR_RSY_RRRD }, 1649 { "loc", 0xf2, INSTR_RSY_RDRM }, 1650 { "stoc", 0xf3, INSTR_RSY_RDRM }, 1651 { "lan", 0xf4, INSTR_RSY_RRRD }, 1652 { "lao", 0xf6, INSTR_RSY_RRRD }, 1653 { "lax", 0xf7, INSTR_RSY_RRRD }, 1654 { "laa", 0xf8, INSTR_RSY_RRRD }, 1655 { "laal", 0xfa, INSTR_RSY_RRRD }, 1656 { "lric", 0x60, INSTR_RSY_RDRM }, 1657 { "stric", 0x61, INSTR_RSY_RDRM }, 1658 { "mric", 0x62, INSTR_RSY_RDRM }, 1659#endif 1660 { "rll", 0x1d, INSTR_RSY_RRRD }, 1661 { "mvclu", 0x8e, INSTR_RSY_RRRD }, 1662 { "tp", 0xc0, INSTR_RSL_R0RD }, 1663 { "", 0, INSTR_INVALID } 1664}; 1665 1666static struct s390_insn opcode_ec[] = { 1667#ifdef CONFIG_64BIT 1668 { "brxhg", 0x44, INSTR_RIE_RRP }, 1669 { "brxlg", 0x45, INSTR_RIE_RRP }, 1670 { { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU }, 1671 { "rnsbg", 0x54, INSTR_RIE_RRUUU }, 1672 { "risbg", 0x55, INSTR_RIE_RRUUU }, 1673 { "rosbg", 0x56, INSTR_RIE_RRUUU }, 1674 { "rxsbg", 0x57, INSTR_RIE_RRUUU }, 1675 { { 0, LONG_INSN_RISBGN }, 0x59, INSTR_RIE_RRUUU }, 1676 { { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU }, 1677 { "cgrj", 0x64, INSTR_RIE_RRPU }, 1678 { "clgrj", 0x65, INSTR_RIE_RRPU }, 1679 { "cgit", 0x70, INSTR_RIE_R0IU }, 1680 { "clgit", 0x71, INSTR_RIE_R0UU }, 1681 { "cit", 0x72, INSTR_RIE_R0IU }, 1682 { "clfit", 0x73, INSTR_RIE_R0UU }, 1683 { "crj", 0x76, INSTR_RIE_RRPU }, 1684 { "clrj", 0x77, INSTR_RIE_RRPU }, 1685 { "cgij", 0x7c, INSTR_RIE_RUPI }, 1686 { "clgij", 0x7d, INSTR_RIE_RUPU }, 1687 { "cij", 0x7e, INSTR_RIE_RUPI }, 1688 { "clij", 0x7f, INSTR_RIE_RUPU }, 1689 { "ahik", 0xd8, INSTR_RIE_RRI0 }, 1690 { "aghik", 0xd9, INSTR_RIE_RRI0 }, 1691 { { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 }, 1692 { { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 }, 1693 { "cgrb", 0xe4, INSTR_RRS_RRRDU }, 1694 { "clgrb", 0xe5, INSTR_RRS_RRRDU }, 1695 { "crb", 0xf6, INSTR_RRS_RRRDU }, 1696 { "clrb", 0xf7, INSTR_RRS_RRRDU }, 1697 { "cgib", 0xfc, INSTR_RIS_RURDI }, 1698 { "clgib", 0xfd, INSTR_RIS_RURDU }, 1699 { "cib", 0xfe, INSTR_RIS_RURDI }, 1700 { "clib", 0xff, INSTR_RIS_RURDU }, 1701#endif 1702 { "", 0, INSTR_INVALID } 1703}; 1704 1705static struct s390_insn opcode_ed[] = { 1706#ifdef CONFIG_64BIT 1707 { "mayl", 0x38, INSTR_RXF_FRRDF }, 1708 { "myl", 0x39, INSTR_RXF_FRRDF }, 1709 { "may", 0x3a, INSTR_RXF_FRRDF }, 1710 { "my", 0x3b, INSTR_RXF_FRRDF }, 1711 { "mayh", 0x3c, INSTR_RXF_FRRDF }, 1712 { "myh", 0x3d, INSTR_RXF_FRRDF }, 1713 { "sldt", 0x40, INSTR_RXF_FRRDF }, 1714 { "srdt", 0x41, INSTR_RXF_FRRDF }, 1715 { "slxt", 0x48, INSTR_RXF_FRRDF }, 1716 { "srxt", 0x49, INSTR_RXF_FRRDF }, 1717 { "tdcet", 0x50, INSTR_RXE_FRRD }, 1718 { "tdget", 0x51, INSTR_RXE_FRRD }, 1719 { "tdcdt", 0x54, INSTR_RXE_FRRD }, 1720 { "tdgdt", 0x55, INSTR_RXE_FRRD }, 1721 { "tdcxt", 0x58, INSTR_RXE_FRRD }, 1722 { "tdgxt", 0x59, INSTR_RXE_FRRD }, 1723 { "ley", 0x64, INSTR_RXY_FRRD }, 1724 { "ldy", 0x65, INSTR_RXY_FRRD }, 1725 { "stey", 0x66, INSTR_RXY_FRRD }, 1726 { "stdy", 0x67, INSTR_RXY_FRRD }, 1727 { "czdt", 0xa8, INSTR_RSL_LRDFU }, 1728 { "czxt", 0xa9, INSTR_RSL_LRDFU }, 1729 { "cdzt", 0xaa, INSTR_RSL_LRDFU }, 1730 { "cxzt", 0xab, INSTR_RSL_LRDFU }, 1731#endif 1732 { "ldeb", 0x04, INSTR_RXE_FRRD }, 1733 { "lxdb", 0x05, INSTR_RXE_FRRD }, 1734 { "lxeb", 0x06, INSTR_RXE_FRRD }, 1735 { "mxdb", 0x07, INSTR_RXE_FRRD }, 1736 { "keb", 0x08, INSTR_RXE_FRRD }, 1737 { "ceb", 0x09, INSTR_RXE_FRRD }, 1738 { "aeb", 0x0a, INSTR_RXE_FRRD }, 1739 { "seb", 0x0b, INSTR_RXE_FRRD }, 1740 { "mdeb", 0x0c, INSTR_RXE_FRRD }, 1741 { "deb", 0x0d, INSTR_RXE_FRRD }, 1742 { "maeb", 0x0e, INSTR_RXF_FRRDF }, 1743 { "mseb", 0x0f, INSTR_RXF_FRRDF }, 1744 { "tceb", 0x10, INSTR_RXE_FRRD }, 1745 { "tcdb", 0x11, INSTR_RXE_FRRD }, 1746 { "tcxb", 0x12, INSTR_RXE_FRRD }, 1747 { "sqeb", 0x14, INSTR_RXE_FRRD }, 1748 { "sqdb", 0x15, INSTR_RXE_FRRD }, 1749 { "meeb", 0x17, INSTR_RXE_FRRD }, 1750 { "kdb", 0x18, INSTR_RXE_FRRD }, 1751 { "cdb", 0x19, INSTR_RXE_FRRD }, 1752 { "adb", 0x1a, INSTR_RXE_FRRD }, 1753 { "sdb", 0x1b, INSTR_RXE_FRRD }, 1754 { "mdb", 0x1c, INSTR_RXE_FRRD }, 1755 { "ddb", 0x1d, INSTR_RXE_FRRD }, 1756 { "madb", 0x1e, INSTR_RXF_FRRDF }, 1757 { "msdb", 0x1f, INSTR_RXF_FRRDF }, 1758 { "lde", 0x24, INSTR_RXE_FRRD }, 1759 { "lxd", 0x25, INSTR_RXE_FRRD }, 1760 { "lxe", 0x26, INSTR_RXE_FRRD }, 1761 { "mae", 0x2e, INSTR_RXF_FRRDF }, 1762 { "mse", 0x2f, INSTR_RXF_FRRDF }, 1763 { "sqe", 0x34, INSTR_RXE_FRRD }, 1764 { "sqd", 0x35, INSTR_RXE_FRRD }, 1765 { "mee", 0x37, INSTR_RXE_FRRD }, 1766 { "mad", 0x3e, INSTR_RXF_FRRDF }, 1767 { "msd", 0x3f, INSTR_RXF_FRRDF }, 1768 { "", 0, INSTR_INVALID } 1769}; 1770 1771/* Extracts an operand value from an instruction. */ 1772static unsigned int extract_operand(unsigned char *code, 1773 const struct s390_operand *operand) 1774{ 1775 unsigned char *cp; 1776 unsigned int val; 1777 int bits; 1778 1779 /* Extract fragments of the operand byte for byte. */ 1780 cp = code + operand->shift / 8; 1781 bits = (operand->shift & 7) + operand->bits; 1782 val = 0; 1783 do { 1784 val <<= 8; 1785 val |= (unsigned int) *cp++; 1786 bits -= 8; 1787 } while (bits > 0); 1788 val >>= -bits; 1789 val &= ((1U << (operand->bits - 1)) << 1) - 1; 1790 1791 /* Check for special long displacement case. */ 1792 if (operand->bits == 20 && operand->shift == 20) 1793 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; 1794 1795 /* Check for register extensions bits for vector registers. */ 1796 if (operand->flags & OPERAND_VR) { 1797 if (operand->shift == 8) 1798 val |= (code[4] & 8) << 1; 1799 else if (operand->shift == 12) 1800 val |= (code[4] & 4) << 2; 1801 else if (operand->shift == 16) 1802 val |= (code[4] & 2) << 3; 1803 else if (operand->shift == 32) 1804 val |= (code[4] & 1) << 4; 1805 } 1806 1807 /* Sign extend value if the operand is signed or pc relative. */ 1808 if ((operand->flags & (OPERAND_SIGNED | OPERAND_PCREL)) && 1809 (val & (1U << (operand->bits - 1)))) 1810 val |= (-1U << (operand->bits - 1)) << 1; 1811 1812 /* Double value if the operand is pc relative. */ 1813 if (operand->flags & OPERAND_PCREL) 1814 val <<= 1; 1815 1816 /* Length x in an instructions has real length x + 1. */ 1817 if (operand->flags & OPERAND_LENGTH) 1818 val++; 1819 return val; 1820} 1821 1822struct s390_insn *find_insn(unsigned char *code) 1823{ 1824 unsigned char opfrag = code[1]; 1825 unsigned char opmask; 1826 struct s390_insn *table; 1827 1828 switch (code[0]) { 1829 case 0x01: 1830 table = opcode_01; 1831 break; 1832 case 0xa5: 1833 table = opcode_a5; 1834 break; 1835 case 0xa7: 1836 table = opcode_a7; 1837 break; 1838 case 0xaa: 1839 table = opcode_aa; 1840 break; 1841 case 0xb2: 1842 table = opcode_b2; 1843 break; 1844 case 0xb3: 1845 table = opcode_b3; 1846 break; 1847 case 0xb9: 1848 table = opcode_b9; 1849 break; 1850 case 0xc0: 1851 table = opcode_c0; 1852 break; 1853 case 0xc2: 1854 table = opcode_c2; 1855 break; 1856 case 0xc4: 1857 table = opcode_c4; 1858 break; 1859 case 0xc6: 1860 table = opcode_c6; 1861 break; 1862 case 0xc8: 1863 table = opcode_c8; 1864 break; 1865 case 0xcc: 1866 table = opcode_cc; 1867 break; 1868 case 0xe3: 1869 table = opcode_e3; 1870 opfrag = code[5]; 1871 break; 1872 case 0xe5: 1873 table = opcode_e5; 1874 break; 1875 case 0xe7: 1876 table = opcode_e7; 1877 opfrag = code[5]; 1878 break; 1879 case 0xeb: 1880 table = opcode_eb; 1881 opfrag = code[5]; 1882 break; 1883 case 0xec: 1884 table = opcode_ec; 1885 opfrag = code[5]; 1886 break; 1887 case 0xed: 1888 table = opcode_ed; 1889 opfrag = code[5]; 1890 break; 1891 default: 1892 table = opcode; 1893 opfrag = code[0]; 1894 break; 1895 } 1896 while (table->format != INSTR_INVALID) { 1897 opmask = formats[table->format][0]; 1898 if (table->opfrag == (opfrag & opmask)) 1899 return table; 1900 table++; 1901 } 1902 return NULL; 1903} 1904 1905/** 1906 * insn_to_mnemonic - decode an s390 instruction 1907 * @instruction: instruction to decode 1908 * @buf: buffer to fill with mnemonic 1909 * @len: length of buffer 1910 * 1911 * Decode the instruction at @instruction and store the corresponding 1912 * mnemonic into @buf of length @len. 1913 * @buf is left unchanged if the instruction could not be decoded. 1914 * Returns: 1915 * %0 on success, %-ENOENT if the instruction was not found. 1916 */ 1917int insn_to_mnemonic(unsigned char *instruction, char *buf, unsigned int len) 1918{ 1919 struct s390_insn *insn; 1920 1921 insn = find_insn(instruction); 1922 if (!insn) 1923 return -ENOENT; 1924 if (insn->name[0] == '\0') 1925 snprintf(buf, len, "%s", 1926 long_insn_name[(int) insn->name[1]]); 1927 else 1928 snprintf(buf, len, "%.5s", insn->name); 1929 return 0; 1930} 1931EXPORT_SYMBOL_GPL(insn_to_mnemonic); 1932 1933static int print_insn(char *buffer, unsigned char *code, unsigned long addr) 1934{ 1935 struct s390_insn *insn; 1936 const unsigned char *ops; 1937 const struct s390_operand *operand; 1938 unsigned int value; 1939 char separator; 1940 char *ptr; 1941 int i; 1942 1943 ptr = buffer; 1944 insn = find_insn(code); 1945 if (insn) { 1946 if (insn->name[0] == '\0') 1947 ptr += sprintf(ptr, "%s\t", 1948 long_insn_name[(int) insn->name[1]]); 1949 else 1950 ptr += sprintf(ptr, "%.5s\t", insn->name); 1951 /* Extract the operands. */ 1952 separator = 0; 1953 for (ops = formats[insn->format] + 1, i = 0; 1954 *ops != 0 && i < 6; ops++, i++) { 1955 operand = operands + *ops; 1956 value = extract_operand(code, operand); 1957 if ((operand->flags & OPERAND_INDEX) && value == 0) 1958 continue; 1959 if ((operand->flags & OPERAND_BASE) && 1960 value == 0 && separator == '(') { 1961 separator = ','; 1962 continue; 1963 } 1964 if (separator) 1965 ptr += sprintf(ptr, "%c", separator); 1966 if (operand->flags & OPERAND_GPR) 1967 ptr += sprintf(ptr, "%%r%i", value); 1968 else if (operand->flags & OPERAND_FPR) 1969 ptr += sprintf(ptr, "%%f%i", value); 1970 else if (operand->flags & OPERAND_AR) 1971 ptr += sprintf(ptr, "%%a%i", value); 1972 else if (operand->flags & OPERAND_CR) 1973 ptr += sprintf(ptr, "%%c%i", value); 1974 else if (operand->flags & OPERAND_VR) 1975 ptr += sprintf(ptr, "%%v%i", value); 1976 else if (operand->flags & OPERAND_PCREL) 1977 ptr += sprintf(ptr, "%lx", (signed int) value 1978 + addr); 1979 else if (operand->flags & OPERAND_SIGNED) 1980 ptr += sprintf(ptr, "%i", value); 1981 else 1982 ptr += sprintf(ptr, "%u", value); 1983 if (operand->flags & OPERAND_DISP) 1984 separator = '('; 1985 else if (operand->flags & OPERAND_BASE) { 1986 ptr += sprintf(ptr, ")"); 1987 separator = ','; 1988 } else 1989 separator = ','; 1990 } 1991 } else 1992 ptr += sprintf(ptr, "unknown"); 1993 return (int) (ptr - buffer); 1994} 1995 1996void show_code(struct pt_regs *regs) 1997{ 1998 char *mode = user_mode(regs) ? "User" : "Krnl"; 1999 unsigned char code[64]; 2000 char buffer[64], *ptr; 2001 mm_segment_t old_fs; 2002 unsigned long addr; 2003 int start, end, opsize, hops, i; 2004 2005 /* Get a snapshot of the 64 bytes surrounding the fault address. */ 2006 old_fs = get_fs(); 2007 set_fs(user_mode(regs) ? USER_DS : KERNEL_DS); 2008 for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) { 2009 addr = regs->psw.addr - 34 + start; 2010 if (__copy_from_user(code + start - 2, 2011 (char __user *) addr, 2)) 2012 break; 2013 } 2014 for (end = 32; end < 64; end += 2) { 2015 addr = regs->psw.addr + end - 32; 2016 if (__copy_from_user(code + end, 2017 (char __user *) addr, 2)) 2018 break; 2019 } 2020 set_fs(old_fs); 2021 /* Code snapshot useable ? */ 2022 if ((regs->psw.addr & 1) || start >= end) { 2023 printk("%s Code: Bad PSW.\n", mode); 2024 return; 2025 } 2026 /* Find a starting point for the disassembly. */ 2027 while (start < 32) { 2028 for (i = 0, hops = 0; start + i < 32 && hops < 3; hops++) { 2029 if (!find_insn(code + start + i)) 2030 break; 2031 i += insn_length(code[start + i]); 2032 } 2033 if (start + i == 32) 2034 /* Looks good, sequence ends at PSW. */ 2035 break; 2036 start += 2; 2037 } 2038 /* Decode the instructions. */ 2039 ptr = buffer; 2040 ptr += sprintf(ptr, "%s Code:", mode); 2041 hops = 0; 2042 while (start < end && hops < 8) { 2043 opsize = insn_length(code[start]); 2044 if (start + opsize == 32) 2045 *ptr++ = '#'; 2046 else if (start == 32) 2047 *ptr++ = '>'; 2048 else 2049 *ptr++ = ' '; 2050 addr = regs->psw.addr + start - 32; 2051 ptr += sprintf(ptr, ONELONG, addr); 2052 if (start + opsize >= end) 2053 break; 2054 for (i = 0; i < opsize; i++) 2055 ptr += sprintf(ptr, "%02x", code[start + i]); 2056 *ptr++ = '\t'; 2057 if (i < 6) 2058 *ptr++ = '\t'; 2059 ptr += print_insn(ptr, code + start, addr); 2060 start += opsize; 2061 printk(buffer); 2062 ptr = buffer; 2063 ptr += sprintf(ptr, "\n "); 2064 hops++; 2065 } 2066 printk("\n"); 2067} 2068 2069void print_fn_code(unsigned char *code, unsigned long len) 2070{ 2071 char buffer[64], *ptr; 2072 int opsize, i; 2073 2074 while (len) { 2075 ptr = buffer; 2076 opsize = insn_length(*code); 2077 if (opsize > len) 2078 break; 2079 ptr += sprintf(ptr, "%p: ", code); 2080 for (i = 0; i < opsize; i++) 2081 ptr += sprintf(ptr, "%02x", code[i]); 2082 *ptr++ = '\t'; 2083 if (i < 4) 2084 *ptr++ = '\t'; 2085 ptr += print_insn(ptr, code, (unsigned long) code); 2086 *ptr++ = '\n'; 2087 *ptr++ = 0; 2088 printk(buffer); 2089 code += opsize; 2090 len -= opsize; 2091 } 2092} 2093