1/* 2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15/** 16 * @file hypervisor.h 17 * The hypervisor's public API. 18 */ 19 20#ifndef _HV_HV_H 21#define _HV_HV_H 22 23#include <arch/chip.h> 24 25/* Linux builds want unsigned long constants, but assembler wants numbers */ 26#ifdef __ASSEMBLER__ 27/** One, for assembler */ 28#define __HV_SIZE_ONE 1 29#elif !defined(__tile__) && CHIP_VA_WIDTH() > 32 30/** One, for 64-bit on host */ 31#define __HV_SIZE_ONE 1ULL 32#else 33/** One, for Linux */ 34#define __HV_SIZE_ONE 1UL 35#endif 36 37/** The log2 of the span of a level-1 page table, in bytes. 38 */ 39#define HV_LOG2_L1_SPAN 32 40 41/** The span of a level-1 page table, in bytes. 42 */ 43#define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN) 44 45/** The log2 of the initial size of small pages, in bytes. 46 * See HV_DEFAULT_PAGE_SIZE_SMALL. 47 */ 48#define HV_LOG2_DEFAULT_PAGE_SIZE_SMALL 16 49 50/** The initial size of small pages, in bytes. This value should be verified 51 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL). 52 * It may also be modified when installing a new context. 53 */ 54#define HV_DEFAULT_PAGE_SIZE_SMALL \ 55 (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_SMALL) 56 57/** The log2 of the initial size of large pages, in bytes. 58 * See HV_DEFAULT_PAGE_SIZE_LARGE. 59 */ 60#define HV_LOG2_DEFAULT_PAGE_SIZE_LARGE 24 61 62/** The initial size of large pages, in bytes. This value should be verified 63 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE). 64 * It may also be modified when installing a new context. 65 */ 66#define HV_DEFAULT_PAGE_SIZE_LARGE \ 67 (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_LARGE) 68 69#if CHIP_VA_WIDTH() > 32 70 71/** The log2 of the initial size of jumbo pages, in bytes. 72 * See HV_DEFAULT_PAGE_SIZE_JUMBO. 73 */ 74#define HV_LOG2_DEFAULT_PAGE_SIZE_JUMBO 32 75 76/** The initial size of jumbo pages, in bytes. This value should 77 * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_JUMBO). 78 * It may also be modified when installing a new context. 79 */ 80#define HV_DEFAULT_PAGE_SIZE_JUMBO \ 81 (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_JUMBO) 82 83#endif 84 85/** The log2 of the granularity at which page tables must be aligned; 86 * in other words, the CPA for a page table must have this many zero 87 * bits at the bottom of the address. 88 */ 89#define HV_LOG2_PAGE_TABLE_ALIGN 11 90 91/** The granularity at which page tables must be aligned. 92 */ 93#define HV_PAGE_TABLE_ALIGN (__HV_SIZE_ONE << HV_LOG2_PAGE_TABLE_ALIGN) 94 95/** Normal start of hypervisor glue in client physical memory. */ 96#define HV_GLUE_START_CPA 0x10000 97 98/** This much space is reserved at HV_GLUE_START_CPA 99 * for the hypervisor glue. The client program must start at 100 * some address higher than this, and in particular the address of 101 * its text section should be equal to zero modulo HV_PAGE_SIZE_LARGE 102 * so that relative offsets to the HV glue are correct. 103 */ 104#define HV_GLUE_RESERVED_SIZE 0x10000 105 106/** Each entry in the hv dispatch array takes this many bytes. */ 107#define HV_DISPATCH_ENTRY_SIZE 32 108 109/** Version of the hypervisor interface defined by this file */ 110#define _HV_VERSION 13 111 112/** Last version of the hypervisor interface with old hv_init() ABI. 113 * 114 * The change from version 12 to version 13 corresponds to launching 115 * the client by default at PL2 instead of PL1 (corresponding to the 116 * hv itself running at PL3 instead of PL2). To make this explicit, 117 * the hv_init() API was also extended so the client can report its 118 * desired PL, resulting in a more helpful failure diagnostic. If you 119 * call hv_init() with _HV_VERSION_OLD_HV_INIT and omit the client_pl 120 * argument, the hypervisor will assume client_pl = 1. 121 * 122 * Note that this is a deprecated solution and we do not expect to 123 * support clients of the Tilera hypervisor running at PL1 indefinitely. 124 */ 125#define _HV_VERSION_OLD_HV_INIT 12 126 127/* Index into hypervisor interface dispatch code blocks. 128 * 129 * Hypervisor calls are invoked from user space by calling code 130 * at an address HV_BASE_ADDRESS + (index) * HV_DISPATCH_ENTRY_SIZE, 131 * where index is one of these enum values. 132 * 133 * Normally a supervisor is expected to produce a set of symbols 134 * starting at HV_BASE_ADDRESS that obey this convention, but a user 135 * program could call directly through function pointers if desired. 136 * 137 * These numbers are part of the binary API and will not be changed 138 * without updating HV_VERSION, which should be a rare event. 139 */ 140 141/** reserved. */ 142#define _HV_DISPATCH_RESERVED 0 143 144/** hv_init */ 145#define HV_DISPATCH_INIT 1 146 147/** hv_install_context */ 148#define HV_DISPATCH_INSTALL_CONTEXT 2 149 150/** hv_sysconf */ 151#define HV_DISPATCH_SYSCONF 3 152 153/** hv_get_rtc */ 154#define HV_DISPATCH_GET_RTC 4 155 156/** hv_set_rtc */ 157#define HV_DISPATCH_SET_RTC 5 158 159/** hv_flush_asid */ 160#define HV_DISPATCH_FLUSH_ASID 6 161 162/** hv_flush_page */ 163#define HV_DISPATCH_FLUSH_PAGE 7 164 165/** hv_flush_pages */ 166#define HV_DISPATCH_FLUSH_PAGES 8 167 168/** hv_restart */ 169#define HV_DISPATCH_RESTART 9 170 171/** hv_halt */ 172#define HV_DISPATCH_HALT 10 173 174/** hv_power_off */ 175#define HV_DISPATCH_POWER_OFF 11 176 177/** hv_inquire_physical */ 178#define HV_DISPATCH_INQUIRE_PHYSICAL 12 179 180/** hv_inquire_memory_controller */ 181#define HV_DISPATCH_INQUIRE_MEMORY_CONTROLLER 13 182 183/** hv_inquire_virtual */ 184#define HV_DISPATCH_INQUIRE_VIRTUAL 14 185 186/** hv_inquire_asid */ 187#define HV_DISPATCH_INQUIRE_ASID 15 188 189/** hv_nanosleep */ 190#define HV_DISPATCH_NANOSLEEP 16 191 192/** hv_console_read_if_ready */ 193#define HV_DISPATCH_CONSOLE_READ_IF_READY 17 194 195/** hv_console_write */ 196#define HV_DISPATCH_CONSOLE_WRITE 18 197 198/** hv_downcall_dispatch */ 199#define HV_DISPATCH_DOWNCALL_DISPATCH 19 200 201/** hv_inquire_topology */ 202#define HV_DISPATCH_INQUIRE_TOPOLOGY 20 203 204/** hv_fs_findfile */ 205#define HV_DISPATCH_FS_FINDFILE 21 206 207/** hv_fs_fstat */ 208#define HV_DISPATCH_FS_FSTAT 22 209 210/** hv_fs_pread */ 211#define HV_DISPATCH_FS_PREAD 23 212 213/** hv_physaddr_read64 */ 214#define HV_DISPATCH_PHYSADDR_READ64 24 215 216/** hv_physaddr_write64 */ 217#define HV_DISPATCH_PHYSADDR_WRITE64 25 218 219/** hv_get_command_line */ 220#define HV_DISPATCH_GET_COMMAND_LINE 26 221 222/** hv_set_caching */ 223#define HV_DISPATCH_SET_CACHING 27 224 225/** hv_bzero_page */ 226#define HV_DISPATCH_BZERO_PAGE 28 227 228/** hv_register_message_state */ 229#define HV_DISPATCH_REGISTER_MESSAGE_STATE 29 230 231/** hv_send_message */ 232#define HV_DISPATCH_SEND_MESSAGE 30 233 234/** hv_receive_message */ 235#define HV_DISPATCH_RECEIVE_MESSAGE 31 236 237/** hv_inquire_context */ 238#define HV_DISPATCH_INQUIRE_CONTEXT 32 239 240/** hv_start_all_tiles */ 241#define HV_DISPATCH_START_ALL_TILES 33 242 243/** hv_dev_open */ 244#define HV_DISPATCH_DEV_OPEN 34 245 246/** hv_dev_close */ 247#define HV_DISPATCH_DEV_CLOSE 35 248 249/** hv_dev_pread */ 250#define HV_DISPATCH_DEV_PREAD 36 251 252/** hv_dev_pwrite */ 253#define HV_DISPATCH_DEV_PWRITE 37 254 255/** hv_dev_poll */ 256#define HV_DISPATCH_DEV_POLL 38 257 258/** hv_dev_poll_cancel */ 259#define HV_DISPATCH_DEV_POLL_CANCEL 39 260 261/** hv_dev_preada */ 262#define HV_DISPATCH_DEV_PREADA 40 263 264/** hv_dev_pwritea */ 265#define HV_DISPATCH_DEV_PWRITEA 41 266 267/** hv_flush_remote */ 268#define HV_DISPATCH_FLUSH_REMOTE 42 269 270/** hv_console_putc */ 271#define HV_DISPATCH_CONSOLE_PUTC 43 272 273/** hv_inquire_tiles */ 274#define HV_DISPATCH_INQUIRE_TILES 44 275 276/** hv_confstr */ 277#define HV_DISPATCH_CONFSTR 45 278 279/** hv_reexec */ 280#define HV_DISPATCH_REEXEC 46 281 282/** hv_set_command_line */ 283#define HV_DISPATCH_SET_COMMAND_LINE 47 284 285#if !CHIP_HAS_IPI() 286 287/** hv_clear_intr */ 288#define HV_DISPATCH_CLEAR_INTR 48 289 290/** hv_enable_intr */ 291#define HV_DISPATCH_ENABLE_INTR 49 292 293/** hv_disable_intr */ 294#define HV_DISPATCH_DISABLE_INTR 50 295 296/** hv_raise_intr */ 297#define HV_DISPATCH_RAISE_INTR 51 298 299/** hv_trigger_ipi */ 300#define HV_DISPATCH_TRIGGER_IPI 52 301 302#endif /* !CHIP_HAS_IPI() */ 303 304/** hv_store_mapping */ 305#define HV_DISPATCH_STORE_MAPPING 53 306 307/** hv_inquire_realpa */ 308#define HV_DISPATCH_INQUIRE_REALPA 54 309 310/** hv_flush_all */ 311#define HV_DISPATCH_FLUSH_ALL 55 312 313#if CHIP_HAS_IPI() 314/** hv_get_ipi_pte */ 315#define HV_DISPATCH_GET_IPI_PTE 56 316#endif 317 318/** hv_set_pte_super_shift */ 319#define HV_DISPATCH_SET_PTE_SUPER_SHIFT 57 320 321/** hv_console_set_ipi */ 322#define HV_DISPATCH_CONSOLE_SET_IPI 63 323 324/** One more than the largest dispatch value */ 325#define _HV_DISPATCH_END 64 326 327 328#ifndef __ASSEMBLER__ 329 330#ifdef __KERNEL__ 331#include <asm/types.h> 332typedef u32 __hv32; /**< 32-bit value */ 333typedef u64 __hv64; /**< 64-bit value */ 334#else 335#include <stdint.h> 336typedef uint32_t __hv32; /**< 32-bit value */ 337typedef uint64_t __hv64; /**< 64-bit value */ 338#endif 339 340 341/** Hypervisor physical address. */ 342typedef __hv64 HV_PhysAddr; 343 344#if CHIP_VA_WIDTH() > 32 345/** Hypervisor virtual address. */ 346typedef __hv64 HV_VirtAddr; 347#else 348/** Hypervisor virtual address. */ 349typedef __hv32 HV_VirtAddr; 350#endif /* CHIP_VA_WIDTH() > 32 */ 351 352/** Hypervisor ASID. */ 353typedef unsigned int HV_ASID; 354 355/** Hypervisor tile location for a memory access 356 * ("location overridden target"). 357 */ 358typedef unsigned int HV_LOTAR; 359 360/** Hypervisor size of a page. */ 361typedef unsigned long HV_PageSize; 362 363/** A page table entry. 364 */ 365typedef struct 366{ 367 __hv64 val; /**< Value of PTE */ 368} HV_PTE; 369 370/** Hypervisor error code. */ 371typedef int HV_Errno; 372 373#endif /* !__ASSEMBLER__ */ 374 375#define HV_OK 0 /**< No error */ 376#define HV_EINVAL -801 /**< Invalid argument */ 377#define HV_ENODEV -802 /**< No such device */ 378#define HV_ENOENT -803 /**< No such file or directory */ 379#define HV_EBADF -804 /**< Bad file number */ 380#define HV_EFAULT -805 /**< Bad address */ 381#define HV_ERECIP -806 /**< Bad recipients */ 382#define HV_E2BIG -807 /**< Message too big */ 383#define HV_ENOTSUP -808 /**< Service not supported */ 384#define HV_EBUSY -809 /**< Device busy */ 385#define HV_ENOSYS -810 /**< Invalid syscall */ 386#define HV_EPERM -811 /**< No permission */ 387#define HV_ENOTREADY -812 /**< Device not ready */ 388#define HV_EIO -813 /**< I/O error */ 389#define HV_ENOMEM -814 /**< Out of memory */ 390#define HV_EAGAIN -815 /**< Try again */ 391 392#define HV_ERR_MAX -801 /**< Largest HV error code */ 393#define HV_ERR_MIN -815 /**< Smallest HV error code */ 394 395#ifndef __ASSEMBLER__ 396 397/** Pass HV_VERSION to hv_init to request this version of the interface. */ 398typedef enum { 399 HV_VERSION = _HV_VERSION, 400 HV_VERSION_OLD_HV_INIT = _HV_VERSION_OLD_HV_INIT, 401 402} HV_VersionNumber; 403 404/** Initializes the hypervisor. 405 * 406 * @param interface_version_number The version of the hypervisor interface 407 * that this program expects, typically HV_VERSION. 408 * @param chip_num Architecture number of the chip the client was built for. 409 * @param chip_rev_num Revision number of the chip the client was built for. 410 * @param client_pl Privilege level the client is built for 411 * (not required if interface_version_number == HV_VERSION_OLD_HV_INIT). 412 */ 413void hv_init(HV_VersionNumber interface_version_number, 414 int chip_num, int chip_rev_num, int client_pl); 415 416 417/** Queries we can make for hv_sysconf(). 418 * 419 * These numbers are part of the binary API and guaranteed not to change. 420 */ 421typedef enum { 422 /** An invalid value; do not use. */ 423 _HV_SYSCONF_RESERVED = 0, 424 425 /** The length of the glue section containing the hv_ procs, in bytes. */ 426 HV_SYSCONF_GLUE_SIZE = 1, 427 428 /** The size of small pages, in bytes. */ 429 HV_SYSCONF_PAGE_SIZE_SMALL = 2, 430 431 /** The size of large pages, in bytes. */ 432 HV_SYSCONF_PAGE_SIZE_LARGE = 3, 433 434 /** Processor clock speed, in hertz. */ 435 HV_SYSCONF_CPU_SPEED = 4, 436 437 /** Processor temperature, in degrees Kelvin. The value 438 * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees 439 * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates 440 * that the temperature has hit an upper limit and is no longer being 441 * accurately tracked. 442 */ 443 HV_SYSCONF_CPU_TEMP = 5, 444 445 /** Board temperature, in degrees Kelvin. The value 446 * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees 447 * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates 448 * that the temperature has hit an upper limit and is no longer being 449 * accurately tracked. 450 */ 451 HV_SYSCONF_BOARD_TEMP = 6, 452 453 /** Legal page size bitmask for hv_install_context(). 454 * For example, if 16KB and 64KB small pages are supported, 455 * it would return "HV_CTX_PG_SM_16K | HV_CTX_PG_SM_64K". 456 */ 457 HV_SYSCONF_VALID_PAGE_SIZES = 7, 458 459 /** The size of jumbo pages, in bytes. 460 * If no jumbo pages are available, zero will be returned. 461 */ 462 HV_SYSCONF_PAGE_SIZE_JUMBO = 8, 463 464} HV_SysconfQuery; 465 466/** Offset to subtract from returned Kelvin temperature to get degrees 467 Celsius. */ 468#define HV_SYSCONF_TEMP_KTOC 273 469 470/** Pseudo-temperature value indicating that the temperature has 471 * pegged at its upper limit and is no longer accurate; note that this is 472 * the value after subtracting HV_SYSCONF_TEMP_KTOC. */ 473#define HV_SYSCONF_OVERTEMP 999 474 475/** Query a configuration value from the hypervisor. 476 * @param query Which value is requested (HV_SYSCONF_xxx). 477 * @return The requested value, or -1 the requested value is illegal or 478 * unavailable. 479 */ 480long hv_sysconf(HV_SysconfQuery query); 481 482 483/** Queries we can make for hv_confstr(). 484 * 485 * These numbers are part of the binary API and guaranteed not to change. 486 */ 487typedef enum { 488 /** An invalid value; do not use. */ 489 _HV_CONFSTR_RESERVED = 0, 490 491 /** Board part number. */ 492 HV_CONFSTR_BOARD_PART_NUM = 1, 493 494 /** Board serial number. */ 495 HV_CONFSTR_BOARD_SERIAL_NUM = 2, 496 497 /** Chip serial number. */ 498 HV_CONFSTR_CHIP_SERIAL_NUM = 3, 499 500 /** Board revision level. */ 501 HV_CONFSTR_BOARD_REV = 4, 502 503 /** Hypervisor software version. */ 504 HV_CONFSTR_HV_SW_VER = 5, 505 506 /** The name for this chip model. */ 507 HV_CONFSTR_CHIP_MODEL = 6, 508 509 /** Human-readable board description. */ 510 HV_CONFSTR_BOARD_DESC = 7, 511 512 /** Human-readable description of the hypervisor configuration. */ 513 HV_CONFSTR_HV_CONFIG = 8, 514 515 /** Human-readable version string for the boot image (for instance, 516 * who built it and when, what configuration file was used). */ 517 HV_CONFSTR_HV_CONFIG_VER = 9, 518 519 /** Mezzanine part number. */ 520 HV_CONFSTR_MEZZ_PART_NUM = 10, 521 522 /** Mezzanine serial number. */ 523 HV_CONFSTR_MEZZ_SERIAL_NUM = 11, 524 525 /** Mezzanine revision level. */ 526 HV_CONFSTR_MEZZ_REV = 12, 527 528 /** Human-readable mezzanine description. */ 529 HV_CONFSTR_MEZZ_DESC = 13, 530 531 /** Control path for the onboard network switch. */ 532 HV_CONFSTR_SWITCH_CONTROL = 14, 533 534 /** Chip revision level. */ 535 HV_CONFSTR_CHIP_REV = 15, 536 537 /** CPU module part number. */ 538 HV_CONFSTR_CPUMOD_PART_NUM = 16, 539 540 /** CPU module serial number. */ 541 HV_CONFSTR_CPUMOD_SERIAL_NUM = 17, 542 543 /** CPU module revision level. */ 544 HV_CONFSTR_CPUMOD_REV = 18, 545 546 /** Human-readable CPU module description. */ 547 HV_CONFSTR_CPUMOD_DESC = 19, 548 549 /** Per-tile hypervisor statistics. When this identifier is specified, 550 * the hv_confstr call takes two extra arguments. The first is the 551 * HV_XY_TO_LOTAR of the target tile's coordinates. The second is 552 * a flag word. The only current flag is the lowest bit, which means 553 * "zero out the stats instead of retrieving them"; in this case the 554 * buffer and buffer length are ignored. */ 555 HV_CONFSTR_HV_STATS = 20 556 557} HV_ConfstrQuery; 558 559/** Query a configuration string from the hypervisor. 560 * 561 * @param query Identifier for the specific string to be retrieved 562 * (HV_CONFSTR_xxx). Some strings may require or permit extra 563 * arguments to be appended which select specific objects to be 564 * described; see the string descriptions above. 565 * @param buf Buffer in which to place the string. 566 * @param len Length of the buffer. 567 * @return If query is valid, then the length of the corresponding string, 568 * including the trailing null; if this is greater than len, the string 569 * was truncated. If query is invalid, HV_EINVAL. If the specified 570 * buffer is not writable by the client, HV_EFAULT. 571 */ 572int hv_confstr(HV_ConfstrQuery query, HV_VirtAddr buf, int len, ...); 573 574/** Tile coordinate */ 575typedef struct 576{ 577 /** X coordinate, relative to supervisor's top-left coordinate */ 578 int x; 579 580 /** Y coordinate, relative to supervisor's top-left coordinate */ 581 int y; 582} HV_Coord; 583 584 585#if CHIP_HAS_IPI() 586 587/** Get the PTE for sending an IPI to a particular tile. 588 * 589 * @param tile Tile which will receive the IPI. 590 * @param pl Indicates which IPI registers: 0 = IPI_0, 1 = IPI_1. 591 * @param pte Filled with resulting PTE. 592 * @result Zero if no error, non-zero for invalid parameters. 593 */ 594int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte); 595 596/** Configure the console interrupt. 597 * 598 * When the console client interrupt is enabled, the hypervisor will 599 * deliver the specified IPI to the client in the following situations: 600 * 601 * - The console has at least one character available for input. 602 * 603 * - The console can accept new characters for output, and the last call 604 * to hv_console_write() did not write all of the characters requested 605 * by the client. 606 * 607 * Note that in some system configurations, console interrupt will not 608 * be available; clients should be prepared for this routine to fail and 609 * to fall back to periodic console polling in that case. 610 * 611 * @param ipi Index of the IPI register which will receive the interrupt. 612 * @param event IPI event number for console interrupt. If less than 0, 613 * disable the console IPI interrupt. 614 * @param coord Tile to be targeted for console interrupt. 615 * @return 0 on success, otherwise, HV_EINVAL if illegal parameter, 616 * HV_ENOTSUP if console interrupt are not available. 617 */ 618int hv_console_set_ipi(int ipi, int event, HV_Coord coord); 619 620#else /* !CHIP_HAS_IPI() */ 621 622/** A set of interrupts. */ 623typedef __hv32 HV_IntrMask; 624 625/** The low interrupt numbers are reserved for use by the client in 626 * delivering IPIs. Any interrupt numbers higher than this value are 627 * reserved for use by HV device drivers. */ 628#define HV_MAX_IPI_INTERRUPT 7 629 630/** Enable a set of device interrupts. 631 * 632 * @param enab_mask Bitmap of interrupts to enable. 633 */ 634void hv_enable_intr(HV_IntrMask enab_mask); 635 636/** Disable a set of device interrupts. 637 * 638 * @param disab_mask Bitmap of interrupts to disable. 639 */ 640void hv_disable_intr(HV_IntrMask disab_mask); 641 642/** Clear a set of device interrupts. 643 * 644 * @param clear_mask Bitmap of interrupts to clear. 645 */ 646void hv_clear_intr(HV_IntrMask clear_mask); 647 648/** Raise a set of device interrupts. 649 * 650 * @param raise_mask Bitmap of interrupts to raise. 651 */ 652void hv_raise_intr(HV_IntrMask raise_mask); 653 654/** Trigger a one-shot interrupt on some tile 655 * 656 * @param tile Which tile to interrupt. 657 * @param interrupt Interrupt number to trigger; must be between 0 and 658 * HV_MAX_IPI_INTERRUPT. 659 * @return HV_OK on success, or a hypervisor error code. 660 */ 661HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt); 662 663#endif /* !CHIP_HAS_IPI() */ 664 665/** Store memory mapping in debug memory so that external debugger can read it. 666 * A maximum of 16 entries can be stored. 667 * 668 * @param va VA of memory that is mapped. 669 * @param len Length of mapped memory. 670 * @param pa PA of memory that is mapped. 671 * @return 0 on success, -1 if the maximum number of mappings is exceeded. 672 */ 673int hv_store_mapping(HV_VirtAddr va, unsigned int len, HV_PhysAddr pa); 674 675/** Given a client PA and a length, return its real (HV) PA. 676 * 677 * @param cpa Client physical address. 678 * @param len Length of mapped memory. 679 * @return physical address, or -1 if cpa or len is not valid. 680 */ 681HV_PhysAddr hv_inquire_realpa(HV_PhysAddr cpa, unsigned int len); 682 683/** RTC return flag for no RTC chip present. 684 */ 685#define HV_RTC_NO_CHIP 0x1 686 687/** RTC return flag for low-voltage condition, indicating that battery had 688 * died and time read is unreliable. 689 */ 690#define HV_RTC_LOW_VOLTAGE 0x2 691 692/** Date/Time of day */ 693typedef struct { 694#if CHIP_WORD_SIZE() > 32 695 __hv64 tm_sec; /**< Seconds, 0-59 */ 696 __hv64 tm_min; /**< Minutes, 0-59 */ 697 __hv64 tm_hour; /**< Hours, 0-23 */ 698 __hv64 tm_mday; /**< Day of month, 0-30 */ 699 __hv64 tm_mon; /**< Month, 0-11 */ 700 __hv64 tm_year; /**< Years since 1900, 0-199 */ 701 __hv64 flags; /**< Return flags, 0 if no error */ 702#else 703 __hv32 tm_sec; /**< Seconds, 0-59 */ 704 __hv32 tm_min; /**< Minutes, 0-59 */ 705 __hv32 tm_hour; /**< Hours, 0-23 */ 706 __hv32 tm_mday; /**< Day of month, 0-30 */ 707 __hv32 tm_mon; /**< Month, 0-11 */ 708 __hv32 tm_year; /**< Years since 1900, 0-199 */ 709 __hv32 flags; /**< Return flags, 0 if no error */ 710#endif 711} HV_RTCTime; 712 713/** Read the current time-of-day clock. 714 * @return HV_RTCTime of current time (GMT). 715 */ 716HV_RTCTime hv_get_rtc(void); 717 718 719/** Set the current time-of-day clock. 720 * @param time time to reset time-of-day to (GMT). 721 */ 722void hv_set_rtc(HV_RTCTime time); 723 724/** Installs a context, comprising a page table and other attributes. 725 * 726 * Once this service completes, page_table will be used to translate 727 * subsequent virtual address references to physical memory. 728 * 729 * Installing a context does not cause an implicit TLB flush. Before 730 * reusing an ASID value for a different address space, the client is 731 * expected to flush old references from the TLB with hv_flush_asid(). 732 * (Alternately, hv_flush_all() may be used to flush many ASIDs at once.) 733 * After invalidating a page table entry, changing its attributes, or 734 * changing its target CPA, the client is expected to flush old references 735 * from the TLB with hv_flush_page() or hv_flush_pages(). Making a 736 * previously invalid page valid does not require a flush. 737 * 738 * Specifying an invalid ASID, or an invalid CPA (client physical address) 739 * (either as page_table_pointer, or within the referenced table), 740 * or another page table data item documented as above as illegal may 741 * lead to client termination; since the validation of the table is 742 * done as needed, this may happen before the service returns, or at 743 * some later time, or never, depending upon the client's pattern of 744 * memory references. Page table entries which supply translations for 745 * invalid virtual addresses may result in client termination, or may 746 * be silently ignored. "Invalid" in this context means a value which 747 * was not provided to the client via the appropriate hv_inquire_* routine. 748 * 749 * To support changing the instruction VAs at the same time as 750 * installing the new page table, this call explicitly supports 751 * setting the "lr" register to a different address and then jumping 752 * directly to the hv_install_context() routine. In this case, the 753 * new page table does not need to contain any mapping for the 754 * hv_install_context address itself. 755 * 756 * At most one HV_CTX_PG_SM_* flag may be specified in "flags"; 757 * if multiple flags are specified, HV_EINVAL is returned. 758 * Specifying none of the flags results in using the default page size. 759 * All cores participating in a given client must request the same 760 * page size, or the results are undefined. 761 * 762 * @param page_table Root of the page table. 763 * @param access PTE providing info on how to read the page table. This 764 * value must be consistent between multiple tiles sharing a page table, 765 * and must also be consistent with any virtual mappings the client 766 * may be using to access the page table. 767 * @param asid HV_ASID the page table is to be used for. 768 * @param flags Context flags, denoting attributes or privileges of the 769 * current context (HV_CTX_xxx). 770 * @return Zero on success, or a hypervisor error code on failure. 771 */ 772int hv_install_context(HV_PhysAddr page_table, HV_PTE access, HV_ASID asid, 773 __hv32 flags); 774 775#endif /* !__ASSEMBLER__ */ 776 777#define HV_CTX_DIRECTIO 0x1 /**< Direct I/O requests are accepted from 778 PL0. */ 779 780#define HV_CTX_PG_SM_4K 0x10 /**< Use 4K small pages, if available. */ 781#define HV_CTX_PG_SM_16K 0x20 /**< Use 16K small pages, if available. */ 782#define HV_CTX_PG_SM_64K 0x40 /**< Use 64K small pages, if available. */ 783#define HV_CTX_PG_SM_MASK 0xf0 /**< Mask of all possible small pages. */ 784 785#ifndef __ASSEMBLER__ 786 787 788/** Set the number of pages ganged together by HV_PTE_SUPER at a 789 * particular level of the page table. 790 * 791 * The current TILE-Gx hardware only supports powers of four 792 * (i.e. log2_count must be a multiple of two), and the requested 793 * "super" page size must be less than the span of the next level in 794 * the page table. The largest size that can be requested is 64GB. 795 * 796 * The shift value is initially "0" for all page table levels, 797 * indicating that the HV_PTE_SUPER bit is effectively ignored. 798 * 799 * If you change the count from one non-zero value to another, the 800 * hypervisor will flush the entire TLB and TSB to avoid confusion. 801 * 802 * @param level Page table level (0, 1, or 2) 803 * @param log2_count Base-2 log of the number of pages to gang together, 804 * i.e. how much to shift left the base page size for the super page size. 805 * @return Zero on success, or a hypervisor error code on failure. 806 */ 807int hv_set_pte_super_shift(int level, int log2_count); 808 809 810/** Value returned from hv_inquire_context(). */ 811typedef struct 812{ 813 /** Physical address of page table */ 814 HV_PhysAddr page_table; 815 816 /** PTE which defines access method for top of page table */ 817 HV_PTE access; 818 819 /** ASID associated with this page table */ 820 HV_ASID asid; 821 822 /** Context flags */ 823 __hv32 flags; 824} HV_Context; 825 826/** Retrieve information about the currently installed context. 827 * @return The data passed to the last successful hv_install_context call. 828 */ 829HV_Context hv_inquire_context(void); 830 831 832/** Flushes all translations associated with the named address space 833 * identifier from the TLB and any other hypervisor data structures. 834 * Translations installed with the "global" bit are not flushed. 835 * 836 * Specifying an invalid ASID may lead to client termination. "Invalid" 837 * in this context means a value which was not provided to the client 838 * via <tt>hv_inquire_asid()</tt>. 839 * 840 * @param asid HV_ASID whose entries are to be flushed. 841 * @return Zero on success, or a hypervisor error code on failure. 842*/ 843int hv_flush_asid(HV_ASID asid); 844 845 846/** Flushes all translations associated with the named virtual address 847 * and page size from the TLB and other hypervisor data structures. Only 848 * pages visible to the current ASID are affected; note that this includes 849 * global pages in addition to pages specific to the current ASID. 850 * 851 * The supplied VA need not be aligned; it may be anywhere in the 852 * subject page. 853 * 854 * Specifying an invalid virtual address may lead to client termination, 855 * or may silently succeed. "Invalid" in this context means a value 856 * which was not provided to the client via hv_inquire_virtual. 857 * 858 * @param address Address of the page to flush. 859 * @param page_size Size of pages to assume. 860 * @return Zero on success, or a hypervisor error code on failure. 861 */ 862int hv_flush_page(HV_VirtAddr address, HV_PageSize page_size); 863 864 865/** Flushes all translations associated with the named virtual address range 866 * and page size from the TLB and other hypervisor data structures. Only 867 * pages visible to the current ASID are affected; note that this includes 868 * global pages in addition to pages specific to the current ASID. 869 * 870 * The supplied VA need not be aligned; it may be anywhere in the 871 * subject page. 872 * 873 * Specifying an invalid virtual address may lead to client termination, 874 * or may silently succeed. "Invalid" in this context means a value 875 * which was not provided to the client via hv_inquire_virtual. 876 * 877 * @param start Address to flush. 878 * @param page_size Size of pages to assume. 879 * @param size The number of bytes to flush. Any page in the range 880 * [start, start + size) will be flushed from the TLB. 881 * @return Zero on success, or a hypervisor error code on failure. 882 */ 883int hv_flush_pages(HV_VirtAddr start, HV_PageSize page_size, 884 unsigned long size); 885 886 887/** Flushes all non-global translations (if preserve_global is true), 888 * or absolutely all translations (if preserve_global is false). 889 * 890 * @param preserve_global Non-zero if we want to preserve "global" mappings. 891 * @return Zero on success, or a hypervisor error code on failure. 892*/ 893int hv_flush_all(int preserve_global); 894 895 896/** Restart machine with optional restart command and optional args. 897 * @param cmd Const pointer to command to restart with, or NULL 898 * @param args Const pointer to argument string to restart with, or NULL 899 */ 900void hv_restart(HV_VirtAddr cmd, HV_VirtAddr args); 901 902 903/** Halt machine. */ 904void hv_halt(void); 905 906 907/** Power off machine. */ 908void hv_power_off(void); 909 910 911/** Re-enter virtual-is-physical memory translation mode and restart 912 * execution at a given address. 913 * @param entry Client physical address at which to begin execution. 914 * @return A hypervisor error code on failure; if the operation is 915 * successful the call does not return. 916 */ 917int hv_reexec(HV_PhysAddr entry); 918 919 920/** Chip topology */ 921typedef struct 922{ 923 /** Relative coordinates of the querying tile */ 924 HV_Coord coord; 925 926 /** Width of the querying supervisor's tile rectangle. */ 927 int width; 928 929 /** Height of the querying supervisor's tile rectangle. */ 930 int height; 931 932} HV_Topology; 933 934/** Returns information about the tile coordinate system. 935 * 936 * Each supervisor is given a rectangle of tiles it potentially controls. 937 * These tiles are labeled using a relative coordinate system with (0,0) as 938 * the upper left tile regardless of their physical location on the chip. 939 * 940 * This call returns both the size of that rectangle and the position 941 * within that rectangle of the querying tile. 942 * 943 * Not all tiles within that rectangle may be available to the supervisor; 944 * to get the precise set of available tiles, you must also call 945 * hv_inquire_tiles(HV_INQ_TILES_AVAIL, ...). 946 **/ 947HV_Topology hv_inquire_topology(void); 948 949/** Sets of tiles we can retrieve with hv_inquire_tiles(). 950 * 951 * These numbers are part of the binary API and guaranteed not to change. 952 */ 953typedef enum { 954 /** An invalid value; do not use. */ 955 _HV_INQ_TILES_RESERVED = 0, 956 957 /** All available tiles within the supervisor's tile rectangle. */ 958 HV_INQ_TILES_AVAIL = 1, 959 960 /** The set of tiles used for hash-for-home caching. */ 961 HV_INQ_TILES_HFH_CACHE = 2, 962 963 /** The set of tiles that can be legally used as a LOTAR for a PTE. */ 964 HV_INQ_TILES_LOTAR = 3 965} HV_InqTileSet; 966 967/** Returns specific information about various sets of tiles within the 968 * supervisor's tile rectangle. 969 * 970 * @param set Which set of tiles to retrieve. 971 * @param cpumask Pointer to a returned bitmask (in row-major order, 972 * supervisor-relative) of tiles. The low bit of the first word 973 * corresponds to the tile at the upper left-hand corner of the 974 * supervisor's rectangle. In order for the supervisor to know the 975 * buffer length to supply, it should first call hv_inquire_topology. 976 * @param length Number of bytes available for the returned bitmask. 977 **/ 978HV_Errno hv_inquire_tiles(HV_InqTileSet set, HV_VirtAddr cpumask, int length); 979 980 981/** An identifier for a memory controller. Multiple memory controllers 982 * may be connected to one chip, and this uniquely identifies each one. 983 */ 984typedef int HV_MemoryController; 985 986/** A range of physical memory. */ 987typedef struct 988{ 989 HV_PhysAddr start; /**< Starting address. */ 990 __hv64 size; /**< Size in bytes. */ 991 HV_MemoryController controller; /**< Which memory controller owns this. */ 992} HV_PhysAddrRange; 993 994/** Returns information about a range of physical memory. 995 * 996 * hv_inquire_physical() returns one of the ranges of client 997 * physical addresses which are available to this client. 998 * 999 * The first range is retrieved by specifying an idx of 0, and 1000 * successive ranges are returned with subsequent idx values. Ranges 1001 * are ordered by increasing start address (i.e., as idx increases, 1002 * so does start), do not overlap, and do not touch (i.e., the 1003 * available memory is described with the fewest possible ranges). 1004 * 1005 * If an out-of-range idx value is specified, the returned size will be zero. 1006 * A client can count the number of ranges by increasing idx until the 1007 * returned size is zero. There will always be at least one valid range. 1008 * 1009 * Some clients might not be prepared to deal with more than one 1010 * physical address range; they still ought to call this routine and 1011 * issue a warning message if they're given more than one range, on the 1012 * theory that whoever configured the hypervisor to provide that memory 1013 * should know that it's being wasted. 1014 */ 1015HV_PhysAddrRange hv_inquire_physical(int idx); 1016 1017/** Possible DIMM types. */ 1018typedef enum 1019{ 1020 NO_DIMM = 0, /**< No DIMM */ 1021 DDR2 = 1, /**< DDR2 */ 1022 DDR3 = 2 /**< DDR3 */ 1023} HV_DIMM_Type; 1024 1025#ifdef __tilegx__ 1026 1027/** Log2 of minimum DIMM bytes supported by the memory controller. */ 1028#define HV_MSH_MIN_DIMM_SIZE_SHIFT 29 1029 1030/** Max number of DIMMs contained by one memory controller. */ 1031#define HV_MSH_MAX_DIMMS 8 1032 1033#else 1034 1035/** Log2 of minimum DIMM bytes supported by the memory controller. */ 1036#define HV_MSH_MIN_DIMM_SIZE_SHIFT 26 1037 1038/** Max number of DIMMs contained by one memory controller. */ 1039#define HV_MSH_MAX_DIMMS 2 1040 1041#endif 1042 1043/** Number of bits to right-shift to get the DIMM type. */ 1044#define HV_DIMM_TYPE_SHIFT 0 1045 1046/** Bits to mask to get the DIMM type. */ 1047#define HV_DIMM_TYPE_MASK 0xf 1048 1049/** Number of bits to right-shift to get the DIMM size. */ 1050#define HV_DIMM_SIZE_SHIFT 4 1051 1052/** Bits to mask to get the DIMM size. */ 1053#define HV_DIMM_SIZE_MASK 0xf 1054 1055/** Memory controller information. */ 1056typedef struct 1057{ 1058 HV_Coord coord; /**< Relative tile coordinates of the port used by a 1059 specified tile to communicate with this controller. */ 1060 __hv64 speed; /**< Speed of this controller in bytes per second. */ 1061} HV_MemoryControllerInfo; 1062 1063/** Returns information about a particular memory controller. 1064 * 1065 * hv_inquire_memory_controller(coord,idx) returns information about a 1066 * particular controller. Two pieces of information are returned: 1067 * - The relative coordinates of the port on the controller that the specified 1068 * tile would use to contact it. The relative coordinates may lie 1069 * outside the supervisor's rectangle, i.e. the controller may not 1070 * be attached to a node managed by the querying node's supervisor. 1071 * In particular note that x or y may be negative. 1072 * - The speed of the memory controller. (This is a not-to-exceed value 1073 * based on the raw hardware data rate, and may not be achievable in 1074 * practice; it is provided to give clients information on the relative 1075 * performance of the available controllers.) 1076 * 1077 * Clients should avoid calling this interface with invalid values. 1078 * A client who does may be terminated. 1079 * @param coord Tile for which to calculate the relative port position. 1080 * @param controller Index of the controller; identical to value returned 1081 * from other routines like hv_inquire_physical. 1082 * @return Information about the controller. 1083 */ 1084HV_MemoryControllerInfo hv_inquire_memory_controller(HV_Coord coord, 1085 int controller); 1086 1087 1088/** A range of virtual memory. */ 1089typedef struct 1090{ 1091 HV_VirtAddr start; /**< Starting address. */ 1092 __hv64 size; /**< Size in bytes. */ 1093} HV_VirtAddrRange; 1094 1095/** Returns information about a range of virtual memory. 1096 * 1097 * hv_inquire_virtual() returns one of the ranges of client 1098 * virtual addresses which are available to this client. 1099 * 1100 * The first range is retrieved by specifying an idx of 0, and 1101 * successive ranges are returned with subsequent idx values. Ranges 1102 * are ordered by increasing start address (i.e., as idx increases, 1103 * so does start), do not overlap, and do not touch (i.e., the 1104 * available memory is described with the fewest possible ranges). 1105 * 1106 * If an out-of-range idx value is specified, the returned size will be zero. 1107 * A client can count the number of ranges by increasing idx until the 1108 * returned size is zero. There will always be at least one valid range. 1109 * 1110 * Some clients may well have various virtual addresses hardwired 1111 * into themselves; for instance, their instruction stream may 1112 * have been compiled expecting to live at a particular address. 1113 * Such clients should use this interface to verify they've been 1114 * given the virtual address space they expect, and issue a (potentially 1115 * fatal) warning message otherwise. 1116 * 1117 * Note that the returned size is a __hv64, not a __hv32, so it is 1118 * possible to express a single range spanning the entire 32-bit 1119 * address space. 1120 */ 1121HV_VirtAddrRange hv_inquire_virtual(int idx); 1122 1123 1124/** A range of ASID values. */ 1125typedef struct 1126{ 1127 HV_ASID start; /**< First ASID in the range. */ 1128 unsigned int size; /**< Number of ASIDs. Zero for an invalid range. */ 1129} HV_ASIDRange; 1130 1131/** Returns information about a range of ASIDs. 1132 * 1133 * hv_inquire_asid() returns one of the ranges of address 1134 * space identifiers which are available to this client. 1135 * 1136 * The first range is retrieved by specifying an idx of 0, and 1137 * successive ranges are returned with subsequent idx values. Ranges 1138 * are ordered by increasing start value (i.e., as idx increases, 1139 * so does start), do not overlap, and do not touch (i.e., the 1140 * available ASIDs are described with the fewest possible ranges). 1141 * 1142 * If an out-of-range idx value is specified, the returned size will be zero. 1143 * A client can count the number of ranges by increasing idx until the 1144 * returned size is zero. There will always be at least one valid range. 1145 */ 1146HV_ASIDRange hv_inquire_asid(int idx); 1147 1148 1149/** Waits for at least the specified number of nanoseconds then returns. 1150 * 1151 * NOTE: this deprecated function currently assumes a 750 MHz clock, 1152 * and is thus not generally suitable for use. New code should call 1153 * hv_sysconf(HV_SYSCONF_CPU_SPEED), compute a cycle count to wait for, 1154 * and delay by looping while checking the cycle counter SPR. 1155 * 1156 * @param nanosecs The number of nanoseconds to sleep. 1157 */ 1158void hv_nanosleep(int nanosecs); 1159 1160 1161/** Reads a character from the console without blocking. 1162 * 1163 * @return A value from 0-255 indicates the value successfully read. 1164 * A negative value means no value was ready. 1165 */ 1166int hv_console_read_if_ready(void); 1167 1168 1169/** Writes a character to the console, blocking if the console is busy. 1170 * 1171 * This call cannot fail. If the console is broken for some reason, 1172 * output will simply vanish. 1173 * @param byte Character to write. 1174 */ 1175void hv_console_putc(int byte); 1176 1177 1178/** Writes a string to the console, blocking if the console is busy. 1179 * @param bytes Pointer to characters to write. 1180 * @param len Number of characters to write. 1181 * @return Number of characters written, or HV_EFAULT if the buffer is invalid. 1182 */ 1183int hv_console_write(HV_VirtAddr bytes, int len); 1184 1185 1186/** Dispatch the next interrupt from the client downcall mechanism. 1187 * 1188 * The hypervisor uses downcalls to notify the client of asynchronous 1189 * events. Some of these events are hypervisor-created (like incoming 1190 * messages). Some are regular interrupts which initially occur in 1191 * the hypervisor, and are normally handled directly by the client; 1192 * when these occur in a client's interrupt critical section, they must 1193 * be delivered through the downcall mechanism. 1194 * 1195 * A downcall is initially delivered to the client as an INTCTRL_CL 1196 * interrupt, where CL is the client's PL. Upon entry to the INTCTRL_CL 1197 * vector, the client must immediately invoke the hv_downcall_dispatch 1198 * service. This service will not return; instead it will cause one of 1199 * the client's actual downcall-handling interrupt vectors to be entered. 1200 * The EX_CONTEXT registers in the client will be set so that when the 1201 * client irets, it will return to the code which was interrupted by the 1202 * INTCTRL_CL interrupt. 1203 * 1204 * Under some circumstances, the firing of INTCTRL_CL can race with 1205 * the lowering of a device interrupt. In such a case, the 1206 * hv_downcall_dispatch service may issue an iret instruction instead 1207 * of entering one of the client's actual downcall-handling interrupt 1208 * vectors. This will return execution to the location that was 1209 * interrupted by INTCTRL_CL. 1210 * 1211 * Any saving of registers should be done by the actual handling 1212 * vectors; no registers should be changed by the INTCTRL_CL handler. 1213 * In particular, the client should not use a jal instruction to invoke 1214 * the hv_downcall_dispatch service, as that would overwrite the client's 1215 * lr register. Note that the hv_downcall_dispatch service may overwrite 1216 * one or more of the client's system save registers. 1217 * 1218 * The client must not modify the INTCTRL_CL_STATUS SPR. The hypervisor 1219 * will set this register to cause a downcall to happen, and will clear 1220 * it when no further downcalls are pending. 1221 * 1222 * When a downcall vector is entered, the INTCTRL_CL interrupt will be 1223 * masked. When the client is done processing a downcall, and is ready 1224 * to accept another, it must unmask this interrupt; if more downcalls 1225 * are pending, this will cause the INTCTRL_CL vector to be reentered. 1226 * Currently the following interrupt vectors can be entered through a 1227 * downcall: 1228 * 1229 * INT_MESSAGE_RCV_DWNCL (hypervisor message available) 1230 * INT_DEV_INTR_DWNCL (device interrupt) 1231 * INT_DMATLB_MISS_DWNCL (DMA TLB miss) 1232 * INT_SNITLB_MISS_DWNCL (SNI TLB miss) 1233 * INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation) 1234 */ 1235void hv_downcall_dispatch(void); 1236 1237#endif /* !__ASSEMBLER__ */ 1238 1239/** We use actual interrupt vectors which never occur (they're only there 1240 * to allow setting MPLs for related SPRs) for our downcall vectors. 1241 */ 1242/** Message receive downcall interrupt vector */ 1243#define INT_MESSAGE_RCV_DWNCL INT_BOOT_ACCESS 1244/** DMA TLB miss downcall interrupt vector */ 1245#define INT_DMATLB_MISS_DWNCL INT_DMA_ASID 1246/** Static nework processor instruction TLB miss interrupt vector */ 1247#define INT_SNITLB_MISS_DWNCL INT_SNI_ASID 1248/** DMA TLB access violation downcall interrupt vector */ 1249#define INT_DMATLB_ACCESS_DWNCL INT_DMA_CPL 1250/** Device interrupt downcall interrupt vector */ 1251#define INT_DEV_INTR_DWNCL INT_WORLD_ACCESS 1252 1253#ifndef __ASSEMBLER__ 1254 1255/** Requests the inode for a specific full pathname. 1256 * 1257 * Performs a lookup in the hypervisor filesystem for a given filename. 1258 * Multiple calls with the same filename will always return the same inode. 1259 * If there is no such filename, HV_ENOENT is returned. 1260 * A bad filename pointer may result in HV_EFAULT instead. 1261 * 1262 * @param filename Constant pointer to name of requested file 1263 * @return Inode of requested file 1264 */ 1265int hv_fs_findfile(HV_VirtAddr filename); 1266 1267 1268/** Data returned from an fstat request. 1269 * Note that this structure should be no more than 40 bytes in size so 1270 * that it can always be returned completely in registers. 1271 */ 1272typedef struct 1273{ 1274 int size; /**< Size of file (or HV_Errno on error) */ 1275 unsigned int flags; /**< Flags (see HV_FS_FSTAT_FLAGS) */ 1276} HV_FS_StatInfo; 1277 1278/** Bitmask flags for fstat request */ 1279typedef enum 1280{ 1281 HV_FS_ISDIR = 0x0001 /**< Is the entry a directory? */ 1282} HV_FS_FSTAT_FLAGS; 1283 1284/** Get stat information on a given file inode. 1285 * 1286 * Return information on the file with the given inode. 1287 * 1288 * IF the HV_FS_ISDIR bit is set, the "file" is a directory. Reading 1289 * it will return NUL-separated filenames (no directory part) relative 1290 * to the path to the inode of the directory "file". These can be 1291 * appended to the path to the directory "file" after a forward slash 1292 * to create additional filenames. Note that it is not required 1293 * that all valid paths be decomposable into valid parent directories; 1294 * a filesystem may validly have just a few files, none of which have 1295 * HV_FS_ISDIR set. However, if clients may wish to enumerate the 1296 * files in the filesystem, it is recommended to include all the 1297 * appropriate parent directory "files" to give a consistent view. 1298 * 1299 * An invalid file inode will cause an HV_EBADF error to be returned. 1300 * 1301 * @param inode The inode number of the query 1302 * @return An HV_FS_StatInfo structure 1303 */ 1304HV_FS_StatInfo hv_fs_fstat(int inode); 1305 1306 1307/** Read data from a specific hypervisor file. 1308 * On error, may return HV_EBADF for a bad inode or HV_EFAULT for a bad buf. 1309 * Reads near the end of the file will return fewer bytes than requested. 1310 * Reads at or beyond the end of a file will return zero. 1311 * 1312 * @param inode the hypervisor file to read 1313 * @param buf the buffer to read data into 1314 * @param length the number of bytes of data to read 1315 * @param offset the offset into the file to read the data from 1316 * @return number of bytes successfully read, or an HV_Errno code 1317 */ 1318int hv_fs_pread(int inode, HV_VirtAddr buf, int length, int offset); 1319 1320 1321/** Read a 64-bit word from the specified physical address. 1322 * The address must be 8-byte aligned. 1323 * Specifying an invalid physical address will lead to client termination. 1324 * @param addr The physical address to read 1325 * @param access The PTE describing how to read the memory 1326 * @return The 64-bit value read from the given address 1327 */ 1328unsigned long long hv_physaddr_read64(HV_PhysAddr addr, HV_PTE access); 1329 1330 1331/** Write a 64-bit word to the specified physical address. 1332 * The address must be 8-byte aligned. 1333 * Specifying an invalid physical address will lead to client termination. 1334 * @param addr The physical address to write 1335 * @param access The PTE that says how to write the memory 1336 * @param val The 64-bit value to write to the given address 1337 */ 1338void hv_physaddr_write64(HV_PhysAddr addr, HV_PTE access, 1339 unsigned long long val); 1340 1341 1342/** Get the value of the command-line for the supervisor, if any. 1343 * This will not include the filename of the booted supervisor, but may 1344 * include configured-in boot arguments or the hv_restart() arguments. 1345 * If the buffer is not long enough the hypervisor will NUL the first 1346 * character of the buffer but not write any other data. 1347 * @param buf The virtual address to write the command-line string to. 1348 * @param length The length of buf, in characters. 1349 * @return The actual length of the command line, including the trailing NUL 1350 * (may be larger than "length"). 1351 */ 1352int hv_get_command_line(HV_VirtAddr buf, int length); 1353 1354 1355/** Set a new value for the command-line for the supervisor, which will 1356 * be returned from subsequent invocations of hv_get_command_line() on 1357 * this tile. 1358 * @param buf The virtual address to read the command-line string from. 1359 * @param length The length of buf, in characters; must be no more than 1360 * HV_COMMAND_LINE_LEN. 1361 * @return Zero if successful, or a hypervisor error code. 1362 */ 1363HV_Errno hv_set_command_line(HV_VirtAddr buf, int length); 1364 1365/** Maximum size of a command line passed to hv_set_command_line(); note 1366 * that a line returned from hv_get_command_line() could be larger than 1367 * this.*/ 1368#define HV_COMMAND_LINE_LEN 256 1369 1370/** Tell the hypervisor how to cache non-priority pages 1371 * (its own as well as pages explicitly represented in page tables). 1372 * Normally these will be represented as red/black pages, but 1373 * when the supervisor starts to allocate "priority" pages in the PTE 1374 * the hypervisor will need to start marking those pages as (e.g.) "red" 1375 * and non-priority pages as either "black" (if they cache-alias 1376 * with the existing priority pages) or "red/black" (if they don't). 1377 * The bitmask provides information on which parts of the cache 1378 * have been used for pinned pages so far on this tile; if (1 << N) 1379 * appears in the bitmask, that indicates that a 4KB region of the 1380 * cache starting at (N * 4KB) is in use by a "priority" page. 1381 * The portion of cache used by a particular page can be computed 1382 * by taking the page's PA, modulo CHIP_L2_CACHE_SIZE(), and setting 1383 * all the "4KB" bits corresponding to the actual page size. 1384 * @param bitmask A bitmap of priority page set values 1385 */ 1386void hv_set_caching(unsigned long bitmask); 1387 1388 1389/** Zero out a specified number of pages. 1390 * The va and size must both be multiples of 4096. 1391 * Caches are bypassed and memory is directly set to zero. 1392 * This API is implemented only in the magic hypervisor and is intended 1393 * to provide a performance boost to the minimal supervisor by 1394 * giving it a fast way to zero memory pages when allocating them. 1395 * @param va Virtual address where the page has been mapped 1396 * @param size Number of bytes (must be a page size multiple) 1397 */ 1398void hv_bzero_page(HV_VirtAddr va, unsigned int size); 1399 1400 1401/** State object for the hypervisor messaging subsystem. */ 1402typedef struct 1403{ 1404#if CHIP_VA_WIDTH() > 32 1405 __hv64 opaque[2]; /**< No user-serviceable parts inside */ 1406#else 1407 __hv32 opaque[2]; /**< No user-serviceable parts inside */ 1408#endif 1409} 1410HV_MsgState; 1411 1412/** Register to receive incoming messages. 1413 * 1414 * This routine configures the current tile so that it can receive 1415 * incoming messages. It must be called before the client can receive 1416 * messages with the hv_receive_message routine, and must be called on 1417 * each tile which will receive messages. 1418 * 1419 * msgstate is the virtual address of a state object of type HV_MsgState. 1420 * Once the state is registered, the client must not read or write the 1421 * state object; doing so will cause undefined results. 1422 * 1423 * If this routine is called with msgstate set to 0, the client's message 1424 * state will be freed and it will no longer be able to receive messages. 1425 * Note that this may cause the loss of any as-yet-undelivered messages 1426 * for the client. 1427 * 1428 * If another client attempts to send a message to a client which has 1429 * not yet called hv_register_message_state, or which has freed its 1430 * message state, the message will not be delivered, as if the client 1431 * had insufficient buffering. 1432 * 1433 * This routine returns HV_OK if the registration was successful, and 1434 * HV_EINVAL if the supplied state object is unsuitable. Note that some 1435 * errors may not be detected during this routine, but might be detected 1436 * during a subsequent message delivery. 1437 * @param msgstate State object. 1438 **/ 1439HV_Errno hv_register_message_state(HV_MsgState* msgstate); 1440 1441/** Possible message recipient states. */ 1442typedef enum 1443{ 1444 HV_TO_BE_SENT, /**< Not sent (not attempted, or recipient not ready) */ 1445 HV_SENT, /**< Successfully sent */ 1446 HV_BAD_RECIP /**< Bad recipient coordinates (permanent error) */ 1447} HV_Recip_State; 1448 1449/** Message recipient. */ 1450typedef struct 1451{ 1452 /** X coordinate, relative to supervisor's top-left coordinate */ 1453 unsigned int x:11; 1454 1455 /** Y coordinate, relative to supervisor's top-left coordinate */ 1456 unsigned int y:11; 1457 1458 /** Status of this recipient */ 1459 HV_Recip_State state:10; 1460} HV_Recipient; 1461 1462/** Send a message to a set of recipients. 1463 * 1464 * This routine sends a message to a set of recipients. 1465 * 1466 * recips is an array of HV_Recipient structures. Each specifies a tile, 1467 * and a message state; initially, it is expected that the state will 1468 * be set to HV_TO_BE_SENT. nrecip specifies the number of recipients 1469 * in the recips array. 1470 * 1471 * For each recipient whose state is HV_TO_BE_SENT, the hypervisor attempts 1472 * to send that tile the specified message. In order to successfully 1473 * receive the message, the receiver must be a valid tile to which the 1474 * sender has access, must not be the sending tile itself, and must have 1475 * sufficient free buffer space. (The hypervisor guarantees that each 1476 * tile which has called hv_register_message_state() will be able to 1477 * buffer one message from every other tile which can legally send to it; 1478 * more space may be provided but is not guaranteed.) If an invalid tile 1479 * is specified, the recipient's state is set to HV_BAD_RECIP; this is a 1480 * permanent delivery error. If the message is successfully delivered 1481 * to the recipient's buffer, the recipient's state is set to HV_SENT. 1482 * Otherwise, the recipient's state is unchanged. Message delivery is 1483 * synchronous; all attempts to send messages are completed before this 1484 * routine returns. 1485 * 1486 * If no permanent delivery errors were encountered, the routine returns 1487 * the number of messages successfully sent: that is, the number of 1488 * recipients whose states changed from HV_TO_BE_SENT to HV_SENT during 1489 * this operation. If any permanent delivery errors were encountered, 1490 * the routine returns HV_ERECIP. In the event of permanent delivery 1491 * errors, it may be the case that delivery was not attempted to all 1492 * recipients; if any messages were successfully delivered, however, 1493 * recipients' state values will be updated appropriately. 1494 * 1495 * It is explicitly legal to specify a recipient structure whose state 1496 * is not HV_TO_BE_SENT; such a recipient is ignored. One suggested way 1497 * of using hv_send_message to send a message to multiple tiles is to set 1498 * up a list of recipients, and then call the routine repeatedly with the 1499 * same list, each time accumulating the number of messages successfully 1500 * sent, until all messages are sent, a permanent error is encountered, 1501 * or the desired number of attempts have been made. When used in this 1502 * way, the routine will deliver each message no more than once to each 1503 * recipient. 1504 * 1505 * Note that a message being successfully delivered to the recipient's 1506 * buffer space does not guarantee that it is received by the recipient, 1507 * either immediately or at any time in the future; the recipient might 1508 * never call hv_receive_message, or could register a different state 1509 * buffer, losing the message. 1510 * 1511 * Specifying the same recipient more than once in the recipient list 1512 * is an error, which will not result in an error return but which may 1513 * or may not result in more than one message being delivered to the 1514 * recipient tile. 1515 * 1516 * buf and buflen specify the message to be sent. buf is a virtual address 1517 * which must be currently mapped in the client's page table; if not, the 1518 * routine returns HV_EFAULT. buflen must be greater than zero and less 1519 * than or equal to HV_MAX_MESSAGE_SIZE, and nrecip must be less than the 1520 * number of tiles to which the sender has access; if not, the routine 1521 * returns HV_EINVAL. 1522 * @param recips List of recipients. 1523 * @param nrecip Number of recipients. 1524 * @param buf Address of message data. 1525 * @param buflen Length of message data. 1526 **/ 1527int hv_send_message(HV_Recipient *recips, int nrecip, 1528 HV_VirtAddr buf, int buflen); 1529 1530/** Maximum hypervisor message size, in bytes */ 1531#define HV_MAX_MESSAGE_SIZE 28 1532 1533 1534/** Return value from hv_receive_message() */ 1535typedef struct 1536{ 1537 int msglen; /**< Message length in bytes, or an error code */ 1538 __hv32 source; /**< Code identifying message sender (HV_MSG_xxx) */ 1539} HV_RcvMsgInfo; 1540 1541#define HV_MSG_TILE 0x0 /**< Message source is another tile */ 1542#define HV_MSG_INTR 0x1 /**< Message source is a driver interrupt */ 1543 1544/** Receive a message. 1545 * 1546 * This routine retrieves a message from the client's incoming message 1547 * buffer. 1548 * 1549 * Multiple messages sent from a particular sending tile to a particular 1550 * receiving tile are received in the order that they were sent; however, 1551 * no ordering is guaranteed between messages sent by different tiles. 1552 * 1553 * Whenever the a client's message buffer is empty, the first message 1554 * subsequently received will cause the client's MESSAGE_RCV_DWNCL 1555 * interrupt vector to be invoked through the interrupt downcall mechanism 1556 * (see the description of the hv_downcall_dispatch() routine for details 1557 * on downcalls). 1558 * 1559 * Another message-available downcall will not occur until a call to 1560 * this routine is made when the message buffer is empty, and a message 1561 * subsequently arrives. Note that such a downcall could occur while 1562 * this routine is executing. If the calling code does not wish this 1563 * to happen, it is recommended that this routine be called with the 1564 * INTCTRL_1 interrupt masked, or inside an interrupt critical section. 1565 * 1566 * msgstate is the value previously passed to hv_register_message_state(). 1567 * buf is the virtual address of the buffer into which the message will 1568 * be written; buflen is the length of the buffer. 1569 * 1570 * This routine returns an HV_RcvMsgInfo structure. The msglen member 1571 * of that structure is the length of the message received, zero if no 1572 * message is available, or HV_E2BIG if the message is too large for the 1573 * specified buffer. If the message is too large, it is not consumed, 1574 * and may be retrieved by a subsequent call to this routine specifying 1575 * a sufficiently large buffer. A buffer which is HV_MAX_MESSAGE_SIZE 1576 * bytes long is guaranteed to be able to receive any possible message. 1577 * 1578 * The source member of the HV_RcvMsgInfo structure describes the sender 1579 * of the message. For messages sent by another client tile via an 1580 * hv_send_message() call, this value is HV_MSG_TILE; for messages sent 1581 * as a result of a device interrupt, this value is HV_MSG_INTR. 1582 */ 1583 1584HV_RcvMsgInfo hv_receive_message(HV_MsgState msgstate, HV_VirtAddr buf, 1585 int buflen); 1586 1587 1588/** Start remaining tiles owned by this supervisor. Initially, only one tile 1589 * executes the client program; after it calls this service, the other tiles 1590 * are started. This allows the initial tile to do one-time configuration 1591 * of shared data structures without having to lock them against simultaneous 1592 * access. 1593 */ 1594void hv_start_all_tiles(void); 1595 1596 1597/** Open a hypervisor device. 1598 * 1599 * This service initializes an I/O device and its hypervisor driver software, 1600 * and makes it available for use. The open operation is per-device per-chip; 1601 * once it has been performed, the device handle returned may be used in other 1602 * device services calls made by any tile. 1603 * 1604 * @param name Name of the device. A base device name is just a text string 1605 * (say, "pcie"). If there is more than one instance of a device, the 1606 * base name is followed by a slash and a device number (say, "pcie/0"). 1607 * Some devices may support further structure beneath those components; 1608 * most notably, devices which require control operations do so by 1609 * supporting reads and/or writes to a control device whose name 1610 * includes a trailing "/ctl" (say, "pcie/0/ctl"). 1611 * @param flags Flags (HV_DEV_xxx). 1612 * @return A positive integer device handle, or a negative error code. 1613 */ 1614int hv_dev_open(HV_VirtAddr name, __hv32 flags); 1615 1616 1617/** Close a hypervisor device. 1618 * 1619 * This service uninitializes an I/O device and its hypervisor driver 1620 * software, and makes it unavailable for use. The close operation is 1621 * per-device per-chip; once it has been performed, the device is no longer 1622 * available. Normally there is no need to ever call the close service. 1623 * 1624 * @param devhdl Device handle of the device to be closed. 1625 * @return Zero if the close is successful, otherwise, a negative error code. 1626 */ 1627int hv_dev_close(int devhdl); 1628 1629 1630/** Read data from a hypervisor device synchronously. 1631 * 1632 * This service transfers data from a hypervisor device to a memory buffer. 1633 * When the service returns, the data has been written from the memory buffer, 1634 * and the buffer will not be further modified by the driver. 1635 * 1636 * No ordering is guaranteed between requests issued from different tiles. 1637 * 1638 * Devices may choose to support both the synchronous and asynchronous read 1639 * operations, only one of them, or neither of them. 1640 * 1641 * @param devhdl Device handle of the device to be read from. 1642 * @param flags Flags (HV_DEV_xxx). 1643 * @param va Virtual address of the target data buffer. This buffer must 1644 * be mapped in the currently installed page table; if not, HV_EFAULT 1645 * may be returned. 1646 * @param len Number of bytes to be transferred. 1647 * @param offset Driver-dependent offset. For a random-access device, this is 1648 * often a byte offset from the beginning of the device; in other cases, 1649 * like on a control device, it may have a different meaning. 1650 * @return A non-negative value if the read was at least partially successful; 1651 * otherwise, a negative error code. The precise interpretation of 1652 * the return value is driver-dependent, but many drivers will return 1653 * the number of bytes successfully transferred. 1654 */ 1655int hv_dev_pread(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len, 1656 __hv64 offset); 1657 1658#define HV_DEV_NB_EMPTY 0x1 /**< Don't block when no bytes of data can 1659 be transferred. */ 1660#define HV_DEV_NB_PARTIAL 0x2 /**< Don't block when some bytes, but not all 1661 of the requested bytes, can be 1662 transferred. */ 1663#define HV_DEV_NOCACHE 0x4 /**< The caller warrants that none of the 1664 cache lines which might contain data 1665 from the requested buffer are valid. 1666 Useful with asynchronous operations 1667 only. */ 1668 1669#define HV_DEV_ALLFLAGS (HV_DEV_NB_EMPTY | HV_DEV_NB_PARTIAL | \ 1670 HV_DEV_NOCACHE) /**< All HV_DEV_xxx flags */ 1671 1672/** Write data to a hypervisor device synchronously. 1673 * 1674 * This service transfers data from a memory buffer to a hypervisor device. 1675 * When the service returns, the data has been read from the memory buffer, 1676 * and the buffer may be overwritten by the client; the data may not 1677 * necessarily have been conveyed to the actual hardware I/O interface. 1678 * 1679 * No ordering is guaranteed between requests issued from different tiles. 1680 * 1681 * Devices may choose to support both the synchronous and asynchronous write 1682 * operations, only one of them, or neither of them. 1683 * 1684 * @param devhdl Device handle of the device to be written to. 1685 * @param flags Flags (HV_DEV_xxx). 1686 * @param va Virtual address of the source data buffer. This buffer must 1687 * be mapped in the currently installed page table; if not, HV_EFAULT 1688 * may be returned. 1689 * @param len Number of bytes to be transferred. 1690 * @param offset Driver-dependent offset. For a random-access device, this is 1691 * often a byte offset from the beginning of the device; in other cases, 1692 * like on a control device, it may have a different meaning. 1693 * @return A non-negative value if the write was at least partially successful; 1694 * otherwise, a negative error code. The precise interpretation of 1695 * the return value is driver-dependent, but many drivers will return 1696 * the number of bytes successfully transferred. 1697 */ 1698int hv_dev_pwrite(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len, 1699 __hv64 offset); 1700 1701 1702/** Interrupt arguments, used in the asynchronous I/O interfaces. */ 1703#if CHIP_VA_WIDTH() > 32 1704typedef __hv64 HV_IntArg; 1705#else 1706typedef __hv32 HV_IntArg; 1707#endif 1708 1709/** Interrupt messages are delivered via the mechanism as normal messages, 1710 * but have a message source of HV_DEV_INTR. The message is formatted 1711 * as an HV_IntrMsg structure. 1712 */ 1713 1714typedef struct 1715{ 1716 HV_IntArg intarg; /**< Interrupt argument, passed to the poll/preada/pwritea 1717 services */ 1718 HV_IntArg intdata; /**< Interrupt-specific interrupt data */ 1719} HV_IntrMsg; 1720 1721/** Request an interrupt message when a device condition is satisfied. 1722 * 1723 * This service requests that an interrupt message be delivered to the 1724 * requesting tile when a device becomes readable or writable, or when any 1725 * data queued to the device via previous write operations from this tile 1726 * has been actually sent out on the hardware I/O interface. Devices may 1727 * choose to support any, all, or none of the available conditions. 1728 * 1729 * If multiple conditions are specified, only one message will be 1730 * delivered. If the event mask delivered to that interrupt handler 1731 * indicates that some of the conditions have not yet occurred, the 1732 * client must issue another poll() call if it wishes to wait for those 1733 * conditions. 1734 * 1735 * Only one poll may be outstanding per device handle per tile. If more than 1736 * one tile is polling on the same device and condition, they will all be 1737 * notified when it happens. Because of this, clients may not assume that 1738 * the condition signaled is necessarily still true when they request a 1739 * subsequent service; for instance, the readable data which caused the 1740 * poll call to interrupt may have been read by another tile in the interim. 1741 * 1742 * The notification interrupt message could come directly, or via the 1743 * downcall (intctrl1) method, depending on what the tile is doing 1744 * when the condition is satisfied. Note that it is possible for the 1745 * requested interrupt to be delivered after this service is called but 1746 * before it returns. 1747 * 1748 * @param devhdl Device handle of the device to be polled. 1749 * @param events Flags denoting the events which will cause the interrupt to 1750 * be delivered (HV_DEVPOLL_xxx). 1751 * @param intarg Value which will be delivered as the intarg member of the 1752 * eventual interrupt message; the intdata member will be set to a 1753 * mask of HV_DEVPOLL_xxx values indicating which conditions have been 1754 * satisifed. 1755 * @return Zero if the interrupt was successfully scheduled; otherwise, a 1756 * negative error code. 1757 */ 1758int hv_dev_poll(int devhdl, __hv32 events, HV_IntArg intarg); 1759 1760#define HV_DEVPOLL_READ 0x1 /**< Test device for readability */ 1761#define HV_DEVPOLL_WRITE 0x2 /**< Test device for writability */ 1762#define HV_DEVPOLL_FLUSH 0x4 /**< Test device for output drained */ 1763 1764 1765/** Cancel a request for an interrupt when a device event occurs. 1766 * 1767 * This service requests that no interrupt be delivered when the events 1768 * noted in the last-issued poll() call happen. Once this service returns, 1769 * the interrupt has been canceled; however, it is possible for the interrupt 1770 * to be delivered after this service is called but before it returns. 1771 * 1772 * @param devhdl Device handle of the device on which to cancel polling. 1773 * @return Zero if the poll was successfully canceled; otherwise, a negative 1774 * error code. 1775 */ 1776int hv_dev_poll_cancel(int devhdl); 1777 1778 1779/** Scatter-gather list for preada/pwritea calls. */ 1780typedef struct 1781#if CHIP_VA_WIDTH() <= 32 1782__attribute__ ((packed, aligned(4))) 1783#endif 1784{ 1785 HV_PhysAddr pa; /**< Client physical address of the buffer segment. */ 1786 HV_PTE pte; /**< Page table entry describing the caching and location 1787 override characteristics of the buffer segment. Some 1788 drivers ignore this element and will require that 1789 the NOCACHE flag be set on their requests. */ 1790 __hv32 len; /**< Length of the buffer segment. */ 1791} HV_SGL; 1792 1793#define HV_SGL_MAXLEN 16 /**< Maximum number of entries in a scatter-gather 1794 list */ 1795 1796/** Read data from a hypervisor device asynchronously. 1797 * 1798 * This service transfers data from a hypervisor device to a memory buffer. 1799 * When the service returns, the read has been scheduled. When the read 1800 * completes, an interrupt message will be delivered, and the buffer will 1801 * not be further modified by the driver. 1802 * 1803 * The number of possible outstanding asynchronous requests is defined by 1804 * each driver, but it is recommended that it be at least two requests 1805 * per tile per device. 1806 * 1807 * No ordering is guaranteed between synchronous and asynchronous requests, 1808 * even those issued on the same tile. 1809 * 1810 * The completion interrupt message could come directly, or via the downcall 1811 * (intctrl1) method, depending on what the tile is doing when the read 1812 * completes. Interrupts do not coalesce; one is delivered for each 1813 * asynchronous I/O request. Note that it is possible for the requested 1814 * interrupt to be delivered after this service is called but before it 1815 * returns. 1816 * 1817 * Devices may choose to support both the synchronous and asynchronous read 1818 * operations, only one of them, or neither of them. 1819 * 1820 * @param devhdl Device handle of the device to be read from. 1821 * @param flags Flags (HV_DEV_xxx). 1822 * @param sgl_len Number of elements in the scatter-gather list. 1823 * @param sgl Scatter-gather list describing the memory to which data will be 1824 * written. 1825 * @param offset Driver-dependent offset. For a random-access device, this is 1826 * often a byte offset from the beginning of the device; in other cases, 1827 * like on a control device, it may have a different meaning. 1828 * @param intarg Value which will be delivered as the intarg member of the 1829 * eventual interrupt message; the intdata member will be set to the 1830 * normal return value from the read request. 1831 * @return Zero if the read was successfully scheduled; otherwise, a negative 1832 * error code. Note that some drivers may choose to pre-validate 1833 * their arguments, and may thus detect certain device error 1834 * conditions at this time rather than when the completion notification 1835 * occurs, but this is not required. 1836 */ 1837int hv_dev_preada(int devhdl, __hv32 flags, __hv32 sgl_len, 1838 HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg); 1839 1840 1841/** Write data to a hypervisor device asynchronously. 1842 * 1843 * This service transfers data from a memory buffer to a hypervisor 1844 * device. When the service returns, the write has been scheduled. 1845 * When the write completes, an interrupt message will be delivered, 1846 * and the buffer may be overwritten by the client; the data may not 1847 * necessarily have been conveyed to the actual hardware I/O interface. 1848 * 1849 * The number of possible outstanding asynchronous requests is defined by 1850 * each driver, but it is recommended that it be at least two requests 1851 * per tile per device. 1852 * 1853 * No ordering is guaranteed between synchronous and asynchronous requests, 1854 * even those issued on the same tile. 1855 * 1856 * The completion interrupt message could come directly, or via the downcall 1857 * (intctrl1) method, depending on what the tile is doing when the read 1858 * completes. Interrupts do not coalesce; one is delivered for each 1859 * asynchronous I/O request. Note that it is possible for the requested 1860 * interrupt to be delivered after this service is called but before it 1861 * returns. 1862 * 1863 * Devices may choose to support both the synchronous and asynchronous write 1864 * operations, only one of them, or neither of them. 1865 * 1866 * @param devhdl Device handle of the device to be read from. 1867 * @param flags Flags (HV_DEV_xxx). 1868 * @param sgl_len Number of elements in the scatter-gather list. 1869 * @param sgl Scatter-gather list describing the memory from which data will be 1870 * read. 1871 * @param offset Driver-dependent offset. For a random-access device, this is 1872 * often a byte offset from the beginning of the device; in other cases, 1873 * like on a control device, it may have a different meaning. 1874 * @param intarg Value which will be delivered as the intarg member of the 1875 * eventual interrupt message; the intdata member will be set to the 1876 * normal return value from the write request. 1877 * @return Zero if the write was successfully scheduled; otherwise, a negative 1878 * error code. Note that some drivers may choose to pre-validate 1879 * their arguments, and may thus detect certain device error 1880 * conditions at this time rather than when the completion notification 1881 * occurs, but this is not required. 1882 */ 1883int hv_dev_pwritea(int devhdl, __hv32 flags, __hv32 sgl_len, 1884 HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg); 1885 1886 1887/** Define a pair of tile and ASID to identify a user process context. */ 1888typedef struct 1889{ 1890 /** X coordinate, relative to supervisor's top-left coordinate */ 1891 unsigned int x:11; 1892 1893 /** Y coordinate, relative to supervisor's top-left coordinate */ 1894 unsigned int y:11; 1895 1896 /** ASID of the process on this x,y tile */ 1897 HV_ASID asid:10; 1898} HV_Remote_ASID; 1899 1900/** Flush cache and/or TLB state on remote tiles. 1901 * 1902 * @param cache_pa Client physical address to flush from cache (ignored if 1903 * the length encoded in cache_control is zero, or if 1904 * HV_FLUSH_EVICT_L2 is set, or if cache_cpumask is NULL). 1905 * @param cache_control This argument allows you to specify a length of 1906 * physical address space to flush (maximum HV_FLUSH_MAX_CACHE_LEN). 1907 * You can "or" in HV_FLUSH_EVICT_L2 to flush the whole L2 cache. 1908 * You can "or" in HV_FLUSH_EVICT_L1I to flush the whole L1I cache. 1909 * HV_FLUSH_ALL flushes all caches. 1910 * @param cache_cpumask Bitmask (in row-major order, supervisor-relative) of 1911 * tile indices to perform cache flush on. The low bit of the first 1912 * word corresponds to the tile at the upper left-hand corner of the 1913 * supervisor's rectangle. If passed as a NULL pointer, equivalent 1914 * to an empty bitmask. On chips which support hash-for-home caching, 1915 * if passed as -1, equivalent to a mask containing tiles which could 1916 * be doing hash-for-home caching. 1917 * @param tlb_va Virtual address to flush from TLB (ignored if 1918 * tlb_length is zero or tlb_cpumask is NULL). 1919 * @param tlb_length Number of bytes of data to flush from the TLB. 1920 * @param tlb_pgsize Page size to use for TLB flushes. 1921 * tlb_va and tlb_length need not be aligned to this size. 1922 * @param tlb_cpumask Bitmask for tlb flush, like cache_cpumask. 1923 * If passed as a NULL pointer, equivalent to an empty bitmask. 1924 * @param asids Pointer to an HV_Remote_ASID array of tile/ASID pairs to flush. 1925 * @param asidcount Number of HV_Remote_ASID entries in asids[]. 1926 * @return Zero for success, or else HV_EINVAL or HV_EFAULT for errors that 1927 * are detected while parsing the arguments. 1928 */ 1929int hv_flush_remote(HV_PhysAddr cache_pa, unsigned long cache_control, 1930 unsigned long* cache_cpumask, 1931 HV_VirtAddr tlb_va, unsigned long tlb_length, 1932 unsigned long tlb_pgsize, unsigned long* tlb_cpumask, 1933 HV_Remote_ASID* asids, int asidcount); 1934 1935/** Include in cache_control to ensure a flush of the entire L2. */ 1936#define HV_FLUSH_EVICT_L2 (1UL << 31) 1937 1938/** Include in cache_control to ensure a flush of the entire L1I. */ 1939#define HV_FLUSH_EVICT_L1I (1UL << 30) 1940 1941/** Maximum legal size to use for the "length" component of cache_control. */ 1942#define HV_FLUSH_MAX_CACHE_LEN ((1UL << 30) - 1) 1943 1944/** Use for cache_control to ensure a flush of all caches. */ 1945#define HV_FLUSH_ALL -1UL 1946 1947#else /* __ASSEMBLER__ */ 1948 1949/** Include in cache_control to ensure a flush of the entire L2. */ 1950#define HV_FLUSH_EVICT_L2 (1 << 31) 1951 1952/** Include in cache_control to ensure a flush of the entire L1I. */ 1953#define HV_FLUSH_EVICT_L1I (1 << 30) 1954 1955/** Maximum legal size to use for the "length" component of cache_control. */ 1956#define HV_FLUSH_MAX_CACHE_LEN ((1 << 30) - 1) 1957 1958/** Use for cache_control to ensure a flush of all caches. */ 1959#define HV_FLUSH_ALL -1 1960 1961#endif /* __ASSEMBLER__ */ 1962 1963#ifndef __ASSEMBLER__ 1964 1965/** Return a 64-bit value corresponding to the PTE if needed */ 1966#define hv_pte_val(pte) ((pte).val) 1967 1968/** Cast a 64-bit value to an HV_PTE */ 1969#define hv_pte(val) ((HV_PTE) { val }) 1970 1971#endif /* !__ASSEMBLER__ */ 1972 1973 1974/** Bits in the size of an HV_PTE */ 1975#define HV_LOG2_PTE_SIZE 3 1976 1977/** Size of an HV_PTE */ 1978#define HV_PTE_SIZE (1 << HV_LOG2_PTE_SIZE) 1979 1980 1981/* Bits in HV_PTE's low word. */ 1982#define HV_PTE_INDEX_PRESENT 0 /**< PTE is valid */ 1983#define HV_PTE_INDEX_MIGRATING 1 /**< Page is migrating */ 1984#define HV_PTE_INDEX_CLIENT0 2 /**< Page client state 0 */ 1985#define HV_PTE_INDEX_CLIENT1 3 /**< Page client state 1 */ 1986#define HV_PTE_INDEX_NC 4 /**< L1$/L2$ incoherent with L3$ */ 1987#define HV_PTE_INDEX_NO_ALLOC_L1 5 /**< Page is uncached in local L1$ */ 1988#define HV_PTE_INDEX_NO_ALLOC_L2 6 /**< Page is uncached in local L2$ */ 1989#define HV_PTE_INDEX_CACHED_PRIORITY 7 /**< Page is priority cached */ 1990#define HV_PTE_INDEX_PAGE 8 /**< PTE describes a page */ 1991#define HV_PTE_INDEX_GLOBAL 9 /**< Page is global */ 1992#define HV_PTE_INDEX_USER 10 /**< Page is user-accessible */ 1993#define HV_PTE_INDEX_ACCESSED 11 /**< Page has been accessed */ 1994#define HV_PTE_INDEX_DIRTY 12 /**< Page has been written */ 1995 /* Bits 13-14 are reserved for 1996 future use. */ 1997#define HV_PTE_INDEX_SUPER 15 /**< Pages ganged together for TLB */ 1998#define HV_PTE_INDEX_MODE 16 /**< Page mode; see HV_PTE_MODE_xxx */ 1999#define HV_PTE_MODE_BITS 3 /**< Number of bits in mode */ 2000#define HV_PTE_INDEX_CLIENT2 19 /**< Page client state 2 */ 2001#define HV_PTE_INDEX_LOTAR 20 /**< Page's LOTAR; must be high bits 2002 of word */ 2003#define HV_PTE_LOTAR_BITS 12 /**< Number of bits in a LOTAR */ 2004 2005/* Bits in HV_PTE's high word. */ 2006#define HV_PTE_INDEX_READABLE 32 /**< Page is readable */ 2007#define HV_PTE_INDEX_WRITABLE 33 /**< Page is writable */ 2008#define HV_PTE_INDEX_EXECUTABLE 34 /**< Page is executable */ 2009#define HV_PTE_INDEX_PTFN 35 /**< Page's PTFN; must be high bits 2010 of word */ 2011#define HV_PTE_PTFN_BITS 29 /**< Number of bits in a PTFN */ 2012 2013/* 2014 * Legal values for the PTE's mode field 2015 */ 2016/** Data is not resident in any caches; loads and stores access memory 2017 * directly. 2018 */ 2019#define HV_PTE_MODE_UNCACHED 1 2020 2021/** Data is resident in the tile's local L1 and/or L2 caches; if a load 2022 * or store misses there, it goes to memory. 2023 * 2024 * The copy in the local L1$/L2$ is not invalidated when the copy in 2025 * memory is changed. 2026 */ 2027#define HV_PTE_MODE_CACHE_NO_L3 2 2028 2029/** Data is resident in the tile's local L1 and/or L2 caches. If a load 2030 * or store misses there, it goes to an L3 cache in a designated tile; 2031 * if it misses there, it goes to memory. 2032 * 2033 * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated 2034 * when the copy in the remote L3$ is changed. Otherwise, such 2035 * invalidation will not occur. 2036 * 2037 * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support 2038 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is 2039 * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode. 2040 */ 2041#define HV_PTE_MODE_CACHE_TILE_L3 3 2042 2043/** Data is resident in the tile's local L1 and/or L2 caches. If a load 2044 * or store misses there, it goes to an L3 cache in one of a set of 2045 * designated tiles; if it misses there, it goes to memory. Which tile 2046 * is chosen from the set depends upon a hash function applied to the 2047 * physical address. This mode is not supported on chips for which 2048 * CHIP_HAS_CBOX_HOME_MAP() is 0. 2049 * 2050 * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated 2051 * when the copy in the remote L3$ is changed. Otherwise, such 2052 * invalidation will not occur. 2053 * 2054 * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support 2055 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is 2056 * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode. 2057 */ 2058#define HV_PTE_MODE_CACHE_HASH_L3 4 2059 2060/** Data is not resident in memory; accesses are instead made to an I/O 2061 * device, whose tile coordinates are given by the PTE's LOTAR field. 2062 * This mode is only supported on chips for which CHIP_HAS_MMIO() is 1. 2063 * The EXECUTABLE bit may not be set in an MMIO PTE. 2064 */ 2065#define HV_PTE_MODE_MMIO 5 2066 2067 2068/* C wants 1ULL so it is typed as __hv64, but the assembler needs just numbers. 2069 * The assembler can't handle shifts greater than 31, but treats them 2070 * as shifts mod 32, so assembler code must be aware of which word 2071 * the bit belongs in when using these macros. 2072 */ 2073#ifdef __ASSEMBLER__ 2074#define __HV_PTE_ONE 1 /**< One, for assembler */ 2075#else 2076#define __HV_PTE_ONE 1ULL /**< One, for C */ 2077#endif 2078 2079/** Is this PTE present? 2080 * 2081 * If this bit is set, this PTE represents a valid translation or level-2 2082 * page table pointer. Otherwise, the page table does not contain a 2083 * translation for the subject virtual pages. 2084 * 2085 * If this bit is not set, the other bits in the PTE are not 2086 * interpreted by the hypervisor, and may contain any value. 2087 */ 2088#define HV_PTE_PRESENT (__HV_PTE_ONE << HV_PTE_INDEX_PRESENT) 2089 2090/** Does this PTE map a page? 2091 * 2092 * If this bit is set in a level-0 page table, the entry should be 2093 * interpreted as a level-2 page table entry mapping a jumbo page. 2094 * 2095 * If this bit is set in a level-1 page table, the entry should be 2096 * interpreted as a level-2 page table entry mapping a large page. 2097 * 2098 * This bit should not be modified by the client while PRESENT is set, as 2099 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits. 2100 * 2101 * In a level-2 page table, this bit is ignored and must be zero. 2102 */ 2103#define HV_PTE_PAGE (__HV_PTE_ONE << HV_PTE_INDEX_PAGE) 2104 2105/** Does this PTE implicitly reference multiple pages? 2106 * 2107 * If this bit is set in the page table (either in the level-2 page table, 2108 * or in a higher level page table in conjunction with the PAGE bit) 2109 * then the PTE specifies a range of contiguous pages, not a single page. 2110 * The hv_set_pte_super_shift() allows you to specify the count for 2111 * each level of the page table. 2112 * 2113 * Note: this bit is not supported on TILEPro systems. 2114 */ 2115#define HV_PTE_SUPER (__HV_PTE_ONE << HV_PTE_INDEX_SUPER) 2116 2117/** Is this a global (non-ASID) mapping? 2118 * 2119 * If this bit is set, the translations established by this PTE will 2120 * not be flushed from the TLB by the hv_flush_asid() service; they 2121 * will be flushed by the hv_flush_page() or hv_flush_pages() services. 2122 * 2123 * Setting this bit for translations which are identical in all page 2124 * tables (for instance, code and data belonging to a client OS) can 2125 * be very beneficial, as it will reduce the number of TLB misses. 2126 * Note that, while it is not an error which will be detected by the 2127 * hypervisor, it is an extremely bad idea to set this bit for 2128 * translations which are _not_ identical in all page tables. 2129 * 2130 * This bit should not be modified by the client while PRESENT is set, as 2131 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits. 2132 * 2133 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2134 */ 2135#define HV_PTE_GLOBAL (__HV_PTE_ONE << HV_PTE_INDEX_GLOBAL) 2136 2137/** Is this mapping accessible to users? 2138 * 2139 * If this bit is set, code running at any PL will be permitted to 2140 * access the virtual addresses mapped by this PTE. Otherwise, only 2141 * code running at PL 1 or above will be allowed to do so. 2142 * 2143 * This bit should not be modified by the client while PRESENT is set, as 2144 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits. 2145 * 2146 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2147 */ 2148#define HV_PTE_USER (__HV_PTE_ONE << HV_PTE_INDEX_USER) 2149 2150/** Has this mapping been accessed? 2151 * 2152 * This bit is set by the hypervisor when the memory described by the 2153 * translation is accessed for the first time. It is never cleared by 2154 * the hypervisor, but may be cleared by the client. After the bit 2155 * has been cleared, subsequent references are not guaranteed to set 2156 * it again until the translation has been flushed from the TLB. 2157 * 2158 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2159 */ 2160#define HV_PTE_ACCESSED (__HV_PTE_ONE << HV_PTE_INDEX_ACCESSED) 2161 2162/** Is this mapping dirty? 2163 * 2164 * This bit is set by the hypervisor when the memory described by the 2165 * translation is written for the first time. It is never cleared by 2166 * the hypervisor, but may be cleared by the client. After the bit 2167 * has been cleared, subsequent references are not guaranteed to set 2168 * it again until the translation has been flushed from the TLB. 2169 * 2170 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2171 */ 2172#define HV_PTE_DIRTY (__HV_PTE_ONE << HV_PTE_INDEX_DIRTY) 2173 2174/** Migrating bit in PTE. 2175 * 2176 * This bit is guaranteed not to be inspected or modified by the 2177 * hypervisor. The name is indicative of the suggested use by the client 2178 * to tag pages whose L3 cache is being migrated from one cpu to another. 2179 */ 2180#define HV_PTE_MIGRATING (__HV_PTE_ONE << HV_PTE_INDEX_MIGRATING) 2181 2182/** Client-private bit in PTE. 2183 * 2184 * This bit is guaranteed not to be inspected or modified by the 2185 * hypervisor. 2186 */ 2187#define HV_PTE_CLIENT0 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT0) 2188 2189/** Client-private bit in PTE. 2190 * 2191 * This bit is guaranteed not to be inspected or modified by the 2192 * hypervisor. 2193 */ 2194#define HV_PTE_CLIENT1 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT1) 2195 2196/** Client-private bit in PTE. 2197 * 2198 * This bit is guaranteed not to be inspected or modified by the 2199 * hypervisor. 2200 */ 2201#define HV_PTE_CLIENT2 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT2) 2202 2203/** Non-coherent (NC) bit in PTE. 2204 * 2205 * If this bit is set, the mapping that is set up will be non-coherent 2206 * (also known as non-inclusive). This means that changes to the L3 2207 * cache will not cause a local copy to be invalidated. It is generally 2208 * recommended only for read-only mappings. 2209 * 2210 * In level-1 PTEs, if the Page bit is clear, this bit determines how the 2211 * level-2 page table is accessed. 2212 */ 2213#define HV_PTE_NC (__HV_PTE_ONE << HV_PTE_INDEX_NC) 2214 2215/** Is this page prevented from filling the L1$? 2216 * 2217 * If this bit is set, the page described by the PTE will not be cached 2218 * the local cpu's L1 cache. 2219 * 2220 * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip, 2221 * it is illegal to use this attribute, and may cause client termination. 2222 * 2223 * In level-1 PTEs, if the Page bit is clear, this bit 2224 * determines how the level-2 page table is accessed. 2225 */ 2226#define HV_PTE_NO_ALLOC_L1 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L1) 2227 2228/** Is this page prevented from filling the L2$? 2229 * 2230 * If this bit is set, the page described by the PTE will not be cached 2231 * the local cpu's L2 cache. 2232 * 2233 * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip, 2234 * it is illegal to use this attribute, and may cause client termination. 2235 * 2236 * In level-1 PTEs, if the Page bit is clear, this bit determines how the 2237 * level-2 page table is accessed. 2238 */ 2239#define HV_PTE_NO_ALLOC_L2 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L2) 2240 2241/** Is this a priority page? 2242 * 2243 * If this bit is set, the page described by the PTE will be given 2244 * priority in the cache. Normally this translates into allowing the 2245 * page to use only the "red" half of the cache. The client may wish to 2246 * then use the hv_set_caching service to specify that other pages which 2247 * alias this page will use only the "black" half of the cache. 2248 * 2249 * If the Cached Priority bit is clear, the hypervisor uses the 2250 * current hv_set_caching() value to choose how to cache the page. 2251 * 2252 * It is illegal to set the Cached Priority bit if the Non-Cached bit 2253 * is set and the Cached Remotely bit is clear, i.e. if requests to 2254 * the page map directly to memory. 2255 * 2256 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2257 */ 2258#define HV_PTE_CACHED_PRIORITY (__HV_PTE_ONE << \ 2259 HV_PTE_INDEX_CACHED_PRIORITY) 2260 2261/** Is this a readable mapping? 2262 * 2263 * If this bit is set, code will be permitted to read from (e.g., 2264 * issue load instructions against) the virtual addresses mapped by 2265 * this PTE. 2266 * 2267 * It is illegal for this bit to be clear if the Writable bit is set. 2268 * 2269 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2270 */ 2271#define HV_PTE_READABLE (__HV_PTE_ONE << HV_PTE_INDEX_READABLE) 2272 2273/** Is this a writable mapping? 2274 * 2275 * If this bit is set, code will be permitted to write to (e.g., issue 2276 * store instructions against) the virtual addresses mapped by this 2277 * PTE. 2278 * 2279 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2280 */ 2281#define HV_PTE_WRITABLE (__HV_PTE_ONE << HV_PTE_INDEX_WRITABLE) 2282 2283/** Is this an executable mapping? 2284 * 2285 * If this bit is set, code will be permitted to execute from 2286 * (e.g., jump to) the virtual addresses mapped by this PTE. 2287 * 2288 * This bit applies to any processor on the tile, if there are more 2289 * than one. 2290 * 2291 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2292 */ 2293#define HV_PTE_EXECUTABLE (__HV_PTE_ONE << HV_PTE_INDEX_EXECUTABLE) 2294 2295/** The width of a LOTAR's x or y bitfield. */ 2296#define HV_LOTAR_WIDTH 11 2297 2298/** Converts an x,y pair to a LOTAR value. */ 2299#define HV_XY_TO_LOTAR(x, y) ((HV_LOTAR)(((x) << HV_LOTAR_WIDTH) | (y))) 2300 2301/** Extracts the X component of a lotar. */ 2302#define HV_LOTAR_X(lotar) ((lotar) >> HV_LOTAR_WIDTH) 2303 2304/** Extracts the Y component of a lotar. */ 2305#define HV_LOTAR_Y(lotar) ((lotar) & ((1 << HV_LOTAR_WIDTH) - 1)) 2306 2307#ifndef __ASSEMBLER__ 2308 2309/** Define accessor functions for a PTE bit. */ 2310#define _HV_BIT(name, bit) \ 2311static __inline int \ 2312hv_pte_get_##name(HV_PTE pte) \ 2313{ \ 2314 return (pte.val >> HV_PTE_INDEX_##bit) & 1; \ 2315} \ 2316 \ 2317static __inline HV_PTE \ 2318hv_pte_set_##name(HV_PTE pte) \ 2319{ \ 2320 pte.val |= 1ULL << HV_PTE_INDEX_##bit; \ 2321 return pte; \ 2322} \ 2323 \ 2324static __inline HV_PTE \ 2325hv_pte_clear_##name(HV_PTE pte) \ 2326{ \ 2327 pte.val &= ~(1ULL << HV_PTE_INDEX_##bit); \ 2328 return pte; \ 2329} 2330 2331/* Generate accessors to get, set, and clear various PTE flags. 2332 */ 2333_HV_BIT(present, PRESENT) 2334_HV_BIT(page, PAGE) 2335_HV_BIT(super, SUPER) 2336_HV_BIT(client0, CLIENT0) 2337_HV_BIT(client1, CLIENT1) 2338_HV_BIT(client2, CLIENT2) 2339_HV_BIT(migrating, MIGRATING) 2340_HV_BIT(nc, NC) 2341_HV_BIT(readable, READABLE) 2342_HV_BIT(writable, WRITABLE) 2343_HV_BIT(executable, EXECUTABLE) 2344_HV_BIT(accessed, ACCESSED) 2345_HV_BIT(dirty, DIRTY) 2346_HV_BIT(no_alloc_l1, NO_ALLOC_L1) 2347_HV_BIT(no_alloc_l2, NO_ALLOC_L2) 2348_HV_BIT(cached_priority, CACHED_PRIORITY) 2349_HV_BIT(global, GLOBAL) 2350_HV_BIT(user, USER) 2351 2352#undef _HV_BIT 2353 2354/** Get the page mode from the PTE. 2355 * 2356 * This field generally determines whether and how accesses to the page 2357 * are cached; the HV_PTE_MODE_xxx symbols define the legal values for the 2358 * page mode. The NC, NO_ALLOC_L1, and NO_ALLOC_L2 bits modify this 2359 * general policy. 2360 */ 2361static __inline unsigned int 2362hv_pte_get_mode(const HV_PTE pte) 2363{ 2364 return (((__hv32) pte.val) >> HV_PTE_INDEX_MODE) & 2365 ((1 << HV_PTE_MODE_BITS) - 1); 2366} 2367 2368/** Set the page mode into a PTE. See hv_pte_get_mode. */ 2369static __inline HV_PTE 2370hv_pte_set_mode(HV_PTE pte, unsigned int val) 2371{ 2372 pte.val &= ~(((1ULL << HV_PTE_MODE_BITS) - 1) << HV_PTE_INDEX_MODE); 2373 pte.val |= val << HV_PTE_INDEX_MODE; 2374 return pte; 2375} 2376 2377/** Get the page frame number from the PTE. 2378 * 2379 * This field contains the upper bits of the CPA (client physical 2380 * address) of the target page; the complete CPA is this field with 2381 * HV_LOG2_PAGE_TABLE_ALIGN zero bits appended to it. 2382 * 2383 * For all PTEs in the lowest-level page table, and for all PTEs with 2384 * the Page bit set in all page tables, the CPA must be aligned modulo 2385 * the relevant page size. 2386 */ 2387static __inline unsigned long 2388hv_pte_get_ptfn(const HV_PTE pte) 2389{ 2390 return pte.val >> HV_PTE_INDEX_PTFN; 2391} 2392 2393/** Set the page table frame number into a PTE. See hv_pte_get_ptfn. */ 2394static __inline HV_PTE 2395hv_pte_set_ptfn(HV_PTE pte, unsigned long val) 2396{ 2397 pte.val &= ~(((1ULL << HV_PTE_PTFN_BITS)-1) << HV_PTE_INDEX_PTFN); 2398 pte.val |= (__hv64) val << HV_PTE_INDEX_PTFN; 2399 return pte; 2400} 2401 2402/** Get the client physical address from the PTE. See hv_pte_set_ptfn. */ 2403static __inline HV_PhysAddr 2404hv_pte_get_pa(const HV_PTE pte) 2405{ 2406 return (__hv64) hv_pte_get_ptfn(pte) << HV_LOG2_PAGE_TABLE_ALIGN; 2407} 2408 2409/** Set the client physical address into a PTE. See hv_pte_get_ptfn. */ 2410static __inline HV_PTE 2411hv_pte_set_pa(HV_PTE pte, HV_PhysAddr pa) 2412{ 2413 return hv_pte_set_ptfn(pte, pa >> HV_LOG2_PAGE_TABLE_ALIGN); 2414} 2415 2416 2417/** Get the remote tile caching this page. 2418 * 2419 * Specifies the remote tile which is providing the L3 cache for this page. 2420 * 2421 * This field is ignored unless the page mode is HV_PTE_MODE_CACHE_TILE_L3. 2422 * 2423 * In level-1 PTEs, if the Page bit is clear, this field determines how the 2424 * level-2 page table is accessed. 2425 */ 2426static __inline unsigned int 2427hv_pte_get_lotar(const HV_PTE pte) 2428{ 2429 unsigned int lotar = ((__hv32) pte.val) >> HV_PTE_INDEX_LOTAR; 2430 2431 return HV_XY_TO_LOTAR( (lotar >> (HV_PTE_LOTAR_BITS / 2)), 2432 (lotar & ((1 << (HV_PTE_LOTAR_BITS / 2)) - 1)) ); 2433} 2434 2435 2436/** Set the remote tile caching a page into a PTE. See hv_pte_get_lotar. */ 2437static __inline HV_PTE 2438hv_pte_set_lotar(HV_PTE pte, unsigned int val) 2439{ 2440 unsigned int x = HV_LOTAR_X(val); 2441 unsigned int y = HV_LOTAR_Y(val); 2442 2443 pte.val &= ~(((1ULL << HV_PTE_LOTAR_BITS)-1) << HV_PTE_INDEX_LOTAR); 2444 pte.val |= (x << (HV_PTE_INDEX_LOTAR + HV_PTE_LOTAR_BITS / 2)) | 2445 (y << HV_PTE_INDEX_LOTAR); 2446 return pte; 2447} 2448 2449#endif /* !__ASSEMBLER__ */ 2450 2451/** Converts a client physical address to a ptfn. */ 2452#define HV_CPA_TO_PTFN(p) ((p) >> HV_LOG2_PAGE_TABLE_ALIGN) 2453 2454/** Converts a ptfn to a client physical address. */ 2455#define HV_PTFN_TO_CPA(p) (((HV_PhysAddr)(p)) << HV_LOG2_PAGE_TABLE_ALIGN) 2456 2457#if CHIP_VA_WIDTH() > 32 2458 2459/* 2460 * Note that we currently do not allow customizing the page size 2461 * of the L0 pages, but fix them at 4GB, so we do not use the 2462 * "_HV_xxx" nomenclature for the L0 macros. 2463 */ 2464 2465/** Log number of HV_PTE entries in L0 page table */ 2466#define HV_LOG2_L0_ENTRIES (CHIP_VA_WIDTH() - HV_LOG2_L1_SPAN) 2467 2468/** Number of HV_PTE entries in L0 page table */ 2469#define HV_L0_ENTRIES (1 << HV_LOG2_L0_ENTRIES) 2470 2471/** Log size of L0 page table in bytes */ 2472#define HV_LOG2_L0_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L0_ENTRIES) 2473 2474/** Size of L0 page table in bytes */ 2475#define HV_L0_SIZE (1 << HV_LOG2_L0_SIZE) 2476 2477#ifdef __ASSEMBLER__ 2478 2479/** Index in L0 for a specific VA */ 2480#define HV_L0_INDEX(va) \ 2481 (((va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1)) 2482 2483#else 2484 2485/** Index in L1 for a specific VA */ 2486#define HV_L0_INDEX(va) \ 2487 (((HV_VirtAddr)(va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1)) 2488 2489#endif 2490 2491#endif /* CHIP_VA_WIDTH() > 32 */ 2492 2493/** Log number of HV_PTE entries in L1 page table */ 2494#define _HV_LOG2_L1_ENTRIES(log2_page_size_large) \ 2495 (HV_LOG2_L1_SPAN - log2_page_size_large) 2496 2497/** Number of HV_PTE entries in L1 page table */ 2498#define _HV_L1_ENTRIES(log2_page_size_large) \ 2499 (1 << _HV_LOG2_L1_ENTRIES(log2_page_size_large)) 2500 2501/** Log size of L1 page table in bytes */ 2502#define _HV_LOG2_L1_SIZE(log2_page_size_large) \ 2503 (HV_LOG2_PTE_SIZE + _HV_LOG2_L1_ENTRIES(log2_page_size_large)) 2504 2505/** Size of L1 page table in bytes */ 2506#define _HV_L1_SIZE(log2_page_size_large) \ 2507 (1 << _HV_LOG2_L1_SIZE(log2_page_size_large)) 2508 2509/** Log number of HV_PTE entries in level-2 page table */ 2510#define _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small) \ 2511 (log2_page_size_large - log2_page_size_small) 2512 2513/** Number of HV_PTE entries in level-2 page table */ 2514#define _HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) \ 2515 (1 << _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small)) 2516 2517/** Log size of level-2 page table in bytes */ 2518#define _HV_LOG2_L2_SIZE(log2_page_size_large, log2_page_size_small) \ 2519 (HV_LOG2_PTE_SIZE + \ 2520 _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small)) 2521 2522/** Size of level-2 page table in bytes */ 2523#define _HV_L2_SIZE(log2_page_size_large, log2_page_size_small) \ 2524 (1 << _HV_LOG2_L2_SIZE(log2_page_size_large, log2_page_size_small)) 2525 2526#ifdef __ASSEMBLER__ 2527 2528#if CHIP_VA_WIDTH() > 32 2529 2530/** Index in L1 for a specific VA */ 2531#define _HV_L1_INDEX(va, log2_page_size_large) \ 2532 (((va) >> log2_page_size_large) & (_HV_L1_ENTRIES(log2_page_size_large) - 1)) 2533 2534#else /* CHIP_VA_WIDTH() > 32 */ 2535 2536/** Index in L1 for a specific VA */ 2537#define _HV_L1_INDEX(va, log2_page_size_large) \ 2538 (((va) >> log2_page_size_large)) 2539 2540#endif /* CHIP_VA_WIDTH() > 32 */ 2541 2542/** Index in level-2 page table for a specific VA */ 2543#define _HV_L2_INDEX(va, log2_page_size_large, log2_page_size_small) \ 2544 (((va) >> log2_page_size_small) & \ 2545 (_HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) - 1)) 2546 2547#else /* __ASSEMBLER __ */ 2548 2549#if CHIP_VA_WIDTH() > 32 2550 2551/** Index in L1 for a specific VA */ 2552#define _HV_L1_INDEX(va, log2_page_size_large) \ 2553 (((HV_VirtAddr)(va) >> log2_page_size_large) & \ 2554 (_HV_L1_ENTRIES(log2_page_size_large) - 1)) 2555 2556#else /* CHIP_VA_WIDTH() > 32 */ 2557 2558/** Index in L1 for a specific VA */ 2559#define _HV_L1_INDEX(va, log2_page_size_large) \ 2560 (((HV_VirtAddr)(va) >> log2_page_size_large)) 2561 2562#endif /* CHIP_VA_WIDTH() > 32 */ 2563 2564/** Index in level-2 page table for a specific VA */ 2565#define _HV_L2_INDEX(va, log2_page_size_large, log2_page_size_small) \ 2566 (((HV_VirtAddr)(va) >> log2_page_size_small) & \ 2567 (_HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) - 1)) 2568 2569#endif /* __ASSEMBLER __ */ 2570 2571/** Position of the PFN field within the PTE (subset of the PTFN). */ 2572#define _HV_PTE_INDEX_PFN(log2_page_size) \ 2573 (HV_PTE_INDEX_PTFN + (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN)) 2574 2575/** Length of the PFN field within the PTE (subset of the PTFN). */ 2576#define _HV_PTE_INDEX_PFN_BITS(log2_page_size) \ 2577 (HV_PTE_INDEX_PTFN_BITS - (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN)) 2578 2579/** Converts a client physical address to a pfn. */ 2580#define _HV_CPA_TO_PFN(p, log2_page_size) ((p) >> log2_page_size) 2581 2582/** Converts a pfn to a client physical address. */ 2583#define _HV_PFN_TO_CPA(p, log2_page_size) \ 2584 (((HV_PhysAddr)(p)) << log2_page_size) 2585 2586/** Converts a ptfn to a pfn. */ 2587#define _HV_PTFN_TO_PFN(p, log2_page_size) \ 2588 ((p) >> (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN)) 2589 2590/** Converts a pfn to a ptfn. */ 2591#define _HV_PFN_TO_PTFN(p, log2_page_size) \ 2592 ((p) << (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN)) 2593 2594#endif /* _HV_HV_H */ 2595