sfi.c revision 0e6fdb5f036338bc38bf660c65c931b3e92a31d7
1/* 2 * intel_mid_sfi.c: Intel MID SFI initialization code 3 * 4 * (C) Copyright 2013 Intel Corporation 5 * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13#include <linux/init.h> 14#include <linux/kernel.h> 15#include <linux/interrupt.h> 16#include <linux/scatterlist.h> 17#include <linux/sfi.h> 18#include <linux/intel_pmic_gpio.h> 19#include <linux/spi/spi.h> 20#include <linux/i2c.h> 21#include <linux/skbuff.h> 22#include <linux/gpio.h> 23#include <linux/gpio_keys.h> 24#include <linux/input.h> 25#include <linux/platform_device.h> 26#include <linux/irq.h> 27#include <linux/module.h> 28#include <linux/notifier.h> 29#include <linux/mmc/core.h> 30#include <linux/mmc/card.h> 31#include <linux/blkdev.h> 32 33#include <asm/setup.h> 34#include <asm/mpspec_def.h> 35#include <asm/hw_irq.h> 36#include <asm/apic.h> 37#include <asm/io_apic.h> 38#include <asm/intel-mid.h> 39#include <asm/intel_mid_vrtc.h> 40#include <asm/io.h> 41#include <asm/i8259.h> 42#include <asm/intel_scu_ipc.h> 43#include <asm/apb_timer.h> 44#include <asm/reboot.h> 45#include "intel_mid_weak_decls.h" 46 47#define SFI_SIG_OEM0 "OEM0" 48#define MAX_IPCDEVS 24 49#define MAX_SCU_SPI 24 50#define MAX_SCU_I2C 24 51 52static struct platform_device *ipc_devs[MAX_IPCDEVS]; 53static struct spi_board_info *spi_devs[MAX_SCU_SPI]; 54static struct i2c_board_info *i2c_devs[MAX_SCU_I2C]; 55static struct sfi_gpio_table_entry *gpio_table; 56static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM]; 57static int ipc_next_dev; 58static int spi_next_dev; 59static int i2c_next_dev; 60static int i2c_bus[MAX_SCU_I2C]; 61static int gpio_num_entry; 62static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM]; 63int sfi_mrtc_num; 64int sfi_mtimer_num; 65 66struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX]; 67EXPORT_SYMBOL_GPL(sfi_mrtc_array); 68 69struct blocking_notifier_head intel_scu_notifier = 70 BLOCKING_NOTIFIER_INIT(intel_scu_notifier); 71EXPORT_SYMBOL_GPL(intel_scu_notifier); 72 73#define intel_mid_sfi_get_pdata(dev, priv) \ 74 ((dev)->get_platform_data ? (dev)->get_platform_data(priv) : NULL) 75 76/* parse all the mtimer info to a static mtimer array */ 77int __init sfi_parse_mtmr(struct sfi_table_header *table) 78{ 79 struct sfi_table_simple *sb; 80 struct sfi_timer_table_entry *pentry; 81 struct mpc_intsrc mp_irq; 82 int totallen; 83 84 sb = (struct sfi_table_simple *)table; 85 if (!sfi_mtimer_num) { 86 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb, 87 struct sfi_timer_table_entry); 88 pentry = (struct sfi_timer_table_entry *) sb->pentry; 89 totallen = sfi_mtimer_num * sizeof(*pentry); 90 memcpy(sfi_mtimer_array, pentry, totallen); 91 } 92 93 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num); 94 pentry = sfi_mtimer_array; 95 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) { 96 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz, irq = %d\n", 97 totallen, (u32)pentry->phys_addr, 98 pentry->freq_hz, pentry->irq); 99 if (!pentry->irq) 100 continue; 101 mp_irq.type = MP_INTSRC; 102 mp_irq.irqtype = mp_INT; 103/* triggering mode edge bit 2-3, active high polarity bit 0-1 */ 104 mp_irq.irqflag = 5; 105 mp_irq.srcbus = MP_BUS_ISA; 106 mp_irq.srcbusirq = pentry->irq; /* IRQ */ 107 mp_irq.dstapic = MP_APIC_ALL; 108 mp_irq.dstirq = pentry->irq; 109 mp_save_irq(&mp_irq); 110 } 111 112 return 0; 113} 114 115struct sfi_timer_table_entry *sfi_get_mtmr(int hint) 116{ 117 int i; 118 if (hint < sfi_mtimer_num) { 119 if (!sfi_mtimer_usage[hint]) { 120 pr_debug("hint taken for timer %d irq %d\n", 121 hint, sfi_mtimer_array[hint].irq); 122 sfi_mtimer_usage[hint] = 1; 123 return &sfi_mtimer_array[hint]; 124 } 125 } 126 /* take the first timer available */ 127 for (i = 0; i < sfi_mtimer_num;) { 128 if (!sfi_mtimer_usage[i]) { 129 sfi_mtimer_usage[i] = 1; 130 return &sfi_mtimer_array[i]; 131 } 132 i++; 133 } 134 return NULL; 135} 136 137void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr) 138{ 139 int i; 140 for (i = 0; i < sfi_mtimer_num;) { 141 if (mtmr->irq == sfi_mtimer_array[i].irq) { 142 sfi_mtimer_usage[i] = 0; 143 return; 144 } 145 i++; 146 } 147} 148 149/* parse all the mrtc info to a global mrtc array */ 150int __init sfi_parse_mrtc(struct sfi_table_header *table) 151{ 152 struct sfi_table_simple *sb; 153 struct sfi_rtc_table_entry *pentry; 154 struct mpc_intsrc mp_irq; 155 156 int totallen; 157 158 sb = (struct sfi_table_simple *)table; 159 if (!sfi_mrtc_num) { 160 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb, 161 struct sfi_rtc_table_entry); 162 pentry = (struct sfi_rtc_table_entry *)sb->pentry; 163 totallen = sfi_mrtc_num * sizeof(*pentry); 164 memcpy(sfi_mrtc_array, pentry, totallen); 165 } 166 167 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num); 168 pentry = sfi_mrtc_array; 169 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) { 170 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n", 171 totallen, (u32)pentry->phys_addr, pentry->irq); 172 mp_irq.type = MP_INTSRC; 173 mp_irq.irqtype = mp_INT; 174 mp_irq.irqflag = 0xf; /* level trigger and active low */ 175 mp_irq.srcbus = MP_BUS_ISA; 176 mp_irq.srcbusirq = pentry->irq; /* IRQ */ 177 mp_irq.dstapic = MP_APIC_ALL; 178 mp_irq.dstirq = pentry->irq; 179 mp_save_irq(&mp_irq); 180 } 181 return 0; 182} 183 184 185/* 186 * Parsing GPIO table first, since the DEVS table will need this table 187 * to map the pin name to the actual pin. 188 */ 189static int __init sfi_parse_gpio(struct sfi_table_header *table) 190{ 191 struct sfi_table_simple *sb; 192 struct sfi_gpio_table_entry *pentry; 193 int num, i; 194 195 if (gpio_table) 196 return 0; 197 sb = (struct sfi_table_simple *)table; 198 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry); 199 pentry = (struct sfi_gpio_table_entry *)sb->pentry; 200 201 gpio_table = kmalloc(num * sizeof(*pentry), GFP_KERNEL); 202 if (!gpio_table) 203 return -1; 204 memcpy(gpio_table, pentry, num * sizeof(*pentry)); 205 gpio_num_entry = num; 206 207 pr_debug("GPIO pin info:\n"); 208 for (i = 0; i < num; i++, pentry++) 209 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s," 210 " pin = %d\n", i, 211 pentry->controller_name, 212 pentry->pin_name, 213 pentry->pin_no); 214 return 0; 215} 216 217int get_gpio_by_name(const char *name) 218{ 219 struct sfi_gpio_table_entry *pentry = gpio_table; 220 int i; 221 222 if (!pentry) 223 return -1; 224 for (i = 0; i < gpio_num_entry; i++, pentry++) { 225 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN)) 226 return pentry->pin_no; 227 } 228 return -1; 229} 230 231void __init intel_scu_device_register(struct platform_device *pdev) 232{ 233 if (ipc_next_dev == MAX_IPCDEVS) 234 pr_err("too many SCU IPC devices"); 235 else 236 ipc_devs[ipc_next_dev++] = pdev; 237} 238 239static void __init intel_scu_spi_device_register(struct spi_board_info *sdev) 240{ 241 struct spi_board_info *new_dev; 242 243 if (spi_next_dev == MAX_SCU_SPI) { 244 pr_err("too many SCU SPI devices"); 245 return; 246 } 247 248 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL); 249 if (!new_dev) { 250 pr_err("failed to alloc mem for delayed spi dev %s\n", 251 sdev->modalias); 252 return; 253 } 254 memcpy(new_dev, sdev, sizeof(*sdev)); 255 256 spi_devs[spi_next_dev++] = new_dev; 257} 258 259static void __init intel_scu_i2c_device_register(int bus, 260 struct i2c_board_info *idev) 261{ 262 struct i2c_board_info *new_dev; 263 264 if (i2c_next_dev == MAX_SCU_I2C) { 265 pr_err("too many SCU I2C devices"); 266 return; 267 } 268 269 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL); 270 if (!new_dev) { 271 pr_err("failed to alloc mem for delayed i2c dev %s\n", 272 idev->type); 273 return; 274 } 275 memcpy(new_dev, idev, sizeof(*idev)); 276 277 i2c_bus[i2c_next_dev] = bus; 278 i2c_devs[i2c_next_dev++] = new_dev; 279} 280 281/* Called by IPC driver */ 282void intel_scu_devices_create(void) 283{ 284 int i; 285 286 for (i = 0; i < ipc_next_dev; i++) 287 platform_device_add(ipc_devs[i]); 288 289 for (i = 0; i < spi_next_dev; i++) 290 spi_register_board_info(spi_devs[i], 1); 291 292 for (i = 0; i < i2c_next_dev; i++) { 293 struct i2c_adapter *adapter; 294 struct i2c_client *client; 295 296 adapter = i2c_get_adapter(i2c_bus[i]); 297 if (adapter) { 298 client = i2c_new_device(adapter, i2c_devs[i]); 299 if (!client) 300 pr_err("can't create i2c device %s\n", 301 i2c_devs[i]->type); 302 } else 303 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1); 304 } 305 intel_scu_notifier_post(SCU_AVAILABLE, NULL); 306} 307EXPORT_SYMBOL_GPL(intel_scu_devices_create); 308 309/* Called by IPC driver */ 310void intel_scu_devices_destroy(void) 311{ 312 int i; 313 314 intel_scu_notifier_post(SCU_DOWN, NULL); 315 316 for (i = 0; i < ipc_next_dev; i++) 317 platform_device_del(ipc_devs[i]); 318} 319EXPORT_SYMBOL_GPL(intel_scu_devices_destroy); 320 321static void __init install_irq_resource(struct platform_device *pdev, int irq) 322{ 323 /* Single threaded */ 324 static struct resource res __initdata = { 325 .name = "IRQ", 326 .flags = IORESOURCE_IRQ, 327 }; 328 res.start = irq; 329 platform_device_add_resources(pdev, &res, 1); 330} 331 332static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry, 333 struct devs_id *dev) 334{ 335 struct platform_device *pdev; 336 void *pdata = NULL; 337 338 pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n", 339 pentry->name, pentry->irq); 340 pdata = intel_mid_sfi_get_pdata(dev, pentry); 341 342 pdev = platform_device_alloc(pentry->name, 0); 343 if (pdev == NULL) { 344 pr_err("out of memory for SFI platform device '%s'.\n", 345 pentry->name); 346 return; 347 } 348 install_irq_resource(pdev, pentry->irq); 349 350 pdev->dev.platform_data = pdata; 351 platform_device_add(pdev); 352} 353 354static void __init sfi_handle_spi_dev(struct sfi_device_table_entry *pentry, 355 struct devs_id *dev) 356{ 357 struct spi_board_info spi_info; 358 void *pdata = NULL; 359 360 memset(&spi_info, 0, sizeof(spi_info)); 361 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN); 362 spi_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq); 363 spi_info.bus_num = pentry->host_num; 364 spi_info.chip_select = pentry->addr; 365 spi_info.max_speed_hz = pentry->max_freq; 366 pr_debug("SPI bus=%d, name=%16.16s, irq=0x%2x, max_freq=%d, cs=%d\n", 367 spi_info.bus_num, 368 spi_info.modalias, 369 spi_info.irq, 370 spi_info.max_speed_hz, 371 spi_info.chip_select); 372 373 pdata = intel_mid_sfi_get_pdata(dev, &spi_info); 374 375 spi_info.platform_data = pdata; 376 if (dev->delay) 377 intel_scu_spi_device_register(&spi_info); 378 else 379 spi_register_board_info(&spi_info, 1); 380} 381 382static void __init sfi_handle_i2c_dev(struct sfi_device_table_entry *pentry, 383 struct devs_id *dev) 384{ 385 struct i2c_board_info i2c_info; 386 void *pdata = NULL; 387 388 memset(&i2c_info, 0, sizeof(i2c_info)); 389 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN); 390 i2c_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq); 391 i2c_info.addr = pentry->addr; 392 pr_debug("I2C bus = %d, name = %16.16s, irq = 0x%2x, addr = 0x%x\n", 393 pentry->host_num, 394 i2c_info.type, 395 i2c_info.irq, 396 i2c_info.addr); 397 pdata = intel_mid_sfi_get_pdata(dev, &i2c_info); 398 i2c_info.platform_data = pdata; 399 400 if (dev->delay) 401 intel_scu_i2c_device_register(pentry->host_num, &i2c_info); 402 else 403 i2c_register_board_info(pentry->host_num, &i2c_info, 1); 404} 405 406static struct devs_id __init *get_device_id(u8 type, char *name) 407{ 408 struct devs_id *dev = device_ids; 409 410 if (device_ids == NULL) 411 return NULL; 412 413 while (dev->name[0]) { 414 if (dev->type == type && 415 !strncmp(dev->name, name, SFI_NAME_LEN)) { 416 return dev; 417 } 418 dev++; 419 } 420 421 return NULL; 422} 423 424static int __init sfi_parse_devs(struct sfi_table_header *table) 425{ 426 struct sfi_table_simple *sb; 427 struct sfi_device_table_entry *pentry; 428 struct devs_id *dev = NULL; 429 int num, i; 430 int ioapic; 431 struct io_apic_irq_attr irq_attr; 432 433 sb = (struct sfi_table_simple *)table; 434 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry); 435 pentry = (struct sfi_device_table_entry *)sb->pentry; 436 437 for (i = 0; i < num; i++, pentry++) { 438 int irq = pentry->irq; 439 440 if (irq != (u8)0xff) { /* native RTE case */ 441 /* these SPI2 devices are not exposed to system as PCI 442 * devices, but they have separate RTE entry in IOAPIC 443 * so we have to enable them one by one here 444 */ 445 ioapic = mp_find_ioapic(irq); 446 irq_attr.ioapic = ioapic; 447 irq_attr.ioapic_pin = irq; 448 irq_attr.trigger = 1; 449 irq_attr.polarity = 1; 450 io_apic_set_pci_routing(NULL, irq, &irq_attr); 451 } else 452 irq = 0; /* No irq */ 453 454 dev = get_device_id(pentry->type, pentry->name); 455 456 if (!dev) 457 continue; 458 459 if (dev->device_handler) { 460 dev->device_handler(pentry, dev); 461 } else { 462 switch (pentry->type) { 463 case SFI_DEV_TYPE_IPC: 464 sfi_handle_ipc_dev(pentry, dev); 465 break; 466 case SFI_DEV_TYPE_SPI: 467 sfi_handle_spi_dev(pentry, dev); 468 break; 469 case SFI_DEV_TYPE_I2C: 470 sfi_handle_i2c_dev(pentry, dev); 471 break; 472 case SFI_DEV_TYPE_UART: 473 case SFI_DEV_TYPE_HSI: 474 default: 475 break; 476 } 477 } 478 } 479 return 0; 480} 481 482static int __init intel_mid_platform_init(void) 483{ 484 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio); 485 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs); 486 return 0; 487} 488arch_initcall(intel_mid_platform_init); 489