intel-gtt.c revision 00fe639a56b40930bf27eabeef9a826344d8f4c4
1/* 2 * Intel GTT (Graphics Translation Table) routines 3 * 4 * Caveat: This driver implements the linux agp interface, but this is far from 5 * a agp driver! GTT support ended up here for purely historical reasons: The 6 * old userspace intel graphics drivers needed an interface to map memory into 7 * the GTT. And the drm provides a default interface for graphic devices sitting 8 * on an agp port. So it made sense to fake the GTT support as an agp port to 9 * avoid having to create a new api. 10 * 11 * With gem this does not make much sense anymore, just needlessly complicates 12 * the code. But as long as the old graphics stack is still support, it's stuck 13 * here. 14 * 15 * /fairy-tale-mode off 16 */ 17 18#include <linux/module.h> 19#include <linux/pci.h> 20#include <linux/init.h> 21#include <linux/kernel.h> 22#include <linux/pagemap.h> 23#include <linux/agp_backend.h> 24#include <linux/delay.h> 25#include <asm/smp.h> 26#include "agp.h" 27#include "intel-agp.h" 28#include <drm/intel-gtt.h> 29 30/* 31 * If we have Intel graphics, we're not going to have anything other than 32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). 34 * Only newer chipsets need to bother with this, of course. 35 */ 36#ifdef CONFIG_INTEL_IOMMU 37#define USE_PCI_DMA_API 1 38#else 39#define USE_PCI_DMA_API 0 40#endif 41 42struct intel_gtt_driver { 43 unsigned int gen : 8; 44 unsigned int is_g33 : 1; 45 unsigned int is_pineview : 1; 46 unsigned int is_ironlake : 1; 47 unsigned int has_pgtbl_enable : 1; 48 unsigned int dma_mask_size : 8; 49 /* Chipset specific GTT setup */ 50 int (*setup)(void); 51 /* This should undo anything done in ->setup() save the unmapping 52 * of the mmio register file, that's done in the generic code. */ 53 void (*cleanup)(void); 54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 55 /* Flags is a more or less chipset specific opaque value. 56 * For chipsets that need to support old ums (non-gem) code, this 57 * needs to be identical to the various supported agp memory types! */ 58 bool (*check_flags)(unsigned int flags); 59 void (*chipset_flush)(void); 60}; 61 62static struct _intel_private { 63 const struct intel_gtt_driver *driver; 64 struct pci_dev *pcidev; /* device one */ 65 struct pci_dev *bridge_dev; 66 u8 __iomem *registers; 67 phys_addr_t gtt_bus_addr; 68 u32 PGETBL_save; 69 u32 __iomem *gtt; /* I915G */ 70 bool clear_fake_agp; /* on first access via agp, fill with scratch */ 71 int num_dcache_entries; 72 void __iomem *i9xx_flush_page; 73 char *i81x_gtt_table; 74 struct resource ifp_resource; 75 int resource_valid; 76 struct page *scratch_page; 77 phys_addr_t scratch_page_dma; 78 int refcount; 79 /* Whether i915 needs to use the dmar apis or not. */ 80 unsigned int needs_dmar : 1; 81 phys_addr_t gma_bus_addr; 82 /* Size of memory reserved for graphics by the BIOS */ 83 unsigned int stolen_size; 84 /* Total number of gtt entries. */ 85 unsigned int gtt_total_entries; 86 /* Part of the gtt that is mappable by the cpu, for those chips where 87 * this is not the full gtt. */ 88 unsigned int gtt_mappable_entries; 89} intel_private; 90 91#define INTEL_GTT_GEN intel_private.driver->gen 92#define IS_G33 intel_private.driver->is_g33 93#define IS_PINEVIEW intel_private.driver->is_pineview 94#define IS_IRONLAKE intel_private.driver->is_ironlake 95#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 96 97#if IS_ENABLED(CONFIG_AGP_INTEL) 98static int intel_gtt_map_memory(struct page **pages, 99 unsigned int num_entries, 100 struct sg_table *st) 101{ 102 struct scatterlist *sg; 103 int i; 104 105 DBG("try mapping %lu pages\n", (unsigned long)num_entries); 106 107 if (sg_alloc_table(st, num_entries, GFP_KERNEL)) 108 goto err; 109 110 for_each_sg(st->sgl, sg, num_entries, i) 111 sg_set_page(sg, pages[i], PAGE_SIZE, 0); 112 113 if (!pci_map_sg(intel_private.pcidev, 114 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL)) 115 goto err; 116 117 return 0; 118 119err: 120 sg_free_table(st); 121 return -ENOMEM; 122} 123 124static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) 125{ 126 struct sg_table st; 127 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 128 129 pci_unmap_sg(intel_private.pcidev, sg_list, 130 num_sg, PCI_DMA_BIDIRECTIONAL); 131 132 st.sgl = sg_list; 133 st.orig_nents = st.nents = num_sg; 134 135 sg_free_table(&st); 136} 137 138static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 139{ 140 return; 141} 142 143/* Exists to support ARGB cursors */ 144static struct page *i8xx_alloc_pages(void) 145{ 146 struct page *page; 147 148 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 149 if (page == NULL) 150 return NULL; 151 152 if (set_pages_uc(page, 4) < 0) { 153 set_pages_wb(page, 4); 154 __free_pages(page, 2); 155 return NULL; 156 } 157 get_page(page); 158 atomic_inc(&agp_bridge->current_memory_agp); 159 return page; 160} 161 162static void i8xx_destroy_pages(struct page *page) 163{ 164 if (page == NULL) 165 return; 166 167 set_pages_wb(page, 4); 168 put_page(page); 169 __free_pages(page, 2); 170 atomic_dec(&agp_bridge->current_memory_agp); 171} 172#endif 173 174#define I810_GTT_ORDER 4 175static int i810_setup(void) 176{ 177 u32 reg_addr; 178 char *gtt_table; 179 180 /* i81x does not preallocate the gtt. It's always 64kb in size. */ 181 gtt_table = alloc_gatt_pages(I810_GTT_ORDER); 182 if (gtt_table == NULL) 183 return -ENOMEM; 184 intel_private.i81x_gtt_table = gtt_table; 185 186 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 187 reg_addr &= 0xfff80000; 188 189 intel_private.registers = ioremap(reg_addr, KB(64)); 190 if (!intel_private.registers) 191 return -ENOMEM; 192 193 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 194 intel_private.registers+I810_PGETBL_CTL); 195 196 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 197 198 if ((readl(intel_private.registers+I810_DRAM_CTL) 199 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 200 dev_info(&intel_private.pcidev->dev, 201 "detected 4MB dedicated video ram\n"); 202 intel_private.num_dcache_entries = 1024; 203 } 204 205 return 0; 206} 207 208static void i810_cleanup(void) 209{ 210 writel(0, intel_private.registers+I810_PGETBL_CTL); 211 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 212} 213 214#if IS_ENABLED(CONFIG_AGP_INTEL) 215static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 216 int type) 217{ 218 int i; 219 220 if ((pg_start + mem->page_count) 221 > intel_private.num_dcache_entries) 222 return -EINVAL; 223 224 if (!mem->is_flushed) 225 global_cache_flush(); 226 227 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 228 dma_addr_t addr = i << PAGE_SHIFT; 229 intel_private.driver->write_entry(addr, 230 i, type); 231 } 232 readl(intel_private.gtt+i-1); 233 234 return 0; 235} 236 237/* 238 * The i810/i830 requires a physical address to program its mouse 239 * pointer into hardware. 240 * However the Xserver still writes to it through the agp aperture. 241 */ 242static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 243{ 244 struct agp_memory *new; 245 struct page *page; 246 247 switch (pg_count) { 248 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 249 break; 250 case 4: 251 /* kludge to get 4 physical pages for ARGB cursor */ 252 page = i8xx_alloc_pages(); 253 break; 254 default: 255 return NULL; 256 } 257 258 if (page == NULL) 259 return NULL; 260 261 new = agp_create_memory(pg_count); 262 if (new == NULL) 263 return NULL; 264 265 new->pages[0] = page; 266 if (pg_count == 4) { 267 /* kludge to get 4 physical pages for ARGB cursor */ 268 new->pages[1] = new->pages[0] + 1; 269 new->pages[2] = new->pages[1] + 1; 270 new->pages[3] = new->pages[2] + 1; 271 } 272 new->page_count = pg_count; 273 new->num_scratch_pages = pg_count; 274 new->type = AGP_PHYS_MEMORY; 275 new->physical = page_to_phys(new->pages[0]); 276 return new; 277} 278 279static void intel_i810_free_by_type(struct agp_memory *curr) 280{ 281 agp_free_key(curr->key); 282 if (curr->type == AGP_PHYS_MEMORY) { 283 if (curr->page_count == 4) 284 i8xx_destroy_pages(curr->pages[0]); 285 else { 286 agp_bridge->driver->agp_destroy_page(curr->pages[0], 287 AGP_PAGE_DESTROY_UNMAP); 288 agp_bridge->driver->agp_destroy_page(curr->pages[0], 289 AGP_PAGE_DESTROY_FREE); 290 } 291 agp_free_page_array(curr); 292 } 293 kfree(curr); 294} 295#endif 296 297static int intel_gtt_setup_scratch_page(void) 298{ 299 struct page *page; 300 dma_addr_t dma_addr; 301 302 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 303 if (page == NULL) 304 return -ENOMEM; 305 get_page(page); 306 set_pages_uc(page, 1); 307 308 if (intel_private.needs_dmar) { 309 dma_addr = pci_map_page(intel_private.pcidev, page, 0, 310 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 311 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 312 return -EINVAL; 313 314 intel_private.scratch_page_dma = dma_addr; 315 } else 316 intel_private.scratch_page_dma = page_to_phys(page); 317 318 intel_private.scratch_page = page; 319 320 return 0; 321} 322 323static void i810_write_entry(dma_addr_t addr, unsigned int entry, 324 unsigned int flags) 325{ 326 u32 pte_flags = I810_PTE_VALID; 327 328 switch (flags) { 329 case AGP_DCACHE_MEMORY: 330 pte_flags |= I810_PTE_LOCAL; 331 break; 332 case AGP_USER_CACHED_MEMORY: 333 pte_flags |= I830_PTE_SYSTEM_CACHED; 334 break; 335 } 336 337 writel(addr | pte_flags, intel_private.gtt + entry); 338} 339 340static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { 341 {32, 8192, 3}, 342 {64, 16384, 4}, 343 {128, 32768, 5}, 344 {256, 65536, 6}, 345 {512, 131072, 7}, 346}; 347 348static unsigned int intel_gtt_stolen_size(void) 349{ 350 u16 gmch_ctrl; 351 u8 rdct; 352 int local = 0; 353 static const int ddt[4] = { 0, 16, 32, 64 }; 354 unsigned int stolen_size = 0; 355 356 if (INTEL_GTT_GEN == 1) 357 return 0; /* no stolen mem on i81x */ 358 359 pci_read_config_word(intel_private.bridge_dev, 360 I830_GMCH_CTRL, &gmch_ctrl); 361 362 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 363 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 364 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 365 case I830_GMCH_GMS_STOLEN_512: 366 stolen_size = KB(512); 367 break; 368 case I830_GMCH_GMS_STOLEN_1024: 369 stolen_size = MB(1); 370 break; 371 case I830_GMCH_GMS_STOLEN_8192: 372 stolen_size = MB(8); 373 break; 374 case I830_GMCH_GMS_LOCAL: 375 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 376 stolen_size = (I830_RDRAM_ND(rdct) + 1) * 377 MB(ddt[I830_RDRAM_DDT(rdct)]); 378 local = 1; 379 break; 380 default: 381 stolen_size = 0; 382 break; 383 } 384 } else { 385 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 386 case I855_GMCH_GMS_STOLEN_1M: 387 stolen_size = MB(1); 388 break; 389 case I855_GMCH_GMS_STOLEN_4M: 390 stolen_size = MB(4); 391 break; 392 case I855_GMCH_GMS_STOLEN_8M: 393 stolen_size = MB(8); 394 break; 395 case I855_GMCH_GMS_STOLEN_16M: 396 stolen_size = MB(16); 397 break; 398 case I855_GMCH_GMS_STOLEN_32M: 399 stolen_size = MB(32); 400 break; 401 case I915_GMCH_GMS_STOLEN_48M: 402 stolen_size = MB(48); 403 break; 404 case I915_GMCH_GMS_STOLEN_64M: 405 stolen_size = MB(64); 406 break; 407 case G33_GMCH_GMS_STOLEN_128M: 408 stolen_size = MB(128); 409 break; 410 case G33_GMCH_GMS_STOLEN_256M: 411 stolen_size = MB(256); 412 break; 413 case INTEL_GMCH_GMS_STOLEN_96M: 414 stolen_size = MB(96); 415 break; 416 case INTEL_GMCH_GMS_STOLEN_160M: 417 stolen_size = MB(160); 418 break; 419 case INTEL_GMCH_GMS_STOLEN_224M: 420 stolen_size = MB(224); 421 break; 422 case INTEL_GMCH_GMS_STOLEN_352M: 423 stolen_size = MB(352); 424 break; 425 default: 426 stolen_size = 0; 427 break; 428 } 429 } 430 431 if (stolen_size > 0) { 432 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 433 stolen_size / KB(1), local ? "local" : "stolen"); 434 } else { 435 dev_info(&intel_private.bridge_dev->dev, 436 "no pre-allocated video memory detected\n"); 437 stolen_size = 0; 438 } 439 440 return stolen_size; 441} 442 443static void i965_adjust_pgetbl_size(unsigned int size_flag) 444{ 445 u32 pgetbl_ctl, pgetbl_ctl2; 446 447 /* ensure that ppgtt is disabled */ 448 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); 449 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; 450 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); 451 452 /* write the new ggtt size */ 453 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 454 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; 455 pgetbl_ctl |= size_flag; 456 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); 457} 458 459static unsigned int i965_gtt_total_entries(void) 460{ 461 int size; 462 u32 pgetbl_ctl; 463 u16 gmch_ctl; 464 465 pci_read_config_word(intel_private.bridge_dev, 466 I830_GMCH_CTRL, &gmch_ctl); 467 468 if (INTEL_GTT_GEN == 5) { 469 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { 470 case G4x_GMCH_SIZE_1M: 471 case G4x_GMCH_SIZE_VT_1M: 472 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); 473 break; 474 case G4x_GMCH_SIZE_VT_1_5M: 475 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); 476 break; 477 case G4x_GMCH_SIZE_2M: 478 case G4x_GMCH_SIZE_VT_2M: 479 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); 480 break; 481 } 482 } 483 484 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 485 486 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 487 case I965_PGETBL_SIZE_128KB: 488 size = KB(128); 489 break; 490 case I965_PGETBL_SIZE_256KB: 491 size = KB(256); 492 break; 493 case I965_PGETBL_SIZE_512KB: 494 size = KB(512); 495 break; 496 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 497 case I965_PGETBL_SIZE_1MB: 498 size = KB(1024); 499 break; 500 case I965_PGETBL_SIZE_2MB: 501 size = KB(2048); 502 break; 503 case I965_PGETBL_SIZE_1_5MB: 504 size = KB(1024 + 512); 505 break; 506 default: 507 dev_info(&intel_private.pcidev->dev, 508 "unknown page table size, assuming 512KB\n"); 509 size = KB(512); 510 } 511 512 return size/4; 513} 514 515static unsigned int intel_gtt_total_entries(void) 516{ 517 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 518 return i965_gtt_total_entries(); 519 else { 520 /* On previous hardware, the GTT size was just what was 521 * required to map the aperture. 522 */ 523 return intel_private.gtt_mappable_entries; 524 } 525} 526 527static unsigned int intel_gtt_mappable_entries(void) 528{ 529 unsigned int aperture_size; 530 531 if (INTEL_GTT_GEN == 1) { 532 u32 smram_miscc; 533 534 pci_read_config_dword(intel_private.bridge_dev, 535 I810_SMRAM_MISCC, &smram_miscc); 536 537 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) 538 == I810_GFX_MEM_WIN_32M) 539 aperture_size = MB(32); 540 else 541 aperture_size = MB(64); 542 } else if (INTEL_GTT_GEN == 2) { 543 u16 gmch_ctrl; 544 545 pci_read_config_word(intel_private.bridge_dev, 546 I830_GMCH_CTRL, &gmch_ctrl); 547 548 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 549 aperture_size = MB(64); 550 else 551 aperture_size = MB(128); 552 } else { 553 /* 9xx supports large sizes, just look at the length */ 554 aperture_size = pci_resource_len(intel_private.pcidev, 2); 555 } 556 557 return aperture_size >> PAGE_SHIFT; 558} 559 560static void intel_gtt_teardown_scratch_page(void) 561{ 562 set_pages_wb(intel_private.scratch_page, 1); 563 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, 564 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 565 put_page(intel_private.scratch_page); 566 __free_page(intel_private.scratch_page); 567} 568 569static void intel_gtt_cleanup(void) 570{ 571 intel_private.driver->cleanup(); 572 573 iounmap(intel_private.gtt); 574 iounmap(intel_private.registers); 575 576 intel_gtt_teardown_scratch_page(); 577} 578 579/* Certain Gen5 chipsets require require idling the GPU before 580 * unmapping anything from the GTT when VT-d is enabled. 581 */ 582static inline int needs_ilk_vtd_wa(void) 583{ 584#ifdef CONFIG_INTEL_IOMMU 585 const unsigned short gpu_devid = intel_private.pcidev->device; 586 587 /* Query intel_iommu to see if we need the workaround. Presumably that 588 * was loaded first. 589 */ 590 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || 591 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && 592 intel_iommu_gfx_mapped) 593 return 1; 594#endif 595 return 0; 596} 597 598static bool intel_gtt_can_wc(void) 599{ 600 if (INTEL_GTT_GEN <= 2) 601 return false; 602 603 if (INTEL_GTT_GEN >= 6) 604 return false; 605 606 /* Reports of major corruption with ILK vt'd enabled */ 607 if (needs_ilk_vtd_wa()) 608 return false; 609 610 return true; 611} 612 613static int intel_gtt_init(void) 614{ 615 u32 gma_addr; 616 u32 gtt_map_size; 617 int ret; 618 619 ret = intel_private.driver->setup(); 620 if (ret != 0) 621 return ret; 622 623 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries(); 624 intel_private.gtt_total_entries = intel_gtt_total_entries(); 625 626 /* save the PGETBL reg for resume */ 627 intel_private.PGETBL_save = 628 readl(intel_private.registers+I810_PGETBL_CTL) 629 & ~I810_PGETBL_ENABLED; 630 /* we only ever restore the register when enabling the PGTBL... */ 631 if (HAS_PGTBL_EN) 632 intel_private.PGETBL_save |= I810_PGETBL_ENABLED; 633 634 dev_info(&intel_private.bridge_dev->dev, 635 "detected gtt size: %dK total, %dK mappable\n", 636 intel_private.gtt_total_entries * 4, 637 intel_private.gtt_mappable_entries * 4); 638 639 gtt_map_size = intel_private.gtt_total_entries * 4; 640 641 intel_private.gtt = NULL; 642 if (intel_gtt_can_wc()) 643 intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, 644 gtt_map_size); 645 if (intel_private.gtt == NULL) 646 intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 647 gtt_map_size); 648 if (intel_private.gtt == NULL) { 649 intel_private.driver->cleanup(); 650 iounmap(intel_private.registers); 651 return -ENOMEM; 652 } 653 654#if IS_ENABLED(CONFIG_AGP_INTEL) 655 global_cache_flush(); /* FIXME: ? */ 656#endif 657 658 intel_private.stolen_size = intel_gtt_stolen_size(); 659 660 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; 661 662 ret = intel_gtt_setup_scratch_page(); 663 if (ret != 0) { 664 intel_gtt_cleanup(); 665 return ret; 666 } 667 668 if (INTEL_GTT_GEN <= 2) 669 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 670 &gma_addr); 671 else 672 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 673 &gma_addr); 674 675 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 676 677 return 0; 678} 679 680#if IS_ENABLED(CONFIG_AGP_INTEL) 681static int intel_fake_agp_fetch_size(void) 682{ 683 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 684 unsigned int aper_size; 685 int i; 686 687 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1); 688 689 for (i = 0; i < num_sizes; i++) { 690 if (aper_size == intel_fake_agp_sizes[i].size) { 691 agp_bridge->current_size = 692 (void *) (intel_fake_agp_sizes + i); 693 return aper_size; 694 } 695 } 696 697 return 0; 698} 699#endif 700 701static void i830_cleanup(void) 702{ 703} 704 705/* The chipset_flush interface needs to get data that has already been 706 * flushed out of the CPU all the way out to main memory, because the GPU 707 * doesn't snoop those buffers. 708 * 709 * The 8xx series doesn't have the same lovely interface for flushing the 710 * chipset write buffers that the later chips do. According to the 865 711 * specs, it's 64 octwords, or 1KB. So, to get those previous things in 712 * that buffer out, we just fill 1KB and clflush it out, on the assumption 713 * that it'll push whatever was in there out. It appears to work. 714 */ 715static void i830_chipset_flush(void) 716{ 717 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 718 719 /* Forcibly evict everything from the CPU write buffers. 720 * clflush appears to be insufficient. 721 */ 722 wbinvd_on_all_cpus(); 723 724 /* Now we've only seen documents for this magic bit on 855GM, 725 * we hope it exists for the other gen2 chipsets... 726 * 727 * Also works as advertised on my 845G. 728 */ 729 writel(readl(intel_private.registers+I830_HIC) | (1<<31), 730 intel_private.registers+I830_HIC); 731 732 while (readl(intel_private.registers+I830_HIC) & (1<<31)) { 733 if (time_after(jiffies, timeout)) 734 break; 735 736 udelay(50); 737 } 738} 739 740static void i830_write_entry(dma_addr_t addr, unsigned int entry, 741 unsigned int flags) 742{ 743 u32 pte_flags = I810_PTE_VALID; 744 745 if (flags == AGP_USER_CACHED_MEMORY) 746 pte_flags |= I830_PTE_SYSTEM_CACHED; 747 748 writel(addr | pte_flags, intel_private.gtt + entry); 749} 750 751bool intel_enable_gtt(void) 752{ 753 u8 __iomem *reg; 754 755 if (INTEL_GTT_GEN == 2) { 756 u16 gmch_ctrl; 757 758 pci_read_config_word(intel_private.bridge_dev, 759 I830_GMCH_CTRL, &gmch_ctrl); 760 gmch_ctrl |= I830_GMCH_ENABLED; 761 pci_write_config_word(intel_private.bridge_dev, 762 I830_GMCH_CTRL, gmch_ctrl); 763 764 pci_read_config_word(intel_private.bridge_dev, 765 I830_GMCH_CTRL, &gmch_ctrl); 766 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { 767 dev_err(&intel_private.pcidev->dev, 768 "failed to enable the GTT: GMCH_CTRL=%x\n", 769 gmch_ctrl); 770 return false; 771 } 772 } 773 774 /* On the resume path we may be adjusting the PGTBL value, so 775 * be paranoid and flush all chipset write buffers... 776 */ 777 if (INTEL_GTT_GEN >= 3) 778 writel(0, intel_private.registers+GFX_FLSH_CNTL); 779 780 reg = intel_private.registers+I810_PGETBL_CTL; 781 writel(intel_private.PGETBL_save, reg); 782 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { 783 dev_err(&intel_private.pcidev->dev, 784 "failed to enable the GTT: PGETBL=%x [expected %x]\n", 785 readl(reg), intel_private.PGETBL_save); 786 return false; 787 } 788 789 if (INTEL_GTT_GEN >= 3) 790 writel(0, intel_private.registers+GFX_FLSH_CNTL); 791 792 return true; 793} 794EXPORT_SYMBOL(intel_enable_gtt); 795 796static int i830_setup(void) 797{ 798 u32 reg_addr; 799 800 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 801 reg_addr &= 0xfff80000; 802 803 intel_private.registers = ioremap(reg_addr, KB(64)); 804 if (!intel_private.registers) 805 return -ENOMEM; 806 807 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 808 809 return 0; 810} 811 812#if IS_ENABLED(CONFIG_AGP_INTEL) 813static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 814{ 815 agp_bridge->gatt_table_real = NULL; 816 agp_bridge->gatt_table = NULL; 817 agp_bridge->gatt_bus_addr = 0; 818 819 return 0; 820} 821 822static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 823{ 824 return 0; 825} 826 827static int intel_fake_agp_configure(void) 828{ 829 if (!intel_enable_gtt()) 830 return -EIO; 831 832 intel_private.clear_fake_agp = true; 833 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 834 835 return 0; 836} 837#endif 838 839static bool i830_check_flags(unsigned int flags) 840{ 841 switch (flags) { 842 case 0: 843 case AGP_PHYS_MEMORY: 844 case AGP_USER_CACHED_MEMORY: 845 case AGP_USER_MEMORY: 846 return true; 847 } 848 849 return false; 850} 851 852void intel_gtt_insert_sg_entries(struct sg_table *st, 853 unsigned int pg_start, 854 unsigned int flags) 855{ 856 struct scatterlist *sg; 857 unsigned int len, m; 858 int i, j; 859 860 j = pg_start; 861 862 /* sg may merge pages, but we have to separate 863 * per-page addr for GTT */ 864 for_each_sg(st->sgl, sg, st->nents, i) { 865 len = sg_dma_len(sg) >> PAGE_SHIFT; 866 for (m = 0; m < len; m++) { 867 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 868 intel_private.driver->write_entry(addr, j, flags); 869 j++; 870 } 871 } 872 readl(intel_private.gtt+j-1); 873} 874EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 875 876#if IS_ENABLED(CONFIG_AGP_INTEL) 877static void intel_gtt_insert_pages(unsigned int first_entry, 878 unsigned int num_entries, 879 struct page **pages, 880 unsigned int flags) 881{ 882 int i, j; 883 884 for (i = 0, j = first_entry; i < num_entries; i++, j++) { 885 dma_addr_t addr = page_to_phys(pages[i]); 886 intel_private.driver->write_entry(addr, 887 j, flags); 888 } 889 readl(intel_private.gtt+j-1); 890} 891 892static int intel_fake_agp_insert_entries(struct agp_memory *mem, 893 off_t pg_start, int type) 894{ 895 int ret = -EINVAL; 896 897 if (intel_private.clear_fake_agp) { 898 int start = intel_private.stolen_size / PAGE_SIZE; 899 int end = intel_private.gtt_mappable_entries; 900 intel_gtt_clear_range(start, end - start); 901 intel_private.clear_fake_agp = false; 902 } 903 904 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) 905 return i810_insert_dcache_entries(mem, pg_start, type); 906 907 if (mem->page_count == 0) 908 goto out; 909 910 if (pg_start + mem->page_count > intel_private.gtt_total_entries) 911 goto out_err; 912 913 if (type != mem->type) 914 goto out_err; 915 916 if (!intel_private.driver->check_flags(type)) 917 goto out_err; 918 919 if (!mem->is_flushed) 920 global_cache_flush(); 921 922 if (intel_private.needs_dmar) { 923 struct sg_table st; 924 925 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st); 926 if (ret != 0) 927 return ret; 928 929 intel_gtt_insert_sg_entries(&st, pg_start, type); 930 mem->sg_list = st.sgl; 931 mem->num_sg = st.nents; 932 } else 933 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, 934 type); 935 936out: 937 ret = 0; 938out_err: 939 mem->is_flushed = true; 940 return ret; 941} 942#endif 943 944void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 945{ 946 unsigned int i; 947 948 for (i = first_entry; i < (first_entry + num_entries); i++) { 949 intel_private.driver->write_entry(intel_private.scratch_page_dma, 950 i, 0); 951 } 952 readl(intel_private.gtt+i-1); 953} 954EXPORT_SYMBOL(intel_gtt_clear_range); 955 956#if IS_ENABLED(CONFIG_AGP_INTEL) 957static int intel_fake_agp_remove_entries(struct agp_memory *mem, 958 off_t pg_start, int type) 959{ 960 if (mem->page_count == 0) 961 return 0; 962 963 intel_gtt_clear_range(pg_start, mem->page_count); 964 965 if (intel_private.needs_dmar) { 966 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); 967 mem->sg_list = NULL; 968 mem->num_sg = 0; 969 } 970 971 return 0; 972} 973 974static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 975 int type) 976{ 977 struct agp_memory *new; 978 979 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { 980 if (pg_count != intel_private.num_dcache_entries) 981 return NULL; 982 983 new = agp_create_memory(1); 984 if (new == NULL) 985 return NULL; 986 987 new->type = AGP_DCACHE_MEMORY; 988 new->page_count = pg_count; 989 new->num_scratch_pages = 0; 990 agp_free_page_array(new); 991 return new; 992 } 993 if (type == AGP_PHYS_MEMORY) 994 return alloc_agpphysmem_i8xx(pg_count, type); 995 /* always return NULL for other allocation types for now */ 996 return NULL; 997} 998#endif 999 1000static int intel_alloc_chipset_flush_resource(void) 1001{ 1002 int ret; 1003 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1004 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1005 pcibios_align_resource, intel_private.bridge_dev); 1006 1007 return ret; 1008} 1009 1010static void intel_i915_setup_chipset_flush(void) 1011{ 1012 int ret; 1013 u32 temp; 1014 1015 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1016 if (!(temp & 0x1)) { 1017 intel_alloc_chipset_flush_resource(); 1018 intel_private.resource_valid = 1; 1019 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1020 } else { 1021 temp &= ~1; 1022 1023 intel_private.resource_valid = 1; 1024 intel_private.ifp_resource.start = temp; 1025 intel_private.ifp_resource.end = temp + PAGE_SIZE; 1026 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1027 /* some BIOSes reserve this area in a pnp some don't */ 1028 if (ret) 1029 intel_private.resource_valid = 0; 1030 } 1031} 1032 1033static void intel_i965_g33_setup_chipset_flush(void) 1034{ 1035 u32 temp_hi, temp_lo; 1036 int ret; 1037 1038 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1039 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1040 1041 if (!(temp_lo & 0x1)) { 1042 1043 intel_alloc_chipset_flush_resource(); 1044 1045 intel_private.resource_valid = 1; 1046 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1047 upper_32_bits(intel_private.ifp_resource.start)); 1048 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1049 } else { 1050 u64 l64; 1051 1052 temp_lo &= ~0x1; 1053 l64 = ((u64)temp_hi << 32) | temp_lo; 1054 1055 intel_private.resource_valid = 1; 1056 intel_private.ifp_resource.start = l64; 1057 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1058 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1059 /* some BIOSes reserve this area in a pnp some don't */ 1060 if (ret) 1061 intel_private.resource_valid = 0; 1062 } 1063} 1064 1065static void intel_i9xx_setup_flush(void) 1066{ 1067 /* return if already configured */ 1068 if (intel_private.ifp_resource.start) 1069 return; 1070 1071 if (INTEL_GTT_GEN == 6) 1072 return; 1073 1074 /* setup a resource for this object */ 1075 intel_private.ifp_resource.name = "Intel Flush Page"; 1076 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1077 1078 /* Setup chipset flush for 915 */ 1079 if (IS_G33 || INTEL_GTT_GEN >= 4) { 1080 intel_i965_g33_setup_chipset_flush(); 1081 } else { 1082 intel_i915_setup_chipset_flush(); 1083 } 1084 1085 if (intel_private.ifp_resource.start) 1086 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1087 if (!intel_private.i9xx_flush_page) 1088 dev_err(&intel_private.pcidev->dev, 1089 "can't ioremap flush page - no chipset flushing\n"); 1090} 1091 1092static void i9xx_cleanup(void) 1093{ 1094 if (intel_private.i9xx_flush_page) 1095 iounmap(intel_private.i9xx_flush_page); 1096 if (intel_private.resource_valid) 1097 release_resource(&intel_private.ifp_resource); 1098 intel_private.ifp_resource.start = 0; 1099 intel_private.resource_valid = 0; 1100} 1101 1102static void i9xx_chipset_flush(void) 1103{ 1104 if (intel_private.i9xx_flush_page) 1105 writel(1, intel_private.i9xx_flush_page); 1106} 1107 1108static void i965_write_entry(dma_addr_t addr, 1109 unsigned int entry, 1110 unsigned int flags) 1111{ 1112 u32 pte_flags; 1113 1114 pte_flags = I810_PTE_VALID; 1115 if (flags == AGP_USER_CACHED_MEMORY) 1116 pte_flags |= I830_PTE_SYSTEM_CACHED; 1117 1118 /* Shift high bits down */ 1119 addr |= (addr >> 28) & 0xf0; 1120 writel(addr | pte_flags, intel_private.gtt + entry); 1121} 1122 1123static int i9xx_setup(void) 1124{ 1125 u32 reg_addr, gtt_addr; 1126 int size = KB(512); 1127 1128 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 1129 1130 reg_addr &= 0xfff80000; 1131 1132 intel_private.registers = ioremap(reg_addr, size); 1133 if (!intel_private.registers) 1134 return -ENOMEM; 1135 1136 switch (INTEL_GTT_GEN) { 1137 case 3: 1138 pci_read_config_dword(intel_private.pcidev, 1139 I915_PTEADDR, >t_addr); 1140 intel_private.gtt_bus_addr = gtt_addr; 1141 break; 1142 case 5: 1143 intel_private.gtt_bus_addr = reg_addr + MB(2); 1144 break; 1145 default: 1146 intel_private.gtt_bus_addr = reg_addr + KB(512); 1147 break; 1148 } 1149 1150 intel_i9xx_setup_flush(); 1151 1152 return 0; 1153} 1154 1155#if IS_ENABLED(CONFIG_AGP_INTEL) 1156static const struct agp_bridge_driver intel_fake_agp_driver = { 1157 .owner = THIS_MODULE, 1158 .size_type = FIXED_APER_SIZE, 1159 .aperture_sizes = intel_fake_agp_sizes, 1160 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1161 .configure = intel_fake_agp_configure, 1162 .fetch_size = intel_fake_agp_fetch_size, 1163 .cleanup = intel_gtt_cleanup, 1164 .agp_enable = intel_fake_agp_enable, 1165 .cache_flush = global_cache_flush, 1166 .create_gatt_table = intel_fake_agp_create_gatt_table, 1167 .free_gatt_table = intel_fake_agp_free_gatt_table, 1168 .insert_memory = intel_fake_agp_insert_entries, 1169 .remove_memory = intel_fake_agp_remove_entries, 1170 .alloc_by_type = intel_fake_agp_alloc_by_type, 1171 .free_by_type = intel_i810_free_by_type, 1172 .agp_alloc_page = agp_generic_alloc_page, 1173 .agp_alloc_pages = agp_generic_alloc_pages, 1174 .agp_destroy_page = agp_generic_destroy_page, 1175 .agp_destroy_pages = agp_generic_destroy_pages, 1176}; 1177#endif 1178 1179static const struct intel_gtt_driver i81x_gtt_driver = { 1180 .gen = 1, 1181 .has_pgtbl_enable = 1, 1182 .dma_mask_size = 32, 1183 .setup = i810_setup, 1184 .cleanup = i810_cleanup, 1185 .check_flags = i830_check_flags, 1186 .write_entry = i810_write_entry, 1187}; 1188static const struct intel_gtt_driver i8xx_gtt_driver = { 1189 .gen = 2, 1190 .has_pgtbl_enable = 1, 1191 .setup = i830_setup, 1192 .cleanup = i830_cleanup, 1193 .write_entry = i830_write_entry, 1194 .dma_mask_size = 32, 1195 .check_flags = i830_check_flags, 1196 .chipset_flush = i830_chipset_flush, 1197}; 1198static const struct intel_gtt_driver i915_gtt_driver = { 1199 .gen = 3, 1200 .has_pgtbl_enable = 1, 1201 .setup = i9xx_setup, 1202 .cleanup = i9xx_cleanup, 1203 /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1204 .write_entry = i830_write_entry, 1205 .dma_mask_size = 32, 1206 .check_flags = i830_check_flags, 1207 .chipset_flush = i9xx_chipset_flush, 1208}; 1209static const struct intel_gtt_driver g33_gtt_driver = { 1210 .gen = 3, 1211 .is_g33 = 1, 1212 .setup = i9xx_setup, 1213 .cleanup = i9xx_cleanup, 1214 .write_entry = i965_write_entry, 1215 .dma_mask_size = 36, 1216 .check_flags = i830_check_flags, 1217 .chipset_flush = i9xx_chipset_flush, 1218}; 1219static const struct intel_gtt_driver pineview_gtt_driver = { 1220 .gen = 3, 1221 .is_pineview = 1, .is_g33 = 1, 1222 .setup = i9xx_setup, 1223 .cleanup = i9xx_cleanup, 1224 .write_entry = i965_write_entry, 1225 .dma_mask_size = 36, 1226 .check_flags = i830_check_flags, 1227 .chipset_flush = i9xx_chipset_flush, 1228}; 1229static const struct intel_gtt_driver i965_gtt_driver = { 1230 .gen = 4, 1231 .has_pgtbl_enable = 1, 1232 .setup = i9xx_setup, 1233 .cleanup = i9xx_cleanup, 1234 .write_entry = i965_write_entry, 1235 .dma_mask_size = 36, 1236 .check_flags = i830_check_flags, 1237 .chipset_flush = i9xx_chipset_flush, 1238}; 1239static const struct intel_gtt_driver g4x_gtt_driver = { 1240 .gen = 5, 1241 .setup = i9xx_setup, 1242 .cleanup = i9xx_cleanup, 1243 .write_entry = i965_write_entry, 1244 .dma_mask_size = 36, 1245 .check_flags = i830_check_flags, 1246 .chipset_flush = i9xx_chipset_flush, 1247}; 1248static const struct intel_gtt_driver ironlake_gtt_driver = { 1249 .gen = 5, 1250 .is_ironlake = 1, 1251 .setup = i9xx_setup, 1252 .cleanup = i9xx_cleanup, 1253 .write_entry = i965_write_entry, 1254 .dma_mask_size = 36, 1255 .check_flags = i830_check_flags, 1256 .chipset_flush = i9xx_chipset_flush, 1257}; 1258 1259/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1260 * driver and gmch_driver must be non-null, and find_gmch will determine 1261 * which one should be used if a gmch_chip_id is present. 1262 */ 1263static const struct intel_gtt_driver_description { 1264 unsigned int gmch_chip_id; 1265 char *name; 1266 const struct intel_gtt_driver *gtt_driver; 1267} intel_gtt_chipsets[] = { 1268 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 1269 &i81x_gtt_driver}, 1270 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 1271 &i81x_gtt_driver}, 1272 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 1273 &i81x_gtt_driver}, 1274 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 1275 &i81x_gtt_driver}, 1276 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1277 &i8xx_gtt_driver}, 1278 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", 1279 &i8xx_gtt_driver}, 1280 { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1281 &i8xx_gtt_driver}, 1282 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1283 &i8xx_gtt_driver}, 1284 { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1285 &i8xx_gtt_driver}, 1286 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1287 &i915_gtt_driver }, 1288 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1289 &i915_gtt_driver }, 1290 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1291 &i915_gtt_driver }, 1292 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1293 &i915_gtt_driver }, 1294 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1295 &i915_gtt_driver }, 1296 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1297 &i915_gtt_driver }, 1298 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1299 &i965_gtt_driver }, 1300 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1301 &i965_gtt_driver }, 1302 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1303 &i965_gtt_driver }, 1304 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1305 &i965_gtt_driver }, 1306 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1307 &i965_gtt_driver }, 1308 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1309 &i965_gtt_driver }, 1310 { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1311 &g33_gtt_driver }, 1312 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1313 &g33_gtt_driver }, 1314 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1315 &g33_gtt_driver }, 1316 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1317 &pineview_gtt_driver }, 1318 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1319 &pineview_gtt_driver }, 1320 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1321 &g4x_gtt_driver }, 1322 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1323 &g4x_gtt_driver }, 1324 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1325 &g4x_gtt_driver }, 1326 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1327 &g4x_gtt_driver }, 1328 { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1329 &g4x_gtt_driver }, 1330 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1331 &g4x_gtt_driver }, 1332 { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1333 &g4x_gtt_driver }, 1334 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1335 "HD Graphics", &ironlake_gtt_driver }, 1336 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1337 "HD Graphics", &ironlake_gtt_driver }, 1338 { 0, NULL, NULL } 1339}; 1340 1341static int find_gmch(u16 device) 1342{ 1343 struct pci_dev *gmch_device; 1344 1345 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1346 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 1347 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 1348 device, gmch_device); 1349 } 1350 1351 if (!gmch_device) 1352 return 0; 1353 1354 intel_private.pcidev = gmch_device; 1355 return 1; 1356} 1357 1358int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 1359 struct agp_bridge_data *bridge) 1360{ 1361 int i, mask; 1362 1363 /* 1364 * Can be called from the fake agp driver but also directly from 1365 * drm/i915.ko. Hence we need to check whether everything is set up 1366 * already. 1367 */ 1368 if (intel_private.driver) { 1369 intel_private.refcount++; 1370 return 1; 1371 } 1372 1373 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 1374 if (gpu_pdev) { 1375 if (gpu_pdev->device == 1376 intel_gtt_chipsets[i].gmch_chip_id) { 1377 intel_private.pcidev = pci_dev_get(gpu_pdev); 1378 intel_private.driver = 1379 intel_gtt_chipsets[i].gtt_driver; 1380 1381 break; 1382 } 1383 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 1384 intel_private.driver = 1385 intel_gtt_chipsets[i].gtt_driver; 1386 break; 1387 } 1388 } 1389 1390 if (!intel_private.driver) 1391 return 0; 1392 1393 intel_private.refcount++; 1394 1395#if IS_ENABLED(CONFIG_AGP_INTEL) 1396 if (bridge) { 1397 bridge->driver = &intel_fake_agp_driver; 1398 bridge->dev_private_data = &intel_private; 1399 bridge->dev = bridge_pdev; 1400 } 1401#endif 1402 1403 intel_private.bridge_dev = pci_dev_get(bridge_pdev); 1404 1405 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 1406 1407 mask = intel_private.driver->dma_mask_size; 1408 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 1409 dev_err(&intel_private.pcidev->dev, 1410 "set gfx device dma mask %d-bit failed!\n", mask); 1411 else 1412 pci_set_consistent_dma_mask(intel_private.pcidev, 1413 DMA_BIT_MASK(mask)); 1414 1415 if (intel_gtt_init() != 0) { 1416 intel_gmch_remove(); 1417 1418 return 0; 1419 } 1420 1421 return 1; 1422} 1423EXPORT_SYMBOL(intel_gmch_probe); 1424 1425void intel_gtt_get(size_t *gtt_total, size_t *stolen_size, 1426 phys_addr_t *mappable_base, unsigned long *mappable_end) 1427{ 1428 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; 1429 *stolen_size = intel_private.stolen_size; 1430 *mappable_base = intel_private.gma_bus_addr; 1431 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; 1432} 1433EXPORT_SYMBOL(intel_gtt_get); 1434 1435void intel_gtt_chipset_flush(void) 1436{ 1437 if (intel_private.driver->chipset_flush) 1438 intel_private.driver->chipset_flush(); 1439} 1440EXPORT_SYMBOL(intel_gtt_chipset_flush); 1441 1442void intel_gmch_remove(void) 1443{ 1444 if (--intel_private.refcount) 1445 return; 1446 1447 if (intel_private.pcidev) 1448 pci_dev_put(intel_private.pcidev); 1449 if (intel_private.bridge_dev) 1450 pci_dev_put(intel_private.bridge_dev); 1451 intel_private.driver = NULL; 1452} 1453EXPORT_SYMBOL(intel_gmch_remove); 1454 1455MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1456MODULE_LICENSE("GPL and additional rights"); 1457