History log of /drivers/char/agp/intel-gtt.c
Revision Date Author Comments
4c020b032b8a15966e1207b71144ffbb75697e29 21-Jan-2014 Paul Gortmaker <paul.gortmaker@windriver.com> drivers/char: delete non-required instances of include <linux/init.h>

None of these files are actually using any __init type directives
and hence don't need to include <linux/init.h>. Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.

Cc: David Airlie <airlied@linux.ie>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Corey Minyard <minyard@acm.org>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Peter Huewe <peterhuewe@gmx.de>
Cc: Ashley Lai <ashley@ashleylai.com>
Cc: Marcel Selhorst <tpmdd@selhorst.net>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
d3572532993c7e8635ad8e5b50f8f613bf855ee2 06-Jan-2014 Bjorn Helgaas <bhelgaas@google.com> agp/intel: Use CPU physical address, not bus address, for ioremap()

In i810_setup(), i830_setup(), and i9xx_setup(), we use the result of
pci_bus_address() as an argument to ioremap() and to compute gtt_phys_addr.
These should use pci_resource_start() instead because we want the CPU
physical address, not the bus address.

If there were an AGP device behind a host bridge that translated addresses,
e.g., a PNP0A08 device with _TRA != 0, this would fix a bug. I'm not aware
of any of those, but they are possible.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
b5e350f919acb8ef6961bc1b62e395f53cea123a 04-Jan-2014 Bjorn Helgaas <bhelgaas@google.com> agp/intel: Use pci_bus_address() to get GTTADR bus address

Per the Intel 915G/915GV/... Chipset spec (document number 301467-005),
GTTADR is a standard PCI BAR.

The PCI core reads GTTADR at enumeration-time. Use pci_bus_address()
instead of reading it again in the driver. This works correctly for both
32-bit and 64-bit BARs. The spec above only mentions 32-bit GTTADR, but we
should still use the standard interface.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
5ef6d8f49533bb28a90ae9eec177ffd1ade54267 04-Jan-2014 Bjorn Helgaas <bhelgaas@google.com> agp/intel: Use pci_bus_address() to get MMADR bus address

Per the Intel 915G/915GV/... Chipset spec (document number 301467-005),
MMADR is a standard PCI BAR.

The PCI core reads MMADR at enumeration-time. Use pci_bus_address()
instead of reading it again in the driver. This works correctly for both
32-bit and 64-bit BARs. The spec above only mentions 32-bit MMADR, but we
should still use the standard interface.

Also, stop clearing the low 19 bits of the bus address because it's invalid
to use addresses outside the region defined by the BAR. The spec claims
MMADR is 512KB; if that's the case, those bits will be zero anyway.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
545b0a746b79f54a45cd3b595dce67abbf35233f 04-Jan-2014 Yinghai Lu <yinghai@kernel.org> agp/intel: Support 64-bit GMADR

Per the Intel 915G/915GV/... Chipset spec (document number 301467-005),
GMADR is a standard PCI BAR.

The PCI core reads GMADR at enumeration-time. Use pci_bus_address()
instead of reading it again in the driver. This works correctly for both
32-bit and 64-bit BARs. The spec above only mentions 32-bit GMADR, but
Yinghai's patch (link below) indicates some devices have a 64-bit GMADR.

[bhelgaas: reworked starting from http://lkml.kernel.org/r/1385851238-21085-13-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
5acc4ce44cd0a9cf5dbcfe50085708e9156e0177 06-Jan-2014 Bjorn Helgaas <bhelgaas@google.com> agp/intel: Rename gtt_bus_addr to gtt_phys_addr

The only use of gtt_bus_addr is as an argument to ioremap(), so it is a CPU
physical address, not a bus address. Rename it to gtt_phys_addr to reflect
this.

No functional change.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
00fe639a56b40930bf27eabeef9a826344d8f4c4 05-Nov-2013 Ville Syrjälä <ville.syrjala@linux.intel.com> drm/i915: Make AGP support optional

We only depend on the intel-gtt module for GTT frobbign on older gens.
The intel_agp module is optional, except for UMS and some old XvMC
userland on gen3. So make AGP support optional. As before, we will
fail the i915 init for UMS and gen3 KMS the same as before if
intel_agp isn't around.

intel-gtt.c is left with a somewhat ugly ifdef mess, but I'm going
to save that for a later cleaning.

At least my gen2 still works with the patch and CONFIG_AGP=n.

v2: Make i915 depend on X86 and PCI, and intel-gtt depend on PCI

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
da88a5f7f7d434e2cde1b3e19d952e6d84533662 13-Feb-2013 Chris Wilson <chris@chris-wilson.co.uk> drm/i915: Disable WC PTE updates to w/a buggy IOMMU on ILK

Whilst IOMMU is enabled for the Intel GPU on Ironlake, it appears that
using WC writes to update the PTE on the GPU fails miserably. The
result looks like the majority of the writes do not land leading to
lots of screen corruption and a hard system hang.

v2: s/</<=/ to preserve the current exclusion of Sandybridge

Reported-by: Nathan Myers <ncm@cantrip.org>
Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=60391
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Nathan Myers <ncm@cantrip.org>
[danvet: Remove cc: stable and add tested-by.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
41907ddc1b71aaa4ef5290f46f0ec49d581d6aac 08-Feb-2013 Ben Widawsky <ben@bwidawsk.net> drm/i915: Fix gen2 mappable calculations

When I refactored the code initially, I forgot that gen2 uses a
different bar for the CPU mappable aperture. The agp-less code knows
nothing of generations less than 5, so we have to expand the gtt_probe
function to include the mappable base and end.

It was originally broken by me:
commit baa09f5fd8a6d033ec075355dda99a65b7f6a0f3
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Thu Jan 24 13:49:57 2013 -0800

drm/i915: Add probe and remove to the gtt ops

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
a54c0c279f3864171fe53c66e769d5a137c5c651 24-Jan-2013 Ben Widawsky <ben@bwidawsk.net> drm/i915: remove intel_gtt structure

With the probe call in our dispatch table, we can now cut away the
last three remaining members in the intel_gtt shared struct and so
remove it completely.

v2: Rebased on top of Daniel's series

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: bikeshed commit message a bit.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
e5c653777986b40e2986d2c918847fddbcba3a34 18-Jan-2013 Ben Widawsky <ben@bwidawsk.net> agp/intel: Add gma_bus_addr

It is no longer used in the i915 code, so isolate it from the shared
struct.

This was originally part of:
commit 0e275518f325418d559c05327775bff894b237f7
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Mon Jan 14 13:35:33 2013 -0800

agp/intel: decouple more of the agp-i915 sharing

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

That commit had some other hunks which can't be used due to issues
Daniel found in previous commits.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: drop squash notice from the commit since it's imo ok to keep
this one separate.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
8d2e630899165d413ae8a2adc36846ac0b71bada 18-Jan-2013 Ben Widawsky <ben@bwidawsk.net> drm/i915: Needs_dmar, not

The reasoning behind our code taking two paths depending upon whether or
not we may have been configured for IOMMU isn't clear to me. It should
always be safe to use the pci mapping functions as they are designed to
abstract the decision we were handling in i915.

Aside from simpler code, removing another member for the intel_gtt
struct is a nice motivation.

I ran this by Chris, and he wasn't concerned about the extra kzalloc,
and memory references vs. page_to_phys calculation in the case without
IOMMU.

v2: Update commit message

v3: Remove needs_dmar addition from Zhenyu upstream

This reverts (and then other stuff)
commit 20652097dadd9a7fb4d652f25466299974bc78f9
Author: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Thu Dec 13 23:47:47 2012 +0800

drm/i915: Fix missed needs_dmar setting

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> (v2)
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Squash in follow-up fix to remove the bogus hunk which
deleted the dma_mask configuration for gen6+.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9c61a32d31a55c8c6e590d83ae5645e14fde09f2 18-Jan-2013 Ben Widawsky <ben@bwidawsk.net> drm/i915: Remove scratch page from shared

We already had a mapping in both (minus the phys_addr in AGP).

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
a81cc00c11ab6816fbcb7dd99a60b50e71765d25 18-Jan-2013 Ben Widawsky <ben@bwidawsk.net> drm/i915: Cut out the infamous ILK w/a from AGP layer

And, move it to where the rest of the logic is.

There is some slight functionality changes. There was extra paranoid
checks in AGP code making sure we never do idle maps on gen2 parts. That
was not duplicated as the simple PCI id check should do the right thing.

v2: use IS_GEN5 && IS_MOBILE check instead. For now, this is the same as
IS_IRONLAKE_M but is more future proof. The workaround docs hint that
more than one platform may be effected, but we've never seen such a
platform in the wild. (Rodrigo, Daniel)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> (v1)
Cc: Dave Airlie <airlied@redhat.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
06e5598fce5ce89fe8bf081398296e5b08d993dd 18-Dec-2012 Ben Widawsky <benjamin.widawsky@intel.com> drm/i915: Move GSM mapping into dev_priv

This removes an unused field from the AGP structure and moves it into
the dev_priv structure (with a slightly better name). This builds upon
the kill-agp series already merged.

GSM is a well defined term in the bspec:
GSM: Graphics Stolen Memory

GTT stolen space is defined for storage of the GFX GTT entries in
physical memory. IA can not access GSM directly , it can only access via
GTTMMADR. GT can access GSM directly or through GTTMMADR.

This is not the entire stolen space.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
009946f89b7795699848a922fc2f7804390017d9 04-Nov-2012 Ben Widawsky <ben@bwidawsk.net> drm/i915: Kill off now unused gen6+ AGP code

v2: Accidently removed an ILK case in i9xx_setup (Nicely found by Chris)

CC: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by [v1] : Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
e76e9aebcdbfebae8f4cd147e3c0f800d36e97f3 04-Nov-2012 Ben Widawsky <ben@bwidawsk.net> drm/i915: Stop using AGP layer for GEN6+

As a quick hack we make the old intel_gtt structure mutable so we can
fool a bunch of the existing code which depends on elements in that data
structure. We can/should try to remove this in a subsequent patch.

This should preserve the old gtt init behavior which upon writing these
patches seems incorrect. The next patch will fix these things.

The one exception is VLV which doesn't have the preserved flush control
write behavior. Since we want to do that for all GEN6+ stuff, we'll
handle that in a later patch. Mainstream VLV support doesn't actually
exist yet anyway.

v2: Update the comment to remove the "voodoo"
Check that the last pte written matches what we readback

v3: actually kill cache_level_to_agp_type since most of the flags will
disappear in an upcoming patch

v4: v3 was actually not what we wanted (Daniel)
Make the ggtt bind assertions better and stricter (Chris)
Fix some uncaught errors at gtt init (Chris)
Some other random stuff that Chris wanted

v5: check for i==0 in gen6_ggtt_bind_object to shut up gcc (Ben)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by [v4]: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Make the cache_level -> agp_flags conversion for pre-gen6 a
tad more robust by mapping everything != CACHE_NONE to the cached agp
flag - we have a 1:1 uncached mapping, but different modes of
cacheable (at least on later generations). Suggested by Chris Wilson.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9169d3a88072b20f42e68a946e916bd7dfbc7f2c 10-Oct-2012 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915: disable wc gtt pte mappings on gen2

It doesn't work since the gtt pte range sits in the middle of the mmio
bar. We didn't notice that since both my and Chris' gen2 machines
don't support PAT and hence all wc io mapping request will
automatically be demoted to uc.

This regression has been introduce in

commit edef7e685da05c13cce50c0126189c80fe2c8f71
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Sep 14 11:57:47 2012 +0100

agp/intel: Use a write-combining map for updating PTEs

Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
edef7e685da05c13cce50c0126189c80fe2c8f71 14-Sep-2012 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Use a write-combining map for updating PTEs

Rewriting the PTE entries using an WC mapping is roughly an order of
magnitude faster than through the uncached mapping. This makes an
observable difference on workloads that cycle through large numbers of
buffers, for example Chromium using ShmPixmaps where virtually all the
CPU time is currently spent rebinding the userptr.

v2: Limit the WC mapping to older generations as we have observed that
the TLB invalidation on SandyBridge+ is unreliable with WC updates.
See i-g-t/tests/gem_gtt_cpu_tlb

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9da3da660d8c19a54f6e93361d147509be3fff84 01-Jun-2012 Chris Wilson <chris@chris-wilson.co.uk> drm/i915: Replace the array of pages with a scatterlist

Rather than have multiple data structures for describing our page layout
in conjunction with the array of pages, we can migrate all users over to
a scatterlist.

One major advantage, other than unifying the page tracking structures,
this offers is that we replace the vmalloc'ed array (which can be up to
a megabyte in size) with a chain of individual pages which helps reduce
memory pressure.

The disadvantage is that we then do not have a simple array to iterate,
or to access randomly. The common case for this is in the relocation
processing, which will typically fit within a single scatterlist page
and so be almost the same cost as the simple array. For iterating over
the array, the extra function call could be optimised away, but in
reality is an insignificant cost of either binding the pages, or
performing the pwrite/pread.

v2: Fix drm_clflush_sg() to not invoke wbinvd as well! And fix the
trivial compile error from rebasing.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
a843af186c3157cee58f1cf689385ab906e1f109 14-Aug-2012 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915: fix hsw uncached pte

They've changed it ... for no apparent reason. Meh.

V2: remove unused 'is_hsw' field.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
da612d880fbc598ac0efcef579355fb90d4bca4e 06-Aug-2012 Paulo Zanoni <paulo.r.zanoni@intel.com> drm/i915: add more Haswell PCI IDs

Also properly indent the HB IDs.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
e597dad846bafe6c9802c9ae2a94d755c5567de9 15-Jun-2012 Jesse Barnes <jbarnes@virtuousgeek.org> agp/intel: use correct GTT offset on VLV

VLV is a gen7 device, but we don't currently handle that in the switch.
So add it and write the PTEs correctly.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
e87c46993e30e8fe2e7a0981a532abe8bba07e62 15-Jun-2012 Jesse Barnes <jbarnes@virtuousgeek.org> agp/intel: allow cacheable and GDFT PTEs on ValleyView

The PTE format is similar to SNB, but we don't support an MLC and don't
need chipset flushing.

Note: I have my questions whether this is right, given that MLC died
for snb & ivb, that ivb has grown a L3$ cache instead (which vlv seems
to have, too) and that the LLC bit here isn't actually LLC, but just
means 'snoop cpu caches'.

But I plan to burn this all with the heat of a thousands suns in my
gtt rework, so who cares ;-)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Added note.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
8ecd1a6615f0d9de6759aafe229bc1cc4ee99c7b 07-Jun-2012 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915: call intel_enable_gtt

When drm/i915 is in control of the gtt, we need to call
the enable function at all the relevant places ourselves.

Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
32e3cd6ecd7ae9b79605b5f2eb993186a509c239 07-Jun-2012 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel-gtt: move gart base addres setup

We need this thing much earlier, and it doesn't make sense
in the hw enabling function intel_enable_gtt - this does not
change over a suspend/resume cycle ...

Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
14be93ddff61eb196382aeaa3ac86f4db844aeb0 08-Jun-2012 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915 + agp/intel-gtt: prep work for direct setup

To be able to directly set up the intel-gtt code from drm/i915 and
avoid setting up the fake-agp driver we need to prepare a few things:
- pass both the bridge and gpu pci_dev to the probe function and add
code to handle the gpu pdev both being present (for drm/i915) and
not present (fake agp).
- add refcounting to the remove function so that unloading drm/i915
doesn't kill the fake agp driver

v2: Fix up the cleanup and refcount, noticed by Jani Nikula.

Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
7e8f6306fe155d6fc3fe99d666be95b4ed24427d 07-Jun-2012 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel-gtt: don't require the agp bridge on setup

We only need it to fake the agp interface and don't actually
use it in the driver anywhere. Hence conditionalize that.

This is just a prep patch to eventually disable the fake agp
driver on gen6+.

Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
dd2757f8b557ab2030154896eac9b2285557dda6 07-Jun-2012 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915: stop using dev->agp->base

For that to work we need to export the base address of the gtt
mmio window from intel-gtt. Also replace all other uses of
dev->agp by values we already have at hand.

Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9b990de76ced807b2d92a601fb7f03863b632c58 07-Jun-2012 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel-gtt: remove dead code

This is a leftover from the conversion of the i81x fake agp driver
over to the new intel-gtt code layoute.

Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
4cae9ae052fe630e63f28be6b0b115fbf52e63fb 29-Mar-2012 Eugeni Dodonov <eugeni.dodonov@intel.com> drm/i915: add Haswell devices and their PCI IDs

This adds product definitions for desktop, mobile and server boards.

v2: split into a separate patch, add .has_pch_split feature.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
650dc07ec3b0eba8ff21da706d2b1876ada59fc3 02-Apr-2012 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915: disable ppgtt on snb when dmar is enabled

Totally unexpected that this regressed. Luckily it sounds like we just
need to have dmar disable on the igfx, not the entire system. At least
that's what a few days of testing between Tony Vroon and me indicates.

Reported-by: Tony Vroon <tony@linx.net>
Cc: Tony Vroon <tony@linx.net>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43024
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
cc22a938fc1db0c8ef5e693a69b159c4b851dab3 30-Mar-2012 Eugeni Dodonov <eugeni.dodonov@intel.com> drm/i915: add Ivy Bridge GT2 Server entries

This adds PCI ID for IVB GT2 server variant which we were missing.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
[danvet: fix up conflict because the patch has been diffed against next. tsk.]
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
64757876215fcc515403639fa0bd19e8da7ab06b 28-Mar-2012 Jesse Barnes <jbarnes@virtuousgeek.org> agp/intel: add ValleyView AGP driver

... and bind it right to the PCI id.

Note that there are still a few things to fix here:
- we need to move the tlb flush to a better place in drm/i915.
- we need to check snoop support on vlv and implement it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: squash follow-on patch and add todo items to commit msg.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
4b60d29ee00cb2114075e8b5c2c23928bbd76c28 28-Mar-2012 Jesse Barnes <jbarnes@virtuousgeek.org> agp/intel: map more registers for use by the GTT code

We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
register for doing so is above the range we normally map. Map the whole
register space to make sure we can get it.

v2: only map the larger space on gen7+ (Daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
428ccb21b740f603a6a1f08cbe6d935fb3177620 09-Feb-2012 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel-gtt: export the gtt pagetable iomapping

We need this because ppgtt page directory entries need to be in the
global gtt pagetable.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
50a4c4a94d24fe13167e3ab1dc1486623369c31a 09-Feb-2012 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel-gtt: export the scratch page dma address

To implement a PPGTT for drm/i915 that fully aliases the GTT, we also
need to properly alias the scratch page.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
a08185a3eb658854b29c05bcbfac0f85038ffe9f 28-Oct-2011 Keith Packard <keithp@keithp.com> agp: iommu_gfx_mapped only available if CONFIG_INTEL_IOMMU is set

Kernels with no iommu support cannot ever need the Ironlake
work-around, so never enable it in that case.

Might be better to completely remove the work-around from the kernel
in this case?

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
35b09c9bf619c4fc6040c52dcea6bd5bd6af7679 28-Oct-2011 Dan Carpenter <dan.carpenter@oracle.com> drm/i915: fix if statement (bogus semi-colon)

The semi-colon is a typo here and it makes the if statement
unconditional.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
c5e62bdd73da80e1017058c923336a5a150af9f2 28-Oct-2011 Keith Packard <keithp@keithp.com> agp: iommu_gfx_mapped only available if CONFIG_INTEL_IOMMU is set

Kernels with no iommu support cannot ever need the Ironlake
work-around, so never enable it in that case.

Might be better to completely remove the work-around from the kernel
in this case?

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
3fca806cf343155d0bb0dfbdbc2e51ef47b65750 28-Oct-2011 Dan Carpenter <dan.carpenter@oracle.com> drm/i915: fix if statement (bogus semi-colon)

The semi-colon is a typo here and it makes the if statement
unconditional.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
5c0422878fcdc279ae9a8e8b66972a15b5efb67f 18-Oct-2011 Ben Widawsky <ben@bwidawsk.net> drm/i915: ILK + VT-d workaround

Idle the GPU before doing any unmaps. We know if VT-d is in use through
an exported variable from iommu code.

This should avoid a known HW issue.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
d3f138106b4b40640dc667f0222fd9f137387b32 24-Aug-2011 Suresh Siddha <suresh.b.siddha@intel.com> iommu: Rename the DMAR and INTR_REMAP config options

Change the CONFIG_DMAR to CONFIG_INTEL_IOMMU to be consistent
with the other IOMMU options.

Rename the CONFIG_INTR_REMAP to CONFIG_IRQ_REMAP to match the
irq subsystem name.

And define the CONFIG_DMAR_TABLE for the common ACPI DMAR
routines shared by both CONFIG_INTEL_IOMMU and CONFIG_IRQ_REMAP.

Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: yinghai@kernel.org
Cc: youquan.song@intel.com
Cc: joerg.roedel@amd.com
Cc: tony.luck@intel.com
Cc: dwmw2@infradead.org
Link: http://lkml.kernel.org/r/20110824001456.558630224@sbsiddha-desk.sc.intel.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
246d08b8f94a5545077611ab5bfb9d47014ede75 17-Feb-2011 Jesse Barnes <jbarnes@virtuousgeek.org> agp/intel: add Ivy Bridge support

Just use the Sandy Bridge routines.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
bdb8b975fc66e081c3f39be6267701f8226d11aa 22-Dec-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Experiment with a 855GM GWB bit

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27187
Tested-by: Thorsten Vollmer <thorsten@thvo.de> (DFI-ACP G5M150-N w/852GME)
Tested-by: Moritz Brunner <2points@gmx.org> (Asus M2400N/i855GM)
Tested-by: Indan Zupancic <indan@nul.nu> (Thinkpad X40/855GM rev 02)
Tested-by: Eric Anholt <eric@anholt.net> (865G)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
452858338aec31c1f4414bf07f31663690479869 22-Dec-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Experiment with a 855GM GWB bit

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27187
Tested-by: Thorsten Vollmer <thorsten@thvo.de> (DFI-ACP G5M150-N w/852GME)
Tested-by: Moritz Brunner <2points@gmx.org> (Asus M2400N/i855GM)
Tested-by: Indan Zupancic <indan@nul.nu> (Thinkpad X40/855GM rev 02)
Tested-by: Eric Anholt <eric@anholt.net> (865G)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
bee4a186c16bed0d7e91425ca9356c2e8c015f8d 21-Jan-2011 Chris Wilson <chris@chris-wilson.co.uk> drm/i915,agp/intel: Do not clear stolen entries

We can only utilize the stolen portion of the GTT if we are in sole
charge of the hardware. This is only true if using GEM and KMS,
otherwise VESA continues to access stolen memory.

Reported-by: Arnd Bergmann <arnd@arndb.de>
Reported-by: Frederic Weisbecker <fweisbec@gmail.com>
Tested-by: Jiri Olsa <jolsa@redhat.com>
Tested-by: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
53371edaef692bef7eee8070bd680401ccf65706 19-Jun-2010 Oswald Buddenhagen <ossi@kde.org> agp/intel: Fix device names of i845 and 845G

They got mixed up when the switch was converted to a table in 2007.

Signed-off-by: Oswald Buddenhagen <ossi@kde.org>
[ickle: minor changes for 2.6.37+]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
d15eda5c6edff4987af6f4423af0bab0c3251e74 12-Jan-2011 Dave Airlie <airlied@gmail.com> i915/gtt: fix ordering causing DMAR errors on object teardown.

Previous to the last GTT rework we always rewrote the GTT then unmapped the
object, somehow this got reversed in the rework in 2.6.37-rc5 timeframe.

This fix needs to go to stable in an alternate form since the code changed.

This fixes DMAR reports on my Ironlake HP2540p.

Signed-off-by: Dave Airlie <airlied@redhat.com>
a46f3108b1cd8bf11d46ac8a5f30df6f6dbdf738 12-Jan-2011 Dave Airlie <airlied@gmail.com> i915/gtt: fix ordering issues with status setup and DMAR

This code was setting up the status page before setting the DMAR-is-on-bit,
so we were getting DMAR errors on the status page. Reverse the two bits
of init code to the correct result.

Signed-off-by: Dave Airlie <airlied@redhat.com>
c97689d8860f086125e7ff9cd730027a0057ca4f 23-Dec-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Flush the chipset write buffers when changing GTT base

Flush the chipset write buffers before and after adjusting the GTT base
register, just in case. We only modify this value upon initialisation
(boot and resume) so there should be no outstanding writes, however
there are always those persistent PGTBL_ER that keep getting reported
upon resume.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
71f4566084eb592fe545f05f7dff41fa9aa42e0b 14-Dec-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Fix missed cached memory flags setting in i965_write_entry()

This fixes regression from a6963596a13e62f8e65b1cf3403a330ff2db407c,
that missed to set cached memory type in GTT entry.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
136711be41ec97f7f1a9c3a5e8535eb7da5fea59 04-Dec-2010 Takashi Iwai <tiwai@suse.de> agp/intel: Fix wrong kunmap in i830_cleanup()

Add a missing NULL check and fix the wrong address passed to kunmap()
in i830_cleanup().

Cc: stable@kernel.org
Signed-off-by: Takashi Iwai <tiwai@suse.de>
[danvet: added cc stable]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7bdc9ab00b1b0fdbb490f41c5c7c2fbc66fed9ee 09-Nov-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Remove duplicate const

drivers/char/agp/intel-gtt.c:340:48: warning: duplicate const

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
4080775b60cc26044e7c4aba5e76e5041b0d7004 06-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: export api for drm/i915

Just some minor shuffling to get rid of any agp traces in the
exported functions.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
f050a8abbda0efcd597c6b1825e3b9ce4d613383 05-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> agp: kill agp_flush_chipset and corresponding ioctl

The intel drm calls the chipset functions now directly. Userspace
never called the corresponding ioctl, hence it can be killed, too.

Cc: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
40ce6575102b23e432932b5ce41c44bf7cc5023b 05-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915/gtt: call chipset flush directly

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
23ed992a5ebe6964ebe312b54142fbc5e8185cdc 05-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915|intel-gtt: consolidate intel-gtt.h headers

... and a few other defines.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
ff26860fb53f2dcfaaaf1bf017b09dbdfddff5ee 05-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: fold i81x-only dcache support into the generic driver

Now the intel-gtt.c rewrite is complete!

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
820647b97a9cbdd976c7177f1b6047fc1f6dd5c0 05-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: switch i81x to the common initialization helpers

Still a separate agp_bridge_driver because of the i81x-only
dedicated vram support.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
625dd9d331d8a1ce5ee4e9924a22f3e55b7ac615 04-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: switch i81x to the write_entry helpers

Initialization is still done with the old code with a few
added things sprinkled in to make the intel_fake_agp helper
functions work.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
24a6b387af7cd5d1e0e5d15b15104644a5105de7 04-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: kill unneeded sandybridge memory types

Used for the now dead agp type_to_mask stuff.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
b47cf66f315a258c458ed4345c443dba396fb787 04-Nov-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: drop dcache support for i830 and later

i830_check_flags already disallows it, so no need to implement it
in the write_entry function. Seems to be a remnant from i810 support.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
c64f7ba5f1006d8c20eacafecf98d4d00a6902a0 23-Nov-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Remove confusion of stolen entries not stolen memory

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
1b6064d79b9a1c5e5aa6fcc6855f3da5e639ff73 23-Nov-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Remove the artificial cap on stolen size

Now that the stolen memory does not also steal entries from the GTT, we
can use all the memory the BIOS set aside for the GPU.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c 02-Nov-2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: fix cache control for sandybridge

This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
8d0f56708292ca5c256ee3b7187d124afee81d93 02-Nov-2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: restore cache behavior on sandybridge

This restores cache behavior for default AGP_USER_MEMORY as
uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only.
I've seen different cache behavior on one sandybridge desktop CPU vs.
another mobile CPU. Until we figure out how to detect the real cache
config, restore back to the original behavior now.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
897ef192514a6b0fc10a0ce3fe7e7aa0de09bc52 02-Nov-2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: restore cache behavior on sandybridge

This restores cache behavior for default AGP_USER_MEMORY as
uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only.
I've seen different cache behavior on one sandybridge desktop CPU vs.
another mobile CPU. Until we figure out how to detect the real cache
config, restore back to the original behavior now.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
d110852513148a7ec44fad4e036455aeb816d713 02-Nov-2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: fix cache control for sandybridge

This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
100519e2f1c20286158746f92f27c3aa14f5a893 31-Oct-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: the GMCH is always enabled for integrated processor graphics

... and trying to set the bit is ineffectual.

Fixes the regression from e380f60 which detected that we were trying to
do undefined operations on the I830_GMCH_CTRL.

Reported-by: Alexey Fisher <bug-track@fisher-privat.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
e380f60b22eddec7825224b8d788572c82b63161 29-Oct-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Sandybridge doesn't require GMCH enabling

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
201728429d6cf336cfd7483fcd1bce47291b2901 24-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: maximize ggtt size on platforms that support this

On VT-d supporting platforms the GGTT is allocated in a stolen mem
section separate from graphcis stolen mem. The GMCH register contains
a bitfield specifying the size of that region. Docs suggest that this
region can only be used for GGTT and PPGTT. Hence ensure that the
PPGTT is disabled and use the complete area for the GGTT.

Unfortunately the graphics core on G33/Pineview can't cope with really
large GTTs and the BIOS usually enables the maximum of 512MB. So
don't bother with maximizing the GTT on these platforms.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
b3eafc5af02a799650757f2c5b2b0d4835dd0a5f 23-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: save PGETBL_CTL later in the setup process

... and switch to a more classical store-reg-on-suspend, restore-on-resume
way of doing things. Obviously this is just preparation for the future,
the code is not there at all, yet.

This is needed because the next patch adjusts this register and everything
in it (not just the pagetable address) needs to be restored on resume.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181 22-Oct-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Restore valid PTE bit for Sandybridge after bdd3072

In cleaning up the mask functions in bdd3072, the setting of the PTE
valid bit was dropped for Sandybridge.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
e61cb0d5fd172ab95a4501917526382f25158e83 24-Sep-2010 Jan Beulich <JBeulich@novell.com> some clean up to intel-gtt.c

In commit e517a5e97080bbe52857bd0d7df9b66602d53c4d the call to
map_page_into_agp() got removed from intel_i830_setup_flush(), but the
counterpart call from intel_i830_fini_flush() to unmap_page_from_agp()
was left in place.

Additionally, the page allocated here never gets its physical address
used for sending to hardware, so there's no need to allocate it with
GFP_DMA32. Nor is __GFP_ZERO really necessary, as the page is used
only to store data to force flushing of some internal processor state.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
ae83dd5c7d80e0f9063739a18e270da7207a91e3 12-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt add a cleanup function for chipset specific stuff

The old code didn't clean up the i830 chipset flush page. And it
looks nicer.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
22533b494ff6a812b3e97248cc6c062858396182 12-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: store the dma mask size in intel_gtt_driver

Storing this explicitly makes for clearer code and hopefully
less further confusion.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
0af9e92e779602bdd6d4d19acf63b4802fab91b6 12-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: clean up gtt size reporting

Consolidate everything in intel-gtt.c and also kill the export
of intel_max_stolen.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
e9b1cc81c2222108d866323c51f482dd6db8d689 12-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: consolidate fake_agp driver structs

They're now all the same.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
1b263f246639c4777fbf6cfda932ecd1ea4bebb9 12-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: move chipset flush to the gtt driver struct

This is the last differentiator between the different fake agp drivers.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
bdd30729b68d708c970125aab363931134698f2d 12-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: kill mask_memory functions

That indirection mess can now go. Add a dummy i81x gtt_driver to
avoid a NULL pointer check.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
90cb149e1a85f8296daa1989c055db18fbf4ea88 11-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: generic (insert|remove)_entries for sandybridge

Like before, but now with the added bonus of being able to kill
quite a bit of no-longer userful code (the old dmar support stuff).

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
450f2b3d51025a1749b694ee13f0e4e23ed58750 11-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: generic (insert|remove)_entries for g33/i965

Like for the i915.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
fefaa70f0c7fa406492039e35b69b83fc13e163a 11-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: generic (insert|remove)_entries for i915

Beef up the generic version to support dmar. Otherwise like for the i830.

v2: Don't try to DMA remap on resume for already remapped pages.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
5cbecafce4ee8ab73c194911e01a77a7a07f034e 11-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: generic (insert|remove)_entries for i830

Well, not all too generic because it does not yet support dmar.
Add a new function check_flags to ensure that non-gem code does
not try to screw us over.

v2: Beautify i830_check_flags with an idea from Chris Wilson.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
d0b6dc4b930e3be9c02cc9638f02e14d271d5f0d 09-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: drop agp scratch page support stuff

intel-gtt.c now handles the scratch page itself, so drop all that
was just there to support it.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3 09-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: introduce pte write function for gen6

Like for i830. intel_i9xx_configure is now unused, so kill it.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
a6963596a13e62f8e65b1cf3403a330ff2db407c 11-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: introduce pte write function for g33/i965/gm45

Like for the i830.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
351bb278d2fd2df93526c15f37500070347328b4 07-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: introduce pte write function for i8xx/i915/i945

And put it to use in the gtt configuration code that writes
the scratch page addr in all gtt ptes. This makes intel_i830_configure
generic, hence rename it to intel_fake_agp_configure.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
0e87d2b06cb4651c874d0b208d31c73addbd638b 07-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: initialize our own scratch page

The intel gtt fake agp driver is the only agp driver to use dma
address remapping. So it makes sense to fold this code back into the
only user (and thus reduce the reliance on the agp code).

This patch does the first step by initializing (and remapping) the
scratch page in a new function intel_gtt_setup_scratch_page.
Unfortunately intel_gtt_cleanup had to move to avoid a forward
declaration. The new scratch page is not yet used, though.

v2: Refactor out scratch page teardown. Suggested by Chris Wilson on
irc. This makes it clear what's going on and results in a nice
symmetry between setup and teardown.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
3f08e4ef807c3103ceebf7993c7463c7a90646f3 14-Sep-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Fix resume regression from 2d2430cf

On i915 [EeePCs] something scribles over the registers during suspend
and resume so we must save a copy of the PGETBL_CTL register programmed
by the BIOS and restore that upon resume.

Reported-by: Sitsofe Wheeler <sitsofe@yahoo.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
b1c5b0f8cc16a1d22e2e521c4236a6ceca1b2983 14-Sep-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Remove redundant setting of gtt_mappable_entries

Two calls enter, only one will leave.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
9e76e7b8bd716413cfd722a807aa22723f3a895f 14-Sep-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Use macro to set the count of the size array

It's a fixed size array so let the compiler do the hard work of updating
all the call sites.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
19966754328d99ee003ddfc7a8c31ceb115483ac 06-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915: die, i915_probe_agp, die

Use the detection from intel-gtt.ko instead. Hooray!

Also move the stolen mem allocator to the other gtt stuff in dev_prv->mem.

v2: Chris Wilson noted that my error handling was crap. Fix it. He also
said that this fixes a problem on his i845. Indeed, i915_probe_agp
misses a special case for i830/i845 stolen mem detection.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=25476
Cc: stable@kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
239918f7a5ac118ecfe9c55a4cfd25d7767b674a 31-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: use chipset generation number some more

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
3b15a9d7cd59b7ec79f61aafabfbe84116561461 29-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: call init_gtt_init in probe function

This way create_gatt_table become dummy glue functions for the fake
agp driver - rename them accordingly (and kill the now unnecessary
i9xx copy).

With this change, the gtt initialization code is almost independant
from the agp stuff. Two things are still missing:
- the scratch page is created by the generic agp code.
- filling the whole gtt with scratch_page ptes is not yet consolidated -
this needs abstracted pte handling, first.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2d2430cf9bf9e8b0ad9ea34a103625f4fe7e4477 29-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: consolidate i9xx setup

The only difference between i915 and i965 was the calculation of the
gtt address. So merge these two paths into one. Otherwise the same
changes as in the i830 setup consolidation.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
73800422a30e9b8b6e0e49c27af9e9d196e52fd9 29-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: consolidate i830 setup

Slighlty reordered sequence was necessary. Also don't set
agp_bridge->gatt_bus_addr anymore. Only used by generic agp helper
functions, hence unnecessary for the intel fake agp driver.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
f67eab664c47b261517b09812477de9a1780b426 29-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: consolidate the gtt ioremap calls

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
fdfb58a965486d2afea4ef0f9b8153dab9b98b2e 29-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: i830: adjust ioremap of regs and gtt to i9xx

This way around this can be extracted into common code.

Also use a common cleanup function (and give it a generic name).

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
210b23c2f7b9721afb0a57459b7dbac3b094862e 28-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: i965: use detected gtt size for mapping

Also move the Sandybdridge size detection into gtt_total_entries, like
the rest.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
ccc4e67be5ac1bd38c4bfd61aca38366597e8afb 08-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: i915: use detected gtt size for mapping

Slight reordering of the init sequence required.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
1a997ff2a0089a07a5494545d31f4366742dea43 08-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: introduce intel_gtt_driver

Same idea as INTEL_INFO from drm/i915. This
- reduces the dependancy on agp_driver
- stops the what-does-IS_I965G-mean confusion (here it's just gen4, in
drm/i915 it's gen >=4)
- further prepares the separation of the fake agp driver from the rest.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
e5e408fc94595aab897f613b6f4e2f5b36870a6f 28-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: fix gtt_total_entries detection

In commit f1befe71 Chris Wilson added some code to clear the full gtt
on g33/pineview instead of just the mappable part. The code looks like
it was copy-pasted from agp/intel-gtt.c, at least an identical piece
of code is still there (in intel_i830_init_gtt_entries). This lead to
a regression in 2.6.35 which was supposedly fixed in commit e7b96f28

Now this commit makes absolutely no sense to me. It seems to be
slightly confused about chipset generations - it references docs for
4th gen but the regression concerns 3rd gen g33. Luckily the the g33
gmch docs are available with the GMCH Graphics Control pci config
register definitions. The other (bigger problem) is that the new
check in there uses the i830 stolen mem bits (.5M, 1M or 8M of stolen
mem). They are different since the i855GM.

The most likely case is that it hits the 512M fallback, which was
probably the right thing for the boxes this was tested on.

So the original approach by Chris Wilson seems to be wrong and the
current code is definitely wrong. There is a third approach by Jesse
Barnes from his RFC patch "Who wants a bigger GTT mapping range?"
where he simply shoves g33 in the same clause like later chipset
generations.

I've asked him and Jesse confirmed that this should work. So implement
it.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=16891$
Tested-by: Anisse Astier <anisse@astier.eu>
Cc: stable@kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
ffdd7510b0bd5ec663b6b11b39810574f2ce3111 27-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: s/i8[13]0/fake_agp for generic functions

Start to separate the fake agp driver from the rest of intel-gtt.c

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
fbe407836b5c8d82c68195962240a392d0ce64ea 27-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: adjust overhead entries in intel_gtt_stolen_entries

agp/intel_gtt.c and drm/i915/i915_dma.c don't calculate this the same
way: The intel-gtt code seems to use the actual gtt size, the drm
module just the mappable. Go with the logic from the drm module because
that's the more conservative choice.

But conserve the original code in intel_gtt_total_size for later use.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
77ad498ecaeb9a614d2a7bbfaab58a35c0cc577d 27-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: drop unnecessary conditions in intel_gtt_stolen_entries

The dedection function in drm/i915/i915_dma.c works without it, so
drop it here, too. All the values are disdinct, anyway.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
d8d9abcd35aeebd633cba2e99c384f4e004ccb84 27-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: sane variable names for intel_gtt_stolen_entries

This somewhat aligns it with the version in drm/i915/i915_dma.c.
Changes:
- s/gtt_entries/stolen_size
- track overhead entries in a seperate var (the effective gtt size
calculation will be extracted later on).
- subtract the overhead at the end instead of in each clause.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
3e921f980fdd5b972efb7f368b2a847a01804184 27-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: generic intel_fake_agp_fetch_size

This uses the new mappable gtt size detection from the previous patch.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
1784a5fb4f7a41b9a5ea066f7782418bfe170c04 08-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: new function intel_gtt_mappable_entries

This implementation is stolen from drm/i915, but is equivalent to
the code sprinkled over intel-gtt.c in the various fetch_size functions.
It's not yet used anywhere, though.

Also introduce intel_gtt_init which only calls intel_gtt_stolen_entries.
Over the course of the next patches, this will grow untill it contains
the complete init sequence starting from the call to gtt_mappable_entries.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
bfde067bebe72293b1f909a8b35ee8d82811f8f5 24-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: s/intel_i830_init_gtt_entries/intel_gtt_stolen_entries

First simple step towards a more generic initialization. This
is needed to disentangle the agp stuff from the stuff that is
actually needed by drm/i915.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
d7cca2f7000243ac43a389110c3d8474f582ae3f 24-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: store a local pointer to the bridge pci dev

When the intel-gtt code now longer depends on agp, we cannot rely
on this. So store a local reference in intel-gtt.c.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
0ade638655f0ef4d807295c14a4c97544bd6b9ca 24-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: introduce drm/intel-gtt.h

Add a few definitions to it that are already shared and that will
be shared in the future (like the number of stolen entries).
No functional changes in here.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
e2404e7c3fe6f46e161edf085c6d9bea06ebe488 08-Sep-2010 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel: make intel-gtt.c into a real source file

Now that the disentangling is complete, stop including intel-gtt.c
from intel-agp.c.

The linux build system _really_ doesn't allow .c source files with the
same name as the module. It fails with the following message when trying
to build such a bugger:

make[3]: Circular drivers/char/agp/intel-agp.o <- drivers/char/agp/intel-agp.o dependency dropped.

Instead of renameing intel-agp.c I've simply created a new module out
of intel-gtt.c. Renaming intel-agp.ko to something else is not an option
for it will surely kill someones boot process.

This also paves the way to use the gtt code without loading the agp
driver.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
02c026ced58f33bb5702d3063c05dae2b651e4ba 24-Aug-2010 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel: split out gmch/gtt probe, part 2

This just splits the device list into two and moves the gtt related stuff
to intel-gtt.c. The two new devices lists also lose the not longer needed
fields. There where only about 5 cases anyway with both a gmch and a
possible agp port, so the duplication of entries is rather small.
Additionally kill 2 out of the three Ironlake mobile entries that
only differed in host bridge pci id.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
8554048070906579ec9fa19ac381deddd2d7b155 07-Sep-2010 Zhenyu Wang <zhenyuw@linux.intel.com> intel_agp,i915: Add more sandybridge graphics device ids

New pci ids for GT2 and GT2+ on desktop and mobile sandybridge,
and graphics device ids for server sandybridge. Also rename original
ids string to reflect GT1 version.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 27-Aug-2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: Fix cache control for Sandybridge

Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.

And set cache control to always LLC only by default on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
8dfc2b14ebf538f28a05565f34913ecffedf5024 23-Aug-2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: fix physical address mask bits for sandybridge

It should shift bit 39-32 into pte's bit 11-4.

Reported-by:Takashi Iwai <tiwai@suse.de>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
df51e7aa2cf204e3a65657a1d60b96cfda133e9b 04-Sep-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Promote warning about failure to setup flush to error.

Make sure we always detect when we fail to correctly allocate the Isoch
Flush Page and print an error to warn the user about the likely memory
corruption that will result in invalid rendering or worse.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
d1d6ca73ef548748e141747e7260798327d6a2c1 08-Jul-2010 Jesse Barnes <jbarnes@virtuousgeek.org> drm/agp/i915: trim stolen space to 32M

Some BIOSes will claim a large chunk of stolen space. Unless we
reclaim it, our aperture for remapping buffer objects will be
constrained. So clamp the stolen space to 32M and ignore the rest.

Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15469 among others.

Adding the ignored stolen memory back into the general pool using the
memory hotplug code is left as an exercise for the reader.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Simon Farnsworth <simon.farnsworth@onelan.com>
Tested-by: Artem S. Tashkinov <t.artem@mailcity.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
831cd4453598b2c8e193f077023910c6b0c39558 24-Jul-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Destroy the scatterlist on allocation failure

A side-effect of being able to use custom page allocations with the
sg_table is that it cannot reap the partially constructed scatterlist if
fails to allocate a page. So we need to call sg_free_table() ourselves
if sg_alloc_table() fails.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc Dave Airlie <airlied@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
a2757b6fab6dee3dbf43bdb7d7226d03747fbdb1 09-Jul-2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: Add actual definitions of the Sandybridge PTE caching bits.
3869d4a8afd3ce97770e66d6a96672af93984cc2 09-Jul-2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: Support the extended physical addressing bits on Sandybridge.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
[anholt: Split this patch out of a larger patch for Sandybridge fixes]
Signed-off-by: Eric Anholt <eric@anholt.net>
8699be3ef1d71d1c5e11eee239f53573d72515a3 16-Jun-2010 Ondrej Zary <linux@rainbow-software.org> intel_agp: Don't oops with zero stolen memory

When "onboard video memory" is set do "disabled" in BIOS on Asus P4P800-VM
board (i865G), kernel oopses with memory corruption:
https://bugs.freedesktop.org/show_bug.cgi?id=28430

Fix that by cleanly aborting the initialization.

Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
e7b96f28c58ca09f15f6c2e8ccbb889a30fab4f7 09-Jul-2010 Tim Gardner <tim.gardner@canonical.com> agp/intel: Use the correct mask to detect i830 aperture size.

BugLink: https://bugs.launchpad.net/bugs/597075

commit f1befe71fa7a79ab733011b045639d8d809924ad introduced a
regression when detecting aperture size of some i915 adapters, e.g.,
those on the Intel Q35 chipset.

The original report: https://bugzilla.kernel.org/show_bug.cgi?id=15733
The regression report: https://bugzilla.kernel.org/show_bug.cgi?id=16294

According to the specification found at
http://intellinuxgraphics.org/VOL_1_graphics_core.pdf, the PCI config
space register I830_GMCH_CTRL is a mirror of GMCH Graphics
Control. The correct macro for isolating the aperture size bits is
therefore I830_GMCH_GMS_MASK along with the attendant changes to the
case statement.

Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
Tested-by: Kees Cook <kees.cook@canonical.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Eric Anholt <eric@anholt.net>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
f1befe71fa7a79ab733011b045639d8d809924ad 18-May-2010 Chris Wilson <chris@chris-wilson.co.uk> agp/intel: Restrict GTT mapping to valid range on i915 and i945

References:

Bug 15733 - Crash when accessing nonexistent GTT entries in i915
https://bugzilla.kernel.org/show_bug.cgi?id=15733

On G33 and above, the size of the GTT space is determined by the GMCH
control register. Prior to this revision, the size is determined by the
size of the aperture. So we must careful to map and fill the appropriate
range depending on chipset.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
e15831656778d032f3c7655949f8cc3997f2b04a 14-Apr-2010 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel-gtt: kill previous_size assignments

Not needed for the GTT and inconsistent: Sometimes the _new_ size
was stored there ...

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
1ca46bd13474f71a361b147b13318aefa714551d 14-Apr-2010 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel-gtt: kill intel_i830_tlbflush

We don't use the generic insert/remove_memory functions that
require this. So kill this useless code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
f51b76621137c18501f6d21a995d36a8bcb49999 14-Apr-2010 Daniel Vetter <daniel.vetter@ffwll.ch> agp/intel: split out the GTT support

intel-agp.c contains actually two different drivers: An agp driver
for _physical_ agp slots an the gtt driver that is used by the intel
drm modules. Split them to prevent any further confusion.

This patch just moves the code and includes intel-gtt.c in intel-agp.c
Later patches will untangle these two drivers further.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>