intel-gtt.c revision a81cc00c11ab6816fbcb7dd99a60b50e71765d25
1/* 2 * Intel GTT (Graphics Translation Table) routines 3 * 4 * Caveat: This driver implements the linux agp interface, but this is far from 5 * a agp driver! GTT support ended up here for purely historical reasons: The 6 * old userspace intel graphics drivers needed an interface to map memory into 7 * the GTT. And the drm provides a default interface for graphic devices sitting 8 * on an agp port. So it made sense to fake the GTT support as an agp port to 9 * avoid having to create a new api. 10 * 11 * With gem this does not make much sense anymore, just needlessly complicates 12 * the code. But as long as the old graphics stack is still support, it's stuck 13 * here. 14 * 15 * /fairy-tale-mode off 16 */ 17 18#include <linux/module.h> 19#include <linux/pci.h> 20#include <linux/init.h> 21#include <linux/kernel.h> 22#include <linux/pagemap.h> 23#include <linux/agp_backend.h> 24#include <linux/delay.h> 25#include <asm/smp.h> 26#include "agp.h" 27#include "intel-agp.h" 28#include <drm/intel-gtt.h> 29 30/* 31 * If we have Intel graphics, we're not going to have anything other than 32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). 34 * Only newer chipsets need to bother with this, of course. 35 */ 36#ifdef CONFIG_INTEL_IOMMU 37#define USE_PCI_DMA_API 1 38#else 39#define USE_PCI_DMA_API 0 40#endif 41 42struct intel_gtt_driver { 43 unsigned int gen : 8; 44 unsigned int is_g33 : 1; 45 unsigned int is_pineview : 1; 46 unsigned int is_ironlake : 1; 47 unsigned int has_pgtbl_enable : 1; 48 unsigned int dma_mask_size : 8; 49 /* Chipset specific GTT setup */ 50 int (*setup)(void); 51 /* This should undo anything done in ->setup() save the unmapping 52 * of the mmio register file, that's done in the generic code. */ 53 void (*cleanup)(void); 54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 55 /* Flags is a more or less chipset specific opaque value. 56 * For chipsets that need to support old ums (non-gem) code, this 57 * needs to be identical to the various supported agp memory types! */ 58 bool (*check_flags)(unsigned int flags); 59 void (*chipset_flush)(void); 60}; 61 62static struct _intel_private { 63 struct intel_gtt base; 64 const struct intel_gtt_driver *driver; 65 struct pci_dev *pcidev; /* device one */ 66 struct pci_dev *bridge_dev; 67 u8 __iomem *registers; 68 phys_addr_t gtt_bus_addr; 69 u32 PGETBL_save; 70 u32 __iomem *gtt; /* I915G */ 71 bool clear_fake_agp; /* on first access via agp, fill with scratch */ 72 int num_dcache_entries; 73 void __iomem *i9xx_flush_page; 74 char *i81x_gtt_table; 75 struct resource ifp_resource; 76 int resource_valid; 77 struct page *scratch_page; 78 int refcount; 79} intel_private; 80 81#define INTEL_GTT_GEN intel_private.driver->gen 82#define IS_G33 intel_private.driver->is_g33 83#define IS_PINEVIEW intel_private.driver->is_pineview 84#define IS_IRONLAKE intel_private.driver->is_ironlake 85#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 86 87static int intel_gtt_map_memory(struct page **pages, 88 unsigned int num_entries, 89 struct sg_table *st) 90{ 91 struct scatterlist *sg; 92 int i; 93 94 DBG("try mapping %lu pages\n", (unsigned long)num_entries); 95 96 if (sg_alloc_table(st, num_entries, GFP_KERNEL)) 97 goto err; 98 99 for_each_sg(st->sgl, sg, num_entries, i) 100 sg_set_page(sg, pages[i], PAGE_SIZE, 0); 101 102 if (!pci_map_sg(intel_private.pcidev, 103 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL)) 104 goto err; 105 106 return 0; 107 108err: 109 sg_free_table(st); 110 return -ENOMEM; 111} 112 113static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) 114{ 115 struct sg_table st; 116 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 117 118 pci_unmap_sg(intel_private.pcidev, sg_list, 119 num_sg, PCI_DMA_BIDIRECTIONAL); 120 121 st.sgl = sg_list; 122 st.orig_nents = st.nents = num_sg; 123 124 sg_free_table(&st); 125} 126 127static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 128{ 129 return; 130} 131 132/* Exists to support ARGB cursors */ 133static struct page *i8xx_alloc_pages(void) 134{ 135 struct page *page; 136 137 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 138 if (page == NULL) 139 return NULL; 140 141 if (set_pages_uc(page, 4) < 0) { 142 set_pages_wb(page, 4); 143 __free_pages(page, 2); 144 return NULL; 145 } 146 get_page(page); 147 atomic_inc(&agp_bridge->current_memory_agp); 148 return page; 149} 150 151static void i8xx_destroy_pages(struct page *page) 152{ 153 if (page == NULL) 154 return; 155 156 set_pages_wb(page, 4); 157 put_page(page); 158 __free_pages(page, 2); 159 atomic_dec(&agp_bridge->current_memory_agp); 160} 161 162#define I810_GTT_ORDER 4 163static int i810_setup(void) 164{ 165 u32 reg_addr; 166 char *gtt_table; 167 168 /* i81x does not preallocate the gtt. It's always 64kb in size. */ 169 gtt_table = alloc_gatt_pages(I810_GTT_ORDER); 170 if (gtt_table == NULL) 171 return -ENOMEM; 172 intel_private.i81x_gtt_table = gtt_table; 173 174 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 175 reg_addr &= 0xfff80000; 176 177 intel_private.registers = ioremap(reg_addr, KB(64)); 178 if (!intel_private.registers) 179 return -ENOMEM; 180 181 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 182 intel_private.registers+I810_PGETBL_CTL); 183 184 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 185 186 if ((readl(intel_private.registers+I810_DRAM_CTL) 187 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 188 dev_info(&intel_private.pcidev->dev, 189 "detected 4MB dedicated video ram\n"); 190 intel_private.num_dcache_entries = 1024; 191 } 192 193 return 0; 194} 195 196static void i810_cleanup(void) 197{ 198 writel(0, intel_private.registers+I810_PGETBL_CTL); 199 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 200} 201 202static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 203 int type) 204{ 205 int i; 206 207 if ((pg_start + mem->page_count) 208 > intel_private.num_dcache_entries) 209 return -EINVAL; 210 211 if (!mem->is_flushed) 212 global_cache_flush(); 213 214 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 215 dma_addr_t addr = i << PAGE_SHIFT; 216 intel_private.driver->write_entry(addr, 217 i, type); 218 } 219 readl(intel_private.gtt+i-1); 220 221 return 0; 222} 223 224/* 225 * The i810/i830 requires a physical address to program its mouse 226 * pointer into hardware. 227 * However the Xserver still writes to it through the agp aperture. 228 */ 229static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 230{ 231 struct agp_memory *new; 232 struct page *page; 233 234 switch (pg_count) { 235 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 236 break; 237 case 4: 238 /* kludge to get 4 physical pages for ARGB cursor */ 239 page = i8xx_alloc_pages(); 240 break; 241 default: 242 return NULL; 243 } 244 245 if (page == NULL) 246 return NULL; 247 248 new = agp_create_memory(pg_count); 249 if (new == NULL) 250 return NULL; 251 252 new->pages[0] = page; 253 if (pg_count == 4) { 254 /* kludge to get 4 physical pages for ARGB cursor */ 255 new->pages[1] = new->pages[0] + 1; 256 new->pages[2] = new->pages[1] + 1; 257 new->pages[3] = new->pages[2] + 1; 258 } 259 new->page_count = pg_count; 260 new->num_scratch_pages = pg_count; 261 new->type = AGP_PHYS_MEMORY; 262 new->physical = page_to_phys(new->pages[0]); 263 return new; 264} 265 266static void intel_i810_free_by_type(struct agp_memory *curr) 267{ 268 agp_free_key(curr->key); 269 if (curr->type == AGP_PHYS_MEMORY) { 270 if (curr->page_count == 4) 271 i8xx_destroy_pages(curr->pages[0]); 272 else { 273 agp_bridge->driver->agp_destroy_page(curr->pages[0], 274 AGP_PAGE_DESTROY_UNMAP); 275 agp_bridge->driver->agp_destroy_page(curr->pages[0], 276 AGP_PAGE_DESTROY_FREE); 277 } 278 agp_free_page_array(curr); 279 } 280 kfree(curr); 281} 282 283static int intel_gtt_setup_scratch_page(void) 284{ 285 struct page *page; 286 dma_addr_t dma_addr; 287 288 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 289 if (page == NULL) 290 return -ENOMEM; 291 get_page(page); 292 set_pages_uc(page, 1); 293 294 if (intel_private.base.needs_dmar) { 295 dma_addr = pci_map_page(intel_private.pcidev, page, 0, 296 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 297 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 298 return -EINVAL; 299 300 intel_private.base.scratch_page_dma = dma_addr; 301 } else 302 intel_private.base.scratch_page_dma = page_to_phys(page); 303 304 intel_private.scratch_page = page; 305 306 return 0; 307} 308 309static void i810_write_entry(dma_addr_t addr, unsigned int entry, 310 unsigned int flags) 311{ 312 u32 pte_flags = I810_PTE_VALID; 313 314 switch (flags) { 315 case AGP_DCACHE_MEMORY: 316 pte_flags |= I810_PTE_LOCAL; 317 break; 318 case AGP_USER_CACHED_MEMORY: 319 pte_flags |= I830_PTE_SYSTEM_CACHED; 320 break; 321 } 322 323 writel(addr | pte_flags, intel_private.gtt + entry); 324} 325 326static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { 327 {32, 8192, 3}, 328 {64, 16384, 4}, 329 {128, 32768, 5}, 330 {256, 65536, 6}, 331 {512, 131072, 7}, 332}; 333 334static unsigned int intel_gtt_stolen_size(void) 335{ 336 u16 gmch_ctrl; 337 u8 rdct; 338 int local = 0; 339 static const int ddt[4] = { 0, 16, 32, 64 }; 340 unsigned int stolen_size = 0; 341 342 if (INTEL_GTT_GEN == 1) 343 return 0; /* no stolen mem on i81x */ 344 345 pci_read_config_word(intel_private.bridge_dev, 346 I830_GMCH_CTRL, &gmch_ctrl); 347 348 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 349 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 350 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 351 case I830_GMCH_GMS_STOLEN_512: 352 stolen_size = KB(512); 353 break; 354 case I830_GMCH_GMS_STOLEN_1024: 355 stolen_size = MB(1); 356 break; 357 case I830_GMCH_GMS_STOLEN_8192: 358 stolen_size = MB(8); 359 break; 360 case I830_GMCH_GMS_LOCAL: 361 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 362 stolen_size = (I830_RDRAM_ND(rdct) + 1) * 363 MB(ddt[I830_RDRAM_DDT(rdct)]); 364 local = 1; 365 break; 366 default: 367 stolen_size = 0; 368 break; 369 } 370 } else { 371 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 372 case I855_GMCH_GMS_STOLEN_1M: 373 stolen_size = MB(1); 374 break; 375 case I855_GMCH_GMS_STOLEN_4M: 376 stolen_size = MB(4); 377 break; 378 case I855_GMCH_GMS_STOLEN_8M: 379 stolen_size = MB(8); 380 break; 381 case I855_GMCH_GMS_STOLEN_16M: 382 stolen_size = MB(16); 383 break; 384 case I855_GMCH_GMS_STOLEN_32M: 385 stolen_size = MB(32); 386 break; 387 case I915_GMCH_GMS_STOLEN_48M: 388 stolen_size = MB(48); 389 break; 390 case I915_GMCH_GMS_STOLEN_64M: 391 stolen_size = MB(64); 392 break; 393 case G33_GMCH_GMS_STOLEN_128M: 394 stolen_size = MB(128); 395 break; 396 case G33_GMCH_GMS_STOLEN_256M: 397 stolen_size = MB(256); 398 break; 399 case INTEL_GMCH_GMS_STOLEN_96M: 400 stolen_size = MB(96); 401 break; 402 case INTEL_GMCH_GMS_STOLEN_160M: 403 stolen_size = MB(160); 404 break; 405 case INTEL_GMCH_GMS_STOLEN_224M: 406 stolen_size = MB(224); 407 break; 408 case INTEL_GMCH_GMS_STOLEN_352M: 409 stolen_size = MB(352); 410 break; 411 default: 412 stolen_size = 0; 413 break; 414 } 415 } 416 417 if (stolen_size > 0) { 418 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 419 stolen_size / KB(1), local ? "local" : "stolen"); 420 } else { 421 dev_info(&intel_private.bridge_dev->dev, 422 "no pre-allocated video memory detected\n"); 423 stolen_size = 0; 424 } 425 426 return stolen_size; 427} 428 429static void i965_adjust_pgetbl_size(unsigned int size_flag) 430{ 431 u32 pgetbl_ctl, pgetbl_ctl2; 432 433 /* ensure that ppgtt is disabled */ 434 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); 435 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; 436 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); 437 438 /* write the new ggtt size */ 439 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 440 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; 441 pgetbl_ctl |= size_flag; 442 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); 443} 444 445static unsigned int i965_gtt_total_entries(void) 446{ 447 int size; 448 u32 pgetbl_ctl; 449 u16 gmch_ctl; 450 451 pci_read_config_word(intel_private.bridge_dev, 452 I830_GMCH_CTRL, &gmch_ctl); 453 454 if (INTEL_GTT_GEN == 5) { 455 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { 456 case G4x_GMCH_SIZE_1M: 457 case G4x_GMCH_SIZE_VT_1M: 458 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); 459 break; 460 case G4x_GMCH_SIZE_VT_1_5M: 461 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); 462 break; 463 case G4x_GMCH_SIZE_2M: 464 case G4x_GMCH_SIZE_VT_2M: 465 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); 466 break; 467 } 468 } 469 470 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 471 472 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 473 case I965_PGETBL_SIZE_128KB: 474 size = KB(128); 475 break; 476 case I965_PGETBL_SIZE_256KB: 477 size = KB(256); 478 break; 479 case I965_PGETBL_SIZE_512KB: 480 size = KB(512); 481 break; 482 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 483 case I965_PGETBL_SIZE_1MB: 484 size = KB(1024); 485 break; 486 case I965_PGETBL_SIZE_2MB: 487 size = KB(2048); 488 break; 489 case I965_PGETBL_SIZE_1_5MB: 490 size = KB(1024 + 512); 491 break; 492 default: 493 dev_info(&intel_private.pcidev->dev, 494 "unknown page table size, assuming 512KB\n"); 495 size = KB(512); 496 } 497 498 return size/4; 499} 500 501static unsigned int intel_gtt_total_entries(void) 502{ 503 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 504 return i965_gtt_total_entries(); 505 else { 506 /* On previous hardware, the GTT size was just what was 507 * required to map the aperture. 508 */ 509 return intel_private.base.gtt_mappable_entries; 510 } 511} 512 513static unsigned int intel_gtt_mappable_entries(void) 514{ 515 unsigned int aperture_size; 516 517 if (INTEL_GTT_GEN == 1) { 518 u32 smram_miscc; 519 520 pci_read_config_dword(intel_private.bridge_dev, 521 I810_SMRAM_MISCC, &smram_miscc); 522 523 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) 524 == I810_GFX_MEM_WIN_32M) 525 aperture_size = MB(32); 526 else 527 aperture_size = MB(64); 528 } else if (INTEL_GTT_GEN == 2) { 529 u16 gmch_ctrl; 530 531 pci_read_config_word(intel_private.bridge_dev, 532 I830_GMCH_CTRL, &gmch_ctrl); 533 534 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 535 aperture_size = MB(64); 536 else 537 aperture_size = MB(128); 538 } else { 539 /* 9xx supports large sizes, just look at the length */ 540 aperture_size = pci_resource_len(intel_private.pcidev, 2); 541 } 542 543 return aperture_size >> PAGE_SHIFT; 544} 545 546static void intel_gtt_teardown_scratch_page(void) 547{ 548 set_pages_wb(intel_private.scratch_page, 1); 549 pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma, 550 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 551 put_page(intel_private.scratch_page); 552 __free_page(intel_private.scratch_page); 553} 554 555static void intel_gtt_cleanup(void) 556{ 557 intel_private.driver->cleanup(); 558 559 iounmap(intel_private.gtt); 560 iounmap(intel_private.registers); 561 562 intel_gtt_teardown_scratch_page(); 563} 564 565static int intel_gtt_init(void) 566{ 567 u32 gma_addr; 568 u32 gtt_map_size; 569 int ret; 570 571 ret = intel_private.driver->setup(); 572 if (ret != 0) 573 return ret; 574 575 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 576 intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 577 578 /* save the PGETBL reg for resume */ 579 intel_private.PGETBL_save = 580 readl(intel_private.registers+I810_PGETBL_CTL) 581 & ~I810_PGETBL_ENABLED; 582 /* we only ever restore the register when enabling the PGTBL... */ 583 if (HAS_PGTBL_EN) 584 intel_private.PGETBL_save |= I810_PGETBL_ENABLED; 585 586 dev_info(&intel_private.bridge_dev->dev, 587 "detected gtt size: %dK total, %dK mappable\n", 588 intel_private.base.gtt_total_entries * 4, 589 intel_private.base.gtt_mappable_entries * 4); 590 591 gtt_map_size = intel_private.base.gtt_total_entries * 4; 592 593 intel_private.gtt = NULL; 594 if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2) 595 intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, 596 gtt_map_size); 597 if (intel_private.gtt == NULL) 598 intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 599 gtt_map_size); 600 if (intel_private.gtt == NULL) { 601 intel_private.driver->cleanup(); 602 iounmap(intel_private.registers); 603 return -ENOMEM; 604 } 605 606 global_cache_flush(); /* FIXME: ? */ 607 608 intel_private.base.stolen_size = intel_gtt_stolen_size(); 609 610 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; 611 612 ret = intel_gtt_setup_scratch_page(); 613 if (ret != 0) { 614 intel_gtt_cleanup(); 615 return ret; 616 } 617 618 if (INTEL_GTT_GEN <= 2) 619 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 620 &gma_addr); 621 else 622 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 623 &gma_addr); 624 625 intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 626 627 return 0; 628} 629 630static int intel_fake_agp_fetch_size(void) 631{ 632 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 633 unsigned int aper_size; 634 int i; 635 636 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) 637 / MB(1); 638 639 for (i = 0; i < num_sizes; i++) { 640 if (aper_size == intel_fake_agp_sizes[i].size) { 641 agp_bridge->current_size = 642 (void *) (intel_fake_agp_sizes + i); 643 return aper_size; 644 } 645 } 646 647 return 0; 648} 649 650static void i830_cleanup(void) 651{ 652} 653 654/* The chipset_flush interface needs to get data that has already been 655 * flushed out of the CPU all the way out to main memory, because the GPU 656 * doesn't snoop those buffers. 657 * 658 * The 8xx series doesn't have the same lovely interface for flushing the 659 * chipset write buffers that the later chips do. According to the 865 660 * specs, it's 64 octwords, or 1KB. So, to get those previous things in 661 * that buffer out, we just fill 1KB and clflush it out, on the assumption 662 * that it'll push whatever was in there out. It appears to work. 663 */ 664static void i830_chipset_flush(void) 665{ 666 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 667 668 /* Forcibly evict everything from the CPU write buffers. 669 * clflush appears to be insufficient. 670 */ 671 wbinvd_on_all_cpus(); 672 673 /* Now we've only seen documents for this magic bit on 855GM, 674 * we hope it exists for the other gen2 chipsets... 675 * 676 * Also works as advertised on my 845G. 677 */ 678 writel(readl(intel_private.registers+I830_HIC) | (1<<31), 679 intel_private.registers+I830_HIC); 680 681 while (readl(intel_private.registers+I830_HIC) & (1<<31)) { 682 if (time_after(jiffies, timeout)) 683 break; 684 685 udelay(50); 686 } 687} 688 689static void i830_write_entry(dma_addr_t addr, unsigned int entry, 690 unsigned int flags) 691{ 692 u32 pte_flags = I810_PTE_VALID; 693 694 if (flags == AGP_USER_CACHED_MEMORY) 695 pte_flags |= I830_PTE_SYSTEM_CACHED; 696 697 writel(addr | pte_flags, intel_private.gtt + entry); 698} 699 700bool intel_enable_gtt(void) 701{ 702 u8 __iomem *reg; 703 704 if (INTEL_GTT_GEN == 2) { 705 u16 gmch_ctrl; 706 707 pci_read_config_word(intel_private.bridge_dev, 708 I830_GMCH_CTRL, &gmch_ctrl); 709 gmch_ctrl |= I830_GMCH_ENABLED; 710 pci_write_config_word(intel_private.bridge_dev, 711 I830_GMCH_CTRL, gmch_ctrl); 712 713 pci_read_config_word(intel_private.bridge_dev, 714 I830_GMCH_CTRL, &gmch_ctrl); 715 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { 716 dev_err(&intel_private.pcidev->dev, 717 "failed to enable the GTT: GMCH_CTRL=%x\n", 718 gmch_ctrl); 719 return false; 720 } 721 } 722 723 /* On the resume path we may be adjusting the PGTBL value, so 724 * be paranoid and flush all chipset write buffers... 725 */ 726 if (INTEL_GTT_GEN >= 3) 727 writel(0, intel_private.registers+GFX_FLSH_CNTL); 728 729 reg = intel_private.registers+I810_PGETBL_CTL; 730 writel(intel_private.PGETBL_save, reg); 731 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { 732 dev_err(&intel_private.pcidev->dev, 733 "failed to enable the GTT: PGETBL=%x [expected %x]\n", 734 readl(reg), intel_private.PGETBL_save); 735 return false; 736 } 737 738 if (INTEL_GTT_GEN >= 3) 739 writel(0, intel_private.registers+GFX_FLSH_CNTL); 740 741 return true; 742} 743EXPORT_SYMBOL(intel_enable_gtt); 744 745static int i830_setup(void) 746{ 747 u32 reg_addr; 748 749 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 750 reg_addr &= 0xfff80000; 751 752 intel_private.registers = ioremap(reg_addr, KB(64)); 753 if (!intel_private.registers) 754 return -ENOMEM; 755 756 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 757 758 return 0; 759} 760 761static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 762{ 763 agp_bridge->gatt_table_real = NULL; 764 agp_bridge->gatt_table = NULL; 765 agp_bridge->gatt_bus_addr = 0; 766 767 return 0; 768} 769 770static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 771{ 772 return 0; 773} 774 775static int intel_fake_agp_configure(void) 776{ 777 if (!intel_enable_gtt()) 778 return -EIO; 779 780 intel_private.clear_fake_agp = true; 781 agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr; 782 783 return 0; 784} 785 786static bool i830_check_flags(unsigned int flags) 787{ 788 switch (flags) { 789 case 0: 790 case AGP_PHYS_MEMORY: 791 case AGP_USER_CACHED_MEMORY: 792 case AGP_USER_MEMORY: 793 return true; 794 } 795 796 return false; 797} 798 799void intel_gtt_insert_sg_entries(struct sg_table *st, 800 unsigned int pg_start, 801 unsigned int flags) 802{ 803 struct scatterlist *sg; 804 unsigned int len, m; 805 int i, j; 806 807 j = pg_start; 808 809 /* sg may merge pages, but we have to separate 810 * per-page addr for GTT */ 811 for_each_sg(st->sgl, sg, st->nents, i) { 812 len = sg_dma_len(sg) >> PAGE_SHIFT; 813 for (m = 0; m < len; m++) { 814 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 815 intel_private.driver->write_entry(addr, j, flags); 816 j++; 817 } 818 } 819 readl(intel_private.gtt+j-1); 820} 821EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 822 823static void intel_gtt_insert_pages(unsigned int first_entry, 824 unsigned int num_entries, 825 struct page **pages, 826 unsigned int flags) 827{ 828 int i, j; 829 830 for (i = 0, j = first_entry; i < num_entries; i++, j++) { 831 dma_addr_t addr = page_to_phys(pages[i]); 832 intel_private.driver->write_entry(addr, 833 j, flags); 834 } 835 readl(intel_private.gtt+j-1); 836} 837 838static int intel_fake_agp_insert_entries(struct agp_memory *mem, 839 off_t pg_start, int type) 840{ 841 int ret = -EINVAL; 842 843 if (intel_private.clear_fake_agp) { 844 int start = intel_private.base.stolen_size / PAGE_SIZE; 845 int end = intel_private.base.gtt_mappable_entries; 846 intel_gtt_clear_range(start, end - start); 847 intel_private.clear_fake_agp = false; 848 } 849 850 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) 851 return i810_insert_dcache_entries(mem, pg_start, type); 852 853 if (mem->page_count == 0) 854 goto out; 855 856 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) 857 goto out_err; 858 859 if (type != mem->type) 860 goto out_err; 861 862 if (!intel_private.driver->check_flags(type)) 863 goto out_err; 864 865 if (!mem->is_flushed) 866 global_cache_flush(); 867 868 if (intel_private.base.needs_dmar) { 869 struct sg_table st; 870 871 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st); 872 if (ret != 0) 873 return ret; 874 875 intel_gtt_insert_sg_entries(&st, pg_start, type); 876 mem->sg_list = st.sgl; 877 mem->num_sg = st.nents; 878 } else 879 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, 880 type); 881 882out: 883 ret = 0; 884out_err: 885 mem->is_flushed = true; 886 return ret; 887} 888 889void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 890{ 891 unsigned int i; 892 893 for (i = first_entry; i < (first_entry + num_entries); i++) { 894 intel_private.driver->write_entry(intel_private.base.scratch_page_dma, 895 i, 0); 896 } 897 readl(intel_private.gtt+i-1); 898} 899EXPORT_SYMBOL(intel_gtt_clear_range); 900 901static int intel_fake_agp_remove_entries(struct agp_memory *mem, 902 off_t pg_start, int type) 903{ 904 if (mem->page_count == 0) 905 return 0; 906 907 intel_gtt_clear_range(pg_start, mem->page_count); 908 909 if (intel_private.base.needs_dmar) { 910 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); 911 mem->sg_list = NULL; 912 mem->num_sg = 0; 913 } 914 915 return 0; 916} 917 918static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 919 int type) 920{ 921 struct agp_memory *new; 922 923 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { 924 if (pg_count != intel_private.num_dcache_entries) 925 return NULL; 926 927 new = agp_create_memory(1); 928 if (new == NULL) 929 return NULL; 930 931 new->type = AGP_DCACHE_MEMORY; 932 new->page_count = pg_count; 933 new->num_scratch_pages = 0; 934 agp_free_page_array(new); 935 return new; 936 } 937 if (type == AGP_PHYS_MEMORY) 938 return alloc_agpphysmem_i8xx(pg_count, type); 939 /* always return NULL for other allocation types for now */ 940 return NULL; 941} 942 943static int intel_alloc_chipset_flush_resource(void) 944{ 945 int ret; 946 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 947 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 948 pcibios_align_resource, intel_private.bridge_dev); 949 950 return ret; 951} 952 953static void intel_i915_setup_chipset_flush(void) 954{ 955 int ret; 956 u32 temp; 957 958 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 959 if (!(temp & 0x1)) { 960 intel_alloc_chipset_flush_resource(); 961 intel_private.resource_valid = 1; 962 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 963 } else { 964 temp &= ~1; 965 966 intel_private.resource_valid = 1; 967 intel_private.ifp_resource.start = temp; 968 intel_private.ifp_resource.end = temp + PAGE_SIZE; 969 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 970 /* some BIOSes reserve this area in a pnp some don't */ 971 if (ret) 972 intel_private.resource_valid = 0; 973 } 974} 975 976static void intel_i965_g33_setup_chipset_flush(void) 977{ 978 u32 temp_hi, temp_lo; 979 int ret; 980 981 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 982 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 983 984 if (!(temp_lo & 0x1)) { 985 986 intel_alloc_chipset_flush_resource(); 987 988 intel_private.resource_valid = 1; 989 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 990 upper_32_bits(intel_private.ifp_resource.start)); 991 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 992 } else { 993 u64 l64; 994 995 temp_lo &= ~0x1; 996 l64 = ((u64)temp_hi << 32) | temp_lo; 997 998 intel_private.resource_valid = 1; 999 intel_private.ifp_resource.start = l64; 1000 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1001 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1002 /* some BIOSes reserve this area in a pnp some don't */ 1003 if (ret) 1004 intel_private.resource_valid = 0; 1005 } 1006} 1007 1008static void intel_i9xx_setup_flush(void) 1009{ 1010 /* return if already configured */ 1011 if (intel_private.ifp_resource.start) 1012 return; 1013 1014 if (INTEL_GTT_GEN == 6) 1015 return; 1016 1017 /* setup a resource for this object */ 1018 intel_private.ifp_resource.name = "Intel Flush Page"; 1019 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1020 1021 /* Setup chipset flush for 915 */ 1022 if (IS_G33 || INTEL_GTT_GEN >= 4) { 1023 intel_i965_g33_setup_chipset_flush(); 1024 } else { 1025 intel_i915_setup_chipset_flush(); 1026 } 1027 1028 if (intel_private.ifp_resource.start) 1029 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1030 if (!intel_private.i9xx_flush_page) 1031 dev_err(&intel_private.pcidev->dev, 1032 "can't ioremap flush page - no chipset flushing\n"); 1033} 1034 1035static void i9xx_cleanup(void) 1036{ 1037 if (intel_private.i9xx_flush_page) 1038 iounmap(intel_private.i9xx_flush_page); 1039 if (intel_private.resource_valid) 1040 release_resource(&intel_private.ifp_resource); 1041 intel_private.ifp_resource.start = 0; 1042 intel_private.resource_valid = 0; 1043} 1044 1045static void i9xx_chipset_flush(void) 1046{ 1047 if (intel_private.i9xx_flush_page) 1048 writel(1, intel_private.i9xx_flush_page); 1049} 1050 1051static void i965_write_entry(dma_addr_t addr, 1052 unsigned int entry, 1053 unsigned int flags) 1054{ 1055 u32 pte_flags; 1056 1057 pte_flags = I810_PTE_VALID; 1058 if (flags == AGP_USER_CACHED_MEMORY) 1059 pte_flags |= I830_PTE_SYSTEM_CACHED; 1060 1061 /* Shift high bits down */ 1062 addr |= (addr >> 28) & 0xf0; 1063 writel(addr | pte_flags, intel_private.gtt + entry); 1064} 1065 1066 1067static int i9xx_setup(void) 1068{ 1069 u32 reg_addr, gtt_addr; 1070 int size = KB(512); 1071 1072 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 1073 1074 reg_addr &= 0xfff80000; 1075 1076 intel_private.registers = ioremap(reg_addr, size); 1077 if (!intel_private.registers) 1078 return -ENOMEM; 1079 1080 switch (INTEL_GTT_GEN) { 1081 case 3: 1082 pci_read_config_dword(intel_private.pcidev, 1083 I915_PTEADDR, >t_addr); 1084 intel_private.gtt_bus_addr = gtt_addr; 1085 break; 1086 case 5: 1087 intel_private.gtt_bus_addr = reg_addr + MB(2); 1088 break; 1089 default: 1090 intel_private.gtt_bus_addr = reg_addr + KB(512); 1091 break; 1092 } 1093 1094 intel_i9xx_setup_flush(); 1095 1096 return 0; 1097} 1098 1099static const struct agp_bridge_driver intel_fake_agp_driver = { 1100 .owner = THIS_MODULE, 1101 .size_type = FIXED_APER_SIZE, 1102 .aperture_sizes = intel_fake_agp_sizes, 1103 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1104 .configure = intel_fake_agp_configure, 1105 .fetch_size = intel_fake_agp_fetch_size, 1106 .cleanup = intel_gtt_cleanup, 1107 .agp_enable = intel_fake_agp_enable, 1108 .cache_flush = global_cache_flush, 1109 .create_gatt_table = intel_fake_agp_create_gatt_table, 1110 .free_gatt_table = intel_fake_agp_free_gatt_table, 1111 .insert_memory = intel_fake_agp_insert_entries, 1112 .remove_memory = intel_fake_agp_remove_entries, 1113 .alloc_by_type = intel_fake_agp_alloc_by_type, 1114 .free_by_type = intel_i810_free_by_type, 1115 .agp_alloc_page = agp_generic_alloc_page, 1116 .agp_alloc_pages = agp_generic_alloc_pages, 1117 .agp_destroy_page = agp_generic_destroy_page, 1118 .agp_destroy_pages = agp_generic_destroy_pages, 1119}; 1120 1121static const struct intel_gtt_driver i81x_gtt_driver = { 1122 .gen = 1, 1123 .has_pgtbl_enable = 1, 1124 .dma_mask_size = 32, 1125 .setup = i810_setup, 1126 .cleanup = i810_cleanup, 1127 .check_flags = i830_check_flags, 1128 .write_entry = i810_write_entry, 1129}; 1130static const struct intel_gtt_driver i8xx_gtt_driver = { 1131 .gen = 2, 1132 .has_pgtbl_enable = 1, 1133 .setup = i830_setup, 1134 .cleanup = i830_cleanup, 1135 .write_entry = i830_write_entry, 1136 .dma_mask_size = 32, 1137 .check_flags = i830_check_flags, 1138 .chipset_flush = i830_chipset_flush, 1139}; 1140static const struct intel_gtt_driver i915_gtt_driver = { 1141 .gen = 3, 1142 .has_pgtbl_enable = 1, 1143 .setup = i9xx_setup, 1144 .cleanup = i9xx_cleanup, 1145 /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1146 .write_entry = i830_write_entry, 1147 .dma_mask_size = 32, 1148 .check_flags = i830_check_flags, 1149 .chipset_flush = i9xx_chipset_flush, 1150}; 1151static const struct intel_gtt_driver g33_gtt_driver = { 1152 .gen = 3, 1153 .is_g33 = 1, 1154 .setup = i9xx_setup, 1155 .cleanup = i9xx_cleanup, 1156 .write_entry = i965_write_entry, 1157 .dma_mask_size = 36, 1158 .check_flags = i830_check_flags, 1159 .chipset_flush = i9xx_chipset_flush, 1160}; 1161static const struct intel_gtt_driver pineview_gtt_driver = { 1162 .gen = 3, 1163 .is_pineview = 1, .is_g33 = 1, 1164 .setup = i9xx_setup, 1165 .cleanup = i9xx_cleanup, 1166 .write_entry = i965_write_entry, 1167 .dma_mask_size = 36, 1168 .check_flags = i830_check_flags, 1169 .chipset_flush = i9xx_chipset_flush, 1170}; 1171static const struct intel_gtt_driver i965_gtt_driver = { 1172 .gen = 4, 1173 .has_pgtbl_enable = 1, 1174 .setup = i9xx_setup, 1175 .cleanup = i9xx_cleanup, 1176 .write_entry = i965_write_entry, 1177 .dma_mask_size = 36, 1178 .check_flags = i830_check_flags, 1179 .chipset_flush = i9xx_chipset_flush, 1180}; 1181static const struct intel_gtt_driver g4x_gtt_driver = { 1182 .gen = 5, 1183 .setup = i9xx_setup, 1184 .cleanup = i9xx_cleanup, 1185 .write_entry = i965_write_entry, 1186 .dma_mask_size = 36, 1187 .check_flags = i830_check_flags, 1188 .chipset_flush = i9xx_chipset_flush, 1189}; 1190static const struct intel_gtt_driver ironlake_gtt_driver = { 1191 .gen = 5, 1192 .is_ironlake = 1, 1193 .setup = i9xx_setup, 1194 .cleanup = i9xx_cleanup, 1195 .write_entry = i965_write_entry, 1196 .dma_mask_size = 36, 1197 .check_flags = i830_check_flags, 1198 .chipset_flush = i9xx_chipset_flush, 1199}; 1200 1201/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1202 * driver and gmch_driver must be non-null, and find_gmch will determine 1203 * which one should be used if a gmch_chip_id is present. 1204 */ 1205static const struct intel_gtt_driver_description { 1206 unsigned int gmch_chip_id; 1207 char *name; 1208 const struct intel_gtt_driver *gtt_driver; 1209} intel_gtt_chipsets[] = { 1210 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 1211 &i81x_gtt_driver}, 1212 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 1213 &i81x_gtt_driver}, 1214 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 1215 &i81x_gtt_driver}, 1216 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 1217 &i81x_gtt_driver}, 1218 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1219 &i8xx_gtt_driver}, 1220 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", 1221 &i8xx_gtt_driver}, 1222 { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1223 &i8xx_gtt_driver}, 1224 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1225 &i8xx_gtt_driver}, 1226 { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1227 &i8xx_gtt_driver}, 1228 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1229 &i915_gtt_driver }, 1230 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1231 &i915_gtt_driver }, 1232 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1233 &i915_gtt_driver }, 1234 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1235 &i915_gtt_driver }, 1236 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1237 &i915_gtt_driver }, 1238 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1239 &i915_gtt_driver }, 1240 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1241 &i965_gtt_driver }, 1242 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1243 &i965_gtt_driver }, 1244 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1245 &i965_gtt_driver }, 1246 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1247 &i965_gtt_driver }, 1248 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1249 &i965_gtt_driver }, 1250 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1251 &i965_gtt_driver }, 1252 { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1253 &g33_gtt_driver }, 1254 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1255 &g33_gtt_driver }, 1256 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1257 &g33_gtt_driver }, 1258 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1259 &pineview_gtt_driver }, 1260 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1261 &pineview_gtt_driver }, 1262 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1263 &g4x_gtt_driver }, 1264 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1265 &g4x_gtt_driver }, 1266 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1267 &g4x_gtt_driver }, 1268 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1269 &g4x_gtt_driver }, 1270 { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1271 &g4x_gtt_driver }, 1272 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1273 &g4x_gtt_driver }, 1274 { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1275 &g4x_gtt_driver }, 1276 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1277 "HD Graphics", &ironlake_gtt_driver }, 1278 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1279 "HD Graphics", &ironlake_gtt_driver }, 1280 { 0, NULL, NULL } 1281}; 1282 1283static int find_gmch(u16 device) 1284{ 1285 struct pci_dev *gmch_device; 1286 1287 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1288 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 1289 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 1290 device, gmch_device); 1291 } 1292 1293 if (!gmch_device) 1294 return 0; 1295 1296 intel_private.pcidev = gmch_device; 1297 return 1; 1298} 1299 1300int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 1301 struct agp_bridge_data *bridge) 1302{ 1303 int i, mask; 1304 1305 /* 1306 * Can be called from the fake agp driver but also directly from 1307 * drm/i915.ko. Hence we need to check whether everything is set up 1308 * already. 1309 */ 1310 if (intel_private.driver) { 1311 intel_private.refcount++; 1312 return 1; 1313 } 1314 1315 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 1316 if (gpu_pdev) { 1317 if (gpu_pdev->device == 1318 intel_gtt_chipsets[i].gmch_chip_id) { 1319 intel_private.pcidev = pci_dev_get(gpu_pdev); 1320 intel_private.driver = 1321 intel_gtt_chipsets[i].gtt_driver; 1322 1323 break; 1324 } 1325 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 1326 intel_private.driver = 1327 intel_gtt_chipsets[i].gtt_driver; 1328 break; 1329 } 1330 } 1331 1332 if (!intel_private.driver) 1333 return 0; 1334 1335 intel_private.refcount++; 1336 1337 if (bridge) { 1338 bridge->driver = &intel_fake_agp_driver; 1339 bridge->dev_private_data = &intel_private; 1340 bridge->dev = bridge_pdev; 1341 } 1342 1343 intel_private.bridge_dev = pci_dev_get(bridge_pdev); 1344 1345 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 1346 1347 mask = intel_private.driver->dma_mask_size; 1348 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 1349 dev_err(&intel_private.pcidev->dev, 1350 "set gfx device dma mask %d-bit failed!\n", mask); 1351 else 1352 pci_set_consistent_dma_mask(intel_private.pcidev, 1353 DMA_BIT_MASK(mask)); 1354 1355 if (intel_gtt_init() != 0) { 1356 intel_gmch_remove(); 1357 1358 return 0; 1359 } 1360 1361 return 1; 1362} 1363EXPORT_SYMBOL(intel_gmch_probe); 1364 1365struct intel_gtt *intel_gtt_get(void) 1366{ 1367 return &intel_private.base; 1368} 1369EXPORT_SYMBOL(intel_gtt_get); 1370 1371void intel_gtt_chipset_flush(void) 1372{ 1373 if (intel_private.driver->chipset_flush) 1374 intel_private.driver->chipset_flush(); 1375} 1376EXPORT_SYMBOL(intel_gtt_chipset_flush); 1377 1378void intel_gmch_remove(void) 1379{ 1380 if (--intel_private.refcount) 1381 return; 1382 1383 if (intel_private.pcidev) 1384 pci_dev_put(intel_private.pcidev); 1385 if (intel_private.bridge_dev) 1386 pci_dev_put(intel_private.bridge_dev); 1387 intel_private.driver = NULL; 1388} 1389EXPORT_SYMBOL(intel_gmch_remove); 1390 1391MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1392MODULE_LICENSE("GPL and additional rights"); 1393