1/*
2 *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/wait.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23
24#include "pmc.h"
25
26#define PLL_STATUS_MASK(id)	(1 << (1 + (id)))
27#define PLL_REG(id)		(AT91_CKGR_PLLAR + ((id) * 4))
28#define PLL_DIV_MASK		0xff
29#define PLL_DIV_MAX		PLL_DIV_MASK
30#define PLL_DIV(reg)		((reg) & PLL_DIV_MASK)
31#define PLL_MUL(reg, layout)	(((reg) >> (layout)->mul_shift) & \
32				 (layout)->mul_mask)
33#define PLL_MUL_MIN		2
34#define PLL_MUL_MASK(layout)	((layout)->mul_mask)
35#define PLL_MUL_MAX(layout)	(PLL_MUL_MASK(layout) + 1)
36#define PLL_ICPR_SHIFT(id)	((id) * 16)
37#define PLL_ICPR_MASK(id)	(0xffff << PLL_ICPR_SHIFT(id))
38#define PLL_MAX_COUNT		0x3f
39#define PLL_COUNT_SHIFT		8
40#define PLL_OUT_SHIFT		14
41#define PLL_MAX_ID		1
42
43struct clk_pll_characteristics {
44	struct clk_range input;
45	int num_output;
46	struct clk_range *output;
47	u16 *icpll;
48	u8 *out;
49};
50
51struct clk_pll_layout {
52	u32 pllr_mask;
53	u16 mul_mask;
54	u8 mul_shift;
55};
56
57#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
58
59struct clk_pll {
60	struct clk_hw hw;
61	struct at91_pmc *pmc;
62	unsigned int irq;
63	wait_queue_head_t wait;
64	u8 id;
65	u8 div;
66	u8 range;
67	u16 mul;
68	const struct clk_pll_layout *layout;
69	const struct clk_pll_characteristics *characteristics;
70};
71
72static irqreturn_t clk_pll_irq_handler(int irq, void *dev_id)
73{
74	struct clk_pll *pll = (struct clk_pll *)dev_id;
75
76	wake_up(&pll->wait);
77	disable_irq_nosync(pll->irq);
78
79	return IRQ_HANDLED;
80}
81
82static int clk_pll_prepare(struct clk_hw *hw)
83{
84	struct clk_pll *pll = to_clk_pll(hw);
85	struct at91_pmc *pmc = pll->pmc;
86	const struct clk_pll_layout *layout = pll->layout;
87	const struct clk_pll_characteristics *characteristics =
88							pll->characteristics;
89	u8 id = pll->id;
90	u32 mask = PLL_STATUS_MASK(id);
91	int offset = PLL_REG(id);
92	u8 out = 0;
93	u32 pllr, icpr;
94	u8 div;
95	u16 mul;
96
97	pllr = pmc_read(pmc, offset);
98	div = PLL_DIV(pllr);
99	mul = PLL_MUL(pllr, layout);
100
101	if ((pmc_read(pmc, AT91_PMC_SR) & mask) &&
102	    (div == pll->div && mul == pll->mul))
103		return 0;
104
105	if (characteristics->out)
106		out = characteristics->out[pll->range];
107	if (characteristics->icpll) {
108		icpr = pmc_read(pmc, AT91_PMC_PLLICPR) & ~PLL_ICPR_MASK(id);
109		icpr |= (characteristics->icpll[pll->range] <<
110			PLL_ICPR_SHIFT(id));
111		pmc_write(pmc, AT91_PMC_PLLICPR, icpr);
112	}
113
114	pllr &= ~layout->pllr_mask;
115	pllr |= layout->pllr_mask &
116	       (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
117		(out << PLL_OUT_SHIFT) |
118		((pll->mul & layout->mul_mask) << layout->mul_shift));
119	pmc_write(pmc, offset, pllr);
120
121	while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) {
122		enable_irq(pll->irq);
123		wait_event(pll->wait,
124			   pmc_read(pmc, AT91_PMC_SR) & mask);
125	}
126
127	return 0;
128}
129
130static int clk_pll_is_prepared(struct clk_hw *hw)
131{
132	struct clk_pll *pll = to_clk_pll(hw);
133	struct at91_pmc *pmc = pll->pmc;
134
135	return !!(pmc_read(pmc, AT91_PMC_SR) &
136		  PLL_STATUS_MASK(pll->id));
137}
138
139static void clk_pll_unprepare(struct clk_hw *hw)
140{
141	struct clk_pll *pll = to_clk_pll(hw);
142	struct at91_pmc *pmc = pll->pmc;
143	const struct clk_pll_layout *layout = pll->layout;
144	int offset = PLL_REG(pll->id);
145	u32 tmp = pmc_read(pmc, offset) & ~(layout->pllr_mask);
146
147	pmc_write(pmc, offset, tmp);
148}
149
150static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
151					 unsigned long parent_rate)
152{
153	struct clk_pll *pll = to_clk_pll(hw);
154
155	if (!pll->div || !pll->mul)
156		return 0;
157
158	return (parent_rate / pll->div) * (pll->mul + 1);
159}
160
161static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
162				     unsigned long parent_rate,
163				     u32 *div, u32 *mul,
164				     u32 *index) {
165	const struct clk_pll_layout *layout = pll->layout;
166	const struct clk_pll_characteristics *characteristics =
167							pll->characteristics;
168	unsigned long bestremainder = ULONG_MAX;
169	unsigned long maxdiv, mindiv, tmpdiv;
170	long bestrate = -ERANGE;
171	unsigned long bestdiv;
172	unsigned long bestmul;
173	int i = 0;
174
175	/* Check if parent_rate is a valid input rate */
176	if (parent_rate < characteristics->input.min ||
177	    parent_rate > characteristics->input.max)
178		return -ERANGE;
179
180	/*
181	 * Calculate minimum divider based on the minimum multiplier, the
182	 * parent_rate and the requested rate.
183	 * Should always be 2 according to the input and output characteristics
184	 * of the PLL blocks.
185	 */
186	mindiv = (parent_rate * PLL_MUL_MIN) / rate;
187	if (!mindiv)
188		mindiv = 1;
189
190	/*
191	 * Calculate the maximum divider which is limited by PLL register
192	 * layout (limited by the MUL or DIV field size).
193	 */
194	maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
195	if (maxdiv > PLL_DIV_MAX)
196		maxdiv = PLL_DIV_MAX;
197
198	/*
199	 * Iterate over the acceptable divider values to find the best
200	 * divider/multiplier pair (the one that generates the closest
201	 * rate to the requested one).
202	 */
203	for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
204		unsigned long remainder;
205		unsigned long tmprate;
206		unsigned long tmpmul;
207
208		/*
209		 * Calculate the multiplier associated with the current
210		 * divider that provide the closest rate to the requested one.
211		 */
212		tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
213		tmprate = (parent_rate / tmpdiv) * tmpmul;
214		if (tmprate > rate)
215			remainder = tmprate - rate;
216		else
217			remainder = rate - tmprate;
218
219		/*
220		 * Compare the remainder with the best remainder found until
221		 * now and elect a new best multiplier/divider pair if the
222		 * current remainder is smaller than the best one.
223		 */
224		if (remainder < bestremainder) {
225			bestremainder = remainder;
226			bestdiv = tmpdiv;
227			bestmul = tmpmul;
228			bestrate = tmprate;
229		}
230
231		/*
232		 * We've found a perfect match!
233		 * Stop searching now and use this multiplier/divider pair.
234		 */
235		if (!remainder)
236			break;
237	}
238
239	/* We haven't found any multiplier/divider pair => return -ERANGE */
240	if (bestrate < 0)
241		return bestrate;
242
243	/* Check if bestrate is a valid output rate  */
244	for (i = 0; i < characteristics->num_output; i++) {
245		if (bestrate >= characteristics->output[i].min &&
246		    bestrate <= characteristics->output[i].max)
247			break;
248	}
249
250	if (i >= characteristics->num_output)
251		return -ERANGE;
252
253	if (div)
254		*div = bestdiv;
255	if (mul)
256		*mul = bestmul - 1;
257	if (index)
258		*index = i;
259
260	return bestrate;
261}
262
263static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
264					unsigned long *parent_rate)
265{
266	struct clk_pll *pll = to_clk_pll(hw);
267
268	return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
269					NULL, NULL, NULL);
270}
271
272static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
273			    unsigned long parent_rate)
274{
275	struct clk_pll *pll = to_clk_pll(hw);
276	long ret;
277	u32 div;
278	u32 mul;
279	u32 index;
280
281	ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
282				       &div, &mul, &index);
283	if (ret < 0)
284		return ret;
285
286	pll->range = index;
287	pll->div = div;
288	pll->mul = mul;
289
290	return 0;
291}
292
293static const struct clk_ops pll_ops = {
294	.prepare = clk_pll_prepare,
295	.unprepare = clk_pll_unprepare,
296	.is_prepared = clk_pll_is_prepared,
297	.recalc_rate = clk_pll_recalc_rate,
298	.round_rate = clk_pll_round_rate,
299	.set_rate = clk_pll_set_rate,
300};
301
302static struct clk * __init
303at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name,
304		      const char *parent_name, u8 id,
305		      const struct clk_pll_layout *layout,
306		      const struct clk_pll_characteristics *characteristics)
307{
308	struct clk_pll *pll;
309	struct clk *clk = NULL;
310	struct clk_init_data init;
311	int ret;
312	int offset = PLL_REG(id);
313	u32 tmp;
314
315	if (id > PLL_MAX_ID)
316		return ERR_PTR(-EINVAL);
317
318	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
319	if (!pll)
320		return ERR_PTR(-ENOMEM);
321
322	init.name = name;
323	init.ops = &pll_ops;
324	init.parent_names = &parent_name;
325	init.num_parents = 1;
326	init.flags = CLK_SET_RATE_GATE;
327
328	pll->id = id;
329	pll->hw.init = &init;
330	pll->layout = layout;
331	pll->characteristics = characteristics;
332	pll->pmc = pmc;
333	pll->irq = irq;
334	tmp = pmc_read(pmc, offset) & layout->pllr_mask;
335	pll->div = PLL_DIV(tmp);
336	pll->mul = PLL_MUL(tmp, layout);
337	init_waitqueue_head(&pll->wait);
338	irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
339	ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
340			  id ? "clk-pllb" : "clk-plla", pll);
341	if (ret)
342		return ERR_PTR(ret);
343
344	clk = clk_register(NULL, &pll->hw);
345	if (IS_ERR(clk))
346		kfree(pll);
347
348	return clk;
349}
350
351
352static const struct clk_pll_layout at91rm9200_pll_layout = {
353	.pllr_mask = 0x7FFFFFF,
354	.mul_shift = 16,
355	.mul_mask = 0x7FF,
356};
357
358static const struct clk_pll_layout at91sam9g45_pll_layout = {
359	.pllr_mask = 0xFFFFFF,
360	.mul_shift = 16,
361	.mul_mask = 0xFF,
362};
363
364static const struct clk_pll_layout at91sam9g20_pllb_layout = {
365	.pllr_mask = 0x3FFFFF,
366	.mul_shift = 16,
367	.mul_mask = 0x3F,
368};
369
370static const struct clk_pll_layout sama5d3_pll_layout = {
371	.pllr_mask = 0x1FFFFFF,
372	.mul_shift = 18,
373	.mul_mask = 0x7F,
374};
375
376
377static struct clk_pll_characteristics * __init
378of_at91_clk_pll_get_characteristics(struct device_node *np)
379{
380	int i;
381	int offset;
382	u32 tmp;
383	int num_output;
384	u32 num_cells;
385	struct clk_range input;
386	struct clk_range *output;
387	u8 *out = NULL;
388	u16 *icpll = NULL;
389	struct clk_pll_characteristics *characteristics;
390
391	if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
392		return NULL;
393
394	if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
395				 &num_cells))
396		return NULL;
397
398	if (num_cells < 2 || num_cells > 4)
399		return NULL;
400
401	if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
402		return NULL;
403	num_output = tmp / (sizeof(u32) * num_cells);
404
405	characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
406	if (!characteristics)
407		return NULL;
408
409	output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
410	if (!output)
411		goto out_free_characteristics;
412
413	if (num_cells > 2) {
414		out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
415		if (!out)
416			goto out_free_output;
417	}
418
419	if (num_cells > 3) {
420		icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
421		if (!icpll)
422			goto out_free_output;
423	}
424
425	for (i = 0; i < num_output; i++) {
426		offset = i * num_cells;
427		if (of_property_read_u32_index(np,
428					       "atmel,pll-clk-output-ranges",
429					       offset, &tmp))
430			goto out_free_output;
431		output[i].min = tmp;
432		if (of_property_read_u32_index(np,
433					       "atmel,pll-clk-output-ranges",
434					       offset + 1, &tmp))
435			goto out_free_output;
436		output[i].max = tmp;
437
438		if (num_cells == 2)
439			continue;
440
441		if (of_property_read_u32_index(np,
442					       "atmel,pll-clk-output-ranges",
443					       offset + 2, &tmp))
444			goto out_free_output;
445		out[i] = tmp;
446
447		if (num_cells == 3)
448			continue;
449
450		if (of_property_read_u32_index(np,
451					       "atmel,pll-clk-output-ranges",
452					       offset + 3, &tmp))
453			goto out_free_output;
454		icpll[i] = tmp;
455	}
456
457	characteristics->input = input;
458	characteristics->num_output = num_output;
459	characteristics->output = output;
460	characteristics->out = out;
461	characteristics->icpll = icpll;
462	return characteristics;
463
464out_free_output:
465	kfree(icpll);
466	kfree(out);
467	kfree(output);
468out_free_characteristics:
469	kfree(characteristics);
470	return NULL;
471}
472
473static void __init
474of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc,
475		      const struct clk_pll_layout *layout)
476{
477	u32 id;
478	unsigned int irq;
479	struct clk *clk;
480	const char *parent_name;
481	const char *name = np->name;
482	struct clk_pll_characteristics *characteristics;
483
484	if (of_property_read_u32(np, "reg", &id))
485		return;
486
487	parent_name = of_clk_get_parent_name(np, 0);
488
489	of_property_read_string(np, "clock-output-names", &name);
490
491	characteristics = of_at91_clk_pll_get_characteristics(np);
492	if (!characteristics)
493		return;
494
495	irq = irq_of_parse_and_map(np, 0);
496	if (!irq)
497		return;
498
499	clk = at91_clk_register_pll(pmc, irq, name, parent_name, id, layout,
500				    characteristics);
501	if (IS_ERR(clk))
502		goto out_free_characteristics;
503
504	of_clk_add_provider(np, of_clk_src_simple_get, clk);
505	return;
506
507out_free_characteristics:
508	kfree(characteristics);
509}
510
511void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
512					       struct at91_pmc *pmc)
513{
514	of_at91_clk_pll_setup(np, pmc, &at91rm9200_pll_layout);
515}
516
517void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
518						struct at91_pmc *pmc)
519{
520	of_at91_clk_pll_setup(np, pmc, &at91sam9g45_pll_layout);
521}
522
523void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
524						 struct at91_pmc *pmc)
525{
526	of_at91_clk_pll_setup(np, pmc, &at91sam9g20_pllb_layout);
527}
528
529void __init of_sama5d3_clk_pll_setup(struct device_node *np,
530					    struct at91_pmc *pmc)
531{
532	of_at91_clk_pll_setup(np, pmc, &sama5d3_pll_layout);
533}
534