1/* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Rahul Sharma <rahul.sharma@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Common Clock Framework support for Exynos5260 SoC. 10 */ 11 12#include <linux/clk.h> 13#include <linux/clkdev.h> 14#include <linux/clk-provider.h> 15#include <linux/of.h> 16#include <linux/of_address.h> 17#include <linux/syscore_ops.h> 18 19#include "clk-exynos5260.h" 20#include "clk.h" 21#include "clk-pll.h" 22 23#include <dt-bindings/clock/exynos5260-clk.h> 24 25static LIST_HEAD(clock_reg_cache_list); 26 27struct exynos5260_clock_reg_cache { 28 struct list_head node; 29 void __iomem *reg_base; 30 struct samsung_clk_reg_dump *rdump; 31 unsigned int rd_num; 32}; 33 34struct exynos5260_cmu_info { 35 /* list of pll clocks and respective count */ 36 struct samsung_pll_clock *pll_clks; 37 unsigned int nr_pll_clks; 38 /* list of mux clocks and respective count */ 39 struct samsung_mux_clock *mux_clks; 40 unsigned int nr_mux_clks; 41 /* list of div clocks and respective count */ 42 struct samsung_div_clock *div_clks; 43 unsigned int nr_div_clks; 44 /* list of gate clocks and respective count */ 45 struct samsung_gate_clock *gate_clks; 46 unsigned int nr_gate_clks; 47 /* list of fixed clocks and respective count */ 48 struct samsung_fixed_rate_clock *fixed_clks; 49 unsigned int nr_fixed_clks; 50 /* total number of clocks with IDs assigned*/ 51 unsigned int nr_clk_ids; 52 53 /* list and number of clocks registers */ 54 unsigned long *clk_regs; 55 unsigned int nr_clk_regs; 56}; 57 58/* 59 * Applicable for all 2550 Type PLLS for Exynos5260, listed below 60 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL. 61 */ 62static struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initdata = { 63 PLL_35XX_RATE(1700000000, 425, 6, 0), 64 PLL_35XX_RATE(1600000000, 200, 3, 0), 65 PLL_35XX_RATE(1500000000, 250, 4, 0), 66 PLL_35XX_RATE(1400000000, 175, 3, 0), 67 PLL_35XX_RATE(1300000000, 325, 6, 0), 68 PLL_35XX_RATE(1200000000, 400, 4, 1), 69 PLL_35XX_RATE(1100000000, 275, 3, 1), 70 PLL_35XX_RATE(1000000000, 250, 3, 1), 71 PLL_35XX_RATE(933000000, 311, 4, 1), 72 PLL_35XX_RATE(900000000, 300, 4, 1), 73 PLL_35XX_RATE(800000000, 200, 3, 1), 74 PLL_35XX_RATE(733000000, 733, 12, 1), 75 PLL_35XX_RATE(700000000, 175, 3, 1), 76 PLL_35XX_RATE(667000000, 667, 12, 1), 77 PLL_35XX_RATE(633000000, 211, 4, 1), 78 PLL_35XX_RATE(620000000, 310, 3, 2), 79 PLL_35XX_RATE(600000000, 400, 4, 2), 80 PLL_35XX_RATE(543000000, 362, 4, 2), 81 PLL_35XX_RATE(533000000, 533, 6, 2), 82 PLL_35XX_RATE(500000000, 250, 3, 2), 83 PLL_35XX_RATE(450000000, 300, 4, 2), 84 PLL_35XX_RATE(400000000, 200, 3, 2), 85 PLL_35XX_RATE(350000000, 175, 3, 2), 86 PLL_35XX_RATE(300000000, 400, 4, 3), 87 PLL_35XX_RATE(266000000, 266, 3, 3), 88 PLL_35XX_RATE(200000000, 200, 3, 3), 89 PLL_35XX_RATE(160000000, 160, 3, 3), 90}; 91 92/* 93 * Applicable for 2650 Type PLL for AUD_PLL. 94 */ 95static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = { 96 PLL_36XX_RATE(1600000000, 200, 3, 0, 0), 97 PLL_36XX_RATE(1200000000, 100, 2, 0, 0), 98 PLL_36XX_RATE(1000000000, 250, 3, 1, 0), 99 PLL_36XX_RATE(800000000, 200, 3, 1, 0), 100 PLL_36XX_RATE(600000000, 100, 2, 1, 0), 101 PLL_36XX_RATE(532000000, 266, 3, 2, 0), 102 PLL_36XX_RATE(480000000, 160, 2, 2, 0), 103 PLL_36XX_RATE(432000000, 144, 2, 2, 0), 104 PLL_36XX_RATE(400000000, 200, 3, 2, 0), 105 PLL_36XX_RATE(394073130, 459, 7, 2, 49282), 106 PLL_36XX_RATE(333000000, 111, 2, 2, 0), 107 PLL_36XX_RATE(300000000, 100, 2, 2, 0), 108 PLL_36XX_RATE(266000000, 266, 3, 3, 0), 109 PLL_36XX_RATE(200000000, 200, 3, 3, 0), 110 PLL_36XX_RATE(166000000, 166, 3, 3, 0), 111 PLL_36XX_RATE(133000000, 266, 3, 4, 0), 112 PLL_36XX_RATE(100000000, 200, 3, 4, 0), 113 PLL_36XX_RATE(66000000, 176, 2, 5, 0), 114}; 115 116#ifdef CONFIG_PM_SLEEP 117 118static int exynos5260_clk_suspend(void) 119{ 120 struct exynos5260_clock_reg_cache *cache; 121 122 list_for_each_entry(cache, &clock_reg_cache_list, node) 123 samsung_clk_save(cache->reg_base, cache->rdump, 124 cache->rd_num); 125 126 return 0; 127} 128 129static void exynos5260_clk_resume(void) 130{ 131 struct exynos5260_clock_reg_cache *cache; 132 133 list_for_each_entry(cache, &clock_reg_cache_list, node) 134 samsung_clk_restore(cache->reg_base, cache->rdump, 135 cache->rd_num); 136} 137 138static struct syscore_ops exynos5260_clk_syscore_ops = { 139 .suspend = exynos5260_clk_suspend, 140 .resume = exynos5260_clk_resume, 141}; 142 143static void exynos5260_clk_sleep_init(void __iomem *reg_base, 144 unsigned long *rdump, 145 unsigned long nr_rdump) 146{ 147 struct exynos5260_clock_reg_cache *reg_cache; 148 149 reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache), 150 GFP_KERNEL); 151 if (!reg_cache) 152 panic("could not allocate register cache.\n"); 153 154 reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump); 155 156 if (!reg_cache->rdump) 157 panic("could not allocate register dump storage.\n"); 158 159 if (list_empty(&clock_reg_cache_list)) 160 register_syscore_ops(&exynos5260_clk_syscore_ops); 161 162 reg_cache->rd_num = nr_rdump; 163 reg_cache->reg_base = reg_base; 164 list_add_tail(®_cache->node, &clock_reg_cache_list); 165} 166 167#else 168static void exynos5260_clk_sleep_init(void __iomem *reg_base, 169 unsigned long *rdump, 170 unsigned long nr_rdump){} 171#endif 172 173/* 174 * Common function which registers plls, muxes, dividers and gates 175 * for each CMU. It also add CMU register list to register cache. 176 */ 177 178void __init exynos5260_cmu_register_one(struct device_node *np, 179 struct exynos5260_cmu_info *cmu) 180{ 181 void __iomem *reg_base; 182 struct samsung_clk_provider *ctx; 183 184 reg_base = of_iomap(np, 0); 185 if (!reg_base) 186 panic("%s: failed to map registers\n", __func__); 187 188 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids); 189 if (!ctx) 190 panic("%s: unable to alllocate ctx\n", __func__); 191 192 if (cmu->pll_clks) 193 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks, 194 reg_base); 195 if (cmu->mux_clks) 196 samsung_clk_register_mux(ctx, cmu->mux_clks, 197 cmu->nr_mux_clks); 198 if (cmu->div_clks) 199 samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks); 200 if (cmu->gate_clks) 201 samsung_clk_register_gate(ctx, cmu->gate_clks, 202 cmu->nr_gate_clks); 203 if (cmu->fixed_clks) 204 samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks, 205 cmu->nr_fixed_clks); 206 if (cmu->clk_regs) 207 exynos5260_clk_sleep_init(reg_base, cmu->clk_regs, 208 cmu->nr_clk_regs); 209 210 samsung_clk_of_add_provider(np, ctx); 211} 212 213 214/* CMU_AUD */ 215 216static unsigned long aud_clk_regs[] __initdata = { 217 MUX_SEL_AUD, 218 DIV_AUD0, 219 DIV_AUD1, 220 EN_ACLK_AUD, 221 EN_PCLK_AUD, 222 EN_SCLK_AUD, 223 EN_IP_AUD, 224}; 225 226PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"}; 227PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"}; 228PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"}; 229 230struct samsung_mux_clock aud_mux_clks[] __initdata = { 231 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p, 232 MUX_SEL_AUD, 0, 1), 233 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, 234 MUX_SEL_AUD, 4, 1), 235 MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, 236 MUX_SEL_AUD, 8, 1), 237}; 238 239struct samsung_div_clock aud_div_clks[] __initdata = { 240 DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user", 241 DIV_AUD0, 0, 4), 242 243 DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s", 244 DIV_AUD1, 0, 4), 245 DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm", 246 DIV_AUD1, 4, 8), 247 DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user", 248 DIV_AUD1, 12, 4), 249}; 250 251struct samsung_gate_clock aud_gate_clks[] __initdata = { 252 GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s", 253 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0), 254 GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", 255 EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0), 256 GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart", 257 EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0), 258 259 GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD, 260 0, 0, 0), 261 GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131", 262 EN_IP_AUD, 1, 0, 0), 263 GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0), 264 GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0), 265 GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131", 266 EN_IP_AUD, 4, 0, 0), 267}; 268 269static void __init exynos5260_clk_aud_init(struct device_node *np) 270{ 271 struct exynos5260_cmu_info cmu = {0}; 272 273 cmu.mux_clks = aud_mux_clks; 274 cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks); 275 cmu.div_clks = aud_div_clks; 276 cmu.nr_div_clks = ARRAY_SIZE(aud_div_clks); 277 cmu.gate_clks = aud_gate_clks; 278 cmu.nr_gate_clks = ARRAY_SIZE(aud_gate_clks); 279 cmu.nr_clk_ids = AUD_NR_CLK; 280 cmu.clk_regs = aud_clk_regs; 281 cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs); 282 283 exynos5260_cmu_register_one(np, &cmu); 284} 285 286CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud", 287 exynos5260_clk_aud_init); 288 289 290/* CMU_DISP */ 291 292static unsigned long disp_clk_regs[] __initdata = { 293 MUX_SEL_DISP0, 294 MUX_SEL_DISP1, 295 MUX_SEL_DISP2, 296 MUX_SEL_DISP3, 297 MUX_SEL_DISP4, 298 DIV_DISP, 299 EN_ACLK_DISP, 300 EN_PCLK_DISP, 301 EN_SCLK_DISP0, 302 EN_SCLK_DISP1, 303 EN_IP_DISP, 304 EN_IP_DISP_BUS, 305}; 306 307PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll", 308 "phyclk_dptx_phy_ch3_txd_clk"}; 309PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll", 310 "phyclk_dptx_phy_ch2_txd_clk"}; 311PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll", 312 "phyclk_dptx_phy_ch1_txd_clk"}; 313PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll", 314 "phyclk_dptx_phy_ch0_txd_clk"}; 315PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"}; 316PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"}; 317PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"}; 318PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll", 319 "phyclk_hdmi_phy_tmds_clko"}; 320PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll", 321 "phyclk_hdmi_phy_ref_clko"}; 322PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll", 323 "phyclk_hdmi_phy_pixel_clko"}; 324PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll", 325 "phyclk_hdmi_link_o_tmds_clkhi"}; 326PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll", 327 "phyclk_mipi_dphy_4l_m_txbyte_clkhs"}; 328PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll", 329 "phyclk_dptx_phy_o_ref_clk_24m"}; 330PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll", 331 "phyclk_dptx_phy_clk_div2"}; 332PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user", 333 "mout_aclk_disp_222_user"}; 334PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll", 335 "phyclk_mipi_dphy_4l_m_rxclkesc0"}; 336PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", 337 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; 338 339struct samsung_mux_clock disp_mux_clks[] __initdata = { 340 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 341 mout_aclk_disp_333_user_p, 342 MUX_SEL_DISP0, 0, 1), 343 MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user", 344 mout_sclk_disp_pixel_user_p, 345 MUX_SEL_DISP0, 4, 1), 346 MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user", 347 mout_aclk_disp_222_user_p, 348 MUX_SEL_DISP0, 8, 1), 349 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER, 350 "mout_phyclk_dptx_phy_ch0_txd_clk_user", 351 mout_phyclk_dptx_phy_ch0_txd_clk_user_p, 352 MUX_SEL_DISP0, 16, 1), 353 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER, 354 "mout_phyclk_dptx_phy_ch1_txd_clk_user", 355 mout_phyclk_dptx_phy_ch1_txd_clk_user_p, 356 MUX_SEL_DISP0, 20, 1), 357 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER, 358 "mout_phyclk_dptx_phy_ch2_txd_clk_user", 359 mout_phyclk_dptx_phy_ch2_txd_clk_user_p, 360 MUX_SEL_DISP0, 24, 1), 361 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER, 362 "mout_phyclk_dptx_phy_ch3_txd_clk_user", 363 mout_phyclk_dptx_phy_ch3_txd_clk_user_p, 364 MUX_SEL_DISP0, 28, 1), 365 366 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER, 367 "mout_phyclk_dptx_phy_clk_div2_user", 368 mout_phyclk_dptx_phy_clk_div2_user_p, 369 MUX_SEL_DISP1, 0, 1), 370 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER, 371 "mout_phyclk_dptx_phy_o_ref_clk_24m_user", 372 mout_phyclk_dptx_phy_o_ref_clk_24m_user_p, 373 MUX_SEL_DISP1, 4, 1), 374 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS, 375 "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs", 376 mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, 377 MUX_SEL_DISP1, 8, 1), 378 MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER, 379 "mout_phyclk_hdmi_link_o_tmds_clkhi_user", 380 mout_phyclk_hdmi_link_o_tmds_clkhi_user_p, 381 MUX_SEL_DISP1, 16, 1), 382 MUX(DISP_MOUT_HDMI_PHY_PIXEL, 383 "mout_phyclk_hdmi_phy_pixel_clko_user", 384 mout_phyclk_hdmi_phy_pixel_clko_user_p, 385 MUX_SEL_DISP1, 20, 1), 386 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER, 387 "mout_phyclk_hdmi_phy_ref_clko_user", 388 mout_phyclk_hdmi_phy_ref_clko_user_p, 389 MUX_SEL_DISP1, 24, 1), 390 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER, 391 "mout_phyclk_hdmi_phy_tmds_clko_user", 392 mout_phyclk_hdmi_phy_tmds_clko_user_p, 393 MUX_SEL_DISP1, 28, 1), 394 395 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER, 396 "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user", 397 mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p, 398 MUX_SEL_DISP2, 0, 1), 399 MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel", 400 mout_sclk_hdmi_pixel_p, 401 MUX_SEL_DISP2, 4, 1), 402 403 MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 404 mout_sclk_hdmi_spdif_p, 405 MUX_SEL_DISP4, 4, 2), 406}; 407 408struct samsung_div_clock disp_div_clks[] __initdata = { 409 DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111", 410 "mout_aclk_disp_222_user", 411 DIV_DISP, 8, 4), 412 DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll", 413 "mout_sclk_disp_pixel_user", 414 DIV_DISP, 12, 4), 415 DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI, 416 "dout_sclk_hdmi_phy_pixel_clki", 417 "mout_sclk_hdmi_pixel", 418 DIV_DISP, 16, 4), 419}; 420 421struct samsung_gate_clock disp_gate_clks[] __initdata = { 422 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel", 423 "mout_phyclk_hdmi_phy_pixel_clko_user", 424 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0), 425 GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki", 426 "dout_sclk_hdmi_phy_pixel_clki", 427 EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0), 428 429 GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user", 430 EN_IP_DISP, 4, 0, 0), 431 GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user", 432 EN_IP_DISP, 5, 0, 0), 433 GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user", 434 EN_IP_DISP, 6, 0, 0), 435 GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user", 436 EN_IP_DISP, 7, 0, 0), 437 GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user", 438 EN_IP_DISP, 8, 0, 0), 439 GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user", 440 EN_IP_DISP, 9, 0, 0), 441 GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user", 442 EN_IP_DISP, 10, 0, 0), 443 GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user", 444 EN_IP_DISP, 11, 0, 0), 445 GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user", 446 EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0), 447 GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user", 448 EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0), 449 GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0", 450 "mout_aclk_disp_222_user", 451 EN_IP_DISP, 22, 0, 0), 452 GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1", 453 "mout_aclk_disp_222_user", 454 EN_IP_DISP, 23, 0, 0), 455 GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user", 456 EN_IP_DISP, 25, 0, 0), 457}; 458 459static void __init exynos5260_clk_disp_init(struct device_node *np) 460{ 461 struct exynos5260_cmu_info cmu = {0}; 462 463 cmu.mux_clks = disp_mux_clks; 464 cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks); 465 cmu.div_clks = disp_div_clks; 466 cmu.nr_div_clks = ARRAY_SIZE(disp_div_clks); 467 cmu.gate_clks = disp_gate_clks; 468 cmu.nr_gate_clks = ARRAY_SIZE(disp_gate_clks); 469 cmu.nr_clk_ids = DISP_NR_CLK; 470 cmu.clk_regs = disp_clk_regs; 471 cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs); 472 473 exynos5260_cmu_register_one(np, &cmu); 474} 475 476CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp", 477 exynos5260_clk_disp_init); 478 479 480/* CMU_EGL */ 481 482static unsigned long egl_clk_regs[] __initdata = { 483 EGL_PLL_LOCK, 484 EGL_PLL_CON0, 485 EGL_PLL_CON1, 486 EGL_PLL_FREQ_DET, 487 MUX_SEL_EGL, 488 MUX_ENABLE_EGL, 489 DIV_EGL, 490 DIV_EGL_PLL_FDET, 491 EN_ACLK_EGL, 492 EN_PCLK_EGL, 493 EN_SCLK_EGL, 494}; 495 496PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; 497PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; 498 499struct samsung_mux_clock egl_mux_clks[] __initdata = { 500 MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p, 501 MUX_SEL_EGL, 4, 1), 502 MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), 503}; 504 505struct samsung_div_clock egl_div_clks[] __initdata = { 506 DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), 507 DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), 508 DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), 509 DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk", 510 DIV_EGL, 12, 3), 511 DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3), 512 DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk", 513 DIV_EGL, 20, 3), 514 DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3), 515}; 516 517static struct samsung_pll_clock egl_pll_clks[] __initdata = { 518 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll", 519 EGL_PLL_LOCK, EGL_PLL_CON0, 520 pll2550_24mhz_tbl), 521}; 522 523static void __init exynos5260_clk_egl_init(struct device_node *np) 524{ 525 struct exynos5260_cmu_info cmu = {0}; 526 527 cmu.pll_clks = egl_pll_clks; 528 cmu.nr_pll_clks = ARRAY_SIZE(egl_pll_clks); 529 cmu.mux_clks = egl_mux_clks; 530 cmu.nr_mux_clks = ARRAY_SIZE(egl_mux_clks); 531 cmu.div_clks = egl_div_clks; 532 cmu.nr_div_clks = ARRAY_SIZE(egl_div_clks); 533 cmu.nr_clk_ids = EGL_NR_CLK; 534 cmu.clk_regs = egl_clk_regs; 535 cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs); 536 537 exynos5260_cmu_register_one(np, &cmu); 538} 539 540CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl", 541 exynos5260_clk_egl_init); 542 543 544/* CMU_FSYS */ 545 546static unsigned long fsys_clk_regs[] __initdata = { 547 MUX_SEL_FSYS0, 548 MUX_SEL_FSYS1, 549 EN_ACLK_FSYS, 550 EN_ACLK_FSYS_SECURE_RTIC, 551 EN_ACLK_FSYS_SECURE_SMMU_RTIC, 552 EN_SCLK_FSYS, 553 EN_IP_FSYS, 554 EN_IP_FSYS_SECURE_RTIC, 555 EN_IP_FSYS_SECURE_SMMU_RTIC, 556}; 557 558PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll", 559 "phyclk_usbhost20_phy_phyclock"}; 560PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll", 561 "phyclk_usbhost20_phy_freeclk"}; 562PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll", 563 "phyclk_usbhost20_phy_clk48mohci"}; 564PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll", 565 "phyclk_usbdrd30_udrd30_pipe_pclk"}; 566PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", 567 "phyclk_usbdrd30_udrd30_phyclock"}; 568 569struct samsung_mux_clock fsys_mux_clks[] __initdata = { 570 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER, 571 "mout_phyclk_usbdrd30_phyclock_user", 572 mout_phyclk_usbdrd30_phyclock_user_p, 573 MUX_SEL_FSYS1, 0, 1), 574 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER, 575 "mout_phyclk_usbdrd30_pipe_pclk_user", 576 mout_phyclk_usbdrd30_pipe_pclk_user_p, 577 MUX_SEL_FSYS1, 4, 1), 578 MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER, 579 "mout_phyclk_usbhost20_clk48mohci_user", 580 mout_phyclk_usbhost20_clk48mohci_user_p, 581 MUX_SEL_FSYS1, 8, 1), 582 MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER, 583 "mout_phyclk_usbhost20_freeclk_user", 584 mout_phyclk_usbhost20_freeclk_user_p, 585 MUX_SEL_FSYS1, 12, 1), 586 MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER, 587 "mout_phyclk_usbhost20_phyclk_user", 588 mout_phyclk_usbhost20_phyclk_user_p, 589 MUX_SEL_FSYS1, 16, 1), 590}; 591 592struct samsung_gate_clock fsys_gate_clks[] __initdata = { 593 GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", 594 "mout_phyclk_usbdrd30_phyclock_user", 595 EN_SCLK_FSYS, 1, 0, 0), 596 GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g", 597 "mout_phyclk_usbdrd30_phyclock_user", 598 EN_SCLK_FSYS, 7, 0, 0), 599 600 GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200", 601 EN_IP_FSYS, 6, 0, 0), 602 GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200", 603 EN_IP_FSYS, 7, 0, 0), 604 GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200", 605 EN_IP_FSYS, 8, 0, 0), 606 GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200", 607 EN_IP_FSYS, 9, 0, 0), 608 GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200", 609 EN_IP_FSYS, 13, 0, 0), 610 GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200", 611 EN_IP_FSYS, 14, 0, 0), 612 GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200", 613 EN_IP_FSYS, 15, 0, 0), 614 GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200", 615 EN_IP_FSYS, 18, 0, 0), 616 GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200", 617 EN_IP_FSYS, 20, 0, 0), 618 619 GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200", 620 EN_IP_FSYS_SECURE_RTIC, 11, 0, 0), 621 GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200", 622 EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0), 623}; 624 625static void __init exynos5260_clk_fsys_init(struct device_node *np) 626{ 627 struct exynos5260_cmu_info cmu = {0}; 628 629 cmu.mux_clks = fsys_mux_clks; 630 cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks); 631 cmu.gate_clks = fsys_gate_clks; 632 cmu.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks); 633 cmu.nr_clk_ids = FSYS_NR_CLK; 634 cmu.clk_regs = fsys_clk_regs; 635 cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs); 636 637 exynos5260_cmu_register_one(np, &cmu); 638} 639 640CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys", 641 exynos5260_clk_fsys_init); 642 643 644/* CMU_G2D */ 645 646static unsigned long g2d_clk_regs[] __initdata = { 647 MUX_SEL_G2D, 648 MUX_STAT_G2D, 649 DIV_G2D, 650 EN_ACLK_G2D, 651 EN_ACLK_G2D_SECURE_SSS, 652 EN_ACLK_G2D_SECURE_SLIM_SSS, 653 EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS, 654 EN_ACLK_G2D_SECURE_SMMU_SSS, 655 EN_ACLK_G2D_SECURE_SMMU_MDMA, 656 EN_ACLK_G2D_SECURE_SMMU_G2D, 657 EN_PCLK_G2D, 658 EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS, 659 EN_PCLK_G2D_SECURE_SMMU_SSS, 660 EN_PCLK_G2D_SECURE_SMMU_MDMA, 661 EN_PCLK_G2D_SECURE_SMMU_G2D, 662 EN_IP_G2D, 663 EN_IP_G2D_SECURE_SSS, 664 EN_IP_G2D_SECURE_SLIM_SSS, 665 EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 666 EN_IP_G2D_SECURE_SMMU_SSS, 667 EN_IP_G2D_SECURE_SMMU_MDMA, 668 EN_IP_G2D_SECURE_SMMU_G2D, 669}; 670 671PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; 672 673struct samsung_mux_clock g2d_mux_clks[] __initdata = { 674 MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user", 675 mout_aclk_g2d_333_user_p, 676 MUX_SEL_G2D, 0, 1), 677}; 678 679struct samsung_div_clock g2d_div_clks[] __initdata = { 680 DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", 681 DIV_G2D, 0, 3), 682}; 683 684struct samsung_gate_clock g2d_gate_clks[] __initdata = { 685 GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user", 686 EN_IP_G2D, 4, 0, 0), 687 GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user", 688 EN_IP_G2D, 5, 0, 0), 689 GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user", 690 EN_IP_G2D, 6, 0, 0), 691 GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user", 692 EN_IP_G2D, 16, 0, 0), 693 694 GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user", 695 EN_IP_G2D_SECURE_SSS, 17, 0, 0), 696 697 GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user", 698 EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0), 699 700 GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss", 701 "mout_aclk_g2d_333_user", 702 EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0), 703 704 GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user", 705 EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0), 706 707 GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user", 708 EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0), 709 710 GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user", 711 EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0), 712}; 713 714static void __init exynos5260_clk_g2d_init(struct device_node *np) 715{ 716 struct exynos5260_cmu_info cmu = {0}; 717 718 cmu.mux_clks = g2d_mux_clks; 719 cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks); 720 cmu.div_clks = g2d_div_clks; 721 cmu.nr_div_clks = ARRAY_SIZE(g2d_div_clks); 722 cmu.gate_clks = g2d_gate_clks; 723 cmu.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks); 724 cmu.nr_clk_ids = G2D_NR_CLK; 725 cmu.clk_regs = g2d_clk_regs; 726 cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs); 727 728 exynos5260_cmu_register_one(np, &cmu); 729} 730 731CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d", 732 exynos5260_clk_g2d_init); 733 734 735/* CMU_G3D */ 736 737static unsigned long g3d_clk_regs[] __initdata = { 738 G3D_PLL_LOCK, 739 G3D_PLL_CON0, 740 G3D_PLL_CON1, 741 G3D_PLL_FDET, 742 MUX_SEL_G3D, 743 DIV_G3D, 744 DIV_G3D_PLL_FDET, 745 EN_ACLK_G3D, 746 EN_PCLK_G3D, 747 EN_SCLK_G3D, 748 EN_IP_G3D, 749}; 750 751PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; 752 753struct samsung_mux_clock g3d_mux_clks[] __initdata = { 754 MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 755 MUX_SEL_G3D, 0, 1), 756}; 757 758struct samsung_div_clock g3d_div_clks[] __initdata = { 759 DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), 760 DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), 761}; 762 763struct samsung_gate_clock g3d_gate_clks[] __initdata = { 764 GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0), 765 GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d", 766 EN_IP_G3D, 3, 0, 0), 767}; 768 769static struct samsung_pll_clock g3d_pll_clks[] __initdata = { 770 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll", 771 G3D_PLL_LOCK, G3D_PLL_CON0, 772 pll2550_24mhz_tbl), 773}; 774 775static void __init exynos5260_clk_g3d_init(struct device_node *np) 776{ 777 struct exynos5260_cmu_info cmu = {0}; 778 779 cmu.pll_clks = g3d_pll_clks; 780 cmu.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks); 781 cmu.mux_clks = g3d_mux_clks; 782 cmu.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks); 783 cmu.div_clks = g3d_div_clks; 784 cmu.nr_div_clks = ARRAY_SIZE(g3d_div_clks); 785 cmu.gate_clks = g3d_gate_clks; 786 cmu.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks); 787 cmu.nr_clk_ids = G3D_NR_CLK; 788 cmu.clk_regs = g3d_clk_regs; 789 cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs); 790 791 exynos5260_cmu_register_one(np, &cmu); 792} 793 794CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d", 795 exynos5260_clk_g3d_init); 796 797 798/* CMU_GSCL */ 799 800static unsigned long gscl_clk_regs[] __initdata = { 801 MUX_SEL_GSCL, 802 DIV_GSCL, 803 EN_ACLK_GSCL, 804 EN_ACLK_GSCL_FIMC, 805 EN_ACLK_GSCL_SECURE_SMMU_GSCL0, 806 EN_ACLK_GSCL_SECURE_SMMU_GSCL1, 807 EN_ACLK_GSCL_SECURE_SMMU_MSCL0, 808 EN_ACLK_GSCL_SECURE_SMMU_MSCL1, 809 EN_PCLK_GSCL, 810 EN_PCLK_GSCL_FIMC, 811 EN_PCLK_GSCL_SECURE_SMMU_GSCL0, 812 EN_PCLK_GSCL_SECURE_SMMU_GSCL1, 813 EN_PCLK_GSCL_SECURE_SMMU_MSCL0, 814 EN_PCLK_GSCL_SECURE_SMMU_MSCL1, 815 EN_SCLK_GSCL, 816 EN_SCLK_GSCL_FIMC, 817 EN_IP_GSCL, 818 EN_IP_GSCL_FIMC, 819 EN_IP_GSCL_SECURE_SMMU_GSCL0, 820 EN_IP_GSCL_SECURE_SMMU_GSCL1, 821 EN_IP_GSCL_SECURE_SMMU_MSCL0, 822 EN_IP_GSCL_SECURE_SMMU_MSCL1, 823}; 824 825PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"}; 826PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; 827PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; 828PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; 829 830struct samsung_mux_clock gscl_mux_clks[] __initdata = { 831 MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 832 mout_aclk_gscl_333_user_p, 833 MUX_SEL_GSCL, 0, 1), 834 MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user", 835 mout_aclk_m2m_400_user_p, 836 MUX_SEL_GSCL, 4, 1), 837 MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user", 838 mout_aclk_gscl_fimc_user_p, 839 MUX_SEL_GSCL, 8, 1), 840 MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p, 841 MUX_SEL_GSCL, 24, 1), 842}; 843 844struct samsung_div_clock gscl_div_clks[] __initdata = { 845 DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100", 846 "mout_aclk_m2m_400_user", 847 DIV_GSCL, 0, 3), 848 DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200", 849 "mout_aclk_m2m_400_user", 850 DIV_GSCL, 4, 3), 851}; 852 853struct samsung_gate_clock gscl_gate_clks[] __initdata = { 854 GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200", 855 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0), 856 GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200", 857 EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0), 858 859 GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user", 860 EN_IP_GSCL, 2, 0, 0), 861 GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user", 862 EN_IP_GSCL, 3, 0, 0), 863 GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user", 864 EN_IP_GSCL, 4, 0, 0), 865 GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user", 866 EN_IP_GSCL, 5, 0, 0), 867 GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0", 868 "mout_aclk_gscl_333_user", 869 EN_IP_GSCL, 8, 0, 0), 870 GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1", 871 "mout_aclk_gscl_333_user", 872 EN_IP_GSCL, 9, 0, 0), 873 874 GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a", 875 "mout_aclk_gscl_fimc_user", 876 EN_IP_GSCL_FIMC, 5, 0, 0), 877 GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b", 878 "mout_aclk_gscl_fimc_user", 879 EN_IP_GSCL_FIMC, 6, 0, 0), 880 GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d", 881 "mout_aclk_gscl_fimc_user", 882 EN_IP_GSCL_FIMC, 7, 0, 0), 883 GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user", 884 EN_IP_GSCL_FIMC, 8, 0, 0), 885 GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user", 886 EN_IP_GSCL_FIMC, 9, 0, 0), 887 GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a", 888 "mout_aclk_gscl_fimc_user", 889 EN_IP_GSCL_FIMC, 10, 0, 0), 890 GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b", 891 "mout_aclk_gscl_fimc_user", 892 EN_IP_GSCL_FIMC, 11, 0, 0), 893 GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d", 894 "mout_aclk_gscl_fimc_user", 895 EN_IP_GSCL_FIMC, 12, 0, 0), 896 897 GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0", 898 "mout_aclk_gscl_333_user", 899 EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0), 900 GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user", 901 EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0), 902 GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0", 903 "mout_aclk_m2m_400_user", 904 EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0), 905 GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1", 906 "mout_aclk_m2m_400_user", 907 EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0), 908}; 909 910static void __init exynos5260_clk_gscl_init(struct device_node *np) 911{ 912 struct exynos5260_cmu_info cmu = {0}; 913 914 cmu.mux_clks = gscl_mux_clks; 915 cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks); 916 cmu.div_clks = gscl_div_clks; 917 cmu.nr_div_clks = ARRAY_SIZE(gscl_div_clks); 918 cmu.gate_clks = gscl_gate_clks; 919 cmu.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks); 920 cmu.nr_clk_ids = GSCL_NR_CLK; 921 cmu.clk_regs = gscl_clk_regs; 922 cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs); 923 924 exynos5260_cmu_register_one(np, &cmu); 925} 926 927CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl", 928 exynos5260_clk_gscl_init); 929 930 931/* CMU_ISP */ 932 933static unsigned long isp_clk_regs[] __initdata = { 934 MUX_SEL_ISP0, 935 MUX_SEL_ISP1, 936 DIV_ISP, 937 EN_ACLK_ISP0, 938 EN_ACLK_ISP1, 939 EN_PCLK_ISP0, 940 EN_PCLK_ISP1, 941 EN_SCLK_ISP, 942 EN_IP_ISP0, 943 EN_IP_ISP1, 944}; 945 946PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; 947PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; 948 949struct samsung_mux_clock isp_mux_clks[] __initdata = { 950 MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p, 951 MUX_SEL_ISP0, 0, 1), 952 MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p, 953 MUX_SEL_ISP0, 4, 1), 954}; 955 956struct samsung_div_clock isp_div_clks[] __initdata = { 957 DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc", 958 DIV_ISP, 0, 3), 959 DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc", 960 DIV_ISP, 4, 4), 961 DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc", 962 DIV_ISP, 12, 3), 963 DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc", 964 DIV_ISP, 16, 4), 965 DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), 966}; 967 968struct samsung_gate_clock isp_gate_clks[] __initdata = { 969 GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266", 970 EN_IP_ISP0, 15, 0, 0), 971 972 GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266", 973 EN_IP_ISP1, 1, 0, 0), 974 GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266", 975 EN_IP_ISP1, 2, 0, 0), 976 GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266", 977 EN_IP_ISP1, 3, 0, 0), 978 GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266", 979 EN_IP_ISP1, 4, 0, 0), 980 GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc", 981 "mout_aclk_isp1_266", 982 EN_IP_ISP1, 5, 0, 0), 983 GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp", 984 "mout_aclk_isp1_266", 985 EN_IP_ISP1, 6, 0, 0), 986 GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266", 987 EN_IP_ISP1, 7, 0, 0), 988 GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266", 989 EN_IP_ISP1, 8, 0, 0), 990 GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266", 991 EN_IP_ISP1, 9, 0, 0), 992 GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266", 993 EN_IP_ISP1, 10, 0, 0), 994 GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266", 995 EN_IP_ISP1, 11, 0, 0), 996 GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266", 997 EN_IP_ISP1, 14, 0, 0), 998 GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266", 999 EN_IP_ISP1, 21, 0, 0), 1000 GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266", 1001 EN_IP_ISP1, 22, 0, 0), 1002 GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266", 1003 EN_IP_ISP1, 23, 0, 0), 1004 GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266", 1005 EN_IP_ISP1, 24, 0, 0), 1006 GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc", 1007 "mout_aclk_isp1_266", 1008 EN_IP_ISP1, 25, 0, 0), 1009 GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp", 1010 "mout_aclk_isp1_266", 1011 EN_IP_ISP1, 26, 0, 0), 1012 GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266", 1013 EN_IP_ISP1, 27, 0, 0), 1014 GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266", 1015 EN_IP_ISP1, 28, 0, 0), 1016 GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266", 1017 EN_IP_ISP1, 31, 0, 0), 1018 GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266", 1019 EN_IP_ISP1, 30, 0, 0), 1020 1021 GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll", 1022 EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0), 1023 GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll", 1024 EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 1025 GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll", 1026 EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0), 1027}; 1028 1029static void __init exynos5260_clk_isp_init(struct device_node *np) 1030{ 1031 struct exynos5260_cmu_info cmu = {0}; 1032 1033 cmu.mux_clks = isp_mux_clks; 1034 cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks); 1035 cmu.div_clks = isp_div_clks; 1036 cmu.nr_div_clks = ARRAY_SIZE(isp_div_clks); 1037 cmu.gate_clks = isp_gate_clks; 1038 cmu.nr_gate_clks = ARRAY_SIZE(isp_gate_clks); 1039 cmu.nr_clk_ids = ISP_NR_CLK; 1040 cmu.clk_regs = isp_clk_regs; 1041 cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs); 1042 1043 exynos5260_cmu_register_one(np, &cmu); 1044} 1045 1046CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp", 1047 exynos5260_clk_isp_init); 1048 1049 1050/* CMU_KFC */ 1051 1052static unsigned long kfc_clk_regs[] __initdata = { 1053 KFC_PLL_LOCK, 1054 KFC_PLL_CON0, 1055 KFC_PLL_CON1, 1056 KFC_PLL_FDET, 1057 MUX_SEL_KFC0, 1058 MUX_SEL_KFC2, 1059 DIV_KFC, 1060 DIV_KFC_PLL_FDET, 1061 EN_ACLK_KFC, 1062 EN_PCLK_KFC, 1063 EN_SCLK_KFC, 1064 EN_IP_KFC, 1065}; 1066 1067PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; 1068PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; 1069 1070struct samsung_mux_clock kfc_mux_clks[] __initdata = { 1071 MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p, 1072 MUX_SEL_KFC0, 0, 1), 1073 MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), 1074}; 1075 1076struct samsung_div_clock kfc_div_clks[] __initdata = { 1077 DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), 1078 DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), 1079 DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), 1080 DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2", 1081 DIV_KFC, 12, 3), 1082 DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3), 1083 DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3), 1084 DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3), 1085}; 1086 1087static struct samsung_pll_clock kfc_pll_clks[] __initdata = { 1088 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll", 1089 KFC_PLL_LOCK, KFC_PLL_CON0, 1090 pll2550_24mhz_tbl), 1091}; 1092 1093static void __init exynos5260_clk_kfc_init(struct device_node *np) 1094{ 1095 struct exynos5260_cmu_info cmu = {0}; 1096 1097 cmu.pll_clks = kfc_pll_clks; 1098 cmu.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks); 1099 cmu.mux_clks = kfc_mux_clks; 1100 cmu.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks); 1101 cmu.div_clks = kfc_div_clks; 1102 cmu.nr_div_clks = ARRAY_SIZE(kfc_div_clks); 1103 cmu.nr_clk_ids = KFC_NR_CLK; 1104 cmu.clk_regs = kfc_clk_regs; 1105 cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs); 1106 1107 exynos5260_cmu_register_one(np, &cmu); 1108} 1109 1110CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc", 1111 exynos5260_clk_kfc_init); 1112 1113 1114/* CMU_MFC */ 1115 1116static unsigned long mfc_clk_regs[] __initdata = { 1117 MUX_SEL_MFC, 1118 DIV_MFC, 1119 EN_ACLK_MFC, 1120 EN_ACLK_SECURE_SMMU2_MFC, 1121 EN_PCLK_MFC, 1122 EN_PCLK_SECURE_SMMU2_MFC, 1123 EN_IP_MFC, 1124 EN_IP_MFC_SECURE_SMMU2_MFC, 1125}; 1126 1127PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; 1128 1129struct samsung_mux_clock mfc_mux_clks[] __initdata = { 1130 MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user", 1131 mout_aclk_mfc_333_user_p, 1132 MUX_SEL_MFC, 0, 1), 1133}; 1134 1135struct samsung_div_clock mfc_div_clks[] __initdata = { 1136 DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", 1137 DIV_MFC, 0, 3), 1138}; 1139 1140struct samsung_gate_clock mfc_gate_clks[] __initdata = { 1141 GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user", 1142 EN_IP_MFC, 1, 0, 0), 1143 GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user", 1144 EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0), 1145 GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user", 1146 EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0), 1147}; 1148 1149static void __init exynos5260_clk_mfc_init(struct device_node *np) 1150{ 1151 struct exynos5260_cmu_info cmu = {0}; 1152 1153 cmu.mux_clks = mfc_mux_clks; 1154 cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks); 1155 cmu.div_clks = mfc_div_clks; 1156 cmu.nr_div_clks = ARRAY_SIZE(mfc_div_clks); 1157 cmu.gate_clks = mfc_gate_clks; 1158 cmu.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks); 1159 cmu.nr_clk_ids = MFC_NR_CLK; 1160 cmu.clk_regs = mfc_clk_regs; 1161 cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs); 1162 1163 exynos5260_cmu_register_one(np, &cmu); 1164} 1165 1166CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc", 1167 exynos5260_clk_mfc_init); 1168 1169 1170/* CMU_MIF */ 1171 1172static unsigned long mif_clk_regs[] __initdata = { 1173 MEM_PLL_LOCK, 1174 BUS_PLL_LOCK, 1175 MEDIA_PLL_LOCK, 1176 MEM_PLL_CON0, 1177 MEM_PLL_CON1, 1178 MEM_PLL_FDET, 1179 BUS_PLL_CON0, 1180 BUS_PLL_CON1, 1181 BUS_PLL_FDET, 1182 MEDIA_PLL_CON0, 1183 MEDIA_PLL_CON1, 1184 MEDIA_PLL_FDET, 1185 MUX_SEL_MIF, 1186 DIV_MIF, 1187 DIV_MIF_PLL_FDET, 1188 EN_ACLK_MIF, 1189 EN_ACLK_MIF_SECURE_DREX1_TZ, 1190 EN_ACLK_MIF_SECURE_DREX0_TZ, 1191 EN_ACLK_MIF_SECURE_INTMEM, 1192 EN_PCLK_MIF, 1193 EN_PCLK_MIF_SECURE_MONOCNT, 1194 EN_PCLK_MIF_SECURE_RTC_APBIF, 1195 EN_PCLK_MIF_SECURE_DREX1_TZ, 1196 EN_PCLK_MIF_SECURE_DREX0_TZ, 1197 EN_SCLK_MIF, 1198 EN_IP_MIF, 1199 EN_IP_MIF_SECURE_MONOCNT, 1200 EN_IP_MIF_SECURE_RTC_APBIF, 1201 EN_IP_MIF_SECURE_DREX1_TZ, 1202 EN_IP_MIF_SECURE_DREX0_TZ, 1203 EN_IP_MIF_SECURE_INTEMEM, 1204}; 1205 1206PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"}; 1207PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"}; 1208PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"}; 1209PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"}; 1210PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"}; 1211PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; 1212PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; 1213 1214struct samsung_mux_clock mif_mux_clks[] __initdata = { 1215 MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p, 1216 MUX_SEL_MIF, 0, 1), 1217 MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, 1218 MUX_SEL_MIF, 4, 1), 1219 MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p, 1220 MUX_SEL_MIF, 8, 1), 1221 MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p, 1222 MUX_SEL_MIF, 12, 1), 1223 MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p, 1224 MUX_SEL_MIF, 16, 1), 1225 MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p, 1226 MUX_SEL_MIF, 20, 1), 1227 MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p, 1228 MUX_SEL_MIF, 24, 1), 1229}; 1230 1231struct samsung_div_clock mif_div_clks[] __initdata = { 1232 DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll", 1233 DIV_MIF, 0, 3), 1234 DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll", 1235 DIV_MIF, 4, 3), 1236 DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1237 DIV_MIF, 8, 3), 1238 DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy", 1239 DIV_MIF, 12, 3), 1240 DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy", 1241 DIV_MIF, 16, 4), 1242 DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy", 1243 DIV_MIF, 20, 3), 1244 DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll", 1245 DIV_MIF, 24, 3), 1246 DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll", 1247 DIV_MIF, 28, 4), 1248}; 1249 1250struct samsung_gate_clock mif_gate_clks[] __initdata = { 1251 GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy", 1252 EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0), 1253 GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy", 1254 EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0), 1255 1256 GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100", 1257 EN_IP_MIF_SECURE_MONOCNT, 22, 1258 CLK_IGNORE_UNUSED, 0), 1259 1260 GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100", 1261 EN_IP_MIF_SECURE_RTC_APBIF, 23, 1262 CLK_IGNORE_UNUSED, 0), 1263 1264 GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466", 1265 EN_IP_MIF_SECURE_DREX1_TZ, 9, 1266 CLK_IGNORE_UNUSED, 0), 1267 1268 GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466", 1269 EN_IP_MIF_SECURE_DREX0_TZ, 9, 1270 CLK_IGNORE_UNUSED, 0), 1271 1272 GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200", 1273 EN_IP_MIF_SECURE_INTEMEM, 11, 1274 CLK_IGNORE_UNUSED, 0), 1275 1276 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0", 1277 "dout_clkm_phy", EN_SCLK_MIF, 0, 1278 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1279 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1", 1280 "dout_clkm_phy", EN_SCLK_MIF, 1, 1281 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1282}; 1283 1284static struct samsung_pll_clock mif_pll_clks[] __initdata = { 1285 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll", 1286 MEM_PLL_LOCK, MEM_PLL_CON0, 1287 pll2550_24mhz_tbl), 1288 PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll", 1289 BUS_PLL_LOCK, BUS_PLL_CON0, 1290 pll2550_24mhz_tbl), 1291 PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll", 1292 MEDIA_PLL_LOCK, MEDIA_PLL_CON0, 1293 pll2550_24mhz_tbl), 1294}; 1295 1296static void __init exynos5260_clk_mif_init(struct device_node *np) 1297{ 1298 struct exynos5260_cmu_info cmu = {0}; 1299 1300 cmu.pll_clks = mif_pll_clks; 1301 cmu.nr_pll_clks = ARRAY_SIZE(mif_pll_clks); 1302 cmu.mux_clks = mif_mux_clks; 1303 cmu.nr_mux_clks = ARRAY_SIZE(mif_mux_clks); 1304 cmu.div_clks = mif_div_clks; 1305 cmu.nr_div_clks = ARRAY_SIZE(mif_div_clks); 1306 cmu.gate_clks = mif_gate_clks; 1307 cmu.nr_gate_clks = ARRAY_SIZE(mif_gate_clks); 1308 cmu.nr_clk_ids = MIF_NR_CLK; 1309 cmu.clk_regs = mif_clk_regs; 1310 cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs); 1311 1312 exynos5260_cmu_register_one(np, &cmu); 1313} 1314 1315CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif", 1316 exynos5260_clk_mif_init); 1317 1318 1319/* CMU_PERI */ 1320 1321static unsigned long peri_clk_regs[] __initdata = { 1322 MUX_SEL_PERI, 1323 MUX_SEL_PERI1, 1324 DIV_PERI, 1325 EN_PCLK_PERI0, 1326 EN_PCLK_PERI1, 1327 EN_PCLK_PERI2, 1328 EN_PCLK_PERI3, 1329 EN_PCLK_PERI_SECURE_CHIPID, 1330 EN_PCLK_PERI_SECURE_PROVKEY0, 1331 EN_PCLK_PERI_SECURE_PROVKEY1, 1332 EN_PCLK_PERI_SECURE_SECKEY, 1333 EN_PCLK_PERI_SECURE_ANTIRBKCNT, 1334 EN_PCLK_PERI_SECURE_TOP_RTC, 1335 EN_PCLK_PERI_SECURE_TZPC, 1336 EN_SCLK_PERI, 1337 EN_SCLK_PERI_SECURE_TOP_RTC, 1338 EN_IP_PERI0, 1339 EN_IP_PERI1, 1340 EN_IP_PERI2, 1341 EN_IP_PERI_SECURE_CHIPID, 1342 EN_IP_PERI_SECURE_PROVKEY0, 1343 EN_IP_PERI_SECURE_PROVKEY1, 1344 EN_IP_PERI_SECURE_SECKEY, 1345 EN_IP_PERI_SECURE_ANTIRBKCNT, 1346 EN_IP_PERI_SECURE_TOP_RTC, 1347 EN_IP_PERI_SECURE_TZPC, 1348}; 1349 1350PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud", 1351 "phyclk_hdmi_phy_ref_cko"}; 1352PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud", 1353 "phyclk_hdmi_phy_ref_cko"}; 1354PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll", 1355 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; 1356 1357struct samsung_mux_clock peri_mux_clks[] __initdata = { 1358 MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p, 1359 MUX_SEL_PERI1, 4, 2), 1360 MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p, 1361 MUX_SEL_PERI1, 12, 2), 1362 MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 1363 MUX_SEL_PERI1, 20, 2), 1364}; 1365 1366struct samsung_div_clock peri_div_clks[] __initdata = { 1367 DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), 1368 DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6), 1369}; 1370 1371struct samsung_gate_clock peri_gate_clks[] __initdata = { 1372 GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, 1373 CLK_SET_RATE_PARENT, 0), 1374 GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, 1375 CLK_SET_RATE_PARENT, 0), 1376 GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b", 1377 EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0), 1378 GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b", 1379 EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0), 1380 GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b", 1381 EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0), 1382 GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b", 1383 EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0), 1384 GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0", 1385 EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0), 1386 GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1", 1387 EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0), 1388 GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2", 1389 EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0), 1390 1391 GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66", 1392 EN_IP_PERI0, 1, 0, 0), 1393 GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66", 1394 EN_IP_PERI0, 5, 0, 0), 1395 GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66", 1396 EN_IP_PERI0, 6, 0, 0), 1397 GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66", 1398 EN_IP_PERI0, 7, 0, 0), 1399 GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66", 1400 EN_IP_PERI0, 8, 0, 0), 1401 GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66", 1402 EN_IP_PERI0, 9, 0, 0), 1403 GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66", 1404 EN_IP_PERI0, 10, 0, 0), 1405 GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66", 1406 EN_IP_PERI0, 11, 0, 0), 1407 GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66", 1408 EN_IP_PERI0, 12, 0, 0), 1409 GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66", 1410 EN_IP_PERI0, 13, 0, 0), 1411 GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66", 1412 EN_IP_PERI0, 14, 0, 0), 1413 GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66", 1414 EN_IP_PERI0, 15, 0, 0), 1415 GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66", 1416 EN_IP_PERI0, 16, 0, 0), 1417 GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66", 1418 EN_IP_PERI0, 17, 0, 0), 1419 GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66", 1420 EN_IP_PERI0, 18, 0, 0), 1421 GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66", 1422 EN_IP_PERI0, 20, 0, 0), 1423 GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66", 1424 EN_IP_PERI0, 21, 0, 0), 1425 GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66", 1426 EN_IP_PERI0, 22, 0, 0), 1427 GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66", 1428 EN_IP_PERI0, 23, 0, 0), 1429 GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66", 1430 EN_IP_PERI0, 24, 0, 0), 1431 GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66", 1432 EN_IP_PERI0, 25, 0, 0), 1433 1434 GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66", 1435 EN_IP_PERI2, 0, 0, 0), 1436 GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66", 1437 EN_IP_PERI2, 3, 0, 0), 1438 GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66", 1439 EN_IP_PERI2, 6, 0, 0), 1440 GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66", 1441 EN_IP_PERI2, 7, 0, 0), 1442 GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66", 1443 EN_IP_PERI2, 8, 0, 0), 1444 GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66", 1445 EN_IP_PERI2, 9, 0, 0), 1446 GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66", 1447 EN_IP_PERI2, 10, 0, 0), 1448 GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66", 1449 EN_IP_PERI2, 11, 0, 0), 1450 GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66", 1451 EN_IP_PERI2, 12, 0, 0), 1452 GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66", 1453 EN_IP_PERI2, 13, 0, 0), 1454 GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66", 1455 EN_IP_PERI2, 14, 0, 0), 1456 GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66", 1457 EN_IP_PERI2, 18, 0, 0), 1458 GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66", 1459 EN_IP_PERI2, 19, 0, 0), 1460 GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66", 1461 EN_IP_PERI2, 20, 0, 0), 1462 GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66", 1463 EN_IP_PERI2, 21, 0, 0), 1464 1465 GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66", 1466 EN_IP_PERI_SECURE_CHIPID, 2, 0, 0), 1467 1468 GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66", 1469 EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0), 1470 1471 GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66", 1472 EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0), 1473 1474 GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66", 1475 EN_IP_PERI_SECURE_SECKEY, 5, 0, 0), 1476 1477 GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66", 1478 EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0), 1479 1480 GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66", 1481 EN_IP_PERI_SECURE_TZPC, 10, 0, 0), 1482 GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66", 1483 EN_IP_PERI_SECURE_TZPC, 11, 0, 0), 1484 GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66", 1485 EN_IP_PERI_SECURE_TZPC, 12, 0, 0), 1486 GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66", 1487 EN_IP_PERI_SECURE_TZPC, 13, 0, 0), 1488 GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66", 1489 EN_IP_PERI_SECURE_TZPC, 14, 0, 0), 1490 GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66", 1491 EN_IP_PERI_SECURE_TZPC, 15, 0, 0), 1492 GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66", 1493 EN_IP_PERI_SECURE_TZPC, 16, 0, 0), 1494 GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66", 1495 EN_IP_PERI_SECURE_TZPC, 17, 0, 0), 1496 GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66", 1497 EN_IP_PERI_SECURE_TZPC, 18, 0, 0), 1498 GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66", 1499 EN_IP_PERI_SECURE_TZPC, 19, 0, 0), 1500 GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66", 1501 EN_IP_PERI_SECURE_TZPC, 20, 0, 0), 1502}; 1503 1504static void __init exynos5260_clk_peri_init(struct device_node *np) 1505{ 1506 struct exynos5260_cmu_info cmu = {0}; 1507 1508 cmu.mux_clks = peri_mux_clks; 1509 cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks); 1510 cmu.div_clks = peri_div_clks; 1511 cmu.nr_div_clks = ARRAY_SIZE(peri_div_clks); 1512 cmu.gate_clks = peri_gate_clks; 1513 cmu.nr_gate_clks = ARRAY_SIZE(peri_gate_clks); 1514 cmu.nr_clk_ids = PERI_NR_CLK; 1515 cmu.clk_regs = peri_clk_regs; 1516 cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs); 1517 1518 exynos5260_cmu_register_one(np, &cmu); 1519} 1520 1521CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri", 1522 exynos5260_clk_peri_init); 1523 1524 1525/* CMU_TOP */ 1526 1527static unsigned long top_clk_regs[] __initdata = { 1528 DISP_PLL_LOCK, 1529 AUD_PLL_LOCK, 1530 DISP_PLL_CON0, 1531 DISP_PLL_CON1, 1532 DISP_PLL_FDET, 1533 AUD_PLL_CON0, 1534 AUD_PLL_CON1, 1535 AUD_PLL_CON2, 1536 AUD_PLL_FDET, 1537 MUX_SEL_TOP_PLL0, 1538 MUX_SEL_TOP_MFC, 1539 MUX_SEL_TOP_G2D, 1540 MUX_SEL_TOP_GSCL, 1541 MUX_SEL_TOP_ISP10, 1542 MUX_SEL_TOP_ISP11, 1543 MUX_SEL_TOP_DISP0, 1544 MUX_SEL_TOP_DISP1, 1545 MUX_SEL_TOP_BUS, 1546 MUX_SEL_TOP_PERI0, 1547 MUX_SEL_TOP_PERI1, 1548 MUX_SEL_TOP_FSYS, 1549 DIV_TOP_G2D_MFC, 1550 DIV_TOP_GSCL_ISP0, 1551 DIV_TOP_ISP10, 1552 DIV_TOP_ISP11, 1553 DIV_TOP_DISP, 1554 DIV_TOP_BUS, 1555 DIV_TOP_PERI0, 1556 DIV_TOP_PERI1, 1557 DIV_TOP_PERI2, 1558 DIV_TOP_FSYS0, 1559 DIV_TOP_FSYS1, 1560 DIV_TOP_HPM, 1561 DIV_TOP_PLL_FDET, 1562 EN_ACLK_TOP, 1563 EN_SCLK_TOP, 1564 EN_IP_TOP, 1565}; 1566 1567/* fixed rate clocks generated inside the soc */ 1568struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = { 1569 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL, 1570 CLK_IS_ROOT, 270000000), 1571 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL, 1572 CLK_IS_ROOT, 270000000), 1573 FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL, 1574 CLK_IS_ROOT, 270000000), 1575 FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL, 1576 CLK_IS_ROOT, 270000000), 1577 FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL, 1578 CLK_IS_ROOT, 250000000), 1579 FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL, 1580 CLK_IS_ROOT, 1660000000), 1581 FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi", 1582 NULL, CLK_IS_ROOT, 125000000), 1583 FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS, 1584 "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL, 1585 CLK_IS_ROOT, 187500000), 1586 FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m", 1587 NULL, CLK_IS_ROOT, 24000000), 1588 FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL, 1589 CLK_IS_ROOT, 135000000), 1590 FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0, 1591 "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 1592 CLK_IS_ROOT, 20000000), 1593 FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock", 1594 NULL, CLK_IS_ROOT, 60000000), 1595 FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk", 1596 NULL, CLK_IS_ROOT, 60000000), 1597 FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI, 1598 "phyclk_usbhost20_phy_clk48mohci", 1599 NULL, CLK_IS_ROOT, 48000000), 1600 FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 1601 "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 1602 CLK_IS_ROOT, 125000000), 1603 FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 1604 "phyclk_usbdrd30_udrd30_phyclock", NULL, 1605 CLK_IS_ROOT, 60000000), 1606}; 1607 1608PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"}; 1609PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"}; 1610PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"}; 1611PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"}; 1612PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"}; 1613PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"}; 1614PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1615PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"}; 1616PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1617PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"}; 1618PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1619PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user", 1620 "mout_gscl_bustop_333"}; 1621PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; 1622PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user", 1623 "mout_m2m_mediatop_400"}; 1624PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1625PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user", 1626 "mout_gscl_bustop_fimc"}; 1627PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user", 1628 "mout_memtop_pll_user"}; 1629PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"}; 1630PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; 1631PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"}; 1632PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"}; 1633PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"}; 1634PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"}; 1635PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; 1636PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"}; 1637PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; 1638PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"}; 1639PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user", 1640 "mout_bustop_pll_user"}; 1641PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"}; 1642PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; 1643PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; 1644PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"}; 1645PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"}; 1646PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"}; 1647PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"}; 1648PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a", 1649 "mout_mediatop_pll_user"}; 1650PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a", 1651 "mout_mediatop_pll_user"}; 1652PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", 1653 "mout_mediatop_pll_user"}; 1654 1655struct samsung_mux_clock top_mux_clks[] __initdata = { 1656 MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user", 1657 mout_mediatop_pll_user_p, 1658 MUX_SEL_TOP_PLL0, 0, 1), 1659 MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user", 1660 mout_memtop_pll_user_p, 1661 MUX_SEL_TOP_PLL0, 4, 1), 1662 MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user", 1663 mout_bustop_pll_user_p, 1664 MUX_SEL_TOP_PLL0, 8, 1), 1665 MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, 1666 MUX_SEL_TOP_PLL0, 12, 1), 1667 MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 1668 MUX_SEL_TOP_PLL0, 16, 1), 1669 MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user", 1670 mout_audtop_pll_user_p, 1671 MUX_SEL_TOP_PLL0, 24, 1), 1672 1673 MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p, 1674 MUX_SEL_TOP_DISP0, 0, 1), 1675 MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p, 1676 MUX_SEL_TOP_DISP0, 8, 1), 1677 MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p, 1678 MUX_SEL_TOP_DISP0, 12, 1), 1679 MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p, 1680 MUX_SEL_TOP_DISP0, 20, 1), 1681 1682 MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p, 1683 MUX_SEL_TOP_DISP1, 0, 1), 1684 MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel", 1685 mout_disp_media_pixel_p, 1686 MUX_SEL_TOP_DISP1, 8, 1), 1687 1688 MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk", 1689 mout_sclk_peri_spi_clk_p, 1690 MUX_SEL_TOP_PERI1, 0, 1), 1691 MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk", 1692 mout_sclk_peri_spi_clk_p, 1693 MUX_SEL_TOP_PERI1, 4, 1), 1694 MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk", 1695 mout_sclk_peri_spi_clk_p, 1696 MUX_SEL_TOP_PERI1, 8, 1), 1697 MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk", 1698 mout_sclk_peri_uart_uclk_p, 1699 MUX_SEL_TOP_PERI1, 12, 1), 1700 MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk", 1701 mout_sclk_peri_uart_uclk_p, 1702 MUX_SEL_TOP_PERI1, 16, 1), 1703 MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk", 1704 mout_sclk_peri_uart_uclk_p, 1705 MUX_SEL_TOP_PERI1, 20, 1), 1706 1707 1708 MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400", 1709 mout_bus_bustop_400_p, 1710 MUX_SEL_TOP_BUS, 0, 1), 1711 MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100", 1712 mout_bus_bustop_100_p, 1713 MUX_SEL_TOP_BUS, 4, 1), 1714 MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100", 1715 mout_bus_bustop_100_p, 1716 MUX_SEL_TOP_BUS, 8, 1), 1717 MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400", 1718 mout_bus_bustop_400_p, 1719 MUX_SEL_TOP_BUS, 12, 1), 1720 MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400", 1721 mout_bus_bustop_400_p, 1722 MUX_SEL_TOP_BUS, 16, 1), 1723 MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100", 1724 mout_bus_bustop_100_p, 1725 MUX_SEL_TOP_BUS, 20, 1), 1726 MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400", 1727 mout_bus_bustop_400_p, 1728 MUX_SEL_TOP_BUS, 24, 1), 1729 MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100", 1730 mout_bus_bustop_100_p, 1731 MUX_SEL_TOP_BUS, 28, 1), 1732 1733 MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb", 1734 mout_sclk_fsys_usb_p, 1735 MUX_SEL_TOP_FSYS, 0, 1), 1736 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a", 1737 mout_sclk_fsys_mmc_sdclkin_a_p, 1738 MUX_SEL_TOP_FSYS, 4, 1), 1739 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b", 1740 mout_sclk_fsys_mmc2_sdclkin_b_p, 1741 MUX_SEL_TOP_FSYS, 8, 1), 1742 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a", 1743 mout_sclk_fsys_mmc_sdclkin_a_p, 1744 MUX_SEL_TOP_FSYS, 12, 1), 1745 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b", 1746 mout_sclk_fsys_mmc1_sdclkin_b_p, 1747 MUX_SEL_TOP_FSYS, 16, 1), 1748 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a", 1749 mout_sclk_fsys_mmc_sdclkin_a_p, 1750 MUX_SEL_TOP_FSYS, 20, 1), 1751 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b", 1752 mout_sclk_fsys_mmc0_sdclkin_b_p, 1753 MUX_SEL_TOP_FSYS, 24, 1), 1754 1755 MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400", 1756 mout_isp1_media_400_p, 1757 MUX_SEL_TOP_ISP10, 4, 1), 1758 MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p, 1759 MUX_SEL_TOP_ISP10, 8 , 1), 1760 MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266", 1761 mout_isp1_media_266_p, 1762 MUX_SEL_TOP_ISP10, 16, 1), 1763 MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p, 1764 MUX_SEL_TOP_ISP10, 20, 1), 1765 1766 MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p, 1767 MUX_SEL_TOP_ISP11, 4, 1), 1768 MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p, 1769 MUX_SEL_TOP_ISP11, 8, 1), 1770 MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart", 1771 mout_sclk_isp_uart_p, 1772 MUX_SEL_TOP_ISP11, 12, 1), 1773 MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0", 1774 mout_sclk_isp_sensor_p, 1775 MUX_SEL_TOP_ISP11, 16, 1), 1776 MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1", 1777 mout_sclk_isp_sensor_p, 1778 MUX_SEL_TOP_ISP11, 20, 1), 1779 MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2", 1780 mout_sclk_isp_sensor_p, 1781 MUX_SEL_TOP_ISP11, 24, 1), 1782 1783 MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333", 1784 mout_mfc_bustop_333_p, 1785 MUX_SEL_TOP_MFC, 4, 1), 1786 MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p, 1787 MUX_SEL_TOP_MFC, 8, 1), 1788 1789 MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333", 1790 mout_g2d_bustop_333_p, 1791 MUX_SEL_TOP_G2D, 4, 1), 1792 MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p, 1793 MUX_SEL_TOP_G2D, 8, 1), 1794 1795 MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400", 1796 mout_m2m_mediatop_400_p, 1797 MUX_SEL_TOP_GSCL, 0, 1), 1798 MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400", 1799 mout_aclk_gscl_400_p, 1800 MUX_SEL_TOP_GSCL, 4, 1), 1801 MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333", 1802 mout_gscl_bustop_333_p, 1803 MUX_SEL_TOP_GSCL, 8, 1), 1804 MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 1805 mout_aclk_gscl_333_p, 1806 MUX_SEL_TOP_GSCL, 12, 1), 1807 MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc", 1808 mout_gscl_bustop_fimc_p, 1809 MUX_SEL_TOP_GSCL, 16, 1), 1810 MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc", 1811 mout_aclk_gscl_fimc_p, 1812 MUX_SEL_TOP_GSCL, 20, 1), 1813}; 1814 1815struct samsung_div_clock top_div_clks[] __initdata = { 1816 DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333", 1817 DIV_TOP_G2D_MFC, 0, 3), 1818 DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333", 1819 DIV_TOP_G2D_MFC, 4, 3), 1820 1821 DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333", 1822 DIV_TOP_GSCL_ISP0, 0, 3), 1823 DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400", 1824 DIV_TOP_GSCL_ISP0, 4, 3), 1825 DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc", 1826 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3), 1827 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a", 1828 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4), 1829 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a", 1830 "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4), 1831 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a", 1832 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4), 1833 1834 DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266", 1835 DIV_TOP_ISP10, 0, 3), 1836 DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400", 1837 DIV_TOP_ISP10, 4, 3), 1838 DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a", 1839 "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4), 1840 DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b", 1841 "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8), 1842 1843 DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a", 1844 "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4), 1845 DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b", 1846 "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8), 1847 DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart", 1848 "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4), 1849 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b", 1850 "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4), 1851 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b", 1852 "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4), 1853 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b", 1854 "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4), 1855 1856 DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk", 1857 "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3), 1858 1859 DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333", 1860 DIV_TOP_DISP, 0, 3), 1861 DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222", 1862 DIV_TOP_DISP, 4, 3), 1863 DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel", 1864 "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3), 1865 1866 DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400", 1867 "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3), 1868 DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100", 1869 "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4), 1870 DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400", 1871 "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3), 1872 DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100", 1873 "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4), 1874 DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400", 1875 "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3), 1876 DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100", 1877 "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4), 1878 DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400", 1879 "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3), 1880 DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100", 1881 "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4), 1882 1883 DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a", 1884 "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4), 1885 DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b", 1886 "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8), 1887 DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a", 1888 "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4), 1889 DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b", 1890 "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8), 1891 1892 DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a", 1893 "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4), 1894 DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b", 1895 "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8), 1896 DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1", 1897 "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4), 1898 DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2", 1899 "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4), 1900 DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0", 1901 "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4), 1902 1903 DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user", 1904 DIV_TOP_PERI2, 20, 4), 1905 DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud", 1906 "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3), 1907 1908 DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200", 1909 "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3), 1910 DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK, 1911 "dout_sclk_fsys_usbdrd30_suspend_clk", 1912 "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4), 1913 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a", 1914 "mout_sclk_fsys_mmc0_sdclkin_b", 1915 DIV_TOP_FSYS0, 12, 4), 1916 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b", 1917 "dout_sclk_fsys_mmc0_sdclkin_a", 1918 DIV_TOP_FSYS0, 16, 8), 1919 1920 1921 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a", 1922 "mout_sclk_fsys_mmc1_sdclkin_b", 1923 DIV_TOP_FSYS1, 0, 4), 1924 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b", 1925 "dout_sclk_fsys_mmc1_sdclkin_a", 1926 DIV_TOP_FSYS1, 4, 8), 1927 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a", 1928 "mout_sclk_fsys_mmc2_sdclkin_b", 1929 DIV_TOP_FSYS1, 12, 4), 1930 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b", 1931 "dout_sclk_fsys_mmc2_sdclkin_a", 1932 DIV_TOP_FSYS1, 16, 8), 1933 1934}; 1935 1936struct samsung_gate_clock top_gate_clks[] __initdata = { 1937 GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", 1938 "dout_sclk_fsys_mmc0_sdclkin_b", 1939 EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0), 1940 GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin", 1941 "dout_sclk_fsys_mmc1_sdclkin_b", 1942 EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0), 1943 GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin", 1944 "dout_sclk_fsys_mmc2_sdclkin_b", 1945 EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0), 1946 GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel", 1947 EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED | 1948 CLK_SET_RATE_PARENT, 0), 1949}; 1950 1951static struct samsung_pll_clock top_pll_clks[] __initdata = { 1952 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", 1953 DISP_PLL_LOCK, DISP_PLL_CON0, 1954 pll2550_24mhz_tbl), 1955 PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", 1956 AUD_PLL_LOCK, AUD_PLL_CON0, 1957 pll2650_24mhz_tbl), 1958}; 1959 1960static void __init exynos5260_clk_top_init(struct device_node *np) 1961{ 1962 struct exynos5260_cmu_info cmu = {0}; 1963 1964 cmu.pll_clks = top_pll_clks; 1965 cmu.nr_pll_clks = ARRAY_SIZE(top_pll_clks); 1966 cmu.mux_clks = top_mux_clks; 1967 cmu.nr_mux_clks = ARRAY_SIZE(top_mux_clks); 1968 cmu.div_clks = top_div_clks; 1969 cmu.nr_div_clks = ARRAY_SIZE(top_div_clks); 1970 cmu.gate_clks = top_gate_clks; 1971 cmu.nr_gate_clks = ARRAY_SIZE(top_gate_clks); 1972 cmu.fixed_clks = fixed_rate_clks; 1973 cmu.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks); 1974 cmu.nr_clk_ids = TOP_NR_CLK; 1975 cmu.clk_regs = top_clk_regs; 1976 cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs); 1977 1978 exynos5260_cmu_register_one(np, &cmu); 1979} 1980 1981CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top", 1982 exynos5260_clk_top_init); 1983