clk-tegra-periph.c revision 76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/delay.h> 24#include <linux/export.h> 25#include <linux/clk/tegra.h> 26 27#include "clk.h" 28#include "clk-id.h" 29 30#define CLK_SOURCE_I2S0 0x1d8 31#define CLK_SOURCE_I2S1 0x100 32#define CLK_SOURCE_I2S2 0x104 33#define CLK_SOURCE_NDFLASH 0x160 34#define CLK_SOURCE_I2S3 0x3bc 35#define CLK_SOURCE_I2S4 0x3c0 36#define CLK_SOURCE_SPDIF_OUT 0x108 37#define CLK_SOURCE_SPDIF_IN 0x10c 38#define CLK_SOURCE_PWM 0x110 39#define CLK_SOURCE_ADX 0x638 40#define CLK_SOURCE_AMX 0x63c 41#define CLK_SOURCE_HDA 0x428 42#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 43#define CLK_SOURCE_SBC1 0x134 44#define CLK_SOURCE_SBC2 0x118 45#define CLK_SOURCE_SBC3 0x11c 46#define CLK_SOURCE_SBC4 0x1b4 47#define CLK_SOURCE_SBC5 0x3c8 48#define CLK_SOURCE_SBC6 0x3cc 49#define CLK_SOURCE_SATA_OOB 0x420 50#define CLK_SOURCE_SATA 0x424 51#define CLK_SOURCE_NDSPEED 0x3f8 52#define CLK_SOURCE_VFIR 0x168 53#define CLK_SOURCE_SDMMC1 0x150 54#define CLK_SOURCE_SDMMC2 0x154 55#define CLK_SOURCE_SDMMC3 0x1bc 56#define CLK_SOURCE_SDMMC4 0x164 57#define CLK_SOURCE_CVE 0x140 58#define CLK_SOURCE_TVO 0x188 59#define CLK_SOURCE_TVDAC 0x194 60#define CLK_SOURCE_VDE 0x1c8 61#define CLK_SOURCE_CSITE 0x1d4 62#define CLK_SOURCE_LA 0x1f8 63#define CLK_SOURCE_TRACE 0x634 64#define CLK_SOURCE_OWR 0x1cc 65#define CLK_SOURCE_NOR 0x1d0 66#define CLK_SOURCE_MIPI 0x174 67#define CLK_SOURCE_I2C1 0x124 68#define CLK_SOURCE_I2C2 0x198 69#define CLK_SOURCE_I2C3 0x1b8 70#define CLK_SOURCE_I2C4 0x3c4 71#define CLK_SOURCE_I2C5 0x128 72#define CLK_SOURCE_UARTA 0x178 73#define CLK_SOURCE_UARTB 0x17c 74#define CLK_SOURCE_UARTC 0x1a0 75#define CLK_SOURCE_UARTD 0x1c0 76#define CLK_SOURCE_UARTE 0x1c4 77#define CLK_SOURCE_3D 0x158 78#define CLK_SOURCE_2D 0x15c 79#define CLK_SOURCE_MPE 0x170 80#define CLK_SOURCE_VI_SENSOR 0x1a8 81#define CLK_SOURCE_VI 0x148 82#define CLK_SOURCE_EPP 0x16c 83#define CLK_SOURCE_MSENC 0x1f0 84#define CLK_SOURCE_TSEC 0x1f4 85#define CLK_SOURCE_HOST1X 0x180 86#define CLK_SOURCE_HDMI 0x18c 87#define CLK_SOURCE_DISP1 0x138 88#define CLK_SOURCE_DISP2 0x13c 89#define CLK_SOURCE_CILAB 0x614 90#define CLK_SOURCE_CILCD 0x618 91#define CLK_SOURCE_CILE 0x61c 92#define CLK_SOURCE_DSIALP 0x620 93#define CLK_SOURCE_DSIBLP 0x624 94#define CLK_SOURCE_TSENSOR 0x3b8 95#define CLK_SOURCE_D_AUDIO 0x3d0 96#define CLK_SOURCE_DAM0 0x3d8 97#define CLK_SOURCE_DAM1 0x3dc 98#define CLK_SOURCE_DAM2 0x3e0 99#define CLK_SOURCE_ACTMON 0x3e8 100#define CLK_SOURCE_EXTERN1 0x3ec 101#define CLK_SOURCE_EXTERN2 0x3f0 102#define CLK_SOURCE_EXTERN3 0x3f4 103#define CLK_SOURCE_I2CSLOW 0x3fc 104#define CLK_SOURCE_SE 0x42c 105#define CLK_SOURCE_MSELECT 0x3b4 106#define CLK_SOURCE_DFLL_REF 0x62c 107#define CLK_SOURCE_DFLL_SOC 0x630 108#define CLK_SOURCE_SOC_THERM 0x644 109#define CLK_SOURCE_XUSB_HOST_SRC 0x600 110#define CLK_SOURCE_XUSB_FALCON_SRC 0x604 111#define CLK_SOURCE_XUSB_FS_SRC 0x608 112#define CLK_SOURCE_XUSB_SS_SRC 0x610 113#define CLK_SOURCE_XUSB_DEV_SRC 0x60c 114 115#define MASK(x) (BIT(x) - 1) 116 117#define MUX(_name, _parents, _offset, \ 118 _clk_num, _gate_flags, _clk_id) \ 119 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 120 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 121 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0) 122 123#define MUX_FLAGS(_name, _parents, _offset,\ 124 _clk_num, _gate_flags, _clk_id, flags)\ 125 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 126 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 127 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags) 128 129#define MUX8(_name, _parents, _offset, \ 130 _clk_num, _gate_flags, _clk_id) \ 131 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 132 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 133 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0) 134 135#define INT(_name, _parents, _offset, \ 136 _clk_num, _gate_flags, _clk_id) \ 137 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 138 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 139 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 140 _clk_id, _parents##_idx, 0) 141 142#define INT_FLAGS(_name, _parents, _offset,\ 143 _clk_num, _gate_flags, _clk_id, flags)\ 144 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 145 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 146 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 147 _clk_id, _parents##_idx, flags) 148 149#define INT8(_name, _parents, _offset,\ 150 _clk_num, _gate_flags, _clk_id) \ 151 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 152 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 153 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 154 _clk_id, _parents##_idx, 0) 155 156#define UART(_name, _parents, _offset,\ 157 _clk_num, _clk_id) \ 158 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 159 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ 160 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\ 161 _parents##_idx, 0) 162 163#define I2C(_name, _parents, _offset,\ 164 _clk_num, _clk_id) \ 165 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 166 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ 167 _clk_num, 0, _clk_id, _parents##_idx, 0) 168 169#define XUSB(_name, _parents, _offset, \ 170 _clk_num, _gate_flags, _clk_id) \ 171 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ 172 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 173 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 174 _clk_id, _parents##_idx, 0) 175 176#define AUDIO(_name, _offset, _clk_num,\ 177 _gate_flags, _clk_id) \ 178 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \ 179 _offset, 16, 0xE01F, 0, 0, 8, 1, \ 180 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \ 181 _clk_id, mux_d_audio_clk_idx, 0) 182 183#define NODIV(_name, _parents, _offset, \ 184 _mux_shift, _mux_mask, _clk_num, \ 185 _gate_flags, _clk_id) \ 186 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 187 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\ 188 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\ 189 _clk_id, _parents##_idx, 0) 190 191#define GATE(_name, _parent_name, \ 192 _clk_num, _gate_flags, _clk_id, _flags) \ 193 { \ 194 .name = _name, \ 195 .clk_id = _clk_id, \ 196 .p.parent_name = _parent_name, \ 197 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \ 198 _clk_num, _gate_flags, 0), \ 199 .flags = _flags \ 200 } 201 202#define PLLP_BASE 0xa0 203#define PLLP_MISC 0xac 204#define PLLP_OUTA 0xa4 205#define PLLP_OUTB 0xa8 206 207#define PLL_BASE_LOCK BIT(27) 208#define PLL_MISC_LOCK_ENABLE 18 209 210static DEFINE_SPINLOCK(PLLP_OUTA_lock); 211static DEFINE_SPINLOCK(PLLP_OUTB_lock); 212 213#define MUX_I2S_SPDIF(_id) \ 214static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 215 #_id, "pll_p",\ 216 "clk_m"}; 217MUX_I2S_SPDIF(audio0) 218MUX_I2S_SPDIF(audio1) 219MUX_I2S_SPDIF(audio2) 220MUX_I2S_SPDIF(audio3) 221MUX_I2S_SPDIF(audio4) 222MUX_I2S_SPDIF(audio) 223 224#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 225#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 226#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 227#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 228#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 229#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 230 231static const char *mux_pllp_pllc_pllm_clkm[] = { 232 "pll_p", "pll_c", "pll_m", "clk_m" 233}; 234#define mux_pllp_pllc_pllm_clkm_idx NULL 235 236static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 237#define mux_pllp_pllc_pllm_idx NULL 238 239static const char *mux_pllp_pllc_clk32_clkm[] = { 240 "pll_p", "pll_c", "clk_32k", "clk_m" 241}; 242#define mux_pllp_pllc_clk32_clkm_idx NULL 243 244static const char *mux_plla_pllc_pllp_clkm[] = { 245 "pll_a_out0", "pll_c", "pll_p", "clk_m" 246}; 247#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 248 249static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 250 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 251}; 252static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 253 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 254}; 255 256static const char *mux_pllp_clkm[] = { 257 "pll_p", "clk_m" 258}; 259static u32 mux_pllp_clkm_idx[] = { 260 [0] = 0, [1] = 3, 261}; 262 263static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 264 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 265}; 266#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 267 268static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 269 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 270 "pll_d2_out0", "clk_m" 271}; 272#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 273 274static const char *mux_pllm_pllc_pllp_plla[] = { 275 "pll_m", "pll_c", "pll_p", "pll_a_out0" 276}; 277#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 278 279static const char *mux_pllp_pllc_clkm[] = { 280 "pll_p", "pll_c", "pll_m" 281}; 282static u32 mux_pllp_pllc_clkm_idx[] = { 283 [0] = 0, [1] = 1, [2] = 3, 284}; 285 286static const char *mux_pllp_pllc_clkm_clk32[] = { 287 "pll_p", "pll_c", "clk_m", "clk_32k" 288}; 289#define mux_pllp_pllc_clkm_clk32_idx NULL 290 291static const char *mux_plla_clk32_pllp_clkm_plle[] = { 292 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 293}; 294#define mux_plla_clk32_pllp_clkm_plle_idx NULL 295 296static const char *mux_clkm_pllp_pllc_pllre[] = { 297 "clk_m", "pll_p", "pll_c", "pll_re_out" 298}; 299static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 300 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 301}; 302 303static const char *mux_clkm_48M_pllp_480M[] = { 304 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 305}; 306#define mux_clkm_48M_pllp_480M_idx NULL 307 308static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 309 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 310}; 311static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 312 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 313}; 314 315static const char *mux_d_audio_clk[] = { 316 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 317 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 318}; 319static u32 mux_d_audio_clk_idx[] = { 320 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 321 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 322}; 323 324static const char *mux_pllp_plld_pllc_clkm[] = { 325 "pll_p", "pll_d_out0", "pll_c", "clk_m" 326}; 327#define mux_pllp_plld_pllc_clkm_idx NULL 328 329static struct tegra_periph_init_data periph_clks[] = { 330 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio), 331 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0), 332 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1), 333 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2), 334 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1), 335 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2), 336 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3), 337 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4), 338 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5), 339 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), 340 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), 341 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), 342 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), 343 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), 344 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), 345 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d), 346 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8), 347 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8), 348 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8), 349 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc), 350 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec), 351 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8), 352 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), 353 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8), 354 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8), 355 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED), 356 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0), 357 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1), 358 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2), 359 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3), 360 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4), 361 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out), 362 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in), 363 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm), 364 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx), 365 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx), 366 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), 367 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), 368 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), 369 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1), 370 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2), 371 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3), 372 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4), 373 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la), 374 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace), 375 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr), 376 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor), 377 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi), 378 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor), 379 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab), 380 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd), 381 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile), 382 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp), 383 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp), 384 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor), 385 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon), 386 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref), 387 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc), 388 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow), 389 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1), 390 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2), 391 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3), 392 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4), 393 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5), 394 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6), 395 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve), 396 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo), 397 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac), 398 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash), 399 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed), 400 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob), 401 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata), 402 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8), 403 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8), 404 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8), 405 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8), 406 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8), 407 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8), 408 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8), 409 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8), 410 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), 411 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1), 412 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2), 413 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3), 414 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), 415 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), 416 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED), 417 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1), 418 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2), 419 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta), 420 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), 421 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), 422 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), 423 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), 424 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), 425 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), 426 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), 427 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src), 428 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), 429}; 430 431static struct tegra_periph_init_data gate_clks[] = { 432 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), 433 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), 434 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), 435 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), 436 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), 437 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), 438 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), 439 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), 440 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), 441 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0), 442 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0), 443 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0), 444 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0), 445 GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0), 446 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0), 447 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0), 448 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0), 449 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0), 450 GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0), 451 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0), 452 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0), 453 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0), 454 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0), 455 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0), 456 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0), 457 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0), 458 GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0), 459 GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0), 460 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED), 461 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0), 462}; 463 464struct pll_out_data { 465 char *div_name; 466 char *pll_out_name; 467 u32 offset; 468 int clk_id; 469 u8 div_shift; 470 u8 div_flags; 471 u8 rst_shift; 472 spinlock_t *lock; 473}; 474 475#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \ 476 {\ 477 .div_name = "pll_p_out" #_num "_div",\ 478 .pll_out_name = "pll_p_out" #_num,\ 479 .offset = _offset,\ 480 .div_shift = _div_shift,\ 481 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\ 482 TEGRA_DIVIDER_ROUND_UP,\ 483 .rst_shift = _rst_shift,\ 484 .clk_id = tegra_clk_ ## _id,\ 485 .lock = &_offset ##_lock,\ 486 } 487 488static struct pll_out_data pllp_out_clks[] = { 489 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1), 490 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2), 491 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int), 492 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3), 493 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4), 494}; 495 496static void __init periph_clk_init(void __iomem *clk_base, 497 struct tegra_clk *tegra_clks) 498{ 499 int i; 500 struct clk *clk; 501 struct clk **dt_clk; 502 503 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { 504 struct tegra_clk_periph_regs *bank; 505 struct tegra_periph_init_data *data; 506 507 data = periph_clks + i; 508 509 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 510 if (!dt_clk) 511 continue; 512 513 bank = get_reg_bank(data->periph.gate.clk_num); 514 if (!bank) 515 continue; 516 517 data->periph.gate.regs = bank; 518 clk = tegra_clk_register_periph(data->name, 519 data->p.parent_names, data->num_parents, 520 &data->periph, clk_base, data->offset, 521 data->flags); 522 *dt_clk = clk; 523 } 524} 525 526static void __init gate_clk_init(void __iomem *clk_base, 527 struct tegra_clk *tegra_clks) 528{ 529 int i; 530 struct clk *clk; 531 struct clk **dt_clk; 532 533 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { 534 struct tegra_periph_init_data *data; 535 536 data = gate_clks + i; 537 538 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 539 if (!dt_clk) 540 continue; 541 542 clk = tegra_clk_register_periph_gate(data->name, 543 data->p.parent_name, data->periph.gate.flags, 544 clk_base, data->flags, 545 data->periph.gate.clk_num, 546 periph_clk_enb_refcnt); 547 *dt_clk = clk; 548 } 549} 550 551static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, 552 struct tegra_clk *tegra_clks, 553 struct tegra_clk_pll_params *pll_params) 554{ 555 struct clk *clk; 556 struct clk **dt_clk; 557 int i; 558 559 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks); 560 if (dt_clk) { 561 /* PLLP */ 562 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, 563 pmc_base, 0, pll_params, NULL); 564 clk_register_clkdev(clk, "pll_p", NULL); 565 *dt_clk = clk; 566 } 567 568 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) { 569 struct pll_out_data *data; 570 571 data = pllp_out_clks + i; 572 573 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 574 if (!dt_clk) 575 continue; 576 577 clk = tegra_clk_register_divider(data->div_name, "pll_p", 578 clk_base + data->offset, 0, data->div_flags, 579 data->div_shift, 8, 1, data->lock); 580 clk = tegra_clk_register_pll_out(data->pll_out_name, 581 data->div_name, clk_base + data->offset, 582 data->rst_shift + 1, data->rst_shift, 583 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 584 data->lock); 585 *dt_clk = clk; 586 } 587} 588 589void __init tegra_periph_clk_init(void __iomem *clk_base, 590 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 591 struct tegra_clk_pll_params *pll_params) 592{ 593 init_pllp(clk_base, pmc_base, tegra_clks, pll_params); 594 periph_clk_init(clk_base, tegra_clks); 595 gate_clk_init(clk_base, tegra_clks); 596} 597