clk-tegra20.c revision 343a607cb79259429afbb9820bf524d33084e66c
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/clk/tegra.h> 24#include <linux/delay.h> 25 26#include "clk.h" 27 28#define OSC_CTRL 0x50 29#define OSC_CTRL_OSC_FREQ_MASK (3<<30) 30#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) 31#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) 32#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) 33#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) 34#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 35 36#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) 37#define OSC_CTRL_PLL_REF_DIV_1 (0<<28) 38#define OSC_CTRL_PLL_REF_DIV_2 (1<<28) 39#define OSC_CTRL_PLL_REF_DIV_4 (2<<28) 40 41#define OSC_FREQ_DET 0x58 42#define OSC_FREQ_DET_TRIG (1<<31) 43 44#define OSC_FREQ_DET_STATUS 0x5c 45#define OSC_FREQ_DET_BUSY (1<<31) 46#define OSC_FREQ_DET_CNT_MASK 0xFFFF 47 48#define TEGRA20_CLK_PERIPH_BANKS 3 49 50#define PLLS_BASE 0xf0 51#define PLLS_MISC 0xf4 52#define PLLC_BASE 0x80 53#define PLLC_MISC 0x8c 54#define PLLM_BASE 0x90 55#define PLLM_MISC 0x9c 56#define PLLP_BASE 0xa0 57#define PLLP_MISC 0xac 58#define PLLA_BASE 0xb0 59#define PLLA_MISC 0xbc 60#define PLLU_BASE 0xc0 61#define PLLU_MISC 0xcc 62#define PLLD_BASE 0xd0 63#define PLLD_MISC 0xdc 64#define PLLX_BASE 0xe0 65#define PLLX_MISC 0xe4 66#define PLLE_BASE 0xe8 67#define PLLE_MISC 0xec 68 69#define PLL_BASE_LOCK BIT(27) 70#define PLLE_MISC_LOCK BIT(11) 71 72#define PLL_MISC_LOCK_ENABLE 18 73#define PLLDU_MISC_LOCK_ENABLE 22 74#define PLLE_MISC_LOCK_ENABLE 9 75 76#define PLLC_OUT 0x84 77#define PLLM_OUT 0x94 78#define PLLP_OUTA 0xa4 79#define PLLP_OUTB 0xa8 80#define PLLA_OUT 0xb4 81 82#define CCLK_BURST_POLICY 0x20 83#define SUPER_CCLK_DIVIDER 0x24 84#define SCLK_BURST_POLICY 0x28 85#define SUPER_SCLK_DIVIDER 0x2c 86#define CLK_SYSTEM_RATE 0x30 87 88#define CCLK_BURST_POLICY_SHIFT 28 89#define CCLK_RUN_POLICY_SHIFT 4 90#define CCLK_IDLE_POLICY_SHIFT 0 91#define CCLK_IDLE_POLICY 1 92#define CCLK_RUN_POLICY 2 93#define CCLK_BURST_POLICY_PLLX 8 94 95#define CLK_SOURCE_I2S1 0x100 96#define CLK_SOURCE_I2S2 0x104 97#define CLK_SOURCE_SPDIF_OUT 0x108 98#define CLK_SOURCE_SPDIF_IN 0x10c 99#define CLK_SOURCE_PWM 0x110 100#define CLK_SOURCE_SPI 0x114 101#define CLK_SOURCE_SBC1 0x134 102#define CLK_SOURCE_SBC2 0x118 103#define CLK_SOURCE_SBC3 0x11c 104#define CLK_SOURCE_SBC4 0x1b4 105#define CLK_SOURCE_XIO 0x120 106#define CLK_SOURCE_TWC 0x12c 107#define CLK_SOURCE_IDE 0x144 108#define CLK_SOURCE_NDFLASH 0x160 109#define CLK_SOURCE_VFIR 0x168 110#define CLK_SOURCE_SDMMC1 0x150 111#define CLK_SOURCE_SDMMC2 0x154 112#define CLK_SOURCE_SDMMC3 0x1bc 113#define CLK_SOURCE_SDMMC4 0x164 114#define CLK_SOURCE_CVE 0x140 115#define CLK_SOURCE_TVO 0x188 116#define CLK_SOURCE_TVDAC 0x194 117#define CLK_SOURCE_HDMI 0x18c 118#define CLK_SOURCE_DISP1 0x138 119#define CLK_SOURCE_DISP2 0x13c 120#define CLK_SOURCE_CSITE 0x1d4 121#define CLK_SOURCE_LA 0x1f8 122#define CLK_SOURCE_OWR 0x1cc 123#define CLK_SOURCE_NOR 0x1d0 124#define CLK_SOURCE_MIPI 0x174 125#define CLK_SOURCE_I2C1 0x124 126#define CLK_SOURCE_I2C2 0x198 127#define CLK_SOURCE_I2C3 0x1b8 128#define CLK_SOURCE_DVC 0x128 129#define CLK_SOURCE_UARTA 0x178 130#define CLK_SOURCE_UARTB 0x17c 131#define CLK_SOURCE_UARTC 0x1a0 132#define CLK_SOURCE_UARTD 0x1c0 133#define CLK_SOURCE_UARTE 0x1c4 134#define CLK_SOURCE_3D 0x158 135#define CLK_SOURCE_2D 0x15c 136#define CLK_SOURCE_MPE 0x170 137#define CLK_SOURCE_EPP 0x16c 138#define CLK_SOURCE_HOST1X 0x180 139#define CLK_SOURCE_VDE 0x1c8 140#define CLK_SOURCE_VI 0x148 141#define CLK_SOURCE_VI_SENSOR 0x1a8 142#define CLK_SOURCE_EMC 0x19c 143 144#define AUDIO_SYNC_CLK 0x38 145 146#define PMC_CTRL 0x0 147#define PMC_CTRL_BLINK_ENB 7 148#define PMC_DPD_PADS_ORIDE 0x1c 149#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 150#define PMC_BLINK_TIMER 0x40 151 152/* Tegra CPU clock and reset control regs */ 153#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 154#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 155#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 156 157#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 158#define CPU_RESET(cpu) (0x1111ul << (cpu)) 159 160#ifdef CONFIG_PM_SLEEP 161static struct cpu_clk_suspend_context { 162 u32 pllx_misc; 163 u32 pllx_base; 164 165 u32 cpu_burst; 166 u32 clk_csite_src; 167 u32 cclk_divider; 168} tegra20_cpu_clk_sctx; 169#endif 170 171static void __iomem *clk_base; 172static void __iomem *pmc_base; 173 174static DEFINE_SPINLOCK(pll_div_lock); 175static DEFINE_SPINLOCK(sysrate_lock); 176 177#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 178 _clk_num, _gate_flags, _clk_id) \ 179 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 180 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 181 _clk_num, \ 182 _gate_flags, _clk_id) 183 184#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 185 _clk_num, _gate_flags, _clk_id) \ 186 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 187 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, \ 188 _clk_num, _gate_flags, \ 189 _clk_id) 190 191#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 192 _clk_num, _gate_flags, _clk_id) \ 193 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 194 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 195 _clk_num, _gate_flags, \ 196 _clk_id) 197 198#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 199 _mux_shift, _mux_width, _clk_num, \ 200 _gate_flags, _clk_id) \ 201 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 202 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \ 203 _clk_num, _gate_flags, \ 204 _clk_id) 205 206/* IDs assigned here must be in sync with DT bindings definition 207 * for Tegra20 clocks . 208 */ 209enum tegra20_clk { 210 cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, 211 ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp, 212 gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma, 213 kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3, 214 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 215 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 216 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb, 217 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1, 218 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve, 219 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0, 220 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1, 221 pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u, 222 pll_x, cop, audio, pll_ref, twd, clk_max, 223}; 224 225static struct clk **clks; 226 227static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 228 { 12000000, 600000000, 600, 12, 0, 8 }, 229 { 13000000, 600000000, 600, 13, 0, 8 }, 230 { 19200000, 600000000, 500, 16, 0, 6 }, 231 { 26000000, 600000000, 600, 26, 0, 8 }, 232 { 0, 0, 0, 0, 0, 0 }, 233}; 234 235static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 236 { 12000000, 666000000, 666, 12, 0, 8}, 237 { 13000000, 666000000, 666, 13, 0, 8}, 238 { 19200000, 666000000, 555, 16, 0, 8}, 239 { 26000000, 666000000, 666, 26, 0, 8}, 240 { 12000000, 600000000, 600, 12, 0, 8}, 241 { 13000000, 600000000, 600, 13, 0, 8}, 242 { 19200000, 600000000, 375, 12, 0, 6}, 243 { 26000000, 600000000, 600, 26, 0, 8}, 244 { 0, 0, 0, 0, 0, 0 }, 245}; 246 247static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 248 { 12000000, 216000000, 432, 12, 1, 8}, 249 { 13000000, 216000000, 432, 13, 1, 8}, 250 { 19200000, 216000000, 90, 4, 1, 1}, 251 { 26000000, 216000000, 432, 26, 1, 8}, 252 { 12000000, 432000000, 432, 12, 0, 8}, 253 { 13000000, 432000000, 432, 13, 0, 8}, 254 { 19200000, 432000000, 90, 4, 0, 1}, 255 { 26000000, 432000000, 432, 26, 0, 8}, 256 { 0, 0, 0, 0, 0, 0 }, 257}; 258 259static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 260 { 28800000, 56448000, 49, 25, 0, 1}, 261 { 28800000, 73728000, 64, 25, 0, 1}, 262 { 28800000, 24000000, 5, 6, 0, 1}, 263 { 0, 0, 0, 0, 0, 0 }, 264}; 265 266static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 267 { 12000000, 216000000, 216, 12, 0, 4}, 268 { 13000000, 216000000, 216, 13, 0, 4}, 269 { 19200000, 216000000, 135, 12, 0, 3}, 270 { 26000000, 216000000, 216, 26, 0, 4}, 271 272 { 12000000, 594000000, 594, 12, 0, 8}, 273 { 13000000, 594000000, 594, 13, 0, 8}, 274 { 19200000, 594000000, 495, 16, 0, 8}, 275 { 26000000, 594000000, 594, 26, 0, 8}, 276 277 { 12000000, 1000000000, 1000, 12, 0, 12}, 278 { 13000000, 1000000000, 1000, 13, 0, 12}, 279 { 19200000, 1000000000, 625, 12, 0, 8}, 280 { 26000000, 1000000000, 1000, 26, 0, 12}, 281 282 { 0, 0, 0, 0, 0, 0 }, 283}; 284 285static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 286 { 12000000, 480000000, 960, 12, 0, 0}, 287 { 13000000, 480000000, 960, 13, 0, 0}, 288 { 19200000, 480000000, 200, 4, 0, 0}, 289 { 26000000, 480000000, 960, 26, 0, 0}, 290 { 0, 0, 0, 0, 0, 0 }, 291}; 292 293static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 294 /* 1 GHz */ 295 { 12000000, 1000000000, 1000, 12, 0, 12}, 296 { 13000000, 1000000000, 1000, 13, 0, 12}, 297 { 19200000, 1000000000, 625, 12, 0, 8}, 298 { 26000000, 1000000000, 1000, 26, 0, 12}, 299 300 /* 912 MHz */ 301 { 12000000, 912000000, 912, 12, 0, 12}, 302 { 13000000, 912000000, 912, 13, 0, 12}, 303 { 19200000, 912000000, 760, 16, 0, 8}, 304 { 26000000, 912000000, 912, 26, 0, 12}, 305 306 /* 816 MHz */ 307 { 12000000, 816000000, 816, 12, 0, 12}, 308 { 13000000, 816000000, 816, 13, 0, 12}, 309 { 19200000, 816000000, 680, 16, 0, 8}, 310 { 26000000, 816000000, 816, 26, 0, 12}, 311 312 /* 760 MHz */ 313 { 12000000, 760000000, 760, 12, 0, 12}, 314 { 13000000, 760000000, 760, 13, 0, 12}, 315 { 19200000, 760000000, 950, 24, 0, 8}, 316 { 26000000, 760000000, 760, 26, 0, 12}, 317 318 /* 750 MHz */ 319 { 12000000, 750000000, 750, 12, 0, 12}, 320 { 13000000, 750000000, 750, 13, 0, 12}, 321 { 19200000, 750000000, 625, 16, 0, 8}, 322 { 26000000, 750000000, 750, 26, 0, 12}, 323 324 /* 608 MHz */ 325 { 12000000, 608000000, 608, 12, 0, 12}, 326 { 13000000, 608000000, 608, 13, 0, 12}, 327 { 19200000, 608000000, 380, 12, 0, 8}, 328 { 26000000, 608000000, 608, 26, 0, 12}, 329 330 /* 456 MHz */ 331 { 12000000, 456000000, 456, 12, 0, 12}, 332 { 13000000, 456000000, 456, 13, 0, 12}, 333 { 19200000, 456000000, 380, 16, 0, 8}, 334 { 26000000, 456000000, 456, 26, 0, 12}, 335 336 /* 312 MHz */ 337 { 12000000, 312000000, 312, 12, 0, 12}, 338 { 13000000, 312000000, 312, 13, 0, 12}, 339 { 19200000, 312000000, 260, 16, 0, 8}, 340 { 26000000, 312000000, 312, 26, 0, 12}, 341 342 { 0, 0, 0, 0, 0, 0 }, 343}; 344 345static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 346 { 12000000, 100000000, 200, 24, 0, 0 }, 347 { 0, 0, 0, 0, 0, 0 }, 348}; 349 350/* PLL parameters */ 351static struct tegra_clk_pll_params pll_c_params = { 352 .input_min = 2000000, 353 .input_max = 31000000, 354 .cf_min = 1000000, 355 .cf_max = 6000000, 356 .vco_min = 20000000, 357 .vco_max = 1400000000, 358 .base_reg = PLLC_BASE, 359 .misc_reg = PLLC_MISC, 360 .lock_mask = PLL_BASE_LOCK, 361 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 362 .lock_delay = 300, 363}; 364 365static struct tegra_clk_pll_params pll_m_params = { 366 .input_min = 2000000, 367 .input_max = 31000000, 368 .cf_min = 1000000, 369 .cf_max = 6000000, 370 .vco_min = 20000000, 371 .vco_max = 1200000000, 372 .base_reg = PLLM_BASE, 373 .misc_reg = PLLM_MISC, 374 .lock_mask = PLL_BASE_LOCK, 375 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 376 .lock_delay = 300, 377}; 378 379static struct tegra_clk_pll_params pll_p_params = { 380 .input_min = 2000000, 381 .input_max = 31000000, 382 .cf_min = 1000000, 383 .cf_max = 6000000, 384 .vco_min = 20000000, 385 .vco_max = 1400000000, 386 .base_reg = PLLP_BASE, 387 .misc_reg = PLLP_MISC, 388 .lock_mask = PLL_BASE_LOCK, 389 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 390 .lock_delay = 300, 391}; 392 393static struct tegra_clk_pll_params pll_a_params = { 394 .input_min = 2000000, 395 .input_max = 31000000, 396 .cf_min = 1000000, 397 .cf_max = 6000000, 398 .vco_min = 20000000, 399 .vco_max = 1400000000, 400 .base_reg = PLLA_BASE, 401 .misc_reg = PLLA_MISC, 402 .lock_mask = PLL_BASE_LOCK, 403 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 404 .lock_delay = 300, 405}; 406 407static struct tegra_clk_pll_params pll_d_params = { 408 .input_min = 2000000, 409 .input_max = 40000000, 410 .cf_min = 1000000, 411 .cf_max = 6000000, 412 .vco_min = 40000000, 413 .vco_max = 1000000000, 414 .base_reg = PLLD_BASE, 415 .misc_reg = PLLD_MISC, 416 .lock_mask = PLL_BASE_LOCK, 417 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 418 .lock_delay = 1000, 419}; 420 421static struct pdiv_map pllu_p[] = { 422 { .pdiv = 1, .hw_val = 1 }, 423 { .pdiv = 2, .hw_val = 0 }, 424 { .pdiv = 0, .hw_val = 0 }, 425}; 426 427static struct tegra_clk_pll_params pll_u_params = { 428 .input_min = 2000000, 429 .input_max = 40000000, 430 .cf_min = 1000000, 431 .cf_max = 6000000, 432 .vco_min = 48000000, 433 .vco_max = 960000000, 434 .base_reg = PLLU_BASE, 435 .misc_reg = PLLU_MISC, 436 .lock_mask = PLL_BASE_LOCK, 437 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 438 .lock_delay = 1000, 439 .pdiv_tohw = pllu_p, 440}; 441 442static struct tegra_clk_pll_params pll_x_params = { 443 .input_min = 2000000, 444 .input_max = 31000000, 445 .cf_min = 1000000, 446 .cf_max = 6000000, 447 .vco_min = 20000000, 448 .vco_max = 1200000000, 449 .base_reg = PLLX_BASE, 450 .misc_reg = PLLX_MISC, 451 .lock_mask = PLL_BASE_LOCK, 452 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 453 .lock_delay = 300, 454}; 455 456static struct tegra_clk_pll_params pll_e_params = { 457 .input_min = 12000000, 458 .input_max = 12000000, 459 .cf_min = 0, 460 .cf_max = 0, 461 .vco_min = 0, 462 .vco_max = 0, 463 .base_reg = PLLE_BASE, 464 .misc_reg = PLLE_MISC, 465 .lock_mask = PLLE_MISC_LOCK, 466 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 467 .lock_delay = 0, 468}; 469 470static unsigned long tegra20_clk_measure_input_freq(void) 471{ 472 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 473 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 474 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 475 unsigned long input_freq; 476 477 switch (auto_clk_control) { 478 case OSC_CTRL_OSC_FREQ_12MHZ: 479 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 480 input_freq = 12000000; 481 break; 482 case OSC_CTRL_OSC_FREQ_13MHZ: 483 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 484 input_freq = 13000000; 485 break; 486 case OSC_CTRL_OSC_FREQ_19_2MHZ: 487 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 488 input_freq = 19200000; 489 break; 490 case OSC_CTRL_OSC_FREQ_26MHZ: 491 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 492 input_freq = 26000000; 493 break; 494 default: 495 pr_err("Unexpected clock autodetect value %d", 496 auto_clk_control); 497 BUG(); 498 return 0; 499 } 500 501 return input_freq; 502} 503 504static unsigned int tegra20_get_pll_ref_div(void) 505{ 506 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 507 OSC_CTRL_PLL_REF_DIV_MASK; 508 509 switch (pll_ref_div) { 510 case OSC_CTRL_PLL_REF_DIV_1: 511 return 1; 512 case OSC_CTRL_PLL_REF_DIV_2: 513 return 2; 514 case OSC_CTRL_PLL_REF_DIV_4: 515 return 4; 516 default: 517 pr_err("Invalied pll ref divider %d\n", pll_ref_div); 518 BUG(); 519 } 520 return 0; 521} 522 523static void tegra20_pll_init(void) 524{ 525 struct clk *clk; 526 527 /* PLLC */ 528 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 529 0, &pll_c_params, TEGRA_PLL_HAS_CPCON, 530 pll_c_freq_table, NULL); 531 clk_register_clkdev(clk, "pll_c", NULL); 532 clks[pll_c] = clk; 533 534 /* PLLC_OUT1 */ 535 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 536 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 537 8, 8, 1, NULL); 538 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 539 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 540 0, NULL); 541 clk_register_clkdev(clk, "pll_c_out1", NULL); 542 clks[pll_c_out1] = clk; 543 544 /* PLLP */ 545 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0, 546 216000000, &pll_p_params, TEGRA_PLL_FIXED | 547 TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL); 548 clk_register_clkdev(clk, "pll_p", NULL); 549 clks[pll_p] = clk; 550 551 /* PLLP_OUT1 */ 552 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 553 clk_base + PLLP_OUTA, 0, 554 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 555 8, 8, 1, &pll_div_lock); 556 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 557 clk_base + PLLP_OUTA, 1, 0, 558 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 559 &pll_div_lock); 560 clk_register_clkdev(clk, "pll_p_out1", NULL); 561 clks[pll_p_out1] = clk; 562 563 /* PLLP_OUT2 */ 564 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 565 clk_base + PLLP_OUTA, 0, 566 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 567 24, 8, 1, &pll_div_lock); 568 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 569 clk_base + PLLP_OUTA, 17, 16, 570 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 571 &pll_div_lock); 572 clk_register_clkdev(clk, "pll_p_out2", NULL); 573 clks[pll_p_out2] = clk; 574 575 /* PLLP_OUT3 */ 576 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 577 clk_base + PLLP_OUTB, 0, 578 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 579 8, 8, 1, &pll_div_lock); 580 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 581 clk_base + PLLP_OUTB, 1, 0, 582 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 583 &pll_div_lock); 584 clk_register_clkdev(clk, "pll_p_out3", NULL); 585 clks[pll_p_out3] = clk; 586 587 /* PLLP_OUT4 */ 588 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 589 clk_base + PLLP_OUTB, 0, 590 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 591 24, 8, 1, &pll_div_lock); 592 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 593 clk_base + PLLP_OUTB, 17, 16, 594 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 595 &pll_div_lock); 596 clk_register_clkdev(clk, "pll_p_out4", NULL); 597 clks[pll_p_out4] = clk; 598 599 /* PLLM */ 600 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 601 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 602 &pll_m_params, TEGRA_PLL_HAS_CPCON, 603 pll_m_freq_table, NULL); 604 clk_register_clkdev(clk, "pll_m", NULL); 605 clks[pll_m] = clk; 606 607 /* PLLM_OUT1 */ 608 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 609 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 610 8, 8, 1, NULL); 611 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 612 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 613 CLK_SET_RATE_PARENT, 0, NULL); 614 clk_register_clkdev(clk, "pll_m_out1", NULL); 615 clks[pll_m_out1] = clk; 616 617 /* PLLX */ 618 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 619 0, &pll_x_params, TEGRA_PLL_HAS_CPCON, 620 pll_x_freq_table, NULL); 621 clk_register_clkdev(clk, "pll_x", NULL); 622 clks[pll_x] = clk; 623 624 /* PLLU */ 625 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 626 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, 627 pll_u_freq_table, NULL); 628 clk_register_clkdev(clk, "pll_u", NULL); 629 clks[pll_u] = clk; 630 631 /* PLLD */ 632 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 633 0, &pll_d_params, TEGRA_PLL_HAS_CPCON, 634 pll_d_freq_table, NULL); 635 clk_register_clkdev(clk, "pll_d", NULL); 636 clks[pll_d] = clk; 637 638 /* PLLD_OUT0 */ 639 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 640 CLK_SET_RATE_PARENT, 1, 2); 641 clk_register_clkdev(clk, "pll_d_out0", NULL); 642 clks[pll_d_out0] = clk; 643 644 /* PLLA */ 645 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 646 0, &pll_a_params, TEGRA_PLL_HAS_CPCON, 647 pll_a_freq_table, NULL); 648 clk_register_clkdev(clk, "pll_a", NULL); 649 clks[pll_a] = clk; 650 651 /* PLLA_OUT0 */ 652 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 653 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 654 8, 8, 1, NULL); 655 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 656 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 657 CLK_SET_RATE_PARENT, 0, NULL); 658 clk_register_clkdev(clk, "pll_a_out0", NULL); 659 clks[pll_a_out0] = clk; 660 661 /* PLLE */ 662 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 663 0, 100000000, &pll_e_params, 664 0, pll_e_freq_table, NULL); 665 clk_register_clkdev(clk, "pll_e", NULL); 666 clks[pll_e] = clk; 667} 668 669static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 670 "pll_p", "pll_p_out4", 671 "pll_p_out3", "clk_d", "pll_x" }; 672static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 673 "pll_p_out3", "pll_p_out2", "clk_d", 674 "clk_32k", "pll_m_out1" }; 675 676static void tegra20_super_clk_init(void) 677{ 678 struct clk *clk; 679 680 /* CCLK */ 681 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 682 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 683 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 684 clk_register_clkdev(clk, "cclk", NULL); 685 clks[cclk] = clk; 686 687 /* SCLK */ 688 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 689 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, 690 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 691 clk_register_clkdev(clk, "sclk", NULL); 692 clks[sclk] = clk; 693 694 /* HCLK */ 695 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 696 clk_base + CLK_SYSTEM_RATE, 4, 2, 0, 697 &sysrate_lock); 698 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, 699 clk_base + CLK_SYSTEM_RATE, 7, 700 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 701 clk_register_clkdev(clk, "hclk", NULL); 702 clks[hclk] = clk; 703 704 /* PCLK */ 705 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 706 clk_base + CLK_SYSTEM_RATE, 0, 2, 0, 707 &sysrate_lock); 708 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, 709 clk_base + CLK_SYSTEM_RATE, 3, 710 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 711 clk_register_clkdev(clk, "pclk", NULL); 712 clks[pclk] = clk; 713 714 /* twd */ 715 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 716 clk_register_clkdev(clk, "twd", NULL); 717 clks[twd] = clk; 718} 719 720static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", 721 "pll_a_out0", "unused", "unused", 722 "unused"}; 723 724static void __init tegra20_audio_clk_init(void) 725{ 726 struct clk *clk; 727 728 /* audio */ 729 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 730 ARRAY_SIZE(audio_parents), 731 CLK_SET_RATE_NO_REPARENT, 732 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 733 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 734 clk_base + AUDIO_SYNC_CLK, 4, 735 CLK_GATE_SET_TO_DISABLE, NULL); 736 clk_register_clkdev(clk, "audio", NULL); 737 clks[audio] = clk; 738 739 /* audio_2x */ 740 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 741 CLK_SET_RATE_PARENT, 2, 1); 742 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 743 TEGRA_PERIPH_NO_RESET, clk_base, 744 CLK_SET_RATE_PARENT, 89, 745 periph_clk_enb_refcnt); 746 clk_register_clkdev(clk, "audio_2x", NULL); 747 clks[audio_2x] = clk; 748 749} 750 751static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 752 "clk_m"}; 753static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 754 "clk_m"}; 755static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 756 "clk_m"}; 757static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"}; 758static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", 759 "clk_32k"}; 760static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; 761static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"}; 762static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", 763 "clk_m"}; 764static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 765 766static struct tegra_periph_init_data tegra_periph_clk_list[] = { 767 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, i2s1), 768 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, i2s2), 769 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, spdif_out), 770 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, spdif_in), 771 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, sbc1), 772 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, sbc2), 773 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, sbc3), 774 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, sbc4), 775 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, spi), 776 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, xio), 777 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, twc), 778 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, ide), 779 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, 0, ndflash), 780 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, vfir), 781 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, 0, csite), 782 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, 0, la), 783 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, owr), 784 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, mipi), 785 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, 0, vde), 786 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, 0, vi), 787 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, 0, epp), 788 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, 0, mpe), 789 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, 0, host1x), 790 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, TEGRA_PERIPH_MANUAL_RESET, gr3d), 791 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, 0, gr2d), 792 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, 0, nor), 793 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, 0, sdmmc1), 794 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, 0, sdmmc2), 795 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, 0, sdmmc3), 796 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, 0, sdmmc4), 797 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, 0, cve), 798 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, 0, tvo), 799 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, 0, tvdac), 800 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, vi_sensor), 801 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, i2c1), 802 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, i2c2), 803 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, i2c3), 804 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, dvc), 805 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, hdmi), 806 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, pwm), 807}; 808 809static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 810 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, uarta), 811 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, uartb), 812 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, uartc), 813 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, uartd), 814 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, uarte), 815 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, disp1), 816 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, disp2), 817}; 818 819static void __init tegra20_periph_clk_init(void) 820{ 821 struct tegra_periph_init_data *data; 822 struct clk *clk; 823 int i; 824 825 /* ac97 */ 826 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 827 TEGRA_PERIPH_ON_APB, 828 clk_base, 0, 3, periph_clk_enb_refcnt); 829 clk_register_clkdev(clk, NULL, "tegra20-ac97"); 830 clks[ac97] = clk; 831 832 /* apbdma */ 833 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 834 0, 34, periph_clk_enb_refcnt); 835 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 836 clks[apbdma] = clk; 837 838 /* rtc */ 839 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 840 TEGRA_PERIPH_NO_RESET, 841 clk_base, 0, 4, periph_clk_enb_refcnt); 842 clk_register_clkdev(clk, NULL, "rtc-tegra"); 843 clks[rtc] = clk; 844 845 /* timer */ 846 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 847 0, 5, periph_clk_enb_refcnt); 848 clk_register_clkdev(clk, NULL, "timer"); 849 clks[timer] = clk; 850 851 /* kbc */ 852 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 853 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 854 clk_base, 0, 36, periph_clk_enb_refcnt); 855 clk_register_clkdev(clk, NULL, "tegra-kbc"); 856 clks[kbc] = clk; 857 858 /* csus */ 859 clk = tegra_clk_register_periph_gate("csus", "clk_m", 860 TEGRA_PERIPH_NO_RESET, 861 clk_base, 0, 92, periph_clk_enb_refcnt); 862 clk_register_clkdev(clk, "csus", "tengra_camera"); 863 clks[csus] = clk; 864 865 /* vcp */ 866 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, 867 clk_base, 0, 29, periph_clk_enb_refcnt); 868 clk_register_clkdev(clk, "vcp", "tegra-avp"); 869 clks[vcp] = clk; 870 871 /* bsea */ 872 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, 873 clk_base, 0, 62, periph_clk_enb_refcnt); 874 clk_register_clkdev(clk, "bsea", "tegra-avp"); 875 clks[bsea] = clk; 876 877 /* bsev */ 878 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, 879 clk_base, 0, 63, periph_clk_enb_refcnt); 880 clk_register_clkdev(clk, "bsev", "tegra-aes"); 881 clks[bsev] = clk; 882 883 /* emc */ 884 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 885 ARRAY_SIZE(mux_pllmcp_clkm), 886 CLK_SET_RATE_NO_REPARENT, 887 clk_base + CLK_SOURCE_EMC, 888 30, 2, 0, NULL); 889 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 890 57, periph_clk_enb_refcnt); 891 clk_register_clkdev(clk, "emc", NULL); 892 clks[emc] = clk; 893 894 /* usbd */ 895 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 896 22, periph_clk_enb_refcnt); 897 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 898 clks[usbd] = clk; 899 900 /* usb2 */ 901 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 902 58, periph_clk_enb_refcnt); 903 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 904 clks[usb2] = clk; 905 906 /* usb3 */ 907 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 908 59, periph_clk_enb_refcnt); 909 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 910 clks[usb3] = clk; 911 912 /* dsi */ 913 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 914 48, periph_clk_enb_refcnt); 915 clk_register_clkdev(clk, NULL, "dsi"); 916 clks[dsi] = clk; 917 918 /* csi */ 919 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 920 0, 52, periph_clk_enb_refcnt); 921 clk_register_clkdev(clk, "csi", "tegra_camera"); 922 clks[csi] = clk; 923 924 /* isp */ 925 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 926 periph_clk_enb_refcnt); 927 clk_register_clkdev(clk, "isp", "tegra_camera"); 928 clks[isp] = clk; 929 930 /* pex */ 931 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 932 periph_clk_enb_refcnt); 933 clk_register_clkdev(clk, "pex", NULL); 934 clks[pex] = clk; 935 936 /* afi */ 937 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 938 periph_clk_enb_refcnt); 939 clk_register_clkdev(clk, "afi", NULL); 940 clks[afi] = clk; 941 942 /* pcie_xclk */ 943 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base, 944 0, 74, periph_clk_enb_refcnt); 945 clk_register_clkdev(clk, "pcie_xclk", NULL); 946 clks[pcie_xclk] = clk; 947 948 /* cdev1 */ 949 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, 950 26000000); 951 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, 952 clk_base, 0, 94, periph_clk_enb_refcnt); 953 clk_register_clkdev(clk, "cdev1", NULL); 954 clks[cdev1] = clk; 955 956 /* cdev2 */ 957 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, 958 26000000); 959 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, 960 clk_base, 0, 93, periph_clk_enb_refcnt); 961 clk_register_clkdev(clk, "cdev2", NULL); 962 clks[cdev2] = clk; 963 964 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 965 data = &tegra_periph_clk_list[i]; 966 clk = tegra_clk_register_periph(data->name, data->parent_names, 967 data->num_parents, &data->periph, 968 clk_base, data->offset, data->flags); 969 clk_register_clkdev(clk, data->con_id, data->dev_id); 970 clks[data->clk_id] = clk; 971 } 972 973 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 974 data = &tegra_periph_nodiv_clk_list[i]; 975 clk = tegra_clk_register_periph_nodiv(data->name, 976 data->parent_names, 977 data->num_parents, &data->periph, 978 clk_base, data->offset); 979 clk_register_clkdev(clk, data->con_id, data->dev_id); 980 clks[data->clk_id] = clk; 981 } 982} 983 984 985static void __init tegra20_fixed_clk_init(void) 986{ 987 struct clk *clk; 988 989 /* clk_32k */ 990 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 991 32768); 992 clk_register_clkdev(clk, "clk_32k", NULL); 993 clks[clk_32k] = clk; 994} 995 996static void __init tegra20_pmc_clk_init(void) 997{ 998 struct clk *clk; 999 1000 /* blink */ 1001 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1002 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1003 pmc_base + PMC_DPD_PADS_ORIDE, 1004 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1005 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1006 pmc_base + PMC_CTRL, 1007 PMC_CTRL_BLINK_ENB, 0, NULL); 1008 clk_register_clkdev(clk, "blink", NULL); 1009 clks[blink] = clk; 1010} 1011 1012static void __init tegra20_osc_clk_init(void) 1013{ 1014 struct clk *clk; 1015 unsigned long input_freq; 1016 unsigned int pll_ref_div; 1017 1018 input_freq = tegra20_clk_measure_input_freq(); 1019 1020 /* clk_m */ 1021 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | 1022 CLK_IGNORE_UNUSED, input_freq); 1023 clk_register_clkdev(clk, "clk_m", NULL); 1024 clks[clk_m] = clk; 1025 1026 /* pll_ref */ 1027 pll_ref_div = tegra20_get_pll_ref_div(); 1028 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1029 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1030 clk_register_clkdev(clk, "pll_ref", NULL); 1031 clks[pll_ref] = clk; 1032} 1033 1034/* Tegra20 CPU clock and reset control functions */ 1035static void tegra20_wait_cpu_in_reset(u32 cpu) 1036{ 1037 unsigned int reg; 1038 1039 do { 1040 reg = readl(clk_base + 1041 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1042 cpu_relax(); 1043 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1044 1045 return; 1046} 1047 1048static void tegra20_put_cpu_in_reset(u32 cpu) 1049{ 1050 writel(CPU_RESET(cpu), 1051 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1052 dmb(); 1053} 1054 1055static void tegra20_cpu_out_of_reset(u32 cpu) 1056{ 1057 writel(CPU_RESET(cpu), 1058 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1059 wmb(); 1060} 1061 1062static void tegra20_enable_cpu_clock(u32 cpu) 1063{ 1064 unsigned int reg; 1065 1066 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1067 writel(reg & ~CPU_CLOCK(cpu), 1068 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1069 barrier(); 1070 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1071} 1072 1073static void tegra20_disable_cpu_clock(u32 cpu) 1074{ 1075 unsigned int reg; 1076 1077 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1078 writel(reg | CPU_CLOCK(cpu), 1079 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1080} 1081 1082#ifdef CONFIG_PM_SLEEP 1083static bool tegra20_cpu_rail_off_ready(void) 1084{ 1085 unsigned int cpu_rst_status; 1086 1087 cpu_rst_status = readl(clk_base + 1088 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1089 1090 return !!(cpu_rst_status & 0x2); 1091} 1092 1093static void tegra20_cpu_clock_suspend(void) 1094{ 1095 /* switch coresite to clk_m, save off original source */ 1096 tegra20_cpu_clk_sctx.clk_csite_src = 1097 readl(clk_base + CLK_SOURCE_CSITE); 1098 writel(3<<30, clk_base + CLK_SOURCE_CSITE); 1099 1100 tegra20_cpu_clk_sctx.cpu_burst = 1101 readl(clk_base + CCLK_BURST_POLICY); 1102 tegra20_cpu_clk_sctx.pllx_base = 1103 readl(clk_base + PLLX_BASE); 1104 tegra20_cpu_clk_sctx.pllx_misc = 1105 readl(clk_base + PLLX_MISC); 1106 tegra20_cpu_clk_sctx.cclk_divider = 1107 readl(clk_base + SUPER_CCLK_DIVIDER); 1108} 1109 1110static void tegra20_cpu_clock_resume(void) 1111{ 1112 unsigned int reg, policy; 1113 1114 /* Is CPU complex already running on PLLX? */ 1115 reg = readl(clk_base + CCLK_BURST_POLICY); 1116 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; 1117 1118 if (policy == CCLK_IDLE_POLICY) 1119 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; 1120 else if (policy == CCLK_RUN_POLICY) 1121 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; 1122 else 1123 BUG(); 1124 1125 if (reg != CCLK_BURST_POLICY_PLLX) { 1126 /* restore PLLX settings if CPU is on different PLL */ 1127 writel(tegra20_cpu_clk_sctx.pllx_misc, 1128 clk_base + PLLX_MISC); 1129 writel(tegra20_cpu_clk_sctx.pllx_base, 1130 clk_base + PLLX_BASE); 1131 1132 /* wait for PLL stabilization if PLLX was enabled */ 1133 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) 1134 udelay(300); 1135 } 1136 1137 /* 1138 * Restore original burst policy setting for calls resulting from CPU 1139 * LP2 in idle or system suspend. 1140 */ 1141 writel(tegra20_cpu_clk_sctx.cclk_divider, 1142 clk_base + SUPER_CCLK_DIVIDER); 1143 writel(tegra20_cpu_clk_sctx.cpu_burst, 1144 clk_base + CCLK_BURST_POLICY); 1145 1146 writel(tegra20_cpu_clk_sctx.clk_csite_src, 1147 clk_base + CLK_SOURCE_CSITE); 1148} 1149#endif 1150 1151static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { 1152 .wait_for_reset = tegra20_wait_cpu_in_reset, 1153 .put_in_reset = tegra20_put_cpu_in_reset, 1154 .out_of_reset = tegra20_cpu_out_of_reset, 1155 .enable_clock = tegra20_enable_cpu_clock, 1156 .disable_clock = tegra20_disable_cpu_clock, 1157#ifdef CONFIG_PM_SLEEP 1158 .rail_off_ready = tegra20_cpu_rail_off_ready, 1159 .suspend = tegra20_cpu_clock_suspend, 1160 .resume = tegra20_cpu_clock_resume, 1161#endif 1162}; 1163 1164static struct tegra_clk_init_table init_table[] __initdata = { 1165 {pll_p, clk_max, 216000000, 1}, 1166 {pll_p_out1, clk_max, 28800000, 1}, 1167 {pll_p_out2, clk_max, 48000000, 1}, 1168 {pll_p_out3, clk_max, 72000000, 1}, 1169 {pll_p_out4, clk_max, 24000000, 1}, 1170 {pll_c, clk_max, 600000000, 1}, 1171 {pll_c_out1, clk_max, 120000000, 1}, 1172 {sclk, pll_c_out1, 0, 1}, 1173 {hclk, clk_max, 0, 1}, 1174 {pclk, clk_max, 60000000, 1}, 1175 {csite, clk_max, 0, 1}, 1176 {emc, clk_max, 0, 1}, 1177 {cclk, clk_max, 0, 1}, 1178 {uarta, pll_p, 0, 0}, 1179 {uartb, pll_p, 0, 0}, 1180 {uartc, pll_p, 0, 0}, 1181 {uartd, pll_p, 0, 0}, 1182 {uarte, pll_p, 0, 0}, 1183 {pll_a, clk_max, 56448000, 1}, 1184 {pll_a_out0, clk_max, 11289600, 1}, 1185 {cdev1, clk_max, 0, 1}, 1186 {blink, clk_max, 32768, 1}, 1187 {i2s1, pll_a_out0, 11289600, 0}, 1188 {i2s2, pll_a_out0, 11289600, 0}, 1189 {sdmmc1, pll_p, 48000000, 0}, 1190 {sdmmc3, pll_p, 48000000, 0}, 1191 {sdmmc4, pll_p, 48000000, 0}, 1192 {spi, pll_p, 20000000, 0}, 1193 {sbc1, pll_p, 100000000, 0}, 1194 {sbc2, pll_p, 100000000, 0}, 1195 {sbc3, pll_p, 100000000, 0}, 1196 {sbc4, pll_p, 100000000, 0}, 1197 {host1x, pll_c, 150000000, 0}, 1198 {disp1, pll_p, 600000000, 0}, 1199 {disp2, pll_p, 600000000, 0}, 1200 {gr2d, pll_c, 300000000, 0}, 1201 {gr3d, pll_c, 300000000, 0}, 1202 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ 1203}; 1204 1205static void __init tegra20_clock_apply_init_table(void) 1206{ 1207 tegra_init_from_table(init_table, clks, clk_max); 1208} 1209 1210/* 1211 * Some clocks may be used by different drivers depending on the board 1212 * configuration. List those here to register them twice in the clock lookup 1213 * table under two names. 1214 */ 1215static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1216 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1217 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1218 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1219 TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"), 1220 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */ 1221}; 1222 1223static const struct of_device_id pmc_match[] __initconst = { 1224 { .compatible = "nvidia,tegra20-pmc" }, 1225 {}, 1226}; 1227 1228static void __init tegra20_clock_init(struct device_node *np) 1229{ 1230 struct device_node *node; 1231 1232 clk_base = of_iomap(np, 0); 1233 if (!clk_base) { 1234 pr_err("Can't map CAR registers\n"); 1235 BUG(); 1236 } 1237 1238 node = of_find_matching_node(NULL, pmc_match); 1239 if (!node) { 1240 pr_err("Failed to find pmc node\n"); 1241 BUG(); 1242 } 1243 1244 pmc_base = of_iomap(node, 0); 1245 if (!pmc_base) { 1246 pr_err("Can't map pmc registers\n"); 1247 BUG(); 1248 } 1249 1250 clks = tegra_clk_init(clk_max, TEGRA20_CLK_PERIPH_BANKS); 1251 if (!clks) 1252 return; 1253 1254 tegra20_osc_clk_init(); 1255 tegra20_pmc_clk_init(); 1256 tegra20_fixed_clk_init(); 1257 tegra20_pll_init(); 1258 tegra20_super_clk_init(); 1259 tegra20_periph_clk_init(); 1260 tegra20_audio_clk_init(); 1261 1262 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1263 1264 tegra_add_of_provider(np); 1265 1266 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1267 1268 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1269} 1270CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init); 1271