| cb6448ab0a9ac5f1d1c72a0f573dd9677d8e5418 |
|
19-Dec-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Add missing Tegra20 fuse clks
Add clocks required for accessing fuses on Tegra20.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
|
| a85f06badc3cff4069f2f5112cea63cd39d99920 |
|
07-Nov-2013 |
Stephen Warren <swarren@nvidia.com> |
clk: tegra: remove bogus PCIE_XCLK
The "pcie_xclk" clock is not actually a clock at all, but rather a reset
domain. Now that the custom Tegra module reset API has been removed, we
can remove the definition of any "clocks" that existed solely to support
it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| 6d5b988e7dc56bb97c39bdcbc006fadcd6ca371b |
|
06-Nov-2013 |
Stephen Warren <swarren@nvidia.com> |
clk: tegra: implement a reset driver
The Tegra CAR module implements both a clock and reset controller. So
far, the driver exposes the clock feature via the common clock API and
the reset feature using a custom API. This patch adds an implementation
of the common reset framework API (include/linux/reset*.h). The legacy
reset implementation will be removed once all drivers have been
converted.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| 5ab5d4048e6ed8811245a4ea45264456c180545e |
|
21-Nov-2013 |
Alexandre Courbot <acourbot@nvidia.com> |
clk: tegra: add FUSE clock device
This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
|
| 540fc26a02a950a523a62a16d75b87f0e2103584 |
|
07-Oct-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: move tegra20 to common infra
Move tegra20 to common tegra clock infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| 76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8 |
|
04-Sep-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: move periph clocks to common file
Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| ebe142b2ad35d5656caae35d5deefdbebe847d3b |
|
04-Oct-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: move fields to tegra_clk_pll_params
Move some fields related to the PLL HW description to the tegra_clk_pll_params.
This allows some PLL code to be moved to common files later.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| 343a607cb79259429afbb9820bf524d33084e66c |
|
02-Sep-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: common periph_clk_enb_refcnt and clks
This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| d5ff89a82a6d272d210db68a9487877682c94a24 |
|
22-Aug-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: simplify periph clock data
This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| 819c1de344c5b8350bffd35be9a0fa74541292d3 |
|
29-Jul-2013 |
James Hogan <james.hogan@imgtec.com> |
clk: add CLK_SET_RATE_NO_REPARENT flag
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.
To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Chew <achew@nvidia.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
|
| a0be7a9e6a63d8b2bd8657f34775d3d369a45624 |
|
08-Aug-2013 |
Sachin Kamat <sachin.kamat@linaro.org> |
clk: tegra20: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
|
| 061cec925f212f145516e826f39962624a738ded |
|
27-May-2013 |
Prashant Gaikwad <pgaikwad@nvidia.com> |
clk: tegra: Use common of_clk_init function
Use common of_clk_init() function for clocks initialization.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
|
| 6ec3240047ee6a4b34f90d45e19ed179bc9b4a2e |
|
06-May-2013 |
Lucas Stach <dev@lynxeye.de> |
clk: tegra: add ac97 controller clock
AC97 controller clock is hardwired to pll_a_out0.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| 7e94984495dbce182260fa3dd15687439236b0a1 |
|
06-May-2013 |
Lucas Stach <dev@lynxeye.de> |
clk: tegra: remove USB from clk init table
The USB clocks are just clock gates, so no need to set a specific clock.
In fact trying to set a specific clock is just a NOP if the requested
clockrate is the same as those of the parent (clk_m) or will trigger a
WARN_ON() if rates don't match up.
As we are not setting a specific rate, nor activating the clocks at
init, there is no point in keeping the the usb entries in the clock init
table.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| a26a029893096204f08a3ff5e262f99e1a75e273 |
|
03-Apr-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Add flags to tegra_clk_periph()
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 3e72771e210348fbd7ff0ea1b9e14cd88380c05b |
|
03-Apr-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: move from a lock bit idx to a lock mask
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f |
|
03-Apr-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Add PLL post divider table
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| dba4072a4a20b2986562cced98ce04a887614528 |
|
03-Apr-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Refactor PLL programming code
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 441f199a37cfd66c5dd8dd45490bd3ea6971117d |
|
25-Mar-2013 |
Stephen Warren <swarren@nvidia.com> |
clk: tegra: defer application of init table
The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.
The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.
To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 82ce742140f32394cc5be75f1c98cdbbff284582 |
|
04-Apr-2013 |
Prashant Gaikwad <pgaikwad@nvidia.com> |
clk: tegra: Fix cdev1 and cdev2 IDs
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| ce910686f814fe220f4e55ecca5cfdea7082b3de |
|
02-Apr-2013 |
Thierry Reding <thierry.reding@avionic-design.de> |
clk: tegra: Make gr2d and gr3d clocks children of pll_c
By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.
gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 0f1bc12e9eddaba2baf52d020d37670dbabe3702 |
|
14-Mar-2013 |
Thierry Reding <thierry.reding@avionic-design.de> |
clk: tegra: Allow PLLE training to succeed
Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
|
| bf161d2163f7b8bf4823829dbc1a14111760187e |
|
08-Feb-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: No 7.1 super clk dividers on Tegra20
Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk.
Remove the clocks related to the divider.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 984b839337da1eb7b4a4fb50e24cf28c2b473862 |
|
01-Mar-2013 |
Prashant Gaikwad <pgaikwad@nvidia.com> |
clk: Tegra: Remove duplicate smp_twd clock
Remove duplicate smp_twd clocks as these clocks are accessed using
DT now.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| 527fad1bc519df8eedd397482febb51526e5d987 |
|
12-Feb-2013 |
Laxman Dewangan <ldewangan@nvidia.com> |
clk: tegra: initialise parent of uart clocks
Initialise the parent of UARTs to PLLP and disabling clock by
default.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 0203d91247090e57063e1ef63a6019e87548dfbc |
|
12-Feb-2013 |
Stephen Warren <swarren@nvidia.com> |
clk: tegra: fix driver to match DT binding
enum tegra*_clk is intended to match the IDs listed in the Tegra clock
bindings. There are a few mismatches, which this patch fixes:
1) pll_s and cop were left out of the Tegra20 enum.
2) spdif_in and spdif_out were swapped relative to the Tegra30 binding.
3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added
to the Tegra30 enum.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
|
| d076a206b2dfa8ef7a735289fe1221e77d1fa83f |
|
07-Feb-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Add missing spinlock for hclk and pclk
The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 4a2e32794e71db679b91df1d9c98921b2e32ec4e |
|
15-Jan-2013 |
Joseph Lo <josephl@nvidia.com> |
clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops
Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| e5dd26302275562d8bedf885e7aa91bd73bfa041 |
|
11-Jan-2013 |
Prashant Gaikwad <pgaikwad@nvidia.com> |
clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s
With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| 37c26a906527b8a6a252614ca83d21ad318c4e84 |
|
11-Jan-2013 |
Prashant Gaikwad <pgaikwad@nvidia.com> |
clk: tegra: add clock support for Tegra20
Add Tegra20 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe,
implemented KBC clock, ensure all OF lookups return valid cookies i.e.
an explicit error pointer or valid pointer not NULL, adapt to renames
in earlier patches, fixed some checkpatch issues.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|