clk-tegra20.c revision a0be7a9e6a63d8b2bd8657f34775d3d369a45624
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/clk/tegra.h> 24#include <linux/delay.h> 25 26#include "clk.h" 27 28#define RST_DEVICES_L 0x004 29#define RST_DEVICES_H 0x008 30#define RST_DEVICES_U 0x00c 31#define RST_DEVICES_SET_L 0x300 32#define RST_DEVICES_CLR_L 0x304 33#define RST_DEVICES_SET_H 0x308 34#define RST_DEVICES_CLR_H 0x30c 35#define RST_DEVICES_SET_U 0x310 36#define RST_DEVICES_CLR_U 0x314 37#define RST_DEVICES_NUM 3 38 39#define CLK_OUT_ENB_L 0x010 40#define CLK_OUT_ENB_H 0x014 41#define CLK_OUT_ENB_U 0x018 42#define CLK_OUT_ENB_SET_L 0x320 43#define CLK_OUT_ENB_CLR_L 0x324 44#define CLK_OUT_ENB_SET_H 0x328 45#define CLK_OUT_ENB_CLR_H 0x32c 46#define CLK_OUT_ENB_SET_U 0x330 47#define CLK_OUT_ENB_CLR_U 0x334 48#define CLK_OUT_ENB_NUM 3 49 50#define OSC_CTRL 0x50 51#define OSC_CTRL_OSC_FREQ_MASK (3<<30) 52#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) 53#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) 54#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) 55#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) 56#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 57 58#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) 59#define OSC_CTRL_PLL_REF_DIV_1 (0<<28) 60#define OSC_CTRL_PLL_REF_DIV_2 (1<<28) 61#define OSC_CTRL_PLL_REF_DIV_4 (2<<28) 62 63#define OSC_FREQ_DET 0x58 64#define OSC_FREQ_DET_TRIG (1<<31) 65 66#define OSC_FREQ_DET_STATUS 0x5c 67#define OSC_FREQ_DET_BUSY (1<<31) 68#define OSC_FREQ_DET_CNT_MASK 0xFFFF 69 70#define PLLS_BASE 0xf0 71#define PLLS_MISC 0xf4 72#define PLLC_BASE 0x80 73#define PLLC_MISC 0x8c 74#define PLLM_BASE 0x90 75#define PLLM_MISC 0x9c 76#define PLLP_BASE 0xa0 77#define PLLP_MISC 0xac 78#define PLLA_BASE 0xb0 79#define PLLA_MISC 0xbc 80#define PLLU_BASE 0xc0 81#define PLLU_MISC 0xcc 82#define PLLD_BASE 0xd0 83#define PLLD_MISC 0xdc 84#define PLLX_BASE 0xe0 85#define PLLX_MISC 0xe4 86#define PLLE_BASE 0xe8 87#define PLLE_MISC 0xec 88 89#define PLL_BASE_LOCK BIT(27) 90#define PLLE_MISC_LOCK BIT(11) 91 92#define PLL_MISC_LOCK_ENABLE 18 93#define PLLDU_MISC_LOCK_ENABLE 22 94#define PLLE_MISC_LOCK_ENABLE 9 95 96#define PLLC_OUT 0x84 97#define PLLM_OUT 0x94 98#define PLLP_OUTA 0xa4 99#define PLLP_OUTB 0xa8 100#define PLLA_OUT 0xb4 101 102#define CCLK_BURST_POLICY 0x20 103#define SUPER_CCLK_DIVIDER 0x24 104#define SCLK_BURST_POLICY 0x28 105#define SUPER_SCLK_DIVIDER 0x2c 106#define CLK_SYSTEM_RATE 0x30 107 108#define CCLK_BURST_POLICY_SHIFT 28 109#define CCLK_RUN_POLICY_SHIFT 4 110#define CCLK_IDLE_POLICY_SHIFT 0 111#define CCLK_IDLE_POLICY 1 112#define CCLK_RUN_POLICY 2 113#define CCLK_BURST_POLICY_PLLX 8 114 115#define CLK_SOURCE_I2S1 0x100 116#define CLK_SOURCE_I2S2 0x104 117#define CLK_SOURCE_SPDIF_OUT 0x108 118#define CLK_SOURCE_SPDIF_IN 0x10c 119#define CLK_SOURCE_PWM 0x110 120#define CLK_SOURCE_SPI 0x114 121#define CLK_SOURCE_SBC1 0x134 122#define CLK_SOURCE_SBC2 0x118 123#define CLK_SOURCE_SBC3 0x11c 124#define CLK_SOURCE_SBC4 0x1b4 125#define CLK_SOURCE_XIO 0x120 126#define CLK_SOURCE_TWC 0x12c 127#define CLK_SOURCE_IDE 0x144 128#define CLK_SOURCE_NDFLASH 0x160 129#define CLK_SOURCE_VFIR 0x168 130#define CLK_SOURCE_SDMMC1 0x150 131#define CLK_SOURCE_SDMMC2 0x154 132#define CLK_SOURCE_SDMMC3 0x1bc 133#define CLK_SOURCE_SDMMC4 0x164 134#define CLK_SOURCE_CVE 0x140 135#define CLK_SOURCE_TVO 0x188 136#define CLK_SOURCE_TVDAC 0x194 137#define CLK_SOURCE_HDMI 0x18c 138#define CLK_SOURCE_DISP1 0x138 139#define CLK_SOURCE_DISP2 0x13c 140#define CLK_SOURCE_CSITE 0x1d4 141#define CLK_SOURCE_LA 0x1f8 142#define CLK_SOURCE_OWR 0x1cc 143#define CLK_SOURCE_NOR 0x1d0 144#define CLK_SOURCE_MIPI 0x174 145#define CLK_SOURCE_I2C1 0x124 146#define CLK_SOURCE_I2C2 0x198 147#define CLK_SOURCE_I2C3 0x1b8 148#define CLK_SOURCE_DVC 0x128 149#define CLK_SOURCE_UARTA 0x178 150#define CLK_SOURCE_UARTB 0x17c 151#define CLK_SOURCE_UARTC 0x1a0 152#define CLK_SOURCE_UARTD 0x1c0 153#define CLK_SOURCE_UARTE 0x1c4 154#define CLK_SOURCE_3D 0x158 155#define CLK_SOURCE_2D 0x15c 156#define CLK_SOURCE_MPE 0x170 157#define CLK_SOURCE_EPP 0x16c 158#define CLK_SOURCE_HOST1X 0x180 159#define CLK_SOURCE_VDE 0x1c8 160#define CLK_SOURCE_VI 0x148 161#define CLK_SOURCE_VI_SENSOR 0x1a8 162#define CLK_SOURCE_EMC 0x19c 163 164#define AUDIO_SYNC_CLK 0x38 165 166#define PMC_CTRL 0x0 167#define PMC_CTRL_BLINK_ENB 7 168#define PMC_DPD_PADS_ORIDE 0x1c 169#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 170#define PMC_BLINK_TIMER 0x40 171 172/* Tegra CPU clock and reset control regs */ 173#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 174#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 175#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 176 177#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 178#define CPU_RESET(cpu) (0x1111ul << (cpu)) 179 180#ifdef CONFIG_PM_SLEEP 181static struct cpu_clk_suspend_context { 182 u32 pllx_misc; 183 u32 pllx_base; 184 185 u32 cpu_burst; 186 u32 clk_csite_src; 187 u32 cclk_divider; 188} tegra20_cpu_clk_sctx; 189#endif 190 191static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 192 193static void __iomem *clk_base; 194static void __iomem *pmc_base; 195 196static DEFINE_SPINLOCK(pll_div_lock); 197static DEFINE_SPINLOCK(sysrate_lock); 198 199#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 200 _clk_num, _regs, _gate_flags, _clk_id) \ 201 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 202 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 203 _regs, _clk_num, periph_clk_enb_refcnt, \ 204 _gate_flags, _clk_id) 205 206#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 207 _clk_num, _regs, _gate_flags, _clk_id) \ 208 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 209 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 210 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 211 _clk_id) 212 213#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 214 _clk_num, _regs, _gate_flags, _clk_id) \ 215 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 216 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \ 217 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 218 _clk_id) 219 220#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 221 _mux_shift, _mux_width, _clk_num, _regs, \ 222 _gate_flags, _clk_id) \ 223 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 224 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 225 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 226 _clk_id) 227 228/* IDs assigned here must be in sync with DT bindings definition 229 * for Tegra20 clocks . 230 */ 231enum tegra20_clk { 232 cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, 233 ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp, 234 gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma, 235 kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3, 236 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 237 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 238 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb, 239 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1, 240 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve, 241 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0, 242 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1, 243 pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u, 244 pll_x, cop, audio, pll_ref, twd, clk_max, 245}; 246 247static struct clk *clks[clk_max]; 248static struct clk_onecell_data clk_data; 249 250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 251 { 12000000, 600000000, 600, 12, 0, 8 }, 252 { 13000000, 600000000, 600, 13, 0, 8 }, 253 { 19200000, 600000000, 500, 16, 0, 6 }, 254 { 26000000, 600000000, 600, 26, 0, 8 }, 255 { 0, 0, 0, 0, 0, 0 }, 256}; 257 258static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 259 { 12000000, 666000000, 666, 12, 0, 8}, 260 { 13000000, 666000000, 666, 13, 0, 8}, 261 { 19200000, 666000000, 555, 16, 0, 8}, 262 { 26000000, 666000000, 666, 26, 0, 8}, 263 { 12000000, 600000000, 600, 12, 0, 8}, 264 { 13000000, 600000000, 600, 13, 0, 8}, 265 { 19200000, 600000000, 375, 12, 0, 6}, 266 { 26000000, 600000000, 600, 26, 0, 8}, 267 { 0, 0, 0, 0, 0, 0 }, 268}; 269 270static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 271 { 12000000, 216000000, 432, 12, 1, 8}, 272 { 13000000, 216000000, 432, 13, 1, 8}, 273 { 19200000, 216000000, 90, 4, 1, 1}, 274 { 26000000, 216000000, 432, 26, 1, 8}, 275 { 12000000, 432000000, 432, 12, 0, 8}, 276 { 13000000, 432000000, 432, 13, 0, 8}, 277 { 19200000, 432000000, 90, 4, 0, 1}, 278 { 26000000, 432000000, 432, 26, 0, 8}, 279 { 0, 0, 0, 0, 0, 0 }, 280}; 281 282static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 283 { 28800000, 56448000, 49, 25, 0, 1}, 284 { 28800000, 73728000, 64, 25, 0, 1}, 285 { 28800000, 24000000, 5, 6, 0, 1}, 286 { 0, 0, 0, 0, 0, 0 }, 287}; 288 289static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 290 { 12000000, 216000000, 216, 12, 0, 4}, 291 { 13000000, 216000000, 216, 13, 0, 4}, 292 { 19200000, 216000000, 135, 12, 0, 3}, 293 { 26000000, 216000000, 216, 26, 0, 4}, 294 295 { 12000000, 594000000, 594, 12, 0, 8}, 296 { 13000000, 594000000, 594, 13, 0, 8}, 297 { 19200000, 594000000, 495, 16, 0, 8}, 298 { 26000000, 594000000, 594, 26, 0, 8}, 299 300 { 12000000, 1000000000, 1000, 12, 0, 12}, 301 { 13000000, 1000000000, 1000, 13, 0, 12}, 302 { 19200000, 1000000000, 625, 12, 0, 8}, 303 { 26000000, 1000000000, 1000, 26, 0, 12}, 304 305 { 0, 0, 0, 0, 0, 0 }, 306}; 307 308static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 309 { 12000000, 480000000, 960, 12, 0, 0}, 310 { 13000000, 480000000, 960, 13, 0, 0}, 311 { 19200000, 480000000, 200, 4, 0, 0}, 312 { 26000000, 480000000, 960, 26, 0, 0}, 313 { 0, 0, 0, 0, 0, 0 }, 314}; 315 316static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 317 /* 1 GHz */ 318 { 12000000, 1000000000, 1000, 12, 0, 12}, 319 { 13000000, 1000000000, 1000, 13, 0, 12}, 320 { 19200000, 1000000000, 625, 12, 0, 8}, 321 { 26000000, 1000000000, 1000, 26, 0, 12}, 322 323 /* 912 MHz */ 324 { 12000000, 912000000, 912, 12, 0, 12}, 325 { 13000000, 912000000, 912, 13, 0, 12}, 326 { 19200000, 912000000, 760, 16, 0, 8}, 327 { 26000000, 912000000, 912, 26, 0, 12}, 328 329 /* 816 MHz */ 330 { 12000000, 816000000, 816, 12, 0, 12}, 331 { 13000000, 816000000, 816, 13, 0, 12}, 332 { 19200000, 816000000, 680, 16, 0, 8}, 333 { 26000000, 816000000, 816, 26, 0, 12}, 334 335 /* 760 MHz */ 336 { 12000000, 760000000, 760, 12, 0, 12}, 337 { 13000000, 760000000, 760, 13, 0, 12}, 338 { 19200000, 760000000, 950, 24, 0, 8}, 339 { 26000000, 760000000, 760, 26, 0, 12}, 340 341 /* 750 MHz */ 342 { 12000000, 750000000, 750, 12, 0, 12}, 343 { 13000000, 750000000, 750, 13, 0, 12}, 344 { 19200000, 750000000, 625, 16, 0, 8}, 345 { 26000000, 750000000, 750, 26, 0, 12}, 346 347 /* 608 MHz */ 348 { 12000000, 608000000, 608, 12, 0, 12}, 349 { 13000000, 608000000, 608, 13, 0, 12}, 350 { 19200000, 608000000, 380, 12, 0, 8}, 351 { 26000000, 608000000, 608, 26, 0, 12}, 352 353 /* 456 MHz */ 354 { 12000000, 456000000, 456, 12, 0, 12}, 355 { 13000000, 456000000, 456, 13, 0, 12}, 356 { 19200000, 456000000, 380, 16, 0, 8}, 357 { 26000000, 456000000, 456, 26, 0, 12}, 358 359 /* 312 MHz */ 360 { 12000000, 312000000, 312, 12, 0, 12}, 361 { 13000000, 312000000, 312, 13, 0, 12}, 362 { 19200000, 312000000, 260, 16, 0, 8}, 363 { 26000000, 312000000, 312, 26, 0, 12}, 364 365 { 0, 0, 0, 0, 0, 0 }, 366}; 367 368static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 369 { 12000000, 100000000, 200, 24, 0, 0 }, 370 { 0, 0, 0, 0, 0, 0 }, 371}; 372 373/* PLL parameters */ 374static struct tegra_clk_pll_params pll_c_params = { 375 .input_min = 2000000, 376 .input_max = 31000000, 377 .cf_min = 1000000, 378 .cf_max = 6000000, 379 .vco_min = 20000000, 380 .vco_max = 1400000000, 381 .base_reg = PLLC_BASE, 382 .misc_reg = PLLC_MISC, 383 .lock_mask = PLL_BASE_LOCK, 384 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 385 .lock_delay = 300, 386}; 387 388static struct tegra_clk_pll_params pll_m_params = { 389 .input_min = 2000000, 390 .input_max = 31000000, 391 .cf_min = 1000000, 392 .cf_max = 6000000, 393 .vco_min = 20000000, 394 .vco_max = 1200000000, 395 .base_reg = PLLM_BASE, 396 .misc_reg = PLLM_MISC, 397 .lock_mask = PLL_BASE_LOCK, 398 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 399 .lock_delay = 300, 400}; 401 402static struct tegra_clk_pll_params pll_p_params = { 403 .input_min = 2000000, 404 .input_max = 31000000, 405 .cf_min = 1000000, 406 .cf_max = 6000000, 407 .vco_min = 20000000, 408 .vco_max = 1400000000, 409 .base_reg = PLLP_BASE, 410 .misc_reg = PLLP_MISC, 411 .lock_mask = PLL_BASE_LOCK, 412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 413 .lock_delay = 300, 414}; 415 416static struct tegra_clk_pll_params pll_a_params = { 417 .input_min = 2000000, 418 .input_max = 31000000, 419 .cf_min = 1000000, 420 .cf_max = 6000000, 421 .vco_min = 20000000, 422 .vco_max = 1400000000, 423 .base_reg = PLLA_BASE, 424 .misc_reg = PLLA_MISC, 425 .lock_mask = PLL_BASE_LOCK, 426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 427 .lock_delay = 300, 428}; 429 430static struct tegra_clk_pll_params pll_d_params = { 431 .input_min = 2000000, 432 .input_max = 40000000, 433 .cf_min = 1000000, 434 .cf_max = 6000000, 435 .vco_min = 40000000, 436 .vco_max = 1000000000, 437 .base_reg = PLLD_BASE, 438 .misc_reg = PLLD_MISC, 439 .lock_mask = PLL_BASE_LOCK, 440 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 441 .lock_delay = 1000, 442}; 443 444static struct pdiv_map pllu_p[] = { 445 { .pdiv = 1, .hw_val = 1 }, 446 { .pdiv = 2, .hw_val = 0 }, 447 { .pdiv = 0, .hw_val = 0 }, 448}; 449 450static struct tegra_clk_pll_params pll_u_params = { 451 .input_min = 2000000, 452 .input_max = 40000000, 453 .cf_min = 1000000, 454 .cf_max = 6000000, 455 .vco_min = 48000000, 456 .vco_max = 960000000, 457 .base_reg = PLLU_BASE, 458 .misc_reg = PLLU_MISC, 459 .lock_mask = PLL_BASE_LOCK, 460 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 461 .lock_delay = 1000, 462 .pdiv_tohw = pllu_p, 463}; 464 465static struct tegra_clk_pll_params pll_x_params = { 466 .input_min = 2000000, 467 .input_max = 31000000, 468 .cf_min = 1000000, 469 .cf_max = 6000000, 470 .vco_min = 20000000, 471 .vco_max = 1200000000, 472 .base_reg = PLLX_BASE, 473 .misc_reg = PLLX_MISC, 474 .lock_mask = PLL_BASE_LOCK, 475 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 476 .lock_delay = 300, 477}; 478 479static struct tegra_clk_pll_params pll_e_params = { 480 .input_min = 12000000, 481 .input_max = 12000000, 482 .cf_min = 0, 483 .cf_max = 0, 484 .vco_min = 0, 485 .vco_max = 0, 486 .base_reg = PLLE_BASE, 487 .misc_reg = PLLE_MISC, 488 .lock_mask = PLLE_MISC_LOCK, 489 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 490 .lock_delay = 0, 491}; 492 493/* Peripheral clock registers */ 494static struct tegra_clk_periph_regs periph_l_regs = { 495 .enb_reg = CLK_OUT_ENB_L, 496 .enb_set_reg = CLK_OUT_ENB_SET_L, 497 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 498 .rst_reg = RST_DEVICES_L, 499 .rst_set_reg = RST_DEVICES_SET_L, 500 .rst_clr_reg = RST_DEVICES_CLR_L, 501}; 502 503static struct tegra_clk_periph_regs periph_h_regs = { 504 .enb_reg = CLK_OUT_ENB_H, 505 .enb_set_reg = CLK_OUT_ENB_SET_H, 506 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 507 .rst_reg = RST_DEVICES_H, 508 .rst_set_reg = RST_DEVICES_SET_H, 509 .rst_clr_reg = RST_DEVICES_CLR_H, 510}; 511 512static struct tegra_clk_periph_regs periph_u_regs = { 513 .enb_reg = CLK_OUT_ENB_U, 514 .enb_set_reg = CLK_OUT_ENB_SET_U, 515 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 516 .rst_reg = RST_DEVICES_U, 517 .rst_set_reg = RST_DEVICES_SET_U, 518 .rst_clr_reg = RST_DEVICES_CLR_U, 519}; 520 521static unsigned long tegra20_clk_measure_input_freq(void) 522{ 523 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 524 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 525 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 526 unsigned long input_freq; 527 528 switch (auto_clk_control) { 529 case OSC_CTRL_OSC_FREQ_12MHZ: 530 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 531 input_freq = 12000000; 532 break; 533 case OSC_CTRL_OSC_FREQ_13MHZ: 534 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 535 input_freq = 13000000; 536 break; 537 case OSC_CTRL_OSC_FREQ_19_2MHZ: 538 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 539 input_freq = 19200000; 540 break; 541 case OSC_CTRL_OSC_FREQ_26MHZ: 542 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 543 input_freq = 26000000; 544 break; 545 default: 546 pr_err("Unexpected clock autodetect value %d", 547 auto_clk_control); 548 BUG(); 549 return 0; 550 } 551 552 return input_freq; 553} 554 555static unsigned int tegra20_get_pll_ref_div(void) 556{ 557 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 558 OSC_CTRL_PLL_REF_DIV_MASK; 559 560 switch (pll_ref_div) { 561 case OSC_CTRL_PLL_REF_DIV_1: 562 return 1; 563 case OSC_CTRL_PLL_REF_DIV_2: 564 return 2; 565 case OSC_CTRL_PLL_REF_DIV_4: 566 return 4; 567 default: 568 pr_err("Invalied pll ref divider %d\n", pll_ref_div); 569 BUG(); 570 } 571 return 0; 572} 573 574static void tegra20_pll_init(void) 575{ 576 struct clk *clk; 577 578 /* PLLC */ 579 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 580 0, &pll_c_params, TEGRA_PLL_HAS_CPCON, 581 pll_c_freq_table, NULL); 582 clk_register_clkdev(clk, "pll_c", NULL); 583 clks[pll_c] = clk; 584 585 /* PLLC_OUT1 */ 586 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 587 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 588 8, 8, 1, NULL); 589 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 590 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 591 0, NULL); 592 clk_register_clkdev(clk, "pll_c_out1", NULL); 593 clks[pll_c_out1] = clk; 594 595 /* PLLP */ 596 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0, 597 216000000, &pll_p_params, TEGRA_PLL_FIXED | 598 TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL); 599 clk_register_clkdev(clk, "pll_p", NULL); 600 clks[pll_p] = clk; 601 602 /* PLLP_OUT1 */ 603 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 604 clk_base + PLLP_OUTA, 0, 605 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 606 8, 8, 1, &pll_div_lock); 607 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 608 clk_base + PLLP_OUTA, 1, 0, 609 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 610 &pll_div_lock); 611 clk_register_clkdev(clk, "pll_p_out1", NULL); 612 clks[pll_p_out1] = clk; 613 614 /* PLLP_OUT2 */ 615 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 616 clk_base + PLLP_OUTA, 0, 617 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 618 24, 8, 1, &pll_div_lock); 619 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 620 clk_base + PLLP_OUTA, 17, 16, 621 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 622 &pll_div_lock); 623 clk_register_clkdev(clk, "pll_p_out2", NULL); 624 clks[pll_p_out2] = clk; 625 626 /* PLLP_OUT3 */ 627 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 628 clk_base + PLLP_OUTB, 0, 629 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 630 8, 8, 1, &pll_div_lock); 631 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 632 clk_base + PLLP_OUTB, 1, 0, 633 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 634 &pll_div_lock); 635 clk_register_clkdev(clk, "pll_p_out3", NULL); 636 clks[pll_p_out3] = clk; 637 638 /* PLLP_OUT4 */ 639 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 640 clk_base + PLLP_OUTB, 0, 641 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 642 24, 8, 1, &pll_div_lock); 643 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 644 clk_base + PLLP_OUTB, 17, 16, 645 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 646 &pll_div_lock); 647 clk_register_clkdev(clk, "pll_p_out4", NULL); 648 clks[pll_p_out4] = clk; 649 650 /* PLLM */ 651 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 652 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 653 &pll_m_params, TEGRA_PLL_HAS_CPCON, 654 pll_m_freq_table, NULL); 655 clk_register_clkdev(clk, "pll_m", NULL); 656 clks[pll_m] = clk; 657 658 /* PLLM_OUT1 */ 659 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 660 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 661 8, 8, 1, NULL); 662 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 663 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 664 CLK_SET_RATE_PARENT, 0, NULL); 665 clk_register_clkdev(clk, "pll_m_out1", NULL); 666 clks[pll_m_out1] = clk; 667 668 /* PLLX */ 669 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 670 0, &pll_x_params, TEGRA_PLL_HAS_CPCON, 671 pll_x_freq_table, NULL); 672 clk_register_clkdev(clk, "pll_x", NULL); 673 clks[pll_x] = clk; 674 675 /* PLLU */ 676 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 677 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, 678 pll_u_freq_table, NULL); 679 clk_register_clkdev(clk, "pll_u", NULL); 680 clks[pll_u] = clk; 681 682 /* PLLD */ 683 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 684 0, &pll_d_params, TEGRA_PLL_HAS_CPCON, 685 pll_d_freq_table, NULL); 686 clk_register_clkdev(clk, "pll_d", NULL); 687 clks[pll_d] = clk; 688 689 /* PLLD_OUT0 */ 690 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 691 CLK_SET_RATE_PARENT, 1, 2); 692 clk_register_clkdev(clk, "pll_d_out0", NULL); 693 clks[pll_d_out0] = clk; 694 695 /* PLLA */ 696 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 697 0, &pll_a_params, TEGRA_PLL_HAS_CPCON, 698 pll_a_freq_table, NULL); 699 clk_register_clkdev(clk, "pll_a", NULL); 700 clks[pll_a] = clk; 701 702 /* PLLA_OUT0 */ 703 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 704 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 705 8, 8, 1, NULL); 706 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 707 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 708 CLK_SET_RATE_PARENT, 0, NULL); 709 clk_register_clkdev(clk, "pll_a_out0", NULL); 710 clks[pll_a_out0] = clk; 711 712 /* PLLE */ 713 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 714 0, 100000000, &pll_e_params, 715 0, pll_e_freq_table, NULL); 716 clk_register_clkdev(clk, "pll_e", NULL); 717 clks[pll_e] = clk; 718} 719 720static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 721 "pll_p", "pll_p_out4", 722 "pll_p_out3", "clk_d", "pll_x" }; 723static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 724 "pll_p_out3", "pll_p_out2", "clk_d", 725 "clk_32k", "pll_m_out1" }; 726 727static void tegra20_super_clk_init(void) 728{ 729 struct clk *clk; 730 731 /* CCLK */ 732 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 733 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 734 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 735 clk_register_clkdev(clk, "cclk", NULL); 736 clks[cclk] = clk; 737 738 /* SCLK */ 739 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 740 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, 741 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 742 clk_register_clkdev(clk, "sclk", NULL); 743 clks[sclk] = clk; 744 745 /* HCLK */ 746 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 747 clk_base + CLK_SYSTEM_RATE, 4, 2, 0, 748 &sysrate_lock); 749 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, 750 clk_base + CLK_SYSTEM_RATE, 7, 751 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 752 clk_register_clkdev(clk, "hclk", NULL); 753 clks[hclk] = clk; 754 755 /* PCLK */ 756 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 757 clk_base + CLK_SYSTEM_RATE, 0, 2, 0, 758 &sysrate_lock); 759 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, 760 clk_base + CLK_SYSTEM_RATE, 3, 761 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 762 clk_register_clkdev(clk, "pclk", NULL); 763 clks[pclk] = clk; 764 765 /* twd */ 766 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 767 clk_register_clkdev(clk, "twd", NULL); 768 clks[twd] = clk; 769} 770 771static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", 772 "pll_a_out0", "unused", "unused", 773 "unused"}; 774 775static void __init tegra20_audio_clk_init(void) 776{ 777 struct clk *clk; 778 779 /* audio */ 780 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 781 ARRAY_SIZE(audio_parents), 0, 782 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 783 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 784 clk_base + AUDIO_SYNC_CLK, 4, 785 CLK_GATE_SET_TO_DISABLE, NULL); 786 clk_register_clkdev(clk, "audio", NULL); 787 clks[audio] = clk; 788 789 /* audio_2x */ 790 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 791 CLK_SET_RATE_PARENT, 2, 1); 792 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 793 TEGRA_PERIPH_NO_RESET, clk_base, 794 CLK_SET_RATE_PARENT, 89, &periph_u_regs, 795 periph_clk_enb_refcnt); 796 clk_register_clkdev(clk, "audio_2x", NULL); 797 clks[audio_2x] = clk; 798 799} 800 801static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 802 "clk_m"}; 803static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 804 "clk_m"}; 805static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 806 "clk_m"}; 807static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"}; 808static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", 809 "clk_32k"}; 810static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; 811static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"}; 812static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", 813 "clk_m"}; 814static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 815 816static struct tegra_periph_init_data tegra_periph_clk_list[] = { 817 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 818 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 819 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 820 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 821 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 822 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 823 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 824 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 825 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, &periph_h_regs, TEGRA_PERIPH_ON_APB, spi), 826 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, &periph_h_regs, 0, xio), 827 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, &periph_l_regs, TEGRA_PERIPH_ON_APB, twc), 828 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, &periph_l_regs, 0, ide), 829 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, 0, ndflash), 830 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 831 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, 0, csite), 832 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, 0, la), 833 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 834 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 835 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 836 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 837 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 838 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe), 839 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 840 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d), 841 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d), 842 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 843 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 844 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 845 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 846 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 847 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve), 848 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo), 849 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac), 850 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 851 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1), 852 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2), 853 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3), 854 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, dvc), 855 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 856 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm), 857}; 858 859static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 860 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, &periph_l_regs, TEGRA_PERIPH_ON_APB, uarta), 861 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, uartb), 862 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, &periph_h_regs, TEGRA_PERIPH_ON_APB, uartc), 863 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, &periph_u_regs, TEGRA_PERIPH_ON_APB, uartd), 864 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, &periph_u_regs, TEGRA_PERIPH_ON_APB, uarte), 865 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, &periph_l_regs, 0, disp1), 866 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, &periph_l_regs, 0, disp2), 867}; 868 869static void __init tegra20_periph_clk_init(void) 870{ 871 struct tegra_periph_init_data *data; 872 struct clk *clk; 873 int i; 874 875 /* ac97 */ 876 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 877 TEGRA_PERIPH_ON_APB, 878 clk_base, 0, 3, &periph_l_regs, 879 periph_clk_enb_refcnt); 880 clk_register_clkdev(clk, NULL, "tegra20-ac97"); 881 clks[ac97] = clk; 882 883 /* apbdma */ 884 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 885 0, 34, &periph_h_regs, 886 periph_clk_enb_refcnt); 887 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 888 clks[apbdma] = clk; 889 890 /* rtc */ 891 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 892 TEGRA_PERIPH_NO_RESET, 893 clk_base, 0, 4, &periph_l_regs, 894 periph_clk_enb_refcnt); 895 clk_register_clkdev(clk, NULL, "rtc-tegra"); 896 clks[rtc] = clk; 897 898 /* timer */ 899 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 900 0, 5, &periph_l_regs, 901 periph_clk_enb_refcnt); 902 clk_register_clkdev(clk, NULL, "timer"); 903 clks[timer] = clk; 904 905 /* kbc */ 906 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 907 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 908 clk_base, 0, 36, &periph_h_regs, 909 periph_clk_enb_refcnt); 910 clk_register_clkdev(clk, NULL, "tegra-kbc"); 911 clks[kbc] = clk; 912 913 /* csus */ 914 clk = tegra_clk_register_periph_gate("csus", "clk_m", 915 TEGRA_PERIPH_NO_RESET, 916 clk_base, 0, 92, &periph_u_regs, 917 periph_clk_enb_refcnt); 918 clk_register_clkdev(clk, "csus", "tengra_camera"); 919 clks[csus] = clk; 920 921 /* vcp */ 922 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, 923 clk_base, 0, 29, &periph_l_regs, 924 periph_clk_enb_refcnt); 925 clk_register_clkdev(clk, "vcp", "tegra-avp"); 926 clks[vcp] = clk; 927 928 /* bsea */ 929 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, 930 clk_base, 0, 62, &periph_h_regs, 931 periph_clk_enb_refcnt); 932 clk_register_clkdev(clk, "bsea", "tegra-avp"); 933 clks[bsea] = clk; 934 935 /* bsev */ 936 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, 937 clk_base, 0, 63, &periph_h_regs, 938 periph_clk_enb_refcnt); 939 clk_register_clkdev(clk, "bsev", "tegra-aes"); 940 clks[bsev] = clk; 941 942 /* emc */ 943 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 944 ARRAY_SIZE(mux_pllmcp_clkm), 0, 945 clk_base + CLK_SOURCE_EMC, 946 30, 2, 0, NULL); 947 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 948 57, &periph_h_regs, periph_clk_enb_refcnt); 949 clk_register_clkdev(clk, "emc", NULL); 950 clks[emc] = clk; 951 952 /* usbd */ 953 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 954 22, &periph_l_regs, periph_clk_enb_refcnt); 955 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 956 clks[usbd] = clk; 957 958 /* usb2 */ 959 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 960 58, &periph_h_regs, periph_clk_enb_refcnt); 961 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 962 clks[usb2] = clk; 963 964 /* usb3 */ 965 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 966 59, &periph_h_regs, periph_clk_enb_refcnt); 967 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 968 clks[usb3] = clk; 969 970 /* dsi */ 971 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 972 48, &periph_h_regs, periph_clk_enb_refcnt); 973 clk_register_clkdev(clk, NULL, "dsi"); 974 clks[dsi] = clk; 975 976 /* csi */ 977 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 978 0, 52, &periph_h_regs, 979 periph_clk_enb_refcnt); 980 clk_register_clkdev(clk, "csi", "tegra_camera"); 981 clks[csi] = clk; 982 983 /* isp */ 984 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 985 &periph_l_regs, periph_clk_enb_refcnt); 986 clk_register_clkdev(clk, "isp", "tegra_camera"); 987 clks[isp] = clk; 988 989 /* pex */ 990 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 991 &periph_u_regs, periph_clk_enb_refcnt); 992 clk_register_clkdev(clk, "pex", NULL); 993 clks[pex] = clk; 994 995 /* afi */ 996 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 997 &periph_u_regs, periph_clk_enb_refcnt); 998 clk_register_clkdev(clk, "afi", NULL); 999 clks[afi] = clk; 1000 1001 /* pcie_xclk */ 1002 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base, 1003 0, 74, &periph_u_regs, 1004 periph_clk_enb_refcnt); 1005 clk_register_clkdev(clk, "pcie_xclk", NULL); 1006 clks[pcie_xclk] = clk; 1007 1008 /* cdev1 */ 1009 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, 1010 26000000); 1011 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, 1012 clk_base, 0, 94, &periph_u_regs, 1013 periph_clk_enb_refcnt); 1014 clk_register_clkdev(clk, "cdev1", NULL); 1015 clks[cdev1] = clk; 1016 1017 /* cdev2 */ 1018 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, 1019 26000000); 1020 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, 1021 clk_base, 0, 93, &periph_u_regs, 1022 periph_clk_enb_refcnt); 1023 clk_register_clkdev(clk, "cdev2", NULL); 1024 clks[cdev2] = clk; 1025 1026 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1027 data = &tegra_periph_clk_list[i]; 1028 clk = tegra_clk_register_periph(data->name, data->parent_names, 1029 data->num_parents, &data->periph, 1030 clk_base, data->offset, data->flags); 1031 clk_register_clkdev(clk, data->con_id, data->dev_id); 1032 clks[data->clk_id] = clk; 1033 } 1034 1035 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1036 data = &tegra_periph_nodiv_clk_list[i]; 1037 clk = tegra_clk_register_periph_nodiv(data->name, 1038 data->parent_names, 1039 data->num_parents, &data->periph, 1040 clk_base, data->offset); 1041 clk_register_clkdev(clk, data->con_id, data->dev_id); 1042 clks[data->clk_id] = clk; 1043 } 1044} 1045 1046 1047static void __init tegra20_fixed_clk_init(void) 1048{ 1049 struct clk *clk; 1050 1051 /* clk_32k */ 1052 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1053 32768); 1054 clk_register_clkdev(clk, "clk_32k", NULL); 1055 clks[clk_32k] = clk; 1056} 1057 1058static void __init tegra20_pmc_clk_init(void) 1059{ 1060 struct clk *clk; 1061 1062 /* blink */ 1063 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1064 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1065 pmc_base + PMC_DPD_PADS_ORIDE, 1066 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1067 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1068 pmc_base + PMC_CTRL, 1069 PMC_CTRL_BLINK_ENB, 0, NULL); 1070 clk_register_clkdev(clk, "blink", NULL); 1071 clks[blink] = clk; 1072} 1073 1074static void __init tegra20_osc_clk_init(void) 1075{ 1076 struct clk *clk; 1077 unsigned long input_freq; 1078 unsigned int pll_ref_div; 1079 1080 input_freq = tegra20_clk_measure_input_freq(); 1081 1082 /* clk_m */ 1083 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | 1084 CLK_IGNORE_UNUSED, input_freq); 1085 clk_register_clkdev(clk, "clk_m", NULL); 1086 clks[clk_m] = clk; 1087 1088 /* pll_ref */ 1089 pll_ref_div = tegra20_get_pll_ref_div(); 1090 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1091 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1092 clk_register_clkdev(clk, "pll_ref", NULL); 1093 clks[pll_ref] = clk; 1094} 1095 1096/* Tegra20 CPU clock and reset control functions */ 1097static void tegra20_wait_cpu_in_reset(u32 cpu) 1098{ 1099 unsigned int reg; 1100 1101 do { 1102 reg = readl(clk_base + 1103 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1104 cpu_relax(); 1105 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1106 1107 return; 1108} 1109 1110static void tegra20_put_cpu_in_reset(u32 cpu) 1111{ 1112 writel(CPU_RESET(cpu), 1113 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1114 dmb(); 1115} 1116 1117static void tegra20_cpu_out_of_reset(u32 cpu) 1118{ 1119 writel(CPU_RESET(cpu), 1120 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1121 wmb(); 1122} 1123 1124static void tegra20_enable_cpu_clock(u32 cpu) 1125{ 1126 unsigned int reg; 1127 1128 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1129 writel(reg & ~CPU_CLOCK(cpu), 1130 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1131 barrier(); 1132 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1133} 1134 1135static void tegra20_disable_cpu_clock(u32 cpu) 1136{ 1137 unsigned int reg; 1138 1139 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1140 writel(reg | CPU_CLOCK(cpu), 1141 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1142} 1143 1144#ifdef CONFIG_PM_SLEEP 1145static bool tegra20_cpu_rail_off_ready(void) 1146{ 1147 unsigned int cpu_rst_status; 1148 1149 cpu_rst_status = readl(clk_base + 1150 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1151 1152 return !!(cpu_rst_status & 0x2); 1153} 1154 1155static void tegra20_cpu_clock_suspend(void) 1156{ 1157 /* switch coresite to clk_m, save off original source */ 1158 tegra20_cpu_clk_sctx.clk_csite_src = 1159 readl(clk_base + CLK_SOURCE_CSITE); 1160 writel(3<<30, clk_base + CLK_SOURCE_CSITE); 1161 1162 tegra20_cpu_clk_sctx.cpu_burst = 1163 readl(clk_base + CCLK_BURST_POLICY); 1164 tegra20_cpu_clk_sctx.pllx_base = 1165 readl(clk_base + PLLX_BASE); 1166 tegra20_cpu_clk_sctx.pllx_misc = 1167 readl(clk_base + PLLX_MISC); 1168 tegra20_cpu_clk_sctx.cclk_divider = 1169 readl(clk_base + SUPER_CCLK_DIVIDER); 1170} 1171 1172static void tegra20_cpu_clock_resume(void) 1173{ 1174 unsigned int reg, policy; 1175 1176 /* Is CPU complex already running on PLLX? */ 1177 reg = readl(clk_base + CCLK_BURST_POLICY); 1178 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; 1179 1180 if (policy == CCLK_IDLE_POLICY) 1181 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; 1182 else if (policy == CCLK_RUN_POLICY) 1183 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; 1184 else 1185 BUG(); 1186 1187 if (reg != CCLK_BURST_POLICY_PLLX) { 1188 /* restore PLLX settings if CPU is on different PLL */ 1189 writel(tegra20_cpu_clk_sctx.pllx_misc, 1190 clk_base + PLLX_MISC); 1191 writel(tegra20_cpu_clk_sctx.pllx_base, 1192 clk_base + PLLX_BASE); 1193 1194 /* wait for PLL stabilization if PLLX was enabled */ 1195 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) 1196 udelay(300); 1197 } 1198 1199 /* 1200 * Restore original burst policy setting for calls resulting from CPU 1201 * LP2 in idle or system suspend. 1202 */ 1203 writel(tegra20_cpu_clk_sctx.cclk_divider, 1204 clk_base + SUPER_CCLK_DIVIDER); 1205 writel(tegra20_cpu_clk_sctx.cpu_burst, 1206 clk_base + CCLK_BURST_POLICY); 1207 1208 writel(tegra20_cpu_clk_sctx.clk_csite_src, 1209 clk_base + CLK_SOURCE_CSITE); 1210} 1211#endif 1212 1213static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { 1214 .wait_for_reset = tegra20_wait_cpu_in_reset, 1215 .put_in_reset = tegra20_put_cpu_in_reset, 1216 .out_of_reset = tegra20_cpu_out_of_reset, 1217 .enable_clock = tegra20_enable_cpu_clock, 1218 .disable_clock = tegra20_disable_cpu_clock, 1219#ifdef CONFIG_PM_SLEEP 1220 .rail_off_ready = tegra20_cpu_rail_off_ready, 1221 .suspend = tegra20_cpu_clock_suspend, 1222 .resume = tegra20_cpu_clock_resume, 1223#endif 1224}; 1225 1226static struct tegra_clk_init_table init_table[] __initdata = { 1227 {pll_p, clk_max, 216000000, 1}, 1228 {pll_p_out1, clk_max, 28800000, 1}, 1229 {pll_p_out2, clk_max, 48000000, 1}, 1230 {pll_p_out3, clk_max, 72000000, 1}, 1231 {pll_p_out4, clk_max, 24000000, 1}, 1232 {pll_c, clk_max, 600000000, 1}, 1233 {pll_c_out1, clk_max, 120000000, 1}, 1234 {sclk, pll_c_out1, 0, 1}, 1235 {hclk, clk_max, 0, 1}, 1236 {pclk, clk_max, 60000000, 1}, 1237 {csite, clk_max, 0, 1}, 1238 {emc, clk_max, 0, 1}, 1239 {cclk, clk_max, 0, 1}, 1240 {uarta, pll_p, 0, 0}, 1241 {uartb, pll_p, 0, 0}, 1242 {uartc, pll_p, 0, 0}, 1243 {uartd, pll_p, 0, 0}, 1244 {uarte, pll_p, 0, 0}, 1245 {pll_a, clk_max, 56448000, 1}, 1246 {pll_a_out0, clk_max, 11289600, 1}, 1247 {cdev1, clk_max, 0, 1}, 1248 {blink, clk_max, 32768, 1}, 1249 {i2s1, pll_a_out0, 11289600, 0}, 1250 {i2s2, pll_a_out0, 11289600, 0}, 1251 {sdmmc1, pll_p, 48000000, 0}, 1252 {sdmmc3, pll_p, 48000000, 0}, 1253 {sdmmc4, pll_p, 48000000, 0}, 1254 {spi, pll_p, 20000000, 0}, 1255 {sbc1, pll_p, 100000000, 0}, 1256 {sbc2, pll_p, 100000000, 0}, 1257 {sbc3, pll_p, 100000000, 0}, 1258 {sbc4, pll_p, 100000000, 0}, 1259 {host1x, pll_c, 150000000, 0}, 1260 {disp1, pll_p, 600000000, 0}, 1261 {disp2, pll_p, 600000000, 0}, 1262 {gr2d, pll_c, 300000000, 0}, 1263 {gr3d, pll_c, 300000000, 0}, 1264 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ 1265}; 1266 1267static void __init tegra20_clock_apply_init_table(void) 1268{ 1269 tegra_init_from_table(init_table, clks, clk_max); 1270} 1271 1272/* 1273 * Some clocks may be used by different drivers depending on the board 1274 * configuration. List those here to register them twice in the clock lookup 1275 * table under two names. 1276 */ 1277static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1278 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1279 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1280 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1281 TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"), 1282 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */ 1283}; 1284 1285static const struct of_device_id pmc_match[] __initconst = { 1286 { .compatible = "nvidia,tegra20-pmc" }, 1287 {}, 1288}; 1289 1290static void __init tegra20_clock_init(struct device_node *np) 1291{ 1292 int i; 1293 struct device_node *node; 1294 1295 clk_base = of_iomap(np, 0); 1296 if (!clk_base) { 1297 pr_err("Can't map CAR registers\n"); 1298 BUG(); 1299 } 1300 1301 node = of_find_matching_node(NULL, pmc_match); 1302 if (!node) { 1303 pr_err("Failed to find pmc node\n"); 1304 BUG(); 1305 } 1306 1307 pmc_base = of_iomap(node, 0); 1308 if (!pmc_base) { 1309 pr_err("Can't map pmc registers\n"); 1310 BUG(); 1311 } 1312 1313 tegra20_osc_clk_init(); 1314 tegra20_pmc_clk_init(); 1315 tegra20_fixed_clk_init(); 1316 tegra20_pll_init(); 1317 tegra20_super_clk_init(); 1318 tegra20_periph_clk_init(); 1319 tegra20_audio_clk_init(); 1320 1321 1322 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1323 if (IS_ERR(clks[i])) { 1324 pr_err("Tegra20 clk %d: register failed with %ld\n", 1325 i, PTR_ERR(clks[i])); 1326 BUG(); 1327 } 1328 if (!clks[i]) 1329 clks[i] = ERR_PTR(-EINVAL); 1330 } 1331 1332 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1333 1334 clk_data.clks = clks; 1335 clk_data.clk_num = ARRAY_SIZE(clks); 1336 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 1337 1338 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1339 1340 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1341} 1342CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init); 1343