clk-tegra20.c revision 4a2e32794e71db679b91df1d9c98921b2e32ec4e
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/clk/tegra.h> 24#include <linux/delay.h> 25 26#include "clk.h" 27 28#define RST_DEVICES_L 0x004 29#define RST_DEVICES_H 0x008 30#define RST_DEVICES_U 0x00c 31#define RST_DEVICES_SET_L 0x300 32#define RST_DEVICES_CLR_L 0x304 33#define RST_DEVICES_SET_H 0x308 34#define RST_DEVICES_CLR_H 0x30c 35#define RST_DEVICES_SET_U 0x310 36#define RST_DEVICES_CLR_U 0x314 37#define RST_DEVICES_NUM 3 38 39#define CLK_OUT_ENB_L 0x010 40#define CLK_OUT_ENB_H 0x014 41#define CLK_OUT_ENB_U 0x018 42#define CLK_OUT_ENB_SET_L 0x320 43#define CLK_OUT_ENB_CLR_L 0x324 44#define CLK_OUT_ENB_SET_H 0x328 45#define CLK_OUT_ENB_CLR_H 0x32c 46#define CLK_OUT_ENB_SET_U 0x330 47#define CLK_OUT_ENB_CLR_U 0x334 48#define CLK_OUT_ENB_NUM 3 49 50#define OSC_CTRL 0x50 51#define OSC_CTRL_OSC_FREQ_MASK (3<<30) 52#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) 53#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) 54#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) 55#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) 56#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 57 58#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) 59#define OSC_CTRL_PLL_REF_DIV_1 (0<<28) 60#define OSC_CTRL_PLL_REF_DIV_2 (1<<28) 61#define OSC_CTRL_PLL_REF_DIV_4 (2<<28) 62 63#define OSC_FREQ_DET 0x58 64#define OSC_FREQ_DET_TRIG (1<<31) 65 66#define OSC_FREQ_DET_STATUS 0x5c 67#define OSC_FREQ_DET_BUSY (1<<31) 68#define OSC_FREQ_DET_CNT_MASK 0xFFFF 69 70#define PLLS_BASE 0xf0 71#define PLLS_MISC 0xf4 72#define PLLC_BASE 0x80 73#define PLLC_MISC 0x8c 74#define PLLM_BASE 0x90 75#define PLLM_MISC 0x9c 76#define PLLP_BASE 0xa0 77#define PLLP_MISC 0xac 78#define PLLA_BASE 0xb0 79#define PLLA_MISC 0xbc 80#define PLLU_BASE 0xc0 81#define PLLU_MISC 0xcc 82#define PLLD_BASE 0xd0 83#define PLLD_MISC 0xdc 84#define PLLX_BASE 0xe0 85#define PLLX_MISC 0xe4 86#define PLLE_BASE 0xe8 87#define PLLE_MISC 0xec 88 89#define PLL_BASE_LOCK 27 90#define PLLE_MISC_LOCK 11 91 92#define PLL_MISC_LOCK_ENABLE 18 93#define PLLDU_MISC_LOCK_ENABLE 22 94#define PLLE_MISC_LOCK_ENABLE 9 95 96#define PLLC_OUT 0x84 97#define PLLM_OUT 0x94 98#define PLLP_OUTA 0xa4 99#define PLLP_OUTB 0xa8 100#define PLLA_OUT 0xb4 101 102#define CCLK_BURST_POLICY 0x20 103#define SUPER_CCLK_DIVIDER 0x24 104#define SCLK_BURST_POLICY 0x28 105#define SUPER_SCLK_DIVIDER 0x2c 106#define CLK_SYSTEM_RATE 0x30 107 108#define CCLK_BURST_POLICY_SHIFT 28 109#define CCLK_RUN_POLICY_SHIFT 4 110#define CCLK_IDLE_POLICY_SHIFT 0 111#define CCLK_IDLE_POLICY 1 112#define CCLK_RUN_POLICY 2 113#define CCLK_BURST_POLICY_PLLX 8 114 115#define CLK_SOURCE_I2S1 0x100 116#define CLK_SOURCE_I2S2 0x104 117#define CLK_SOURCE_SPDIF_OUT 0x108 118#define CLK_SOURCE_SPDIF_IN 0x10c 119#define CLK_SOURCE_PWM 0x110 120#define CLK_SOURCE_SPI 0x114 121#define CLK_SOURCE_SBC1 0x134 122#define CLK_SOURCE_SBC2 0x118 123#define CLK_SOURCE_SBC3 0x11c 124#define CLK_SOURCE_SBC4 0x1b4 125#define CLK_SOURCE_XIO 0x120 126#define CLK_SOURCE_TWC 0x12c 127#define CLK_SOURCE_IDE 0x144 128#define CLK_SOURCE_NDFLASH 0x160 129#define CLK_SOURCE_VFIR 0x168 130#define CLK_SOURCE_SDMMC1 0x150 131#define CLK_SOURCE_SDMMC2 0x154 132#define CLK_SOURCE_SDMMC3 0x1bc 133#define CLK_SOURCE_SDMMC4 0x164 134#define CLK_SOURCE_CVE 0x140 135#define CLK_SOURCE_TVO 0x188 136#define CLK_SOURCE_TVDAC 0x194 137#define CLK_SOURCE_HDMI 0x18c 138#define CLK_SOURCE_DISP1 0x138 139#define CLK_SOURCE_DISP2 0x13c 140#define CLK_SOURCE_CSITE 0x1d4 141#define CLK_SOURCE_LA 0x1f8 142#define CLK_SOURCE_OWR 0x1cc 143#define CLK_SOURCE_NOR 0x1d0 144#define CLK_SOURCE_MIPI 0x174 145#define CLK_SOURCE_I2C1 0x124 146#define CLK_SOURCE_I2C2 0x198 147#define CLK_SOURCE_I2C3 0x1b8 148#define CLK_SOURCE_DVC 0x128 149#define CLK_SOURCE_UARTA 0x178 150#define CLK_SOURCE_UARTB 0x17c 151#define CLK_SOURCE_UARTC 0x1a0 152#define CLK_SOURCE_UARTD 0x1c0 153#define CLK_SOURCE_UARTE 0x1c4 154#define CLK_SOURCE_3D 0x158 155#define CLK_SOURCE_2D 0x15c 156#define CLK_SOURCE_MPE 0x170 157#define CLK_SOURCE_EPP 0x16c 158#define CLK_SOURCE_HOST1X 0x180 159#define CLK_SOURCE_VDE 0x1c8 160#define CLK_SOURCE_VI 0x148 161#define CLK_SOURCE_VI_SENSOR 0x1a8 162#define CLK_SOURCE_EMC 0x19c 163 164#define AUDIO_SYNC_CLK 0x38 165 166#define PMC_CTRL 0x0 167#define PMC_CTRL_BLINK_ENB 7 168#define PMC_DPD_PADS_ORIDE 0x1c 169#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 170#define PMC_BLINK_TIMER 0x40 171 172/* Tegra CPU clock and reset control regs */ 173#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 174#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 175#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 176 177#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 178#define CPU_RESET(cpu) (0x1111ul << (cpu)) 179 180#ifdef CONFIG_PM_SLEEP 181static struct cpu_clk_suspend_context { 182 u32 pllx_misc; 183 u32 pllx_base; 184 185 u32 cpu_burst; 186 u32 clk_csite_src; 187 u32 cclk_divider; 188} tegra20_cpu_clk_sctx; 189#endif 190 191static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 192 193static void __iomem *clk_base; 194static void __iomem *pmc_base; 195 196static DEFINE_SPINLOCK(pll_div_lock); 197 198#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 199 _clk_num, _regs, _gate_flags, _clk_id) \ 200 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 201 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 202 _regs, _clk_num, periph_clk_enb_refcnt, \ 203 _gate_flags, _clk_id) 204 205#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 206 _clk_num, _regs, _gate_flags, _clk_id) \ 207 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 208 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 209 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 210 _clk_id) 211 212#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 213 _clk_num, _regs, _gate_flags, _clk_id) \ 214 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 215 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \ 216 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 217 _clk_id) 218 219#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 220 _mux_shift, _mux_width, _clk_num, _regs, \ 221 _gate_flags, _clk_id) \ 222 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 223 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 224 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 225 _clk_id) 226 227/* IDs assigned here must be in sync with DT bindings definition 228 * for Tegra20 clocks . 229 */ 230enum tegra20_clk { 231 cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, 232 ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp, 233 gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma, 234 kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3, 235 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 236 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 237 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb, 238 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2, 239 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve, 240 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0, 241 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1, 242 pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u, 243 pll_x, audio, pll_ref, twd, clk_max, 244}; 245 246static struct clk *clks[clk_max]; 247static struct clk_onecell_data clk_data; 248 249static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 250 { 12000000, 600000000, 600, 12, 1, 8 }, 251 { 13000000, 600000000, 600, 13, 1, 8 }, 252 { 19200000, 600000000, 500, 16, 1, 6 }, 253 { 26000000, 600000000, 600, 26, 1, 8 }, 254 { 0, 0, 0, 0, 0, 0 }, 255}; 256 257static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 258 { 12000000, 666000000, 666, 12, 1, 8}, 259 { 13000000, 666000000, 666, 13, 1, 8}, 260 { 19200000, 666000000, 555, 16, 1, 8}, 261 { 26000000, 666000000, 666, 26, 1, 8}, 262 { 12000000, 600000000, 600, 12, 1, 8}, 263 { 13000000, 600000000, 600, 13, 1, 8}, 264 { 19200000, 600000000, 375, 12, 1, 6}, 265 { 26000000, 600000000, 600, 26, 1, 8}, 266 { 0, 0, 0, 0, 0, 0 }, 267}; 268 269static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 270 { 12000000, 216000000, 432, 12, 2, 8}, 271 { 13000000, 216000000, 432, 13, 2, 8}, 272 { 19200000, 216000000, 90, 4, 2, 1}, 273 { 26000000, 216000000, 432, 26, 2, 8}, 274 { 12000000, 432000000, 432, 12, 1, 8}, 275 { 13000000, 432000000, 432, 13, 1, 8}, 276 { 19200000, 432000000, 90, 4, 1, 1}, 277 { 26000000, 432000000, 432, 26, 1, 8}, 278 { 0, 0, 0, 0, 0, 0 }, 279}; 280 281static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 282 { 28800000, 56448000, 49, 25, 1, 1}, 283 { 28800000, 73728000, 64, 25, 1, 1}, 284 { 28800000, 24000000, 5, 6, 1, 1}, 285 { 0, 0, 0, 0, 0, 0 }, 286}; 287 288static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 289 { 12000000, 216000000, 216, 12, 1, 4}, 290 { 13000000, 216000000, 216, 13, 1, 4}, 291 { 19200000, 216000000, 135, 12, 1, 3}, 292 { 26000000, 216000000, 216, 26, 1, 4}, 293 294 { 12000000, 594000000, 594, 12, 1, 8}, 295 { 13000000, 594000000, 594, 13, 1, 8}, 296 { 19200000, 594000000, 495, 16, 1, 8}, 297 { 26000000, 594000000, 594, 26, 1, 8}, 298 299 { 12000000, 1000000000, 1000, 12, 1, 12}, 300 { 13000000, 1000000000, 1000, 13, 1, 12}, 301 { 19200000, 1000000000, 625, 12, 1, 8}, 302 { 26000000, 1000000000, 1000, 26, 1, 12}, 303 304 { 0, 0, 0, 0, 0, 0 }, 305}; 306 307static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 308 { 12000000, 480000000, 960, 12, 2, 0}, 309 { 13000000, 480000000, 960, 13, 2, 0}, 310 { 19200000, 480000000, 200, 4, 2, 0}, 311 { 26000000, 480000000, 960, 26, 2, 0}, 312 { 0, 0, 0, 0, 0, 0 }, 313}; 314 315static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 316 /* 1 GHz */ 317 { 12000000, 1000000000, 1000, 12, 1, 12}, 318 { 13000000, 1000000000, 1000, 13, 1, 12}, 319 { 19200000, 1000000000, 625, 12, 1, 8}, 320 { 26000000, 1000000000, 1000, 26, 1, 12}, 321 322 /* 912 MHz */ 323 { 12000000, 912000000, 912, 12, 1, 12}, 324 { 13000000, 912000000, 912, 13, 1, 12}, 325 { 19200000, 912000000, 760, 16, 1, 8}, 326 { 26000000, 912000000, 912, 26, 1, 12}, 327 328 /* 816 MHz */ 329 { 12000000, 816000000, 816, 12, 1, 12}, 330 { 13000000, 816000000, 816, 13, 1, 12}, 331 { 19200000, 816000000, 680, 16, 1, 8}, 332 { 26000000, 816000000, 816, 26, 1, 12}, 333 334 /* 760 MHz */ 335 { 12000000, 760000000, 760, 12, 1, 12}, 336 { 13000000, 760000000, 760, 13, 1, 12}, 337 { 19200000, 760000000, 950, 24, 1, 8}, 338 { 26000000, 760000000, 760, 26, 1, 12}, 339 340 /* 750 MHz */ 341 { 12000000, 750000000, 750, 12, 1, 12}, 342 { 13000000, 750000000, 750, 13, 1, 12}, 343 { 19200000, 750000000, 625, 16, 1, 8}, 344 { 26000000, 750000000, 750, 26, 1, 12}, 345 346 /* 608 MHz */ 347 { 12000000, 608000000, 608, 12, 1, 12}, 348 { 13000000, 608000000, 608, 13, 1, 12}, 349 { 19200000, 608000000, 380, 12, 1, 8}, 350 { 26000000, 608000000, 608, 26, 1, 12}, 351 352 /* 456 MHz */ 353 { 12000000, 456000000, 456, 12, 1, 12}, 354 { 13000000, 456000000, 456, 13, 1, 12}, 355 { 19200000, 456000000, 380, 16, 1, 8}, 356 { 26000000, 456000000, 456, 26, 1, 12}, 357 358 /* 312 MHz */ 359 { 12000000, 312000000, 312, 12, 1, 12}, 360 { 13000000, 312000000, 312, 13, 1, 12}, 361 { 19200000, 312000000, 260, 16, 1, 8}, 362 { 26000000, 312000000, 312, 26, 1, 12}, 363 364 { 0, 0, 0, 0, 0, 0 }, 365}; 366 367static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 368 { 12000000, 100000000, 200, 24, 1, 0 }, 369 { 0, 0, 0, 0, 0, 0 }, 370}; 371 372/* PLL parameters */ 373static struct tegra_clk_pll_params pll_c_params = { 374 .input_min = 2000000, 375 .input_max = 31000000, 376 .cf_min = 1000000, 377 .cf_max = 6000000, 378 .vco_min = 20000000, 379 .vco_max = 1400000000, 380 .base_reg = PLLC_BASE, 381 .misc_reg = PLLC_MISC, 382 .lock_bit_idx = PLL_BASE_LOCK, 383 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 384 .lock_delay = 300, 385}; 386 387static struct tegra_clk_pll_params pll_m_params = { 388 .input_min = 2000000, 389 .input_max = 31000000, 390 .cf_min = 1000000, 391 .cf_max = 6000000, 392 .vco_min = 20000000, 393 .vco_max = 1200000000, 394 .base_reg = PLLM_BASE, 395 .misc_reg = PLLM_MISC, 396 .lock_bit_idx = PLL_BASE_LOCK, 397 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 398 .lock_delay = 300, 399}; 400 401static struct tegra_clk_pll_params pll_p_params = { 402 .input_min = 2000000, 403 .input_max = 31000000, 404 .cf_min = 1000000, 405 .cf_max = 6000000, 406 .vco_min = 20000000, 407 .vco_max = 1400000000, 408 .base_reg = PLLP_BASE, 409 .misc_reg = PLLP_MISC, 410 .lock_bit_idx = PLL_BASE_LOCK, 411 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 412 .lock_delay = 300, 413}; 414 415static struct tegra_clk_pll_params pll_a_params = { 416 .input_min = 2000000, 417 .input_max = 31000000, 418 .cf_min = 1000000, 419 .cf_max = 6000000, 420 .vco_min = 20000000, 421 .vco_max = 1400000000, 422 .base_reg = PLLA_BASE, 423 .misc_reg = PLLA_MISC, 424 .lock_bit_idx = PLL_BASE_LOCK, 425 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 426 .lock_delay = 300, 427}; 428 429static struct tegra_clk_pll_params pll_d_params = { 430 .input_min = 2000000, 431 .input_max = 40000000, 432 .cf_min = 1000000, 433 .cf_max = 6000000, 434 .vco_min = 40000000, 435 .vco_max = 1000000000, 436 .base_reg = PLLD_BASE, 437 .misc_reg = PLLD_MISC, 438 .lock_bit_idx = PLL_BASE_LOCK, 439 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 440 .lock_delay = 1000, 441}; 442 443static struct tegra_clk_pll_params pll_u_params = { 444 .input_min = 2000000, 445 .input_max = 40000000, 446 .cf_min = 1000000, 447 .cf_max = 6000000, 448 .vco_min = 48000000, 449 .vco_max = 960000000, 450 .base_reg = PLLU_BASE, 451 .misc_reg = PLLU_MISC, 452 .lock_bit_idx = PLL_BASE_LOCK, 453 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 454 .lock_delay = 1000, 455}; 456 457static struct tegra_clk_pll_params pll_x_params = { 458 .input_min = 2000000, 459 .input_max = 31000000, 460 .cf_min = 1000000, 461 .cf_max = 6000000, 462 .vco_min = 20000000, 463 .vco_max = 1200000000, 464 .base_reg = PLLX_BASE, 465 .misc_reg = PLLX_MISC, 466 .lock_bit_idx = PLL_BASE_LOCK, 467 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 468 .lock_delay = 300, 469}; 470 471static struct tegra_clk_pll_params pll_e_params = { 472 .input_min = 12000000, 473 .input_max = 12000000, 474 .cf_min = 0, 475 .cf_max = 0, 476 .vco_min = 0, 477 .vco_max = 0, 478 .base_reg = PLLE_BASE, 479 .misc_reg = PLLE_MISC, 480 .lock_bit_idx = PLLE_MISC_LOCK, 481 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 482 .lock_delay = 0, 483}; 484 485/* Peripheral clock registers */ 486static struct tegra_clk_periph_regs periph_l_regs = { 487 .enb_reg = CLK_OUT_ENB_L, 488 .enb_set_reg = CLK_OUT_ENB_SET_L, 489 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 490 .rst_reg = RST_DEVICES_L, 491 .rst_set_reg = RST_DEVICES_SET_L, 492 .rst_clr_reg = RST_DEVICES_CLR_L, 493}; 494 495static struct tegra_clk_periph_regs periph_h_regs = { 496 .enb_reg = CLK_OUT_ENB_H, 497 .enb_set_reg = CLK_OUT_ENB_SET_H, 498 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 499 .rst_reg = RST_DEVICES_H, 500 .rst_set_reg = RST_DEVICES_SET_H, 501 .rst_clr_reg = RST_DEVICES_CLR_H, 502}; 503 504static struct tegra_clk_periph_regs periph_u_regs = { 505 .enb_reg = CLK_OUT_ENB_U, 506 .enb_set_reg = CLK_OUT_ENB_SET_U, 507 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 508 .rst_reg = RST_DEVICES_U, 509 .rst_set_reg = RST_DEVICES_SET_U, 510 .rst_clr_reg = RST_DEVICES_CLR_U, 511}; 512 513static unsigned long tegra20_clk_measure_input_freq(void) 514{ 515 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 516 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 517 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 518 unsigned long input_freq; 519 520 switch (auto_clk_control) { 521 case OSC_CTRL_OSC_FREQ_12MHZ: 522 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 523 input_freq = 12000000; 524 break; 525 case OSC_CTRL_OSC_FREQ_13MHZ: 526 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 527 input_freq = 13000000; 528 break; 529 case OSC_CTRL_OSC_FREQ_19_2MHZ: 530 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 531 input_freq = 19200000; 532 break; 533 case OSC_CTRL_OSC_FREQ_26MHZ: 534 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 535 input_freq = 26000000; 536 break; 537 default: 538 pr_err("Unexpected clock autodetect value %d", 539 auto_clk_control); 540 BUG(); 541 return 0; 542 } 543 544 return input_freq; 545} 546 547static unsigned int tegra20_get_pll_ref_div(void) 548{ 549 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 550 OSC_CTRL_PLL_REF_DIV_MASK; 551 552 switch (pll_ref_div) { 553 case OSC_CTRL_PLL_REF_DIV_1: 554 return 1; 555 case OSC_CTRL_PLL_REF_DIV_2: 556 return 2; 557 case OSC_CTRL_PLL_REF_DIV_4: 558 return 4; 559 default: 560 pr_err("Invalied pll ref divider %d\n", pll_ref_div); 561 BUG(); 562 } 563 return 0; 564} 565 566static void tegra20_pll_init(void) 567{ 568 struct clk *clk; 569 570 /* PLLC */ 571 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 572 0, &pll_c_params, TEGRA_PLL_HAS_CPCON, 573 pll_c_freq_table, NULL); 574 clk_register_clkdev(clk, "pll_c", NULL); 575 clks[pll_c] = clk; 576 577 /* PLLC_OUT1 */ 578 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 579 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 580 8, 8, 1, NULL); 581 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 582 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 583 0, NULL); 584 clk_register_clkdev(clk, "pll_c_out1", NULL); 585 clks[pll_c_out1] = clk; 586 587 /* PLLP */ 588 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0, 589 216000000, &pll_p_params, TEGRA_PLL_FIXED | 590 TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL); 591 clk_register_clkdev(clk, "pll_p", NULL); 592 clks[pll_p] = clk; 593 594 /* PLLP_OUT1 */ 595 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 596 clk_base + PLLP_OUTA, 0, 597 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 598 8, 8, 1, &pll_div_lock); 599 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 600 clk_base + PLLP_OUTA, 1, 0, 601 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 602 &pll_div_lock); 603 clk_register_clkdev(clk, "pll_p_out1", NULL); 604 clks[pll_p_out1] = clk; 605 606 /* PLLP_OUT2 */ 607 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 608 clk_base + PLLP_OUTA, 0, 609 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 610 24, 8, 1, &pll_div_lock); 611 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 612 clk_base + PLLP_OUTA, 17, 16, 613 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 614 &pll_div_lock); 615 clk_register_clkdev(clk, "pll_p_out2", NULL); 616 clks[pll_p_out2] = clk; 617 618 /* PLLP_OUT3 */ 619 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 620 clk_base + PLLP_OUTB, 0, 621 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 622 8, 8, 1, &pll_div_lock); 623 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 624 clk_base + PLLP_OUTB, 1, 0, 625 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 626 &pll_div_lock); 627 clk_register_clkdev(clk, "pll_p_out3", NULL); 628 clks[pll_p_out3] = clk; 629 630 /* PLLP_OUT4 */ 631 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 632 clk_base + PLLP_OUTB, 0, 633 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, 634 24, 8, 1, &pll_div_lock); 635 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 636 clk_base + PLLP_OUTB, 17, 16, 637 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 638 &pll_div_lock); 639 clk_register_clkdev(clk, "pll_p_out4", NULL); 640 clks[pll_p_out4] = clk; 641 642 /* PLLM */ 643 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 644 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 645 &pll_m_params, TEGRA_PLL_HAS_CPCON, 646 pll_m_freq_table, NULL); 647 clk_register_clkdev(clk, "pll_m", NULL); 648 clks[pll_m] = clk; 649 650 /* PLLM_OUT1 */ 651 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 652 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 653 8, 8, 1, NULL); 654 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 655 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 656 CLK_SET_RATE_PARENT, 0, NULL); 657 clk_register_clkdev(clk, "pll_m_out1", NULL); 658 clks[pll_m_out1] = clk; 659 660 /* PLLX */ 661 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 662 0, &pll_x_params, TEGRA_PLL_HAS_CPCON, 663 pll_x_freq_table, NULL); 664 clk_register_clkdev(clk, "pll_x", NULL); 665 clks[pll_x] = clk; 666 667 /* PLLU */ 668 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 669 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, 670 pll_u_freq_table, NULL); 671 clk_register_clkdev(clk, "pll_u", NULL); 672 clks[pll_u] = clk; 673 674 /* PLLD */ 675 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 676 0, &pll_d_params, TEGRA_PLL_HAS_CPCON, 677 pll_d_freq_table, NULL); 678 clk_register_clkdev(clk, "pll_d", NULL); 679 clks[pll_d] = clk; 680 681 /* PLLD_OUT0 */ 682 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 683 CLK_SET_RATE_PARENT, 1, 2); 684 clk_register_clkdev(clk, "pll_d_out0", NULL); 685 clks[pll_d_out0] = clk; 686 687 /* PLLA */ 688 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 689 0, &pll_a_params, TEGRA_PLL_HAS_CPCON, 690 pll_a_freq_table, NULL); 691 clk_register_clkdev(clk, "pll_a", NULL); 692 clks[pll_a] = clk; 693 694 /* PLLA_OUT0 */ 695 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 696 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 697 8, 8, 1, NULL); 698 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 699 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 700 CLK_SET_RATE_PARENT, 0, NULL); 701 clk_register_clkdev(clk, "pll_a_out0", NULL); 702 clks[pll_a_out0] = clk; 703 704 /* PLLE */ 705 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL, 706 0, 100000000, &pll_e_params, 707 0, pll_e_freq_table, NULL); 708 clk_register_clkdev(clk, "pll_e", NULL); 709 clks[pll_e] = clk; 710} 711 712static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 713 "pll_p_cclk", "pll_p_out4_cclk", 714 "pll_p_out3_cclk", "clk_d", "pll_x" }; 715static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 716 "pll_p_out3", "pll_p_out2", "clk_d", 717 "clk_32k", "pll_m_out1" }; 718 719static void tegra20_super_clk_init(void) 720{ 721 struct clk *clk; 722 723 /* 724 * DIV_U71 dividers for CCLK, these dividers are used only 725 * if parent clock is fixed rate. 726 */ 727 728 /* 729 * Clock input to cclk divided from pll_p using 730 * U71 divider of cclk. 731 */ 732 clk = tegra_clk_register_divider("pll_p_cclk", "pll_p", 733 clk_base + SUPER_CCLK_DIVIDER, 0, 734 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 735 clk_register_clkdev(clk, "pll_p_cclk", NULL); 736 737 /* 738 * Clock input to cclk divided from pll_p_out3 using 739 * U71 divider of cclk. 740 */ 741 clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3", 742 clk_base + SUPER_CCLK_DIVIDER, 0, 743 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 744 clk_register_clkdev(clk, "pll_p_out3_cclk", NULL); 745 746 /* 747 * Clock input to cclk divided from pll_p_out4 using 748 * U71 divider of cclk. 749 */ 750 clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4", 751 clk_base + SUPER_CCLK_DIVIDER, 0, 752 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 753 clk_register_clkdev(clk, "pll_p_out4_cclk", NULL); 754 755 /* CCLK */ 756 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 757 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 758 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 759 clk_register_clkdev(clk, "cclk", NULL); 760 clks[cclk] = clk; 761 762 /* SCLK */ 763 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 764 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, 765 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 766 clk_register_clkdev(clk, "sclk", NULL); 767 clks[sclk] = clk; 768 769 /* HCLK */ 770 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 771 clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL); 772 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, 773 clk_base + CLK_SYSTEM_RATE, 7, 774 CLK_GATE_SET_TO_DISABLE, NULL); 775 clk_register_clkdev(clk, "hclk", NULL); 776 clks[hclk] = clk; 777 778 /* PCLK */ 779 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 780 clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL); 781 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, 782 clk_base + CLK_SYSTEM_RATE, 3, 783 CLK_GATE_SET_TO_DISABLE, NULL); 784 clk_register_clkdev(clk, "pclk", NULL); 785 clks[pclk] = clk; 786 787 /* twd */ 788 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 789 clk_register_clkdev(clk, "twd", NULL); 790 clks[twd] = clk; 791} 792 793static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", 794 "pll_a_out0", "unused", "unused", 795 "unused"}; 796 797static void __init tegra20_audio_clk_init(void) 798{ 799 struct clk *clk; 800 801 /* audio */ 802 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 803 ARRAY_SIZE(audio_parents), 0, 804 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 805 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 806 clk_base + AUDIO_SYNC_CLK, 4, 807 CLK_GATE_SET_TO_DISABLE, NULL); 808 clk_register_clkdev(clk, "audio", NULL); 809 clks[audio] = clk; 810 811 /* audio_2x */ 812 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 813 CLK_SET_RATE_PARENT, 2, 1); 814 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 815 TEGRA_PERIPH_NO_RESET, clk_base, 816 CLK_SET_RATE_PARENT, 89, &periph_u_regs, 817 periph_clk_enb_refcnt); 818 clk_register_clkdev(clk, "audio_2x", NULL); 819 clks[audio_2x] = clk; 820 821} 822 823static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 824 "clk_m"}; 825static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 826 "clk_m"}; 827static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 828 "clk_m"}; 829static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"}; 830static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", 831 "clk_32k"}; 832static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; 833static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"}; 834static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", 835 "clk_m"}; 836static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 837 838static struct tegra_periph_init_data tegra_periph_clk_list[] = { 839 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 840 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 841 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 842 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 843 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 844 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 845 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 846 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 847 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, &periph_h_regs, TEGRA_PERIPH_ON_APB, spi), 848 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, &periph_h_regs, 0, xio), 849 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, &periph_l_regs, TEGRA_PERIPH_ON_APB, twc), 850 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, &periph_l_regs, 0, ide), 851 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, 0, ndflash), 852 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 853 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, 0, csite), 854 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, 0, la), 855 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 856 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 857 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 858 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 859 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 860 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe), 861 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 862 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d), 863 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d), 864 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 865 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 866 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 867 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 868 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 869 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve), 870 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo), 871 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac), 872 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 873 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1), 874 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2), 875 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3), 876 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, dvc), 877 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 878 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm), 879}; 880 881static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 882 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, &periph_l_regs, TEGRA_PERIPH_ON_APB, uarta), 883 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, uartb), 884 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, &periph_h_regs, TEGRA_PERIPH_ON_APB, uartc), 885 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, &periph_u_regs, TEGRA_PERIPH_ON_APB, uartd), 886 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, &periph_u_regs, TEGRA_PERIPH_ON_APB, uarte), 887 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, &periph_l_regs, 0, disp1), 888 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, &periph_l_regs, 0, disp2), 889}; 890 891static void __init tegra20_periph_clk_init(void) 892{ 893 struct tegra_periph_init_data *data; 894 struct clk *clk; 895 int i; 896 897 /* apbdma */ 898 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 899 0, 34, &periph_h_regs, 900 periph_clk_enb_refcnt); 901 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 902 clks[apbdma] = clk; 903 904 /* rtc */ 905 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 906 TEGRA_PERIPH_NO_RESET, 907 clk_base, 0, 4, &periph_l_regs, 908 periph_clk_enb_refcnt); 909 clk_register_clkdev(clk, NULL, "rtc-tegra"); 910 clks[rtc] = clk; 911 912 /* timer */ 913 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 914 0, 5, &periph_l_regs, 915 periph_clk_enb_refcnt); 916 clk_register_clkdev(clk, NULL, "timer"); 917 clks[timer] = clk; 918 919 /* kbc */ 920 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 921 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 922 clk_base, 0, 36, &periph_h_regs, 923 periph_clk_enb_refcnt); 924 clk_register_clkdev(clk, NULL, "tegra-kbc"); 925 clks[kbc] = clk; 926 927 /* csus */ 928 clk = tegra_clk_register_periph_gate("csus", "clk_m", 929 TEGRA_PERIPH_NO_RESET, 930 clk_base, 0, 92, &periph_u_regs, 931 periph_clk_enb_refcnt); 932 clk_register_clkdev(clk, "csus", "tengra_camera"); 933 clks[csus] = clk; 934 935 /* vcp */ 936 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, 937 clk_base, 0, 29, &periph_l_regs, 938 periph_clk_enb_refcnt); 939 clk_register_clkdev(clk, "vcp", "tegra-avp"); 940 clks[vcp] = clk; 941 942 /* bsea */ 943 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, 944 clk_base, 0, 62, &periph_h_regs, 945 periph_clk_enb_refcnt); 946 clk_register_clkdev(clk, "bsea", "tegra-avp"); 947 clks[bsea] = clk; 948 949 /* bsev */ 950 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, 951 clk_base, 0, 63, &periph_h_regs, 952 periph_clk_enb_refcnt); 953 clk_register_clkdev(clk, "bsev", "tegra-aes"); 954 clks[bsev] = clk; 955 956 /* emc */ 957 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 958 ARRAY_SIZE(mux_pllmcp_clkm), 0, 959 clk_base + CLK_SOURCE_EMC, 960 30, 2, 0, NULL); 961 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 962 57, &periph_h_regs, periph_clk_enb_refcnt); 963 clk_register_clkdev(clk, "emc", NULL); 964 clks[emc] = clk; 965 966 /* usbd */ 967 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 968 22, &periph_l_regs, periph_clk_enb_refcnt); 969 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 970 clks[usbd] = clk; 971 972 /* usb2 */ 973 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 974 58, &periph_h_regs, periph_clk_enb_refcnt); 975 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 976 clks[usb2] = clk; 977 978 /* usb3 */ 979 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 980 59, &periph_h_regs, periph_clk_enb_refcnt); 981 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 982 clks[usb3] = clk; 983 984 /* dsi */ 985 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 986 48, &periph_h_regs, periph_clk_enb_refcnt); 987 clk_register_clkdev(clk, NULL, "dsi"); 988 clks[dsi] = clk; 989 990 /* csi */ 991 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 992 0, 52, &periph_h_regs, 993 periph_clk_enb_refcnt); 994 clk_register_clkdev(clk, "csi", "tegra_camera"); 995 clks[csi] = clk; 996 997 /* isp */ 998 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 999 &periph_l_regs, periph_clk_enb_refcnt); 1000 clk_register_clkdev(clk, "isp", "tegra_camera"); 1001 clks[isp] = clk; 1002 1003 /* pex */ 1004 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 1005 &periph_u_regs, periph_clk_enb_refcnt); 1006 clk_register_clkdev(clk, "pex", NULL); 1007 clks[pex] = clk; 1008 1009 /* afi */ 1010 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1011 &periph_u_regs, periph_clk_enb_refcnt); 1012 clk_register_clkdev(clk, "afi", NULL); 1013 clks[afi] = clk; 1014 1015 /* pcie_xclk */ 1016 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base, 1017 0, 74, &periph_u_regs, 1018 periph_clk_enb_refcnt); 1019 clk_register_clkdev(clk, "pcie_xclk", NULL); 1020 clks[pcie_xclk] = clk; 1021 1022 /* cdev1 */ 1023 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, 1024 26000000); 1025 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, 1026 clk_base, 0, 94, &periph_u_regs, 1027 periph_clk_enb_refcnt); 1028 clk_register_clkdev(clk, "cdev1", NULL); 1029 clks[cdev1] = clk; 1030 1031 /* cdev2 */ 1032 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, 1033 26000000); 1034 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, 1035 clk_base, 0, 93, &periph_u_regs, 1036 periph_clk_enb_refcnt); 1037 clk_register_clkdev(clk, "cdev2", NULL); 1038 clks[cdev2] = clk; 1039 1040 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1041 data = &tegra_periph_clk_list[i]; 1042 clk = tegra_clk_register_periph(data->name, data->parent_names, 1043 data->num_parents, &data->periph, 1044 clk_base, data->offset); 1045 clk_register_clkdev(clk, data->con_id, data->dev_id); 1046 clks[data->clk_id] = clk; 1047 } 1048 1049 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1050 data = &tegra_periph_nodiv_clk_list[i]; 1051 clk = tegra_clk_register_periph_nodiv(data->name, 1052 data->parent_names, 1053 data->num_parents, &data->periph, 1054 clk_base, data->offset); 1055 clk_register_clkdev(clk, data->con_id, data->dev_id); 1056 clks[data->clk_id] = clk; 1057 } 1058} 1059 1060 1061static void __init tegra20_fixed_clk_init(void) 1062{ 1063 struct clk *clk; 1064 1065 /* clk_32k */ 1066 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1067 32768); 1068 clk_register_clkdev(clk, "clk_32k", NULL); 1069 clks[clk_32k] = clk; 1070} 1071 1072static void __init tegra20_pmc_clk_init(void) 1073{ 1074 struct clk *clk; 1075 1076 /* blink */ 1077 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1078 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1079 pmc_base + PMC_DPD_PADS_ORIDE, 1080 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1081 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1082 pmc_base + PMC_CTRL, 1083 PMC_CTRL_BLINK_ENB, 0, NULL); 1084 clk_register_clkdev(clk, "blink", NULL); 1085 clks[blink] = clk; 1086} 1087 1088static void __init tegra20_osc_clk_init(void) 1089{ 1090 struct clk *clk; 1091 unsigned long input_freq; 1092 unsigned int pll_ref_div; 1093 1094 input_freq = tegra20_clk_measure_input_freq(); 1095 1096 /* clk_m */ 1097 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | 1098 CLK_IGNORE_UNUSED, input_freq); 1099 clk_register_clkdev(clk, "clk_m", NULL); 1100 clks[clk_m] = clk; 1101 1102 /* pll_ref */ 1103 pll_ref_div = tegra20_get_pll_ref_div(); 1104 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1105 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1106 clk_register_clkdev(clk, "pll_ref", NULL); 1107 clks[pll_ref] = clk; 1108} 1109 1110/* Tegra20 CPU clock and reset control functions */ 1111static void tegra20_wait_cpu_in_reset(u32 cpu) 1112{ 1113 unsigned int reg; 1114 1115 do { 1116 reg = readl(clk_base + 1117 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1118 cpu_relax(); 1119 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1120 1121 return; 1122} 1123 1124static void tegra20_put_cpu_in_reset(u32 cpu) 1125{ 1126 writel(CPU_RESET(cpu), 1127 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1128 dmb(); 1129} 1130 1131static void tegra20_cpu_out_of_reset(u32 cpu) 1132{ 1133 writel(CPU_RESET(cpu), 1134 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1135 wmb(); 1136} 1137 1138static void tegra20_enable_cpu_clock(u32 cpu) 1139{ 1140 unsigned int reg; 1141 1142 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1143 writel(reg & ~CPU_CLOCK(cpu), 1144 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1145 barrier(); 1146 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1147} 1148 1149static void tegra20_disable_cpu_clock(u32 cpu) 1150{ 1151 unsigned int reg; 1152 1153 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1154 writel(reg | CPU_CLOCK(cpu), 1155 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1156} 1157 1158#ifdef CONFIG_PM_SLEEP 1159static bool tegra20_cpu_rail_off_ready(void) 1160{ 1161 unsigned int cpu_rst_status; 1162 1163 cpu_rst_status = readl(clk_base + 1164 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1165 1166 return !!(cpu_rst_status & 0x2); 1167} 1168 1169static void tegra20_cpu_clock_suspend(void) 1170{ 1171 /* switch coresite to clk_m, save off original source */ 1172 tegra20_cpu_clk_sctx.clk_csite_src = 1173 readl(clk_base + CLK_SOURCE_CSITE); 1174 writel(3<<30, clk_base + CLK_SOURCE_CSITE); 1175 1176 tegra20_cpu_clk_sctx.cpu_burst = 1177 readl(clk_base + CCLK_BURST_POLICY); 1178 tegra20_cpu_clk_sctx.pllx_base = 1179 readl(clk_base + PLLX_BASE); 1180 tegra20_cpu_clk_sctx.pllx_misc = 1181 readl(clk_base + PLLX_MISC); 1182 tegra20_cpu_clk_sctx.cclk_divider = 1183 readl(clk_base + SUPER_CCLK_DIVIDER); 1184} 1185 1186static void tegra20_cpu_clock_resume(void) 1187{ 1188 unsigned int reg, policy; 1189 1190 /* Is CPU complex already running on PLLX? */ 1191 reg = readl(clk_base + CCLK_BURST_POLICY); 1192 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; 1193 1194 if (policy == CCLK_IDLE_POLICY) 1195 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; 1196 else if (policy == CCLK_RUN_POLICY) 1197 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; 1198 else 1199 BUG(); 1200 1201 if (reg != CCLK_BURST_POLICY_PLLX) { 1202 /* restore PLLX settings if CPU is on different PLL */ 1203 writel(tegra20_cpu_clk_sctx.pllx_misc, 1204 clk_base + PLLX_MISC); 1205 writel(tegra20_cpu_clk_sctx.pllx_base, 1206 clk_base + PLLX_BASE); 1207 1208 /* wait for PLL stabilization if PLLX was enabled */ 1209 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) 1210 udelay(300); 1211 } 1212 1213 /* 1214 * Restore original burst policy setting for calls resulting from CPU 1215 * LP2 in idle or system suspend. 1216 */ 1217 writel(tegra20_cpu_clk_sctx.cclk_divider, 1218 clk_base + SUPER_CCLK_DIVIDER); 1219 writel(tegra20_cpu_clk_sctx.cpu_burst, 1220 clk_base + CCLK_BURST_POLICY); 1221 1222 writel(tegra20_cpu_clk_sctx.clk_csite_src, 1223 clk_base + CLK_SOURCE_CSITE); 1224} 1225#endif 1226 1227static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { 1228 .wait_for_reset = tegra20_wait_cpu_in_reset, 1229 .put_in_reset = tegra20_put_cpu_in_reset, 1230 .out_of_reset = tegra20_cpu_out_of_reset, 1231 .enable_clock = tegra20_enable_cpu_clock, 1232 .disable_clock = tegra20_disable_cpu_clock, 1233#ifdef CONFIG_PM_SLEEP 1234 .rail_off_ready = tegra20_cpu_rail_off_ready, 1235 .suspend = tegra20_cpu_clock_suspend, 1236 .resume = tegra20_cpu_clock_resume, 1237#endif 1238}; 1239 1240static __initdata struct tegra_clk_init_table init_table[] = { 1241 {pll_p, clk_max, 216000000, 1}, 1242 {pll_p_out1, clk_max, 28800000, 1}, 1243 {pll_p_out2, clk_max, 48000000, 1}, 1244 {pll_p_out3, clk_max, 72000000, 1}, 1245 {pll_p_out4, clk_max, 24000000, 1}, 1246 {pll_c, clk_max, 600000000, 1}, 1247 {pll_c_out1, clk_max, 120000000, 1}, 1248 {sclk, pll_c_out1, 0, 1}, 1249 {hclk, clk_max, 0, 1}, 1250 {pclk, clk_max, 60000000, 1}, 1251 {csite, clk_max, 0, 1}, 1252 {emc, clk_max, 0, 1}, 1253 {cclk, clk_max, 0, 1}, 1254 {uarta, pll_p, 0, 1}, 1255 {uartd, pll_p, 0, 1}, 1256 {usbd, clk_max, 12000000, 0}, 1257 {usb2, clk_max, 12000000, 0}, 1258 {usb3, clk_max, 12000000, 0}, 1259 {pll_a, clk_max, 56448000, 1}, 1260 {pll_a_out0, clk_max, 11289600, 1}, 1261 {cdev1, clk_max, 0, 1}, 1262 {blink, clk_max, 32768, 1}, 1263 {i2s1, pll_a_out0, 11289600, 0}, 1264 {i2s2, pll_a_out0, 11289600, 0}, 1265 {sdmmc1, pll_p, 48000000, 0}, 1266 {sdmmc3, pll_p, 48000000, 0}, 1267 {sdmmc4, pll_p, 48000000, 0}, 1268 {spi, pll_p, 20000000, 0}, 1269 {sbc1, pll_p, 100000000, 0}, 1270 {sbc2, pll_p, 100000000, 0}, 1271 {sbc3, pll_p, 100000000, 0}, 1272 {sbc4, pll_p, 100000000, 0}, 1273 {host1x, pll_c, 150000000, 0}, 1274 {disp1, pll_p, 600000000, 0}, 1275 {disp2, pll_p, 600000000, 0}, 1276 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ 1277}; 1278 1279/* 1280 * Some clocks may be used by different drivers depending on the board 1281 * configuration. List those here to register them twice in the clock lookup 1282 * table under two names. 1283 */ 1284static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1285 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1286 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1287 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1288 TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"), 1289 TEGRA_CLK_DUPLICATE(twd, "smp_twd", NULL), 1290 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */ 1291}; 1292 1293static const struct of_device_id pmc_match[] __initconst = { 1294 { .compatible = "nvidia,tegra20-pmc" }, 1295 {}, 1296}; 1297 1298void __init tegra20_clock_init(struct device_node *np) 1299{ 1300 int i; 1301 struct device_node *node; 1302 1303 clk_base = of_iomap(np, 0); 1304 if (!clk_base) { 1305 pr_err("Can't map CAR registers\n"); 1306 BUG(); 1307 } 1308 1309 node = of_find_matching_node(NULL, pmc_match); 1310 if (!node) { 1311 pr_err("Failed to find pmc node\n"); 1312 BUG(); 1313 } 1314 1315 pmc_base = of_iomap(node, 0); 1316 if (!pmc_base) { 1317 pr_err("Can't map pmc registers\n"); 1318 BUG(); 1319 } 1320 1321 tegra20_osc_clk_init(); 1322 tegra20_pmc_clk_init(); 1323 tegra20_fixed_clk_init(); 1324 tegra20_pll_init(); 1325 tegra20_super_clk_init(); 1326 tegra20_periph_clk_init(); 1327 tegra20_audio_clk_init(); 1328 1329 1330 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1331 if (IS_ERR(clks[i])) { 1332 pr_err("Tegra20 clk %d: register failed with %ld\n", 1333 i, PTR_ERR(clks[i])); 1334 BUG(); 1335 } 1336 if (!clks[i]) 1337 clks[i] = ERR_PTR(-EINVAL); 1338 } 1339 1340 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1341 1342 clk_data.clks = clks; 1343 clk_data.clk_num = ARRAY_SIZE(clks); 1344 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 1345 1346 tegra_init_from_table(init_table, clks, clk_max); 1347 1348 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1349} 1350