1/* 2 * DRA7 ATL (Audio Tracking Logic) clock driver 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Peter Ujfalusi <peter.ujfalusi@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#include <linux/module.h> 19#include <linux/clk-provider.h> 20#include <linux/slab.h> 21#include <linux/io.h> 22#include <linux/of.h> 23#include <linux/of_address.h> 24#include <linux/platform_device.h> 25#include <linux/pm_runtime.h> 26 27#define DRA7_ATL_INSTANCES 4 28 29#define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80)) 30#define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80)) 31#define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80)) 32#define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80)) 33#define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80)) 34#define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80)) 35#define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80)) 36 37#define DRA7_ATL_SWEN BIT(0) 38#define DRA7_ATL_DIVIDER_MASK (0x1f) 39#define DRA7_ATL_PCLKMUX BIT(0) 40struct dra7_atl_clock_info; 41 42struct dra7_atl_desc { 43 struct clk *clk; 44 struct clk_hw hw; 45 struct dra7_atl_clock_info *cinfo; 46 int id; 47 48 bool probed; /* the driver for the IP has been loaded */ 49 bool valid; /* configured */ 50 bool enabled; 51 u32 bws; /* Baseband Word Select Mux */ 52 u32 aws; /* Audio Word Select Mux */ 53 u32 divider; /* Cached divider value */ 54}; 55 56struct dra7_atl_clock_info { 57 struct device *dev; 58 void __iomem *iobase; 59 60 struct dra7_atl_desc *cdesc; 61}; 62 63#define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw) 64 65static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg, 66 u32 val) 67{ 68 __raw_writel(val, cinfo->iobase + reg); 69} 70 71static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg) 72{ 73 return __raw_readl(cinfo->iobase + reg); 74} 75 76static int atl_clk_enable(struct clk_hw *hw) 77{ 78 struct dra7_atl_desc *cdesc = to_atl_desc(hw); 79 80 if (!cdesc->probed) 81 goto out; 82 83 if (unlikely(!cdesc->valid)) 84 dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n", 85 cdesc->id); 86 pm_runtime_get_sync(cdesc->cinfo->dev); 87 88 atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id), 89 cdesc->divider - 1); 90 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN); 91 92out: 93 cdesc->enabled = true; 94 95 return 0; 96} 97 98static void atl_clk_disable(struct clk_hw *hw) 99{ 100 struct dra7_atl_desc *cdesc = to_atl_desc(hw); 101 102 if (!cdesc->probed) 103 goto out; 104 105 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0); 106 pm_runtime_put_sync(cdesc->cinfo->dev); 107 108out: 109 cdesc->enabled = false; 110} 111 112static int atl_clk_is_enabled(struct clk_hw *hw) 113{ 114 struct dra7_atl_desc *cdesc = to_atl_desc(hw); 115 116 return cdesc->enabled; 117} 118 119static unsigned long atl_clk_recalc_rate(struct clk_hw *hw, 120 unsigned long parent_rate) 121{ 122 struct dra7_atl_desc *cdesc = to_atl_desc(hw); 123 124 return parent_rate / cdesc->divider; 125} 126 127static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate, 128 unsigned long *parent_rate) 129{ 130 unsigned divider; 131 132 divider = (*parent_rate + rate / 2) / rate; 133 if (divider > DRA7_ATL_DIVIDER_MASK + 1) 134 divider = DRA7_ATL_DIVIDER_MASK + 1; 135 136 return *parent_rate / divider; 137} 138 139static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate, 140 unsigned long parent_rate) 141{ 142 struct dra7_atl_desc *cdesc; 143 u32 divider; 144 145 if (!hw || !rate) 146 return -EINVAL; 147 148 cdesc = to_atl_desc(hw); 149 divider = ((parent_rate + rate / 2) / rate) - 1; 150 if (divider > DRA7_ATL_DIVIDER_MASK) 151 divider = DRA7_ATL_DIVIDER_MASK; 152 153 cdesc->divider = divider + 1; 154 155 return 0; 156} 157 158const struct clk_ops atl_clk_ops = { 159 .enable = atl_clk_enable, 160 .disable = atl_clk_disable, 161 .is_enabled = atl_clk_is_enabled, 162 .recalc_rate = atl_clk_recalc_rate, 163 .round_rate = atl_clk_round_rate, 164 .set_rate = atl_clk_set_rate, 165}; 166 167static void __init of_dra7_atl_clock_setup(struct device_node *node) 168{ 169 struct dra7_atl_desc *clk_hw = NULL; 170 struct clk_init_data init = { 0 }; 171 const char **parent_names = NULL; 172 struct clk *clk; 173 174 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 175 if (!clk_hw) { 176 pr_err("%s: could not allocate dra7_atl_desc\n", __func__); 177 return; 178 } 179 180 clk_hw->hw.init = &init; 181 clk_hw->divider = 1; 182 init.name = node->name; 183 init.ops = &atl_clk_ops; 184 init.flags = CLK_IGNORE_UNUSED; 185 init.num_parents = of_clk_get_parent_count(node); 186 187 if (init.num_parents != 1) { 188 pr_err("%s: atl clock %s must have 1 parent\n", __func__, 189 node->name); 190 goto cleanup; 191 } 192 193 parent_names = kzalloc(sizeof(char *), GFP_KERNEL); 194 195 if (!parent_names) 196 goto cleanup; 197 198 parent_names[0] = of_clk_get_parent_name(node, 0); 199 200 init.parent_names = parent_names; 201 202 clk = clk_register(NULL, &clk_hw->hw); 203 204 if (!IS_ERR(clk)) { 205 of_clk_add_provider(node, of_clk_src_simple_get, clk); 206 kfree(parent_names); 207 return; 208 } 209cleanup: 210 kfree(parent_names); 211 kfree(clk_hw); 212} 213CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup); 214 215static int of_dra7_atl_clk_probe(struct platform_device *pdev) 216{ 217 struct device_node *node = pdev->dev.of_node; 218 struct dra7_atl_clock_info *cinfo; 219 int i; 220 int ret = 0; 221 222 if (!node) 223 return -ENODEV; 224 225 cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL); 226 if (!cinfo) 227 return -ENOMEM; 228 229 cinfo->iobase = of_iomap(node, 0); 230 cinfo->dev = &pdev->dev; 231 pm_runtime_enable(cinfo->dev); 232 pm_runtime_irq_safe(cinfo->dev); 233 234 pm_runtime_get_sync(cinfo->dev); 235 atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX); 236 237 for (i = 0; i < DRA7_ATL_INSTANCES; i++) { 238 struct device_node *cfg_node; 239 char prop[5]; 240 struct dra7_atl_desc *cdesc; 241 struct of_phandle_args clkspec; 242 struct clk *clk; 243 int rc; 244 245 rc = of_parse_phandle_with_args(node, "ti,provided-clocks", 246 NULL, i, &clkspec); 247 248 if (rc) { 249 pr_err("%s: failed to lookup atl clock %d\n", __func__, 250 i); 251 return -EINVAL; 252 } 253 254 clk = of_clk_get_from_provider(&clkspec); 255 256 cdesc = to_atl_desc(__clk_get_hw(clk)); 257 cdesc->cinfo = cinfo; 258 cdesc->id = i; 259 260 /* Get configuration for the ATL instances */ 261 snprintf(prop, sizeof(prop), "atl%u", i); 262 cfg_node = of_find_node_by_name(node, prop); 263 if (cfg_node) { 264 ret = of_property_read_u32(cfg_node, "bws", 265 &cdesc->bws); 266 ret |= of_property_read_u32(cfg_node, "aws", 267 &cdesc->aws); 268 if (!ret) { 269 cdesc->valid = true; 270 atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i), 271 cdesc->bws); 272 atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i), 273 cdesc->aws); 274 } 275 } 276 277 cdesc->probed = true; 278 /* 279 * Enable the clock if it has been asked prior to loading the 280 * hw driver 281 */ 282 if (cdesc->enabled) 283 atl_clk_enable(__clk_get_hw(clk)); 284 } 285 pm_runtime_put_sync(cinfo->dev); 286 287 return ret; 288} 289 290static int of_dra7_atl_clk_remove(struct platform_device *pdev) 291{ 292 pm_runtime_disable(&pdev->dev); 293 294 return 0; 295} 296 297static struct of_device_id of_dra7_atl_clk_match_tbl[] = { 298 { .compatible = "ti,dra7-atl", }, 299 {}, 300}; 301MODULE_DEVICE_TABLE(of, of_dra7_atl_clk_match_tbl); 302 303static struct platform_driver dra7_atl_clk_driver = { 304 .driver = { 305 .name = "dra7-atl", 306 .of_match_table = of_dra7_atl_clk_match_tbl, 307 }, 308 .probe = of_dra7_atl_clk_probe, 309 .remove = of_dra7_atl_clk_remove, 310}; 311 312module_platform_driver(dra7_atl_clk_driver); 313 314MODULE_DESCRIPTION("Clock driver for DRA7 Audio Tracking Logic"); 315MODULE_ALIAS("platform:dra7-atl-clock"); 316MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 317MODULE_LICENSE("GPL v2"); 318