time-armada-370-xp.c revision ec8e51120a5b167e22ee29f4f427a0cb66eb445b 
1/*
2 * Marvell Armada 370/XP SoC timer handling.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2.  This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Timer 0 is used as free-running clocksource, while timer 1 is
15 * used as clock_event_device.
16 *
17 * ---
18 * Clocksource driver for Armada 370 and Armada XP SoC.
19 * This driver implements one compatible string for each SoC, given
20 * each has its own characteristics:
21 *
22 *   * Armada 370 has no 25 MHz fixed timer.
23 *
24 *   * Armada XP cannot work properly without such 25 MHz fixed timer as
25 *     doing otherwise leads to using a clocksource whose frequency varies
26 *     when doing cpufreq frequency changes.
27 *
28 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
29 */
30
31#include <linux/init.h>
32#include <linux/platform_device.h>
33#include <linux/kernel.h>
34#include <linux/clk.h>
35#include <linux/timer.h>
36#include <linux/clockchips.h>
37#include <linux/interrupt.h>
38#include <linux/of.h>
39#include <linux/of_irq.h>
40#include <linux/of_address.h>
41#include <linux/irq.h>
42#include <linux/module.h>
43#include <linux/sched_clock.h>
44
45#include <asm/localtimer.h>
46#include <linux/percpu.h>
47/*
48 * Timer block registers.
49 */
50#define TIMER_CTRL_OFF		0x0000
51#define  TIMER0_EN		 BIT(0)
52#define  TIMER0_RELOAD_EN	 BIT(1)
53#define  TIMER0_25MHZ            BIT(11)
54#define  TIMER0_DIV(div)         ((div) << 19)
55#define  TIMER1_EN		 BIT(2)
56#define  TIMER1_RELOAD_EN	 BIT(3)
57#define  TIMER1_25MHZ            BIT(12)
58#define  TIMER1_DIV(div)         ((div) << 22)
59#define TIMER_EVENTS_STATUS	0x0004
60#define  TIMER0_CLR_MASK         (~0x1)
61#define  TIMER1_CLR_MASK         (~0x100)
62#define TIMER0_RELOAD_OFF	0x0010
63#define TIMER0_VAL_OFF		0x0014
64#define TIMER1_RELOAD_OFF	0x0018
65#define TIMER1_VAL_OFF		0x001c
66
67#define LCL_TIMER_EVENTS_STATUS	0x0028
68/* Global timers are connected to the coherency fabric clock, and the
69   below divider reduces their incrementing frequency. */
70#define TIMER_DIVIDER_SHIFT     5
71#define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)
72
73/*
74 * SoC-specific data.
75 */
76static void __iomem *timer_base, *local_base;
77static unsigned int timer_clk;
78static bool timer25Mhz = true;
79
80/*
81 * Number of timer ticks per jiffy.
82 */
83static u32 ticks_per_jiffy;
84
85static struct clock_event_device __percpu **percpu_armada_370_xp_evt;
86
87static void timer_ctrl_clrset(u32 clr, u32 set)
88{
89	writel((readl(timer_base + TIMER_CTRL_OFF) & ~clr) | set,
90		timer_base + TIMER_CTRL_OFF);
91}
92
93static void local_timer_ctrl_clrset(u32 clr, u32 set)
94{
95	writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
96		local_base + TIMER_CTRL_OFF);
97}
98
99static u32 notrace armada_370_xp_read_sched_clock(void)
100{
101	return ~readl(timer_base + TIMER0_VAL_OFF);
102}
103
104/*
105 * Clockevent handling.
106 */
107static int
108armada_370_xp_clkevt_next_event(unsigned long delta,
109				struct clock_event_device *dev)
110{
111	/*
112	 * Clear clockevent timer interrupt.
113	 */
114	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
115
116	/*
117	 * Setup new clockevent timer value.
118	 */
119	writel(delta, local_base + TIMER0_VAL_OFF);
120
121	/*
122	 * Enable the timer.
123	 */
124	local_timer_ctrl_clrset(TIMER0_RELOAD_EN,
125				TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT));
126	return 0;
127}
128
129static void
130armada_370_xp_clkevt_mode(enum clock_event_mode mode,
131			  struct clock_event_device *dev)
132{
133	if (mode == CLOCK_EVT_MODE_PERIODIC) {
134
135		/*
136		 * Setup timer to fire at 1/HZ intervals.
137		 */
138		writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
139		writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
140
141		/*
142		 * Enable timer.
143		 */
144		local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN |
145					   TIMER0_EN |
146					   TIMER0_DIV(TIMER_DIVIDER_SHIFT));
147	} else {
148		/*
149		 * Disable timer.
150		 */
151		local_timer_ctrl_clrset(TIMER0_EN, 0);
152
153		/*
154		 * ACK pending timer interrupt.
155		 */
156		writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
157	}
158}
159
160static struct clock_event_device armada_370_xp_clkevt = {
161	.name		= "armada_370_xp_per_cpu_tick",
162	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
163	.shift		= 32,
164	.rating		= 300,
165	.set_next_event	= armada_370_xp_clkevt_next_event,
166	.set_mode	= armada_370_xp_clkevt_mode,
167};
168
169static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
170{
171	/*
172	 * ACK timer interrupt and call event handler.
173	 */
174	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
175
176	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
177	evt->event_handler(evt);
178
179	return IRQ_HANDLED;
180}
181
182/*
183 * Setup the local clock events for a CPU.
184 */
185static int armada_370_xp_timer_setup(struct clock_event_device *evt)
186{
187	u32 clr = 0, set = 0;
188	int cpu = smp_processor_id();
189
190	/* Use existing clock_event for cpu 0 */
191	if (!smp_processor_id())
192		return 0;
193
194	if (timer25Mhz)
195		set = TIMER0_25MHZ;
196	else
197		clr = TIMER0_25MHZ;
198	local_timer_ctrl_clrset(clr, set);
199
200	evt->name		= armada_370_xp_clkevt.name;
201	evt->irq		= armada_370_xp_clkevt.irq;
202	evt->features		= armada_370_xp_clkevt.features;
203	evt->shift		= armada_370_xp_clkevt.shift;
204	evt->rating		= armada_370_xp_clkevt.rating,
205	evt->set_next_event	= armada_370_xp_clkevt_next_event,
206	evt->set_mode		= armada_370_xp_clkevt_mode,
207	evt->cpumask		= cpumask_of(cpu);
208
209	*__this_cpu_ptr(percpu_armada_370_xp_evt) = evt;
210
211	clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
212	enable_percpu_irq(evt->irq, 0);
213
214	return 0;
215}
216
217static void  armada_370_xp_timer_stop(struct clock_event_device *evt)
218{
219	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
220	disable_percpu_irq(evt->irq);
221}
222
223static struct local_timer_ops armada_370_xp_local_timer_ops = {
224	.setup	= armada_370_xp_timer_setup,
225	.stop	=  armada_370_xp_timer_stop,
226};
227
228static void __init armada_370_xp_timer_common_init(struct device_node *np)
229{
230	u32 clr = 0, set = 0;
231	int res;
232
233	timer_base = of_iomap(np, 0);
234	WARN_ON(!timer_base);
235	local_base = of_iomap(np, 1);
236
237	if (timer25Mhz)
238		set = TIMER0_25MHZ;
239	else
240		clr = TIMER0_25MHZ;
241	timer_ctrl_clrset(clr, set);
242	local_timer_ctrl_clrset(clr, set);
243
244	/*
245	 * We use timer 0 as clocksource, and private(local) timer 0
246	 * for clockevents
247	 */
248	armada_370_xp_clkevt.irq = irq_of_parse_and_map(np, 4);
249
250	ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
251
252	/*
253	 * Set scale and timer for sched_clock.
254	 */
255	setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk);
256
257	/*
258	 * Setup free-running clocksource timer (interrupts
259	 * disabled).
260	 */
261	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
262	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
263
264	timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN |
265			     TIMER0_DIV(TIMER_DIVIDER_SHIFT));
266
267	clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
268			      "armada_370_xp_clocksource",
269			      timer_clk, 300, 32, clocksource_mmio_readl_down);
270
271	/* Register the clockevent on the private timer of CPU 0 */
272	armada_370_xp_clkevt.cpumask = cpumask_of(0);
273	clockevents_config_and_register(&armada_370_xp_clkevt,
274					timer_clk, 1, 0xfffffffe);
275
276	percpu_armada_370_xp_evt = alloc_percpu(struct clock_event_device *);
277
278
279	/*
280	 * Setup clockevent timer (interrupt-driven).
281	 */
282	*__this_cpu_ptr(percpu_armada_370_xp_evt) = &armada_370_xp_clkevt;
283	res = request_percpu_irq(armada_370_xp_clkevt.irq,
284				armada_370_xp_timer_interrupt,
285				armada_370_xp_clkevt.name,
286				percpu_armada_370_xp_evt);
287	if (!res) {
288		enable_percpu_irq(armada_370_xp_clkevt.irq, 0);
289#ifdef CONFIG_LOCAL_TIMERS
290		local_timer_register(&armada_370_xp_local_timer_ops);
291#endif
292	}
293}
294
295static void __init armada_xp_timer_init(struct device_node *np)
296{
297	/* The fixed 25MHz timer is required, timer25Mhz is true by default */
298	timer_clk = 25000000;
299
300	armada_370_xp_timer_common_init(np);
301}
302CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
303		       armada_xp_timer_init);
304
305static void __init armada_370_timer_init(struct device_node *np)
306{
307	struct clk *clk = of_clk_get(np, 0);
308
309	BUG_ON(IS_ERR(clk));
310	timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
311	timer25Mhz = false;
312
313	armada_370_xp_timer_common_init(np);
314}
315CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
316		       armada_370_timer_init);
317