1/* 2 This file is provided under a dual BSD/GPLv2 license. When using or 3 redistributing this file, you may do so under either license. 4 5 GPL LICENSE SUMMARY 6 Copyright(c) 2014 Intel Corporation. 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of version 2 of the GNU General Public License as 9 published by the Free Software Foundation. 10 11 This program is distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 Contact Information: 17 qat-linux@intel.com 18 19 BSD LICENSE 20 Copyright(c) 2014 Intel Corporation. 21 Redistribution and use in source and binary forms, with or without 22 modification, are permitted provided that the following conditions 23 are met: 24 25 * Redistributions of source code must retain the above copyright 26 notice, this list of conditions and the following disclaimer. 27 * Redistributions in binary form must reproduce the above copyright 28 notice, this list of conditions and the following disclaimer in 29 the documentation and/or other materials provided with the 30 distribution. 31 * Neither the name of Intel Corporation nor the names of its 32 contributors may be used to endorse or promote products derived 33 from this software without specific prior written permission. 34 35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46*/ 47#ifndef _ICP_QAT_FW_LA_H_ 48#define _ICP_QAT_FW_LA_H_ 49#include "icp_qat_fw.h" 50 51enum icp_qat_fw_la_cmd_id { 52 ICP_QAT_FW_LA_CMD_CIPHER = 0, 53 ICP_QAT_FW_LA_CMD_AUTH = 1, 54 ICP_QAT_FW_LA_CMD_CIPHER_HASH = 2, 55 ICP_QAT_FW_LA_CMD_HASH_CIPHER = 3, 56 ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4, 57 ICP_QAT_FW_LA_CMD_TRNG_TEST = 5, 58 ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6, 59 ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7, 60 ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8, 61 ICP_QAT_FW_LA_CMD_MGF1 = 9, 62 ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10, 63 ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11, 64 ICP_QAT_FW_LA_CMD_DELIMITER = 12 65}; 66 67#define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK 68#define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 69#define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK 70#define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 71 72struct icp_qat_fw_la_bulk_req { 73 struct icp_qat_fw_comn_req_hdr comn_hdr; 74 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars; 75 struct icp_qat_fw_comn_req_mid comn_mid; 76 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars; 77 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; 78}; 79 80#define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1 81#define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0 82#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12 83#define ICP_QAT_FW_LA_ZUC_3G_PROTO 1 84#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1 85#define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11 86#define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1 87#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1 88#define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0 89#define QAT_LA_DIGEST_IN_BUFFER_BITPOS 10 90#define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1 91#define ICP_QAT_FW_LA_SNOW_3G_PROTO 4 92#define ICP_QAT_FW_LA_GCM_PROTO 2 93#define ICP_QAT_FW_LA_CCM_PROTO 1 94#define ICP_QAT_FW_LA_NO_PROTO 0 95#define QAT_LA_PROTO_BITPOS 7 96#define QAT_LA_PROTO_MASK 0x7 97#define ICP_QAT_FW_LA_CMP_AUTH_RES 1 98#define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0 99#define QAT_LA_CMP_AUTH_RES_BITPOS 6 100#define QAT_LA_CMP_AUTH_RES_MASK 0x1 101#define ICP_QAT_FW_LA_RET_AUTH_RES 1 102#define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0 103#define QAT_LA_RET_AUTH_RES_BITPOS 5 104#define QAT_LA_RET_AUTH_RES_MASK 0x1 105#define ICP_QAT_FW_LA_UPDATE_STATE 1 106#define ICP_QAT_FW_LA_NO_UPDATE_STATE 0 107#define QAT_LA_UPDATE_STATE_BITPOS 4 108#define QAT_LA_UPDATE_STATE_MASK 0x1 109#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0 110#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1 111#define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3 112#define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1 113#define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0 114#define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1 115#define QAT_LA_CIPH_IV_FLD_BITPOS 2 116#define QAT_LA_CIPH_IV_FLD_MASK 0x1 117#define ICP_QAT_FW_LA_PARTIAL_NONE 0 118#define ICP_QAT_FW_LA_PARTIAL_START 1 119#define ICP_QAT_FW_LA_PARTIAL_MID 3 120#define ICP_QAT_FW_LA_PARTIAL_END 2 121#define QAT_LA_PARTIAL_BITPOS 0 122#define QAT_LA_PARTIAL_MASK 0x3 123#define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \ 124 cmp_auth, ret_auth, update_state, \ 125 ciph_iv, ciphcfg, partial) \ 126 (((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \ 127 QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \ 128 ((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \ 129 QAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \ 130 ((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \ 131 QAT_LA_DIGEST_IN_BUFFER_BITPOS) | \ 132 ((proto & QAT_LA_PROTO_MASK) << \ 133 QAT_LA_PROTO_BITPOS) | \ 134 ((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \ 135 QAT_LA_CMP_AUTH_RES_BITPOS) | \ 136 ((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \ 137 QAT_LA_RET_AUTH_RES_BITPOS) | \ 138 ((update_state & QAT_LA_UPDATE_STATE_MASK) << \ 139 QAT_LA_UPDATE_STATE_BITPOS) | \ 140 ((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \ 141 QAT_LA_CIPH_IV_FLD_BITPOS) | \ 142 ((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \ 143 QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \ 144 ((partial & QAT_LA_PARTIAL_MASK) << \ 145 QAT_LA_PARTIAL_BITPOS)) 146 147#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \ 148 QAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \ 149 QAT_LA_CIPH_IV_FLD_MASK) 150 151#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \ 152 QAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \ 153 QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) 154 155#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \ 156 QAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \ 157 QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) 158 159#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \ 160 QAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \ 161 QAT_LA_GCM_IV_LEN_FLAG_MASK) 162 163#define ICP_QAT_FW_LA_PROTO_GET(flags) \ 164 QAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK) 165 166#define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \ 167 QAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \ 168 QAT_LA_CMP_AUTH_RES_MASK) 169 170#define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \ 171 QAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \ 172 QAT_LA_RET_AUTH_RES_MASK) 173 174#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \ 175 QAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \ 176 QAT_LA_DIGEST_IN_BUFFER_MASK) 177 178#define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \ 179 QAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \ 180 QAT_LA_UPDATE_STATE_MASK) 181 182#define ICP_QAT_FW_LA_PARTIAL_GET(flags) \ 183 QAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \ 184 QAT_LA_PARTIAL_MASK) 185 186#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \ 187 QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \ 188 QAT_LA_CIPH_IV_FLD_MASK) 189 190#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \ 191 QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \ 192 QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) 193 194#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \ 195 QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \ 196 QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) 197 198#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \ 199 QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \ 200 QAT_LA_GCM_IV_LEN_FLAG_MASK) 201 202#define ICP_QAT_FW_LA_PROTO_SET(flags, val) \ 203 QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \ 204 QAT_LA_PROTO_MASK) 205 206#define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \ 207 QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \ 208 QAT_LA_CMP_AUTH_RES_MASK) 209 210#define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \ 211 QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \ 212 QAT_LA_RET_AUTH_RES_MASK) 213 214#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \ 215 QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \ 216 QAT_LA_DIGEST_IN_BUFFER_MASK) 217 218#define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \ 219 QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \ 220 QAT_LA_UPDATE_STATE_MASK) 221 222#define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \ 223 QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \ 224 QAT_LA_PARTIAL_MASK) 225 226struct icp_qat_fw_cipher_req_hdr_cd_pars { 227 union { 228 struct { 229 uint64_t content_desc_addr; 230 uint16_t content_desc_resrvd1; 231 uint8_t content_desc_params_sz; 232 uint8_t content_desc_hdr_resrvd2; 233 uint32_t content_desc_resrvd3; 234 } s; 235 struct { 236 uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4]; 237 } s1; 238 } u; 239}; 240 241struct icp_qat_fw_cipher_auth_req_hdr_cd_pars { 242 union { 243 struct { 244 uint64_t content_desc_addr; 245 uint16_t content_desc_resrvd1; 246 uint8_t content_desc_params_sz; 247 uint8_t content_desc_hdr_resrvd2; 248 uint32_t content_desc_resrvd3; 249 } s; 250 struct { 251 uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4]; 252 } sl; 253 } u; 254}; 255 256struct icp_qat_fw_cipher_cd_ctrl_hdr { 257 uint8_t cipher_state_sz; 258 uint8_t cipher_key_sz; 259 uint8_t cipher_cfg_offset; 260 uint8_t next_curr_id; 261 uint8_t cipher_padding_sz; 262 uint8_t resrvd1; 263 uint16_t resrvd2; 264 uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3]; 265}; 266 267struct icp_qat_fw_auth_cd_ctrl_hdr { 268 uint32_t resrvd1; 269 uint8_t resrvd2; 270 uint8_t hash_flags; 271 uint8_t hash_cfg_offset; 272 uint8_t next_curr_id; 273 uint8_t resrvd3; 274 uint8_t outer_prefix_sz; 275 uint8_t final_sz; 276 uint8_t inner_res_sz; 277 uint8_t resrvd4; 278 uint8_t inner_state1_sz; 279 uint8_t inner_state2_offset; 280 uint8_t inner_state2_sz; 281 uint8_t outer_config_offset; 282 uint8_t outer_state1_sz; 283 uint8_t outer_res_sz; 284 uint8_t outer_prefix_offset; 285}; 286 287struct icp_qat_fw_cipher_auth_cd_ctrl_hdr { 288 uint8_t cipher_state_sz; 289 uint8_t cipher_key_sz; 290 uint8_t cipher_cfg_offset; 291 uint8_t next_curr_id_cipher; 292 uint8_t cipher_padding_sz; 293 uint8_t hash_flags; 294 uint8_t hash_cfg_offset; 295 uint8_t next_curr_id_auth; 296 uint8_t resrvd1; 297 uint8_t outer_prefix_sz; 298 uint8_t final_sz; 299 uint8_t inner_res_sz; 300 uint8_t resrvd2; 301 uint8_t inner_state1_sz; 302 uint8_t inner_state2_offset; 303 uint8_t inner_state2_sz; 304 uint8_t outer_config_offset; 305 uint8_t outer_state1_sz; 306 uint8_t outer_res_sz; 307 uint8_t outer_prefix_offset; 308}; 309 310#define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1 311#define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0 312#define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX 240 313#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \ 314 (sizeof(struct icp_qat_fw_la_cipher_req_params_t)) 315#define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0) 316 317struct icp_qat_fw_la_cipher_req_params { 318 uint32_t cipher_offset; 319 uint32_t cipher_length; 320 union { 321 uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4]; 322 struct { 323 uint64_t cipher_IV_ptr; 324 uint64_t resrvd1; 325 } s; 326 } u; 327}; 328 329struct icp_qat_fw_la_auth_req_params { 330 uint32_t auth_off; 331 uint32_t auth_len; 332 union { 333 uint64_t auth_partial_st_prefix; 334 uint64_t aad_adr; 335 } u1; 336 uint64_t auth_res_addr; 337 union { 338 uint8_t inner_prefix_sz; 339 uint8_t aad_sz; 340 } u2; 341 uint8_t resrvd1; 342 uint8_t hash_state_sz; 343 uint8_t auth_res_sz; 344} __packed; 345 346struct icp_qat_fw_la_auth_req_params_resrvd_flds { 347 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6]; 348 union { 349 uint8_t inner_prefix_sz; 350 uint8_t aad_sz; 351 } u2; 352 uint8_t resrvd1; 353 uint16_t resrvd2; 354}; 355 356struct icp_qat_fw_la_resp { 357 struct icp_qat_fw_comn_resp_hdr comn_resp; 358 uint64_t opaque_data; 359 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; 360}; 361 362#define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \ 363 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \ 364 ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 365 366#define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 367{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \ 368 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \ 369 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 370 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ 371 & ICP_QAT_FW_COMN_NEXT_ID_MASK)) } 372 373#define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \ 374 (((cd_ctrl_hdr_t)->next_curr_id_cipher) \ 375 & ICP_QAT_FW_COMN_CURR_ID_MASK) 376 377#define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 378{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \ 379 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \ 380 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 381 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) } 382 383#define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \ 384 ((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \ 385 >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 386 387#define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 388{ (cd_ctrl_hdr_t)->next_curr_id_auth = \ 389 ((((cd_ctrl_hdr_t)->next_curr_id_auth) \ 390 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 391 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ 392 & ICP_QAT_FW_COMN_NEXT_ID_MASK)) } 393 394#define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \ 395 (((cd_ctrl_hdr_t)->next_curr_id_auth) \ 396 & ICP_QAT_FW_COMN_CURR_ID_MASK) 397 398#define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 399{ (cd_ctrl_hdr_t)->next_curr_id_auth = \ 400 ((((cd_ctrl_hdr_t)->next_curr_id_auth) \ 401 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 402 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) } 403 404#endif 405