1/* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21#ifndef IOATDMA_H 22#define IOATDMA_H 23 24#include <linux/dmaengine.h> 25#include "hw.h" 26#include "registers.h" 27#include <linux/init.h> 28#include <linux/dmapool.h> 29#include <linux/cache.h> 30#include <linux/pci_ids.h> 31#include <net/tcp.h> 32 33#define IOAT_DMA_VERSION "4.00" 34 35#define IOAT_LOW_COMPLETION_MASK 0xffffffc0 36#define IOAT_DMA_DCA_ANY_CPU ~0 37 38#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) 39#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) 40#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd) 41#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev) 42#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev) 43 44#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) 45 46/* 47 * workaround for IOAT ver.3.0 null descriptor issue 48 * (channel returns error when size is 0) 49 */ 50#define NULL_DESC_BUFFER_SIZE 1 51 52enum ioat_irq_mode { 53 IOAT_NOIRQ = 0, 54 IOAT_MSIX, 55 IOAT_MSI, 56 IOAT_INTX 57}; 58 59/** 60 * struct ioatdma_device - internal representation of a IOAT device 61 * @pdev: PCI-Express device 62 * @reg_base: MMIO register space base address 63 * @dma_pool: for allocating DMA descriptors 64 * @common: embedded struct dma_device 65 * @version: version of ioatdma device 66 * @msix_entries: irq handlers 67 * @idx: per channel data 68 * @dca: direct cache access context 69 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) 70 * @enumerate_channels: hw version specific channel enumeration 71 * @reset_hw: hw version specific channel (re)initialization 72 * @cleanup_fn: select between the v2 and v3 cleanup routines 73 * @timer_fn: select between the v2 and v3 timer watchdog routines 74 * @self_test: hardware version specific self test for each supported op type 75 * 76 * Note: the v3 cleanup routine supports raid operations 77 */ 78struct ioatdma_device { 79 struct pci_dev *pdev; 80 void __iomem *reg_base; 81 struct pci_pool *dma_pool; 82 struct pci_pool *completion_pool; 83#define MAX_SED_POOLS 5 84 struct dma_pool *sed_hw_pool[MAX_SED_POOLS]; 85 struct dma_device common; 86 u8 version; 87 struct msix_entry msix_entries[4]; 88 struct ioat_chan_common *idx[4]; 89 struct dca_provider *dca; 90 enum ioat_irq_mode irq_mode; 91 u32 cap; 92 void (*intr_quirk)(struct ioatdma_device *device); 93 int (*enumerate_channels)(struct ioatdma_device *device); 94 int (*reset_hw)(struct ioat_chan_common *chan); 95 void (*cleanup_fn)(unsigned long data); 96 void (*timer_fn)(unsigned long data); 97 int (*self_test)(struct ioatdma_device *device); 98}; 99 100struct ioat_chan_common { 101 struct dma_chan common; 102 void __iomem *reg_base; 103 dma_addr_t last_completion; 104 spinlock_t cleanup_lock; 105 unsigned long state; 106 #define IOAT_COMPLETION_PENDING 0 107 #define IOAT_COMPLETION_ACK 1 108 #define IOAT_RESET_PENDING 2 109 #define IOAT_KOBJ_INIT_FAIL 3 110 #define IOAT_RESHAPE_PENDING 4 111 #define IOAT_RUN 5 112 #define IOAT_CHAN_ACTIVE 6 113 struct timer_list timer; 114 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 115 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 116 #define RESET_DELAY msecs_to_jiffies(100) 117 struct ioatdma_device *device; 118 dma_addr_t completion_dma; 119 u64 *completion; 120 struct tasklet_struct cleanup_task; 121 struct kobject kobj; 122}; 123 124struct ioat_sysfs_entry { 125 struct attribute attr; 126 ssize_t (*show)(struct dma_chan *, char *); 127}; 128 129/** 130 * struct ioat_dma_chan - internal representation of a DMA channel 131 */ 132struct ioat_dma_chan { 133 struct ioat_chan_common base; 134 135 size_t xfercap; /* XFERCAP register value expanded out */ 136 137 spinlock_t desc_lock; 138 struct list_head free_desc; 139 struct list_head used_desc; 140 141 int pending; 142 u16 desccount; 143 u16 active; 144}; 145 146/** 147 * struct ioat_sed_ent - wrapper around super extended hardware descriptor 148 * @hw: hardware SED 149 * @sed_dma: dma address for the SED 150 * @list: list member 151 * @parent: point to the dma descriptor that's the parent 152 */ 153struct ioat_sed_ent { 154 struct ioat_sed_raw_descriptor *hw; 155 dma_addr_t dma; 156 struct ioat_ring_ent *parent; 157 unsigned int hw_pool; 158}; 159 160static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) 161{ 162 return container_of(c, struct ioat_chan_common, common); 163} 164 165static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c) 166{ 167 struct ioat_chan_common *chan = to_chan_common(c); 168 169 return container_of(chan, struct ioat_dma_chan, base); 170} 171 172/* wrapper around hardware descriptor format + additional software fields */ 173 174/** 175 * struct ioat_desc_sw - wrapper around hardware descriptor 176 * @hw: hardware DMA descriptor (for memcpy) 177 * @node: this descriptor will either be on the free list, 178 * or attached to a transaction list (tx_list) 179 * @txd: the generic software descriptor for all engines 180 * @id: identifier for debug 181 */ 182struct ioat_desc_sw { 183 struct ioat_dma_descriptor *hw; 184 struct list_head node; 185 size_t len; 186 struct list_head tx_list; 187 struct dma_async_tx_descriptor txd; 188 #ifdef DEBUG 189 int id; 190 #endif 191}; 192 193#ifdef DEBUG 194#define set_desc_id(desc, i) ((desc)->id = (i)) 195#define desc_id(desc) ((desc)->id) 196#else 197#define set_desc_id(desc, i) 198#define desc_id(desc) (0) 199#endif 200 201static inline void 202__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw, 203 struct dma_async_tx_descriptor *tx, int id) 204{ 205 struct device *dev = to_dev(chan); 206 207 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 208 " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id, 209 (unsigned long long) tx->phys, 210 (unsigned long long) hw->next, tx->cookie, tx->flags, 211 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 212} 213 214#define dump_desc_dbg(c, d) \ 215 ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; }) 216 217static inline struct ioat_chan_common * 218ioat_chan_by_index(struct ioatdma_device *device, int index) 219{ 220 return device->idx[index]; 221} 222 223static inline u64 ioat_chansts_32(struct ioat_chan_common *chan) 224{ 225 u8 ver = chan->device->version; 226 u64 status; 227 u32 status_lo; 228 229 /* We need to read the low address first as this causes the 230 * chipset to latch the upper bits for the subsequent read 231 */ 232 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); 233 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); 234 status <<= 32; 235 status |= status_lo; 236 237 return status; 238} 239 240#if BITS_PER_LONG == 64 241 242static inline u64 ioat_chansts(struct ioat_chan_common *chan) 243{ 244 u8 ver = chan->device->version; 245 u64 status; 246 247 /* With IOAT v3.3 the status register is 64bit. */ 248 if (ver >= IOAT_VER_3_3) 249 status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); 250 else 251 status = ioat_chansts_32(chan); 252 253 return status; 254} 255 256#else 257#define ioat_chansts ioat_chansts_32 258#endif 259 260static inline void ioat_start(struct ioat_chan_common *chan) 261{ 262 u8 ver = chan->device->version; 263 264 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 265} 266 267static inline u64 ioat_chansts_to_addr(u64 status) 268{ 269 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 270} 271 272static inline u32 ioat_chanerr(struct ioat_chan_common *chan) 273{ 274 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); 275} 276 277static inline void ioat_suspend(struct ioat_chan_common *chan) 278{ 279 u8 ver = chan->device->version; 280 281 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 282} 283 284static inline void ioat_reset(struct ioat_chan_common *chan) 285{ 286 u8 ver = chan->device->version; 287 288 writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 289} 290 291static inline bool ioat_reset_pending(struct ioat_chan_common *chan) 292{ 293 u8 ver = chan->device->version; 294 u8 cmd; 295 296 cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 297 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; 298} 299 300static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr) 301{ 302 struct ioat_chan_common *chan = &ioat->base; 303 304 writel(addr & 0x00000000FFFFFFFF, 305 chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); 306 writel(addr >> 32, 307 chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); 308} 309 310static inline bool is_ioat_active(unsigned long status) 311{ 312 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 313} 314 315static inline bool is_ioat_idle(unsigned long status) 316{ 317 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 318} 319 320static inline bool is_ioat_halted(unsigned long status) 321{ 322 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 323} 324 325static inline bool is_ioat_suspended(unsigned long status) 326{ 327 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 328} 329 330/* channel was fatally programmed */ 331static inline bool is_ioat_bug(unsigned long err) 332{ 333 return !!err; 334} 335 336int ioat_probe(struct ioatdma_device *device); 337int ioat_register(struct ioatdma_device *device); 338int ioat1_dma_probe(struct ioatdma_device *dev, int dca); 339int ioat_dma_self_test(struct ioatdma_device *device); 340void ioat_dma_remove(struct ioatdma_device *device); 341struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); 342dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan); 343void ioat_init_channel(struct ioatdma_device *device, 344 struct ioat_chan_common *chan, int idx); 345enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, 346 struct dma_tx_state *txstate); 347bool ioat_cleanup_preamble(struct ioat_chan_common *chan, 348 dma_addr_t *phys_complete); 349void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type); 350void ioat_kobject_del(struct ioatdma_device *device); 351int ioat_dma_setup_interrupts(struct ioatdma_device *device); 352void ioat_stop(struct ioat_chan_common *chan); 353extern const struct sysfs_ops ioat_sysfs_ops; 354extern struct ioat_sysfs_entry ioat_version_attr; 355extern struct ioat_sysfs_entry ioat_cap_attr; 356#endif /* IOATDMA_H */ 357