1/*
2 * amd8111_edac.h, EDAC defs for AMD8111 hypertransport chip
3 *
4 * Copyright (c) 2008 Wind River Systems, Inc.
5 *
6 * Authors:	Cao Qingtao <qingtao.cao@windriver.com>
7 * 		Benjamin Walsh <benjamin.walsh@windriver.com>
8 * 		Hu Yongqi <yongqi.hu@windriver.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef _AMD8111_EDAC_H_
25#define _AMD8111_EDAC_H_
26
27/************************************************************
28 *	PCI Bridge Status and Command Register, DevA:0x04
29 ************************************************************/
30#define REG_PCI_STSCMD	0x04
31enum pci_stscmd_bits {
32	PCI_STSCMD_SSE		= BIT(30),
33	PCI_STSCMD_RMA		= BIT(29),
34	PCI_STSCMD_RTA		= BIT(28),
35	PCI_STSCMD_SERREN	= BIT(8),
36	PCI_STSCMD_CLEAR_MASK	= (PCI_STSCMD_SSE |
37				   PCI_STSCMD_RMA |
38				   PCI_STSCMD_RTA)
39};
40
41/************************************************************
42 *	PCI Bridge Memory Base-Limit Register, DevA:0x1c
43 ************************************************************/
44#define REG_MEM_LIM     0x1c
45enum mem_limit_bits {
46	MEM_LIMIT_DPE   = BIT(31),
47	MEM_LIMIT_RSE   = BIT(30),
48	MEM_LIMIT_RMA   = BIT(29),
49	MEM_LIMIT_RTA   = BIT(28),
50	MEM_LIMIT_STA   = BIT(27),
51	MEM_LIMIT_MDPE  = BIT(24),
52	MEM_LIMIT_CLEAR_MASK  = (MEM_LIMIT_DPE |
53				 MEM_LIMIT_RSE |
54				 MEM_LIMIT_RMA |
55				 MEM_LIMIT_RTA |
56				 MEM_LIMIT_STA |
57				 MEM_LIMIT_MDPE)
58};
59
60/************************************************************
61 *	HyperTransport Link Control Register, DevA:0xc4
62 ************************************************************/
63#define REG_HT_LINK	0xc4
64enum ht_link_bits {
65	HT_LINK_LKFAIL	= BIT(4),
66	HT_LINK_CRCFEN	= BIT(1),
67	HT_LINK_CLEAR_MASK = (HT_LINK_LKFAIL)
68};
69
70/************************************************************
71 *	PCI Bridge Interrupt and Bridge Control, DevA:0x3c
72 ************************************************************/
73#define REG_PCI_INTBRG_CTRL	0x3c
74enum pci_intbrg_ctrl_bits {
75	PCI_INTBRG_CTRL_DTSERREN	= BIT(27),
76	PCI_INTBRG_CTRL_DTSTAT		= BIT(26),
77	PCI_INTBRG_CTRL_MARSP		= BIT(21),
78	PCI_INTBRG_CTRL_SERREN		= BIT(17),
79	PCI_INTBRG_CTRL_PEREN		= BIT(16),
80	PCI_INTBRG_CTRL_CLEAR_MASK	= (PCI_INTBRG_CTRL_DTSTAT),
81	PCI_INTBRG_CTRL_POLL_MASK	= (PCI_INTBRG_CTRL_DTSERREN |
82					   PCI_INTBRG_CTRL_MARSP |
83					   PCI_INTBRG_CTRL_SERREN)
84};
85
86/************************************************************
87 *		I/O Control 1 Register, DevB:0x40
88 ************************************************************/
89#define REG_IO_CTRL_1 0x40
90enum io_ctrl_1_bits {
91	IO_CTRL_1_NMIONERR	= BIT(7),
92	IO_CTRL_1_LPC_ERR	= BIT(6),
93	IO_CTRL_1_PW2LPC	= BIT(1),
94	IO_CTRL_1_CLEAR_MASK	= (IO_CTRL_1_LPC_ERR | IO_CTRL_1_PW2LPC)
95};
96
97/************************************************************
98 *		Legacy I/O Space Registers
99 ************************************************************/
100#define REG_AT_COMPAT 0x61
101enum at_compat_bits {
102	AT_COMPAT_SERR		= BIT(7),
103	AT_COMPAT_IOCHK		= BIT(6),
104	AT_COMPAT_CLRIOCHK	= BIT(3),
105	AT_COMPAT_CLRSERR	= BIT(2),
106};
107
108struct amd8111_dev_info {
109	u16 err_dev;	/* PCI Device ID */
110	struct pci_dev *dev;
111	int edac_idx;	/* device index */
112	char *ctl_name;
113	struct edac_device_ctl_info *edac_dev;
114	void (*init)(struct amd8111_dev_info *dev_info);
115	void (*exit)(struct amd8111_dev_info *dev_info);
116	void (*check)(struct edac_device_ctl_info *edac_dev);
117};
118
119struct amd8111_pci_info {
120	u16 err_dev;	/* PCI Device ID */
121	struct pci_dev *dev;
122	int edac_idx;	/* pci index */
123	const char *ctl_name;
124	struct edac_pci_ctl_info *edac_dev;
125	void (*init)(struct amd8111_pci_info *dev_info);
126	void (*exit)(struct amd8111_pci_info *dev_info);
127	void (*check)(struct edac_pci_ctl_info *edac_dev);
128};
129
130#endif /* _AMD8111_EDAC_H_ */
131