1/*
2 * Intel 3000/3010 Memory Controller kernel module
3 * Copyright (C) 2007 Akamai Technologies, Inc.
4 * Shamelessly copied from:
5 * 	Intel D82875P Memory Controller kernel module
6 * 	(C) 2003 Linux Networx (http://lnxi.com)
7 *
8 * This file may be distributed under the terms of the
9 * GNU General Public License.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/pci_ids.h>
16#include <linux/edac.h>
17#include "edac_core.h"
18
19#define I3000_REVISION		"1.1"
20
21#define EDAC_MOD_STR		"i3000_edac"
22
23#define I3000_RANKS		8
24#define I3000_RANKS_PER_CHANNEL	4
25#define I3000_CHANNELS		2
26
27/* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
28
29#define I3000_MCHBAR		0x44	/* MCH Memory Mapped Register BAR */
30#define I3000_MCHBAR_MASK	0xffffc000
31#define I3000_MMR_WINDOW_SIZE	16384
32
33#define I3000_EDEAP	0x70	/* Extended DRAM Error Address Pointer (8b)
34				 *
35				 * 7:1   reserved
36				 * 0     bit 32 of address
37				 */
38#define I3000_DEAP	0x58	/* DRAM Error Address Pointer (32b)
39				 *
40				 * 31:7  address
41				 * 6:1   reserved
42				 * 0     Error channel 0/1
43				 */
44#define I3000_DEAP_GRAIN 		(1 << 7)
45
46/*
47 * Helper functions to decode the DEAP/EDEAP hardware registers.
48 *
49 * The type promotion here is deliberate; we're deriving an
50 * unsigned long pfn and offset from hardware regs which are u8/u32.
51 */
52
53static inline unsigned long deap_pfn(u8 edeap, u32 deap)
54{
55	deap >>= PAGE_SHIFT;
56	deap |= (edeap & 1) << (32 - PAGE_SHIFT);
57	return deap;
58}
59
60static inline unsigned long deap_offset(u32 deap)
61{
62	return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
63}
64
65static inline int deap_channel(u32 deap)
66{
67	return deap & 1;
68}
69
70#define I3000_DERRSYN	0x5c	/* DRAM Error Syndrome (8b)
71				 *
72				 *  7:0  DRAM ECC Syndrome
73				 */
74
75#define I3000_ERRSTS	0xc8	/* Error Status Register (16b)
76				 *
77				 * 15:12 reserved
78				 * 11    MCH Thermal Sensor Event
79				 *         for SMI/SCI/SERR
80				 * 10    reserved
81				 *  9    LOCK to non-DRAM Memory Flag (LCKF)
82				 *  8    Received Refresh Timeout Flag (RRTOF)
83				 *  7:2  reserved
84				 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
85				 *  0    Single-bit DRAM ECC Error Flag (DSERR)
86				 */
87#define I3000_ERRSTS_BITS	0x0b03	/* bits which indicate errors */
88#define I3000_ERRSTS_UE		0x0002
89#define I3000_ERRSTS_CE		0x0001
90
91#define I3000_ERRCMD	0xca	/* Error Command (16b)
92				 *
93				 * 15:12 reserved
94				 * 11    SERR on MCH Thermal Sensor Event
95				 *         (TSESERR)
96				 * 10    reserved
97				 *  9    SERR on LOCK to non-DRAM Memory
98				 *         (LCKERR)
99				 *  8    SERR on DRAM Refresh Timeout
100				 *         (DRTOERR)
101				 *  7:2  reserved
102				 *  1    SERR Multi-Bit DRAM ECC Error
103				 *         (DMERR)
104				 *  0    SERR on Single-Bit ECC Error
105				 *         (DSERR)
106				 */
107
108/* Intel  MMIO register space - device 0 function 0 - MMR space */
109
110#define I3000_DRB_SHIFT 25	/* 32MiB grain */
111
112#define I3000_C0DRB	0x100	/* Channel 0 DRAM Rank Boundary (8b x 4)
113				 *
114				 * 7:0   Channel 0 DRAM Rank Boundary Address
115				 */
116#define I3000_C1DRB	0x180	/* Channel 1 DRAM Rank Boundary (8b x 4)
117				 *
118				 * 7:0   Channel 1 DRAM Rank Boundary Address
119				 */
120
121#define I3000_C0DRA	0x108	/* Channel 0 DRAM Rank Attribute (8b x 2)
122				 *
123				 * 7     reserved
124				 * 6:4   DRAM odd Rank Attribute
125				 * 3     reserved
126				 * 2:0   DRAM even Rank Attribute
127				 *
128				 * Each attribute defines the page
129				 * size of the corresponding rank:
130				 *     000: unpopulated
131				 *     001: reserved
132				 *     010: 4 KB
133				 *     011: 8 KB
134				 *     100: 16 KB
135				 *     Others: reserved
136				 */
137#define I3000_C1DRA	0x188	/* Channel 1 DRAM Rank Attribute (8b x 2) */
138
139static inline unsigned char odd_rank_attrib(unsigned char dra)
140{
141	return (dra & 0x70) >> 4;
142}
143
144static inline unsigned char even_rank_attrib(unsigned char dra)
145{
146	return dra & 0x07;
147}
148
149#define I3000_C0DRC0	0x120	/* DRAM Controller Mode 0 (32b)
150				 *
151				 * 31:30 reserved
152				 * 29    Initialization Complete (IC)
153				 * 28:11 reserved
154				 * 10:8  Refresh Mode Select (RMS)
155				 * 7     reserved
156				 * 6:4   Mode Select (SMS)
157				 * 3:2   reserved
158				 * 1:0   DRAM Type (DT)
159				 */
160
161#define I3000_C0DRC1	0x124	/* DRAM Controller Mode 1 (32b)
162				 *
163				 * 31    Enhanced Addressing Enable (ENHADE)
164				 * 30:0  reserved
165				 */
166
167enum i3000p_chips {
168	I3000 = 0,
169};
170
171struct i3000_dev_info {
172	const char *ctl_name;
173};
174
175struct i3000_error_info {
176	u16 errsts;
177	u8 derrsyn;
178	u8 edeap;
179	u32 deap;
180	u16 errsts2;
181};
182
183static const struct i3000_dev_info i3000_devs[] = {
184	[I3000] = {
185		.ctl_name = "i3000"},
186};
187
188static struct pci_dev *mci_pdev;
189static int i3000_registered = 1;
190static struct edac_pci_ctl_info *i3000_pci;
191
192static void i3000_get_error_info(struct mem_ctl_info *mci,
193				 struct i3000_error_info *info)
194{
195	struct pci_dev *pdev;
196
197	pdev = to_pci_dev(mci->pdev);
198
199	/*
200	 * This is a mess because there is no atomic way to read all the
201	 * registers at once and the registers can transition from CE being
202	 * overwritten by UE.
203	 */
204	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
205	if (!(info->errsts & I3000_ERRSTS_BITS))
206		return;
207	pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
208	pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
209	pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
210	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
211
212	/*
213	 * If the error is the same for both reads then the first set
214	 * of reads is valid.  If there is a change then there is a CE
215	 * with no info and the second set of reads is valid and
216	 * should be UE info.
217	 */
218	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
219		pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
220		pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
221		pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
222	}
223
224	/*
225	 * Clear any error bits.
226	 * (Yes, we really clear bits by writing 1 to them.)
227	 */
228	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
229			 I3000_ERRSTS_BITS);
230}
231
232static int i3000_process_error_info(struct mem_ctl_info *mci,
233				struct i3000_error_info *info,
234				int handle_errors)
235{
236	int row, multi_chan, channel;
237	unsigned long pfn, offset;
238
239	multi_chan = mci->csrows[0]->nr_channels - 1;
240
241	if (!(info->errsts & I3000_ERRSTS_BITS))
242		return 0;
243
244	if (!handle_errors)
245		return 1;
246
247	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
248		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
249				     -1, -1, -1,
250				     "UE overwrote CE", "");
251		info->errsts = info->errsts2;
252	}
253
254	pfn = deap_pfn(info->edeap, info->deap);
255	offset = deap_offset(info->deap);
256	channel = deap_channel(info->deap);
257
258	row = edac_mc_find_csrow_by_page(mci, pfn);
259
260	if (info->errsts & I3000_ERRSTS_UE)
261		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
262				     pfn, offset, 0,
263				     row, -1, -1,
264				     "i3000 UE", "");
265	else
266		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
267				     pfn, offset, info->derrsyn,
268				     row, multi_chan ? channel : 0, -1,
269				     "i3000 CE", "");
270
271	return 1;
272}
273
274static void i3000_check(struct mem_ctl_info *mci)
275{
276	struct i3000_error_info info;
277
278	edac_dbg(1, "MC%d\n", mci->mc_idx);
279	i3000_get_error_info(mci, &info);
280	i3000_process_error_info(mci, &info, 1);
281}
282
283static int i3000_is_interleaved(const unsigned char *c0dra,
284				const unsigned char *c1dra,
285				const unsigned char *c0drb,
286				const unsigned char *c1drb)
287{
288	int i;
289
290	/*
291	 * If the channels aren't populated identically then
292	 * we're not interleaved.
293	 */
294	for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
295		if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
296			even_rank_attrib(c0dra[i]) !=
297						even_rank_attrib(c1dra[i]))
298			return 0;
299
300	/*
301	 * If the rank boundaries for the two channels are different
302	 * then we're not interleaved.
303	 */
304	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
305		if (c0drb[i] != c1drb[i])
306			return 0;
307
308	return 1;
309}
310
311static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
312{
313	int rc;
314	int i, j;
315	struct mem_ctl_info *mci = NULL;
316	struct edac_mc_layer layers[2];
317	unsigned long last_cumul_size, nr_pages;
318	int interleaved, nr_channels;
319	unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
320	unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
321	unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
322	unsigned long mchbar;
323	void __iomem *window;
324
325	edac_dbg(0, "MC:\n");
326
327	pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
328	mchbar &= I3000_MCHBAR_MASK;
329	window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
330	if (!window) {
331		printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
332			mchbar);
333		return -ENODEV;
334	}
335
336	c0dra[0] = readb(window + I3000_C0DRA + 0);	/* ranks 0,1 */
337	c0dra[1] = readb(window + I3000_C0DRA + 1);	/* ranks 2,3 */
338	c1dra[0] = readb(window + I3000_C1DRA + 0);	/* ranks 0,1 */
339	c1dra[1] = readb(window + I3000_C1DRA + 1);	/* ranks 2,3 */
340
341	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
342		c0drb[i] = readb(window + I3000_C0DRB + i);
343		c1drb[i] = readb(window + I3000_C1DRB + i);
344	}
345
346	iounmap(window);
347
348	/*
349	 * Figure out how many channels we have.
350	 *
351	 * If we have what the datasheet calls "asymmetric channels"
352	 * (essentially the same as what was called "virtual single
353	 * channel mode" in the i82875) then it's a single channel as
354	 * far as EDAC is concerned.
355	 */
356	interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
357	nr_channels = interleaved ? 2 : 1;
358
359	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
360	layers[0].size = I3000_RANKS / nr_channels;
361	layers[0].is_virt_csrow = true;
362	layers[1].type = EDAC_MC_LAYER_CHANNEL;
363	layers[1].size = nr_channels;
364	layers[1].is_virt_csrow = false;
365	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
366	if (!mci)
367		return -ENOMEM;
368
369	edac_dbg(3, "MC: init mci\n");
370
371	mci->pdev = &pdev->dev;
372	mci->mtype_cap = MEM_FLAG_DDR2;
373
374	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
375	mci->edac_cap = EDAC_FLAG_SECDED;
376
377	mci->mod_name = EDAC_MOD_STR;
378	mci->mod_ver = I3000_REVISION;
379	mci->ctl_name = i3000_devs[dev_idx].ctl_name;
380	mci->dev_name = pci_name(pdev);
381	mci->edac_check = i3000_check;
382	mci->ctl_page_to_phys = NULL;
383
384	/*
385	 * The dram rank boundary (DRB) reg values are boundary addresses
386	 * for each DRAM rank with a granularity of 32MB.  DRB regs are
387	 * cumulative; the last one will contain the total memory
388	 * contained in all ranks.
389	 *
390	 * If we're in interleaved mode then we're only walking through
391	 * the ranks of controller 0, so we double all the values we see.
392	 */
393	for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
394		u8 value;
395		u32 cumul_size;
396		struct csrow_info *csrow = mci->csrows[i];
397
398		value = drb[i];
399		cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
400		if (interleaved)
401			cumul_size <<= 1;
402		edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
403		if (cumul_size == last_cumul_size)
404			continue;
405
406		csrow->first_page = last_cumul_size;
407		csrow->last_page = cumul_size - 1;
408		nr_pages = cumul_size - last_cumul_size;
409		last_cumul_size = cumul_size;
410
411		for (j = 0; j < nr_channels; j++) {
412			struct dimm_info *dimm = csrow->channels[j]->dimm;
413
414			dimm->nr_pages = nr_pages / nr_channels;
415			dimm->grain = I3000_DEAP_GRAIN;
416			dimm->mtype = MEM_DDR2;
417			dimm->dtype = DEV_UNKNOWN;
418			dimm->edac_mode = EDAC_UNKNOWN;
419		}
420	}
421
422	/*
423	 * Clear any error bits.
424	 * (Yes, we really clear bits by writing 1 to them.)
425	 */
426	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
427			 I3000_ERRSTS_BITS);
428
429	rc = -ENODEV;
430	if (edac_mc_add_mc(mci)) {
431		edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
432		goto fail;
433	}
434
435	/* allocating generic PCI control info */
436	i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
437	if (!i3000_pci) {
438		printk(KERN_WARNING
439			"%s(): Unable to create PCI control\n",
440			__func__);
441		printk(KERN_WARNING
442			"%s(): PCI error report via EDAC not setup\n",
443			__func__);
444	}
445
446	/* get this far and it's successful */
447	edac_dbg(3, "MC: success\n");
448	return 0;
449
450fail:
451	if (mci)
452		edac_mc_free(mci);
453
454	return rc;
455}
456
457/* returns count (>= 0), or negative on error */
458static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
459{
460	int rc;
461
462	edac_dbg(0, "MC:\n");
463
464	if (pci_enable_device(pdev) < 0)
465		return -EIO;
466
467	rc = i3000_probe1(pdev, ent->driver_data);
468	if (!mci_pdev)
469		mci_pdev = pci_dev_get(pdev);
470
471	return rc;
472}
473
474static void i3000_remove_one(struct pci_dev *pdev)
475{
476	struct mem_ctl_info *mci;
477
478	edac_dbg(0, "\n");
479
480	if (i3000_pci)
481		edac_pci_release_generic_ctl(i3000_pci);
482
483	mci = edac_mc_del_mc(&pdev->dev);
484	if (!mci)
485		return;
486
487	edac_mc_free(mci);
488}
489
490static const struct pci_device_id i3000_pci_tbl[] = {
491	{
492	 PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
493	 I3000},
494	{
495	 0,
496	 }			/* 0 terminated list. */
497};
498
499MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
500
501static struct pci_driver i3000_driver = {
502	.name = EDAC_MOD_STR,
503	.probe = i3000_init_one,
504	.remove = i3000_remove_one,
505	.id_table = i3000_pci_tbl,
506};
507
508static int __init i3000_init(void)
509{
510	int pci_rc;
511
512	edac_dbg(3, "MC:\n");
513
514       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
515       opstate_init();
516
517	pci_rc = pci_register_driver(&i3000_driver);
518	if (pci_rc < 0)
519		goto fail0;
520
521	if (!mci_pdev) {
522		i3000_registered = 0;
523		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
524					PCI_DEVICE_ID_INTEL_3000_HB, NULL);
525		if (!mci_pdev) {
526			edac_dbg(0, "i3000 pci_get_device fail\n");
527			pci_rc = -ENODEV;
528			goto fail1;
529		}
530
531		pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
532		if (pci_rc < 0) {
533			edac_dbg(0, "i3000 init fail\n");
534			pci_rc = -ENODEV;
535			goto fail1;
536		}
537	}
538
539	return 0;
540
541fail1:
542	pci_unregister_driver(&i3000_driver);
543
544fail0:
545	if (mci_pdev)
546		pci_dev_put(mci_pdev);
547
548	return pci_rc;
549}
550
551static void __exit i3000_exit(void)
552{
553	edac_dbg(3, "MC:\n");
554
555	pci_unregister_driver(&i3000_driver);
556	if (!i3000_registered) {
557		i3000_remove_one(mci_pdev);
558		pci_dev_put(mci_pdev);
559	}
560}
561
562module_init(i3000_init);
563module_exit(i3000_exit);
564
565MODULE_LICENSE("GPL");
566MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
567MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
568
569module_param(edac_op_state, int, 0444);
570MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
571