1/* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25#ifndef __INTEL_DRV_H__ 26#define __INTEL_DRV_H__ 27 28#include <linux/async.h> 29#include <linux/i2c.h> 30#include <linux/hdmi.h> 31#include <drm/i915_drm.h> 32#include "i915_drv.h" 33#include <drm/drm_crtc.h> 34#include <drm/drm_crtc_helper.h> 35#include <drm/drm_fb_helper.h> 36#include <drm/drm_dp_mst_helper.h> 37 38#define DIV_ROUND_CLOSEST_ULL(ll, d) \ 39({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) 40 41/** 42 * _wait_for - magic (register) wait macro 43 * 44 * Does the right thing for modeset paths when run under kdgb or similar atomic 45 * contexts. Note that it's important that we check the condition again after 46 * having timed out, since the timeout could be due to preemption or similar and 47 * we've never had a chance to check the condition before the timeout. 48 */ 49#define _wait_for(COND, MS, W) ({ \ 50 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 51 int ret__ = 0; \ 52 while (!(COND)) { \ 53 if (time_after(jiffies, timeout__)) { \ 54 if (!(COND)) \ 55 ret__ = -ETIMEDOUT; \ 56 break; \ 57 } \ 58 if (W && drm_can_sleep()) { \ 59 msleep(W); \ 60 } else { \ 61 cpu_relax(); \ 62 } \ 63 } \ 64 ret__; \ 65}) 66 67#define wait_for(COND, MS) _wait_for(COND, MS, 1) 68#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 69#define wait_for_atomic_us(COND, US) _wait_for((COND), \ 70 DIV_ROUND_UP((US), 1000), 0) 71 72#define KHz(x) (1000 * (x)) 73#define MHz(x) KHz(1000 * (x)) 74 75/* 76 * Display related stuff 77 */ 78 79/* store information about an Ixxx DVO */ 80/* The i830->i865 use multiple DVOs with multiple i2cs */ 81/* the i915, i945 have a single sDVO i2c bus - which is different */ 82#define MAX_OUTPUTS 6 83/* maximum connectors per crtcs in the mode set */ 84 85/* Maximum cursor sizes */ 86#define GEN2_CURSOR_WIDTH 64 87#define GEN2_CURSOR_HEIGHT 64 88#define MAX_CURSOR_WIDTH 256 89#define MAX_CURSOR_HEIGHT 256 90 91#define INTEL_I2C_BUS_DVO 1 92#define INTEL_I2C_BUS_SDVO 2 93 94/* these are outputs from the chip - integrated only 95 external chips are via DVO or SDVO output */ 96#define INTEL_OUTPUT_UNUSED 0 97#define INTEL_OUTPUT_ANALOG 1 98#define INTEL_OUTPUT_DVO 2 99#define INTEL_OUTPUT_SDVO 3 100#define INTEL_OUTPUT_LVDS 4 101#define INTEL_OUTPUT_TVOUT 5 102#define INTEL_OUTPUT_HDMI 6 103#define INTEL_OUTPUT_DISPLAYPORT 7 104#define INTEL_OUTPUT_EDP 8 105#define INTEL_OUTPUT_DSI 9 106#define INTEL_OUTPUT_UNKNOWN 10 107#define INTEL_OUTPUT_DP_MST 11 108 109#define INTEL_DVO_CHIP_NONE 0 110#define INTEL_DVO_CHIP_LVDS 1 111#define INTEL_DVO_CHIP_TMDS 2 112#define INTEL_DVO_CHIP_TVOUT 4 113 114#define INTEL_DSI_VIDEO_MODE 0 115#define INTEL_DSI_COMMAND_MODE 1 116 117struct intel_framebuffer { 118 struct drm_framebuffer base; 119 struct drm_i915_gem_object *obj; 120}; 121 122struct intel_fbdev { 123 struct drm_fb_helper helper; 124 struct intel_framebuffer *fb; 125 struct list_head fbdev_list; 126 struct drm_display_mode *our_mode; 127 int preferred_bpp; 128}; 129 130struct intel_encoder { 131 struct drm_encoder base; 132 /* 133 * The new crtc this encoder will be driven from. Only differs from 134 * base->crtc while a modeset is in progress. 135 */ 136 struct intel_crtc *new_crtc; 137 138 int type; 139 unsigned int cloneable; 140 bool connectors_active; 141 void (*hot_plug)(struct intel_encoder *); 142 bool (*compute_config)(struct intel_encoder *, 143 struct intel_crtc_config *); 144 void (*pre_pll_enable)(struct intel_encoder *); 145 void (*pre_enable)(struct intel_encoder *); 146 void (*enable)(struct intel_encoder *); 147 void (*mode_set)(struct intel_encoder *intel_encoder); 148 void (*disable)(struct intel_encoder *); 149 void (*post_disable)(struct intel_encoder *); 150 /* Read out the current hw state of this connector, returning true if 151 * the encoder is active. If the encoder is enabled it also set the pipe 152 * it is connected to in the pipe parameter. */ 153 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 154 /* Reconstructs the equivalent mode flags for the current hardware 155 * state. This must be called _after_ display->get_pipe_config has 156 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 157 * be set correctly before calling this function. */ 158 void (*get_config)(struct intel_encoder *, 159 struct intel_crtc_config *pipe_config); 160 /* 161 * Called during system suspend after all pending requests for the 162 * encoder are flushed (for example for DP AUX transactions) and 163 * device interrupts are disabled. 164 */ 165 void (*suspend)(struct intel_encoder *); 166 int crtc_mask; 167 enum hpd_pin hpd_pin; 168}; 169 170struct intel_panel { 171 struct drm_display_mode *fixed_mode; 172 struct drm_display_mode *downclock_mode; 173 int fitting_mode; 174 175 /* backlight */ 176 struct { 177 bool present; 178 u32 level; 179 u32 min; 180 u32 max; 181 bool enabled; 182 bool combination_mode; /* gen 2/4 only */ 183 bool active_low_pwm; 184 struct backlight_device *device; 185 } backlight; 186 187 void (*backlight_power)(struct intel_connector *, bool enable); 188}; 189 190struct intel_connector { 191 struct drm_connector base; 192 /* 193 * The fixed encoder this connector is connected to. 194 */ 195 struct intel_encoder *encoder; 196 197 /* 198 * The new encoder this connector will be driven. Only differs from 199 * encoder while a modeset is in progress. 200 */ 201 struct intel_encoder *new_encoder; 202 203 /* Reads out the current hw, returning true if the connector is enabled 204 * and active (i.e. dpms ON state). */ 205 bool (*get_hw_state)(struct intel_connector *); 206 207 /* 208 * Removes all interfaces through which the connector is accessible 209 * - like sysfs, debugfs entries -, so that no new operations can be 210 * started on the connector. Also makes sure all currently pending 211 * operations finish before returing. 212 */ 213 void (*unregister)(struct intel_connector *); 214 215 /* Panel info for eDP and LVDS */ 216 struct intel_panel panel; 217 218 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 219 struct edid *edid; 220 struct edid *detect_edid; 221 222 /* since POLL and HPD connectors may use the same HPD line keep the native 223 state of connector->polled in case hotplug storm detection changes it */ 224 u8 polled; 225 226 void *port; /* store this opaque as its illegal to dereference it */ 227 228 struct intel_dp *mst_port; 229}; 230 231typedef struct dpll { 232 /* given values */ 233 int n; 234 int m1, m2; 235 int p1, p2; 236 /* derived values */ 237 int dot; 238 int vco; 239 int m; 240 int p; 241} intel_clock_t; 242 243struct intel_plane_config { 244 bool tiled; 245 int size; 246 u32 base; 247}; 248 249struct intel_crtc_config { 250 /** 251 * quirks - bitfield with hw state readout quirks 252 * 253 * For various reasons the hw state readout code might not be able to 254 * completely faithfully read out the current state. These cases are 255 * tracked with quirk flags so that fastboot and state checker can act 256 * accordingly. 257 */ 258#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 259#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ 260 unsigned long quirks; 261 262 /* User requested mode, only valid as a starting point to 263 * compute adjusted_mode, except in the case of (S)DVO where 264 * it's also for the output timings of the (S)DVO chip. 265 * adjusted_mode will then correspond to the S(DVO) chip's 266 * preferred input timings. */ 267 struct drm_display_mode requested_mode; 268 /* Actual pipe timings ie. what we program into the pipe timing 269 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ 270 struct drm_display_mode adjusted_mode; 271 272 /* Pipe source size (ie. panel fitter input size) 273 * All planes will be positioned inside this space, 274 * and get clipped at the edges. */ 275 int pipe_src_w, pipe_src_h; 276 277 /* Whether to set up the PCH/FDI. Note that we never allow sharing 278 * between pch encoders and cpu encoders. */ 279 bool has_pch_encoder; 280 281 /* CPU Transcoder for the pipe. Currently this can only differ from the 282 * pipe on Haswell (where we have a special eDP transcoder). */ 283 enum transcoder cpu_transcoder; 284 285 /* 286 * Use reduced/limited/broadcast rbg range, compressing from the full 287 * range fed into the crtcs. 288 */ 289 bool limited_color_range; 290 291 /* DP has a bunch of special case unfortunately, so mark the pipe 292 * accordingly. */ 293 bool has_dp_encoder; 294 295 /* Whether we should send NULL infoframes. Required for audio. */ 296 bool has_hdmi_sink; 297 298 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 299 * has_dp_encoder is set. */ 300 bool has_audio; 301 302 /* 303 * Enable dithering, used when the selected pipe bpp doesn't match the 304 * plane bpp. 305 */ 306 bool dither; 307 308 /* Controls for the clock computation, to override various stages. */ 309 bool clock_set; 310 311 /* SDVO TV has a bunch of special case. To make multifunction encoders 312 * work correctly, we need to track this at runtime.*/ 313 bool sdvo_tv_clock; 314 315 /* 316 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 317 * required. This is set in the 2nd loop of calling encoder's 318 * ->compute_config if the first pick doesn't work out. 319 */ 320 bool bw_constrained; 321 322 /* Settings for the intel dpll used on pretty much everything but 323 * haswell. */ 324 struct dpll dpll; 325 326 /* Selected dpll when shared or DPLL_ID_PRIVATE. */ 327 enum intel_dpll_id shared_dpll; 328 329 /* PORT_CLK_SEL for DDI ports. */ 330 uint32_t ddi_pll_sel; 331 332 /* Actual register state of the dpll, for shared dpll cross-checking. */ 333 struct intel_dpll_hw_state dpll_hw_state; 334 335 int pipe_bpp; 336 struct intel_link_m_n dp_m_n; 337 338 /* m2_n2 for eDP downclock */ 339 struct intel_link_m_n dp_m2_n2; 340 bool has_drrs; 341 342 /* 343 * Frequence the dpll for the port should run at. Differs from the 344 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also 345 * already multiplied by pixel_multiplier. 346 */ 347 int port_clock; 348 349 /* Used by SDVO (and if we ever fix it, HDMI). */ 350 unsigned pixel_multiplier; 351 352 /* Panel fitter controls for gen2-gen4 + VLV */ 353 struct { 354 u32 control; 355 u32 pgm_ratios; 356 u32 lvds_border_bits; 357 } gmch_pfit; 358 359 /* Panel fitter placement and size for Ironlake+ */ 360 struct { 361 u32 pos; 362 u32 size; 363 bool enabled; 364 bool force_thru; 365 } pch_pfit; 366 367 /* FDI configuration, only valid if has_pch_encoder is set. */ 368 int fdi_lanes; 369 struct intel_link_m_n fdi_m_n; 370 371 bool ips_enabled; 372 373 bool double_wide; 374 375 bool dp_encoder_is_mst; 376 int pbn; 377}; 378 379struct intel_pipe_wm { 380 struct intel_wm_level wm[5]; 381 uint32_t linetime; 382 bool fbc_wm_enabled; 383 bool pipe_enabled; 384 bool sprites_enabled; 385 bool sprites_scaled; 386}; 387 388struct intel_mmio_flip { 389 u32 seqno; 390 u32 ring_id; 391}; 392 393struct intel_crtc { 394 struct drm_crtc base; 395 enum pipe pipe; 396 enum plane plane; 397 u8 lut_r[256], lut_g[256], lut_b[256]; 398 /* 399 * Whether the crtc and the connected output pipeline is active. Implies 400 * that crtc->enabled is set, i.e. the current mode configuration has 401 * some outputs connected to this crtc. 402 */ 403 bool active; 404 unsigned long enabled_power_domains; 405 bool primary_enabled; /* is the primary plane (partially) visible? */ 406 bool lowfreq_avail; 407 struct intel_overlay *overlay; 408 struct intel_unpin_work *unpin_work; 409 410 atomic_t unpin_work_count; 411 412 /* Display surface base address adjustement for pageflips. Note that on 413 * gen4+ this only adjusts up to a tile, offsets within a tile are 414 * handled in the hw itself (with the TILEOFF register). */ 415 unsigned long dspaddr_offset; 416 417 struct drm_i915_gem_object *cursor_bo; 418 uint32_t cursor_addr; 419 int16_t cursor_width, cursor_height; 420 uint32_t cursor_cntl; 421 uint32_t cursor_size; 422 uint32_t cursor_base; 423 424 struct intel_plane_config plane_config; 425 struct intel_crtc_config config; 426 struct intel_crtc_config *new_config; 427 bool new_enabled; 428 429 /* reset counter value when the last flip was submitted */ 430 unsigned int reset_counter; 431 432 /* Access to these should be protected by dev_priv->irq_lock. */ 433 bool cpu_fifo_underrun_disabled; 434 bool pch_fifo_underrun_disabled; 435 436 /* per-pipe watermark state */ 437 struct { 438 /* watermarks currently being used */ 439 struct intel_pipe_wm active; 440 } wm; 441 442 int scanline_offset; 443 struct intel_mmio_flip mmio_flip; 444}; 445 446struct intel_plane_wm_parameters { 447 uint32_t horiz_pixels; 448 uint32_t vert_pixels; 449 uint8_t bytes_per_pixel; 450 bool enabled; 451 bool scaled; 452}; 453 454struct intel_plane { 455 struct drm_plane base; 456 int plane; 457 enum pipe pipe; 458 struct drm_i915_gem_object *obj; 459 bool can_scale; 460 int max_downscale; 461 int crtc_x, crtc_y; 462 unsigned int crtc_w, crtc_h; 463 uint32_t src_x, src_y; 464 uint32_t src_w, src_h; 465 unsigned int rotation; 466 467 /* Since we need to change the watermarks before/after 468 * enabling/disabling the planes, we need to store the parameters here 469 * as the other pieces of the struct may not reflect the values we want 470 * for the watermark calculations. Currently only Haswell uses this. 471 */ 472 struct intel_plane_wm_parameters wm; 473 474 void (*update_plane)(struct drm_plane *plane, 475 struct drm_crtc *crtc, 476 struct drm_framebuffer *fb, 477 struct drm_i915_gem_object *obj, 478 int crtc_x, int crtc_y, 479 unsigned int crtc_w, unsigned int crtc_h, 480 uint32_t x, uint32_t y, 481 uint32_t src_w, uint32_t src_h); 482 void (*disable_plane)(struct drm_plane *plane, 483 struct drm_crtc *crtc); 484 int (*update_colorkey)(struct drm_plane *plane, 485 struct drm_intel_sprite_colorkey *key); 486 void (*get_colorkey)(struct drm_plane *plane, 487 struct drm_intel_sprite_colorkey *key); 488}; 489 490struct intel_watermark_params { 491 unsigned long fifo_size; 492 unsigned long max_wm; 493 unsigned long default_wm; 494 unsigned long guard_size; 495 unsigned long cacheline_size; 496}; 497 498struct cxsr_latency { 499 int is_desktop; 500 int is_ddr3; 501 unsigned long fsb_freq; 502 unsigned long mem_freq; 503 unsigned long display_sr; 504 unsigned long display_hpll_disable; 505 unsigned long cursor_sr; 506 unsigned long cursor_hpll_disable; 507}; 508 509#define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 510#define to_intel_connector(x) container_of(x, struct intel_connector, base) 511#define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 512#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 513#define to_intel_plane(x) container_of(x, struct intel_plane, base) 514#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) 515 516struct intel_hdmi { 517 u32 hdmi_reg; 518 int ddc_bus; 519 uint32_t color_range; 520 bool color_range_auto; 521 bool has_hdmi_sink; 522 bool has_audio; 523 enum hdmi_force_audio force_audio; 524 bool rgb_quant_range_selectable; 525 enum hdmi_picture_aspect aspect_ratio; 526 void (*write_infoframe)(struct drm_encoder *encoder, 527 enum hdmi_infoframe_type type, 528 const void *frame, ssize_t len); 529 void (*set_infoframes)(struct drm_encoder *encoder, 530 bool enable, 531 struct drm_display_mode *adjusted_mode); 532}; 533 534struct intel_dp_mst_encoder; 535#define DP_MAX_DOWNSTREAM_PORTS 0x10 536 537/** 538 * HIGH_RR is the highest eDP panel refresh rate read from EDID 539 * LOW_RR is the lowest eDP panel refresh rate found from EDID 540 * parsing for same resolution. 541 */ 542enum edp_drrs_refresh_rate_type { 543 DRRS_HIGH_RR, 544 DRRS_LOW_RR, 545 DRRS_MAX_RR, /* RR count */ 546}; 547 548struct intel_dp { 549 uint32_t output_reg; 550 uint32_t aux_ch_ctl_reg; 551 uint32_t DP; 552 bool has_audio; 553 enum hdmi_force_audio force_audio; 554 uint32_t color_range; 555 bool color_range_auto; 556 uint8_t link_bw; 557 uint8_t lane_count; 558 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 559 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 560 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 561 struct drm_dp_aux aux; 562 uint8_t train_set[4]; 563 int panel_power_up_delay; 564 int panel_power_down_delay; 565 int panel_power_cycle_delay; 566 int backlight_on_delay; 567 int backlight_off_delay; 568 struct delayed_work panel_vdd_work; 569 bool want_panel_vdd; 570 unsigned long last_power_cycle; 571 unsigned long last_power_on; 572 unsigned long last_backlight_off; 573 574 struct notifier_block edp_notifier; 575 576 /* 577 * Pipe whose power sequencer is currently locked into 578 * this port. Only relevant on VLV/CHV. 579 */ 580 enum pipe pps_pipe; 581 582 bool use_tps3; 583 bool can_mst; /* this port supports mst */ 584 bool is_mst; 585 int active_mst_links; 586 /* connector directly attached - won't be use for modeset in mst world */ 587 struct intel_connector *attached_connector; 588 589 /* mst connector list */ 590 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 591 struct drm_dp_mst_topology_mgr mst_mgr; 592 593 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); 594 /* 595 * This function returns the value we have to program the AUX_CTL 596 * register with to kick off an AUX transaction. 597 */ 598 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, 599 bool has_aux_irq, 600 int send_bytes, 601 uint32_t aux_clock_divider); 602 struct { 603 enum drrs_support_type type; 604 enum edp_drrs_refresh_rate_type refresh_rate_type; 605 struct mutex mutex; 606 } drrs_state; 607 608}; 609 610struct intel_digital_port { 611 struct intel_encoder base; 612 enum port port; 613 u32 saved_port_bits; 614 struct intel_dp dp; 615 struct intel_hdmi hdmi; 616 bool (*hpd_pulse)(struct intel_digital_port *, bool); 617}; 618 619struct intel_dp_mst_encoder { 620 struct intel_encoder base; 621 enum pipe pipe; 622 struct intel_digital_port *primary; 623 void *port; /* store this opaque as its illegal to dereference it */ 624}; 625 626static inline int 627vlv_dport_to_channel(struct intel_digital_port *dport) 628{ 629 switch (dport->port) { 630 case PORT_B: 631 case PORT_D: 632 return DPIO_CH0; 633 case PORT_C: 634 return DPIO_CH1; 635 default: 636 BUG(); 637 } 638} 639 640static inline int 641vlv_pipe_to_channel(enum pipe pipe) 642{ 643 switch (pipe) { 644 case PIPE_A: 645 case PIPE_C: 646 return DPIO_CH0; 647 case PIPE_B: 648 return DPIO_CH1; 649 default: 650 BUG(); 651 } 652} 653 654static inline struct drm_crtc * 655intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 656{ 657 struct drm_i915_private *dev_priv = dev->dev_private; 658 return dev_priv->pipe_to_crtc_mapping[pipe]; 659} 660 661static inline struct drm_crtc * 662intel_get_crtc_for_plane(struct drm_device *dev, int plane) 663{ 664 struct drm_i915_private *dev_priv = dev->dev_private; 665 return dev_priv->plane_to_crtc_mapping[plane]; 666} 667 668struct intel_unpin_work { 669 struct work_struct work; 670 struct drm_crtc *crtc; 671 struct drm_i915_gem_object *old_fb_obj; 672 struct drm_i915_gem_object *pending_flip_obj; 673 struct drm_pending_vblank_event *event; 674 atomic_t pending; 675#define INTEL_FLIP_INACTIVE 0 676#define INTEL_FLIP_PENDING 1 677#define INTEL_FLIP_COMPLETE 2 678 u32 flip_count; 679 u32 gtt_offset; 680 struct intel_engine_cs *flip_queued_ring; 681 u32 flip_queued_seqno; 682 int flip_queued_vblank; 683 int flip_ready_vblank; 684 bool enable_stall_check; 685}; 686 687struct intel_set_config { 688 struct drm_encoder **save_connector_encoders; 689 struct drm_crtc **save_encoder_crtcs; 690 bool *save_crtc_enabled; 691 692 bool fb_changed; 693 bool mode_changed; 694}; 695 696struct intel_load_detect_pipe { 697 struct drm_framebuffer *release_fb; 698 bool load_detect_temp; 699 int dpms_mode; 700}; 701 702static inline struct intel_encoder * 703intel_attached_encoder(struct drm_connector *connector) 704{ 705 return to_intel_connector(connector)->encoder; 706} 707 708static inline struct intel_digital_port * 709enc_to_dig_port(struct drm_encoder *encoder) 710{ 711 return container_of(encoder, struct intel_digital_port, base.base); 712} 713 714static inline struct intel_dp_mst_encoder * 715enc_to_mst(struct drm_encoder *encoder) 716{ 717 return container_of(encoder, struct intel_dp_mst_encoder, base.base); 718} 719 720static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 721{ 722 return &enc_to_dig_port(encoder)->dp; 723} 724 725static inline struct intel_digital_port * 726dp_to_dig_port(struct intel_dp *intel_dp) 727{ 728 return container_of(intel_dp, struct intel_digital_port, dp); 729} 730 731static inline struct intel_digital_port * 732hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 733{ 734 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 735} 736 737 738/* i915_irq.c */ 739bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 740 enum pipe pipe, bool enable); 741bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, 742 enum transcoder pch_transcoder, 743 bool enable); 744void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 745void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 746void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 747void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 748void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 749void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 750void intel_runtime_pm_disable_interrupts(struct drm_device *dev); 751void intel_runtime_pm_restore_interrupts(struct drm_device *dev); 752static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 753{ 754 /* 755 * We only use drm_irq_uninstall() at unload and VT switch, so 756 * this is the only thing we need to check. 757 */ 758 return !dev_priv->pm._irqs_disabled; 759} 760 761int intel_get_crtc_scanline(struct intel_crtc *crtc); 762void i9xx_check_fifo_underruns(struct drm_device *dev); 763void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); 764 765/* intel_crt.c */ 766void intel_crt_init(struct drm_device *dev); 767 768 769/* intel_ddi.c */ 770void intel_prepare_ddi(struct drm_device *dev); 771void hsw_fdi_link_train(struct drm_crtc *crtc); 772void intel_ddi_init(struct drm_device *dev, enum port port); 773enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); 774bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); 775int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); 776void intel_ddi_pll_init(struct drm_device *dev); 777void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); 778void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 779 enum transcoder cpu_transcoder); 780void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 781void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 782bool intel_ddi_pll_select(struct intel_crtc *crtc); 783void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 784void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 785bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 786void intel_ddi_fdi_disable(struct drm_crtc *crtc); 787void intel_ddi_get_config(struct intel_encoder *encoder, 788 struct intel_crtc_config *pipe_config); 789 790void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); 791void intel_ddi_clock_get(struct intel_encoder *encoder, 792 struct intel_crtc_config *pipe_config); 793void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); 794 795/* intel_display.c */ 796const char *intel_output_name(int output); 797bool intel_has_pending_fb_unpin(struct drm_device *dev); 798int intel_pch_rawclk(struct drm_device *dev); 799void intel_mark_busy(struct drm_device *dev); 800void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, 801 struct intel_engine_cs *ring); 802void intel_frontbuffer_flip_prepare(struct drm_device *dev, 803 unsigned frontbuffer_bits); 804void intel_frontbuffer_flip_complete(struct drm_device *dev, 805 unsigned frontbuffer_bits); 806void intel_frontbuffer_flush(struct drm_device *dev, 807 unsigned frontbuffer_bits); 808/** 809 * intel_frontbuffer_flip - prepare frontbuffer flip 810 * @dev: DRM device 811 * @frontbuffer_bits: frontbuffer plane tracking bits 812 * 813 * This function gets called after scheduling a flip on @obj. This is for 814 * synchronous plane updates which will happen on the next vblank and which will 815 * not get delayed by pending gpu rendering. 816 * 817 * Can be called without any locks held. 818 */ 819static inline 820void intel_frontbuffer_flip(struct drm_device *dev, 821 unsigned frontbuffer_bits) 822{ 823 intel_frontbuffer_flush(dev, frontbuffer_bits); 824} 825 826void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); 827void intel_mark_idle(struct drm_device *dev); 828void intel_crtc_restore_mode(struct drm_crtc *crtc); 829void intel_crtc_control(struct drm_crtc *crtc, bool enable); 830void intel_crtc_update_dpms(struct drm_crtc *crtc); 831void intel_encoder_destroy(struct drm_encoder *encoder); 832void intel_connector_dpms(struct drm_connector *, int mode); 833bool intel_connector_get_hw_state(struct intel_connector *connector); 834void intel_modeset_check_state(struct drm_device *dev); 835bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 836 struct intel_digital_port *port); 837void intel_connector_attach_encoder(struct intel_connector *connector, 838 struct intel_encoder *encoder); 839struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 840struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 841 struct drm_crtc *crtc); 842enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); 843int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 844 struct drm_file *file_priv); 845enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 846 enum pipe pipe); 847void intel_wait_for_vblank(struct drm_device *dev, int pipe); 848int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 849void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 850 struct intel_digital_port *dport); 851bool intel_get_load_detect_pipe(struct drm_connector *connector, 852 struct drm_display_mode *mode, 853 struct intel_load_detect_pipe *old, 854 struct drm_modeset_acquire_ctx *ctx); 855void intel_release_load_detect_pipe(struct drm_connector *connector, 856 struct intel_load_detect_pipe *old); 857int intel_pin_and_fence_fb_obj(struct drm_device *dev, 858 struct drm_i915_gem_object *obj, 859 struct intel_engine_cs *pipelined); 860void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 861struct drm_framebuffer * 862__intel_framebuffer_create(struct drm_device *dev, 863 struct drm_mode_fb_cmd2 *mode_cmd, 864 struct drm_i915_gem_object *obj); 865void intel_prepare_page_flip(struct drm_device *dev, int plane); 866void intel_finish_page_flip(struct drm_device *dev, int pipe); 867void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 868void intel_check_page_flip(struct drm_device *dev, int pipe); 869 870/* shared dpll functions */ 871struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); 872void assert_shared_dpll(struct drm_i915_private *dev_priv, 873 struct intel_shared_dpll *pll, 874 bool state); 875#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 876#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 877struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc); 878void intel_put_shared_dpll(struct intel_crtc *crtc); 879 880/* modesetting asserts */ 881void assert_pll(struct drm_i915_private *dev_priv, 882 enum pipe pipe, bool state); 883#define assert_pll_enabled(d, p) assert_pll(d, p, true) 884#define assert_pll_disabled(d, p) assert_pll(d, p, false) 885void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 886 enum pipe pipe, bool state); 887#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 888#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 889void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); 890#define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 891#define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 892void intel_write_eld(struct drm_encoder *encoder, 893 struct drm_display_mode *mode); 894unsigned long intel_gen4_compute_page_offset(int *x, int *y, 895 unsigned int tiling_mode, 896 unsigned int bpp, 897 unsigned int pitch); 898void intel_display_handle_reset(struct drm_device *dev); 899void hsw_enable_pc8(struct drm_i915_private *dev_priv); 900void hsw_disable_pc8(struct drm_i915_private *dev_priv); 901void intel_dp_get_m_n(struct intel_crtc *crtc, 902 struct intel_crtc_config *pipe_config); 903void intel_dp_set_m_n(struct intel_crtc *crtc); 904int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 905void 906ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, 907 int dotclock); 908bool intel_crtc_active(struct drm_crtc *crtc); 909void hsw_enable_ips(struct intel_crtc *crtc); 910void hsw_disable_ips(struct intel_crtc *crtc); 911void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); 912enum intel_display_power_domain 913intel_display_port_power_domain(struct intel_encoder *intel_encoder); 914void intel_mode_from_pipe_config(struct drm_display_mode *mode, 915 struct intel_crtc_config *pipe_config); 916int intel_format_to_fourcc(int format); 917void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); 918void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); 919 920/* intel_dp.c */ 921void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); 922bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 923 struct intel_connector *intel_connector); 924void intel_dp_start_link_train(struct intel_dp *intel_dp); 925void intel_dp_complete_link_train(struct intel_dp *intel_dp); 926void intel_dp_stop_link_train(struct intel_dp *intel_dp); 927void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 928void intel_dp_encoder_destroy(struct drm_encoder *encoder); 929void intel_dp_check_link_status(struct intel_dp *intel_dp); 930int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); 931bool intel_dp_compute_config(struct intel_encoder *encoder, 932 struct intel_crtc_config *pipe_config); 933bool intel_dp_is_edp(struct drm_device *dev, enum port port); 934bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, 935 bool long_hpd); 936void intel_edp_backlight_on(struct intel_dp *intel_dp); 937void intel_edp_backlight_off(struct intel_dp *intel_dp); 938void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); 939void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder); 940void intel_edp_panel_on(struct intel_dp *intel_dp); 941void intel_edp_panel_off(struct intel_dp *intel_dp); 942void intel_edp_psr_enable(struct intel_dp *intel_dp); 943void intel_edp_psr_disable(struct intel_dp *intel_dp); 944void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); 945void intel_edp_psr_invalidate(struct drm_device *dev, 946 unsigned frontbuffer_bits); 947void intel_edp_psr_flush(struct drm_device *dev, 948 unsigned frontbuffer_bits); 949void intel_edp_psr_init(struct drm_device *dev); 950 951int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd); 952void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); 953void intel_dp_mst_suspend(struct drm_device *dev); 954void intel_dp_mst_resume(struct drm_device *dev); 955int intel_dp_max_link_bw(struct intel_dp *intel_dp); 956void intel_dp_hot_plug(struct intel_encoder *intel_encoder); 957void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); 958/* intel_dp_mst.c */ 959int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); 960void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); 961/* intel_dsi.c */ 962void intel_dsi_init(struct drm_device *dev); 963 964 965/* intel_dvo.c */ 966void intel_dvo_init(struct drm_device *dev); 967 968 969/* legacy fbdev emulation in intel_fbdev.c */ 970#ifdef CONFIG_DRM_I915_FBDEV 971extern int intel_fbdev_init(struct drm_device *dev); 972extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); 973extern void intel_fbdev_fini(struct drm_device *dev); 974extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); 975extern void intel_fbdev_output_poll_changed(struct drm_device *dev); 976extern void intel_fbdev_restore_mode(struct drm_device *dev); 977#else 978static inline int intel_fbdev_init(struct drm_device *dev) 979{ 980 return 0; 981} 982 983static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) 984{ 985} 986 987static inline void intel_fbdev_fini(struct drm_device *dev) 988{ 989} 990 991static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) 992{ 993} 994 995static inline void intel_fbdev_restore_mode(struct drm_device *dev) 996{ 997} 998#endif 999 1000/* intel_hdmi.c */ 1001void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); 1002void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1003 struct intel_connector *intel_connector); 1004struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 1005bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1006 struct intel_crtc_config *pipe_config); 1007 1008 1009/* intel_lvds.c */ 1010void intel_lvds_init(struct drm_device *dev); 1011bool intel_is_dual_link_lvds(struct drm_device *dev); 1012 1013 1014/* intel_modes.c */ 1015int intel_connector_update_modes(struct drm_connector *connector, 1016 struct edid *edid); 1017int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); 1018void intel_attach_force_audio_property(struct drm_connector *connector); 1019void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 1020 1021 1022/* intel_overlay.c */ 1023void intel_setup_overlay(struct drm_device *dev); 1024void intel_cleanup_overlay(struct drm_device *dev); 1025int intel_overlay_switch_off(struct intel_overlay *overlay); 1026int intel_overlay_put_image(struct drm_device *dev, void *data, 1027 struct drm_file *file_priv); 1028int intel_overlay_attrs(struct drm_device *dev, void *data, 1029 struct drm_file *file_priv); 1030 1031 1032/* intel_panel.c */ 1033int intel_panel_init(struct intel_panel *panel, 1034 struct drm_display_mode *fixed_mode, 1035 struct drm_display_mode *downclock_mode); 1036void intel_panel_fini(struct intel_panel *panel); 1037void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, 1038 struct drm_display_mode *adjusted_mode); 1039void intel_pch_panel_fitting(struct intel_crtc *crtc, 1040 struct intel_crtc_config *pipe_config, 1041 int fitting_mode); 1042void intel_gmch_panel_fitting(struct intel_crtc *crtc, 1043 struct intel_crtc_config *pipe_config, 1044 int fitting_mode); 1045void intel_panel_set_backlight_acpi(struct intel_connector *connector, 1046 u32 level, u32 max); 1047int intel_panel_setup_backlight(struct drm_connector *connector); 1048void intel_panel_enable_backlight(struct intel_connector *connector); 1049void intel_panel_disable_backlight(struct intel_connector *connector); 1050void intel_panel_destroy_backlight(struct drm_connector *connector); 1051void intel_panel_init_backlight_funcs(struct drm_device *dev); 1052enum drm_connector_status intel_panel_detect(struct drm_device *dev); 1053extern struct drm_display_mode *intel_find_panel_downclock( 1054 struct drm_device *dev, 1055 struct drm_display_mode *fixed_mode, 1056 struct drm_connector *connector); 1057 1058/* intel_pm.c */ 1059void intel_init_clock_gating(struct drm_device *dev); 1060void intel_suspend_hw(struct drm_device *dev); 1061int ilk_wm_max_level(const struct drm_device *dev); 1062void intel_update_watermarks(struct drm_crtc *crtc); 1063void intel_update_sprite_watermarks(struct drm_plane *plane, 1064 struct drm_crtc *crtc, 1065 uint32_t sprite_width, 1066 uint32_t sprite_height, 1067 int pixel_size, 1068 bool enabled, bool scaled); 1069void intel_init_pm(struct drm_device *dev); 1070void intel_pm_setup(struct drm_device *dev); 1071bool intel_fbc_enabled(struct drm_device *dev); 1072void intel_update_fbc(struct drm_device *dev); 1073void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 1074void intel_gpu_ips_teardown(void); 1075int intel_power_domains_init(struct drm_i915_private *); 1076void intel_power_domains_remove(struct drm_i915_private *); 1077bool intel_display_power_enabled(struct drm_i915_private *dev_priv, 1078 enum intel_display_power_domain domain); 1079bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, 1080 enum intel_display_power_domain domain); 1081void intel_display_power_get(struct drm_i915_private *dev_priv, 1082 enum intel_display_power_domain domain); 1083void intel_display_power_put(struct drm_i915_private *dev_priv, 1084 enum intel_display_power_domain domain); 1085void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); 1086void intel_init_gt_powersave(struct drm_device *dev); 1087void intel_cleanup_gt_powersave(struct drm_device *dev); 1088void intel_enable_gt_powersave(struct drm_device *dev); 1089void intel_disable_gt_powersave(struct drm_device *dev); 1090void intel_suspend_gt_powersave(struct drm_device *dev); 1091void intel_reset_gt_powersave(struct drm_device *dev); 1092void ironlake_teardown_rc6(struct drm_device *dev); 1093void gen6_update_ring_freq(struct drm_device *dev); 1094void gen6_rps_idle(struct drm_i915_private *dev_priv); 1095void gen6_rps_boost(struct drm_i915_private *dev_priv); 1096void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); 1097void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); 1098void intel_runtime_pm_get(struct drm_i915_private *dev_priv); 1099void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); 1100void intel_runtime_pm_put(struct drm_i915_private *dev_priv); 1101void intel_init_runtime_pm(struct drm_i915_private *dev_priv); 1102void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); 1103void ilk_wm_get_hw_state(struct drm_device *dev); 1104 1105 1106/* intel_sdvo.c */ 1107bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); 1108 1109 1110/* intel_sprite.c */ 1111int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); 1112void intel_flush_primary_plane(struct drm_i915_private *dev_priv, 1113 enum plane plane); 1114int intel_plane_set_property(struct drm_plane *plane, 1115 struct drm_property *prop, 1116 uint64_t val); 1117int intel_plane_restore(struct drm_plane *plane); 1118void intel_plane_disable(struct drm_plane *plane); 1119int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 1120 struct drm_file *file_priv); 1121int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 1122 struct drm_file *file_priv); 1123 1124 1125/* intel_tv.c */ 1126void intel_tv_init(struct drm_device *dev); 1127 1128#endif /* __INTEL_DRV_H__ */ 1129