1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "nv50.h"
26
27void
28nv94_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
29{
30	u32 intr = nv_rd32(i2c, 0x00e06c);
31	u32 stat = nv_rd32(i2c, 0x00e068) & intr, i;
32	for (i = 0, *hi = *lo = *rq = *tx = 0; i < 8; i++) {
33		if ((stat & (1 << (i * 4)))) *hi |= 1 << i;
34		if ((stat & (2 << (i * 4)))) *lo |= 1 << i;
35		if ((stat & (4 << (i * 4)))) *rq |= 1 << i;
36		if ((stat & (8 << (i * 4)))) *tx |= 1 << i;
37	}
38	nv_wr32(i2c, 0x00e06c, intr);
39}
40
41void
42nv94_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data)
43{
44	u32 temp = nv_rd32(i2c, 0x00e068), i;
45	for (i = 0; i < 8; i++) {
46		if (mask & (1 << i)) {
47			if (!(data & (1 << i))) {
48				temp &= ~(type << (i * 4));
49				continue;
50			}
51			temp |= type << (i * 4);
52		}
53	}
54	nv_wr32(i2c, 0x00e068, temp);
55}
56
57#define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
58#define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
59
60static void
61auxch_fini(struct nouveau_i2c *aux, int ch)
62{
63	nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
64}
65
66static int
67auxch_init(struct nouveau_i2c *aux, int ch)
68{
69	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
70	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
71	const u32 urep = unksel ? 0x01000000 : 0x02000000;
72	u32 ctrl, timeout;
73
74	/* wait up to 1ms for any previous transaction to be done... */
75	timeout = 1000;
76	do {
77		ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
78		udelay(1);
79		if (!timeout--) {
80			AUX_ERR("begin idle timeout 0x%08x\n", ctrl);
81			return -EBUSY;
82		}
83	} while (ctrl & 0x03010000);
84
85	/* set some magic, and wait up to 1ms for it to appear */
86	nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
87	timeout = 1000;
88	do {
89		ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
90		udelay(1);
91		if (!timeout--) {
92			AUX_ERR("magic wait 0x%08x\n", ctrl);
93			auxch_fini(aux, ch);
94			return -EBUSY;
95		}
96	} while ((ctrl & 0x03000000) != urep);
97
98	return 0;
99}
100
101int
102nv94_aux(struct nouveau_i2c_port *base, bool retry,
103	 u8 type, u32 addr, u8 *data, u8 size)
104{
105	struct nouveau_i2c *aux = nouveau_i2c(base);
106	struct nv50_i2c_port *port = (void *)base;
107	u32 ctrl, stat, timeout, retries;
108	u32 xbuf[4] = {};
109	int ch = port->addr;
110	int ret, i;
111
112	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
113
114	ret = auxch_init(aux, ch);
115	if (ret)
116		goto out;
117
118	stat = nv_rd32(aux, 0x00e4e8 + (ch * 0x50));
119	if (!(stat & 0x10000000)) {
120		AUX_DBG("sink not detected\n");
121		ret = -ENXIO;
122		goto out;
123	}
124
125	if (!(type & 1)) {
126		memcpy(xbuf, data, size);
127		for (i = 0; i < 16; i += 4) {
128			AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
129			nv_wr32(aux, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
130		}
131	}
132
133	ctrl  = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
134	ctrl &= ~0x0001f0ff;
135	ctrl |= type << 12;
136	ctrl |= size - 1;
137	nv_wr32(aux, 0x00e4e0 + (ch * 0x50), addr);
138
139	/* (maybe) retry transaction a number of times on failure... */
140	for (retries = 0; !ret && retries < 32; retries++) {
141		/* reset, and delay a while if this is a retry */
142		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
143		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
144		if (retries)
145			udelay(400);
146
147		/* transaction request, wait up to 1ms for it to complete */
148		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
149
150		timeout = 1000;
151		do {
152			ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
153			udelay(1);
154			if (!timeout--) {
155				AUX_ERR("tx req timeout 0x%08x\n", ctrl);
156				ret = -EIO;
157				goto out;
158			}
159		} while (ctrl & 0x00010000);
160		ret = 1;
161
162		/* read status, and check if transaction completed ok */
163		stat = nv_mask(aux, 0x00e4e8 + (ch * 0x50), 0, 0);
164		if ((stat & 0x000f0000) == 0x00080000 ||
165		    (stat & 0x000f0000) == 0x00020000)
166			ret = retry ? 0 : 1;
167		if ((stat & 0x00000100))
168			ret = -ETIMEDOUT;
169		if ((stat & 0x00000e00))
170			ret = -EIO;
171
172		AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
173	}
174
175	if (type & 1) {
176		for (i = 0; i < 16; i += 4) {
177			xbuf[i / 4] = nv_rd32(aux, 0x00e4d0 + (ch * 0x50) + i);
178			AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
179		}
180		memcpy(data, xbuf, size);
181	}
182
183out:
184	auxch_fini(aux, ch);
185	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
186}
187
188static const struct nouveau_i2c_func
189nv94_i2c_func = {
190	.drive_scl = nv50_i2c_drive_scl,
191	.drive_sda = nv50_i2c_drive_sda,
192	.sense_scl = nv50_i2c_sense_scl,
193	.sense_sda = nv50_i2c_sense_sda,
194};
195
196static int
197nv94_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
198		   struct nouveau_oclass *oclass, void *data, u32 index,
199		   struct nouveau_object **pobject)
200{
201	struct dcb_i2c_entry *info = data;
202	struct nv50_i2c_port *port;
203	int ret;
204
205	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
206				      &nouveau_i2c_bit_algo, &nv94_i2c_func,
207				      &port);
208	*pobject = nv_object(port);
209	if (ret)
210		return ret;
211
212	if (info->drive >= nv50_i2c_addr_nr)
213		return -EINVAL;
214
215	port->state = 7;
216	port->addr = nv50_i2c_addr[info->drive];
217	if (info->share != DCB_I2C_UNUSED) {
218		port->ctrl = 0x00e500 + (info->share * 0x50);
219		port->data = 0x0000e001;
220	}
221	return 0;
222}
223
224static const struct nouveau_i2c_func
225nv94_aux_func = {
226	.aux       = nv94_aux,
227};
228
229int
230nv94_aux_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
231		   struct nouveau_oclass *oclass, void *data, u32 index,
232		   struct nouveau_object **pobject)
233{
234	struct dcb_i2c_entry *info = data;
235	struct nv50_i2c_port *port;
236	int ret;
237
238	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
239				      &nouveau_i2c_aux_algo, &nv94_aux_func,
240				      &port);
241	*pobject = nv_object(port);
242	if (ret)
243		return ret;
244
245	port->base.aux = info->drive;
246	port->addr = info->drive;
247	if (info->share != DCB_I2C_UNUSED) {
248		port->ctrl = 0x00e500 + (info->drive * 0x50);
249		port->data = 0x00002002;
250	}
251
252	return 0;
253}
254
255static struct nouveau_oclass
256nv94_i2c_sclass[] = {
257	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
258	  .ofuncs = &(struct nouveau_ofuncs) {
259		  .ctor = nv94_i2c_port_ctor,
260		  .dtor = _nouveau_i2c_port_dtor,
261		  .init = nv50_i2c_port_init,
262		  .fini = _nouveau_i2c_port_fini,
263	  },
264	},
265	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
266	  .ofuncs = &(struct nouveau_ofuncs) {
267		  .ctor = nv94_aux_port_ctor,
268		  .dtor = _nouveau_i2c_port_dtor,
269		  .init = _nouveau_i2c_port_init,
270		  .fini = _nouveau_i2c_port_fini,
271	  },
272	},
273	{}
274};
275
276struct nouveau_oclass *
277nv94_i2c_oclass = &(struct nouveau_i2c_impl) {
278	.base.handle = NV_SUBDEV(I2C, 0x94),
279	.base.ofuncs = &(struct nouveau_ofuncs) {
280		.ctor = _nouveau_i2c_ctor,
281		.dtor = _nouveau_i2c_dtor,
282		.init = _nouveau_i2c_init,
283		.fini = _nouveau_i2c_fini,
284	},
285	.sclass = nv94_i2c_sclass,
286	.pad_x = &nv04_i2c_pad_oclass,
287	.pad_s = &nv94_i2c_pad_oclass,
288	.aux = 4,
289	.aux_stat = nv94_aux_stat,
290	.aux_mask = nv94_aux_mask,
291}.base;
292