1#ifndef __NOUVEAU_ABI16_H__
2#define __NOUVEAU_ABI16_H__
3
4#define ABI16_IOCTL_ARGS                                                       \
5	struct drm_device *dev, void *data, struct drm_file *file_priv
6
7int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
8int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
9int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
10int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
11int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
12int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
13int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
14
15struct nouveau_abi16_ntfy {
16	struct list_head head;
17	struct nouveau_mm_node *node;
18	u32 handle;
19};
20
21struct nouveau_abi16_chan {
22	struct list_head head;
23	struct nouveau_channel *chan;
24	struct list_head notifiers;
25	struct nouveau_bo *ntfy;
26	struct nouveau_vma ntfy_vma;
27	struct nouveau_mm  heap;
28};
29
30struct nouveau_abi16 {
31	struct nvif_device device;
32	struct list_head channels;
33	u64 handles;
34};
35
36struct nouveau_drm;
37struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *, struct drm_device *);
38int  nouveau_abi16_put(struct nouveau_abi16 *, int);
39void nouveau_abi16_fini(struct nouveau_abi16 *);
40u16  nouveau_abi16_swclass(struct nouveau_drm *);
41
42#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
43#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
44
45struct drm_nouveau_channel_alloc {
46	uint32_t     fb_ctxdma_handle;
47	uint32_t     tt_ctxdma_handle;
48
49	int          channel;
50	uint32_t     pushbuf_domains;
51
52	/* Notifier memory */
53	uint32_t     notifier_handle;
54
55	/* DRM-enforced subchannel assignments */
56	struct {
57		uint32_t handle;
58		uint32_t grclass;
59	} subchan[8];
60	uint32_t nr_subchan;
61};
62
63struct drm_nouveau_channel_free {
64	int channel;
65};
66
67struct drm_nouveau_grobj_alloc {
68	int      channel;
69	uint32_t handle;
70	int      class;
71};
72
73struct drm_nouveau_notifierobj_alloc {
74	uint32_t channel;
75	uint32_t handle;
76	uint32_t size;
77	uint32_t offset;
78};
79
80struct drm_nouveau_gpuobj_free {
81	int      channel;
82	uint32_t handle;
83};
84
85#define NOUVEAU_GETPARAM_PCI_VENDOR      3
86#define NOUVEAU_GETPARAM_PCI_DEVICE      4
87#define NOUVEAU_GETPARAM_BUS_TYPE        5
88#define NOUVEAU_GETPARAM_FB_SIZE         8
89#define NOUVEAU_GETPARAM_AGP_SIZE        9
90#define NOUVEAU_GETPARAM_CHIPSET_ID      11
91#define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
92#define NOUVEAU_GETPARAM_GRAPH_UNITS     13
93#define NOUVEAU_GETPARAM_PTIMER_TIME     14
94#define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
95#define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
96struct drm_nouveau_getparam {
97	uint64_t param;
98	uint64_t value;
99};
100
101struct drm_nouveau_setparam {
102	uint64_t param;
103	uint64_t value;
104};
105
106#define DRM_IOCTL_NOUVEAU_GETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
107#define DRM_IOCTL_NOUVEAU_SETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
108#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
109#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
110#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
111#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC  DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
112#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
113
114#endif
115