1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
34#include "radeon_drv.h"
35
36#include <drm/drm_pciids.h>
37#include <linux/console.h>
38#include <linux/module.h>
39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
41#include <drm/drm_gem.h>
42
43#include "drm_crtc_helper.h"
44/*
45 * KMS wrapper.
46 * - 2.0.0 - initial interface
47 * - 2.1.0 - add square tiling interface
48 * - 2.2.0 - add r6xx/r7xx const buffer support
49 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
50 * - 2.4.0 - add crtc id query
51 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
52 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
53 *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
54 *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
55 *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
56 *   2.10.0 - fusion 2D tiling
57 *   2.11.0 - backend map, initial compute support for the CS checker
58 *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
59 *   2.13.0 - virtual memory support, streamout
60 *   2.14.0 - add evergreen tiling informations
61 *   2.15.0 - add max_pipes query
62 *   2.16.0 - fix evergreen 2D tiled surface calculation
63 *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
64 *   2.18.0 - r600-eg: allow "invalid" DB formats
65 *   2.19.0 - r600-eg: MSAA textures
66 *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
67 *   2.21.0 - r600-r700: FMASK and CMASK
68 *   2.22.0 - r600 only: RESOLVE_BOX allowed
69 *   2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
70 *   2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71 *   2.25.0 - eg+: new info request for num SE and num SH
72 *   2.26.0 - r600-eg: fix htile size computation
73 *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
74 *   2.28.0 - r600-eg: Add MEM_WRITE packet support
75 *   2.29.0 - R500 FP16 color clear registers
76 *   2.30.0 - fix for FMASK texturing
77 *   2.31.0 - Add fastfb support for rs690
78 *   2.32.0 - new info request for rings working
79 *   2.33.0 - Add SI tiling mode array query
80 *   2.34.0 - Add CIK tiling mode array query
81 *   2.35.0 - Add CIK macrotile mode array query
82 *   2.36.0 - Fix CIK DCE tiling setup
83 *   2.37.0 - allow GS ring setup on r6xx/r7xx
84 *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
85 *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
86 *   2.39.0 - Add INFO query for number of active CUs
87 *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
88 *            CS to GPU on >= r600
89 */
90#define KMS_DRIVER_MAJOR	2
91#define KMS_DRIVER_MINOR	40
92#define KMS_DRIVER_PATCHLEVEL	0
93int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
94int radeon_driver_unload_kms(struct drm_device *dev);
95void radeon_driver_lastclose_kms(struct drm_device *dev);
96int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
97void radeon_driver_postclose_kms(struct drm_device *dev,
98				 struct drm_file *file_priv);
99void radeon_driver_preclose_kms(struct drm_device *dev,
100				struct drm_file *file_priv);
101int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
102int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
103u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
104int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
105void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
106int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
107				    int *max_error,
108				    struct timeval *vblank_time,
109				    unsigned flags);
110void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
111int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
112void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
113irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
114void radeon_gem_object_free(struct drm_gem_object *obj);
115int radeon_gem_object_open(struct drm_gem_object *obj,
116				struct drm_file *file_priv);
117void radeon_gem_object_close(struct drm_gem_object *obj,
118				struct drm_file *file_priv);
119struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
120					struct drm_gem_object *gobj,
121					int flags);
122extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
123				      unsigned int flags,
124				      int *vpos, int *hpos, ktime_t *stime,
125				      ktime_t *etime);
126extern bool radeon_is_px(struct drm_device *dev);
127extern const struct drm_ioctl_desc radeon_ioctls_kms[];
128extern int radeon_max_kms_ioctl;
129int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
130int radeon_mode_dumb_mmap(struct drm_file *filp,
131			  struct drm_device *dev,
132			  uint32_t handle, uint64_t *offset_p);
133int radeon_mode_dumb_create(struct drm_file *file_priv,
134			    struct drm_device *dev,
135			    struct drm_mode_create_dumb *args);
136struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
137struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
138							struct dma_buf_attachment *,
139							struct sg_table *sg);
140int radeon_gem_prime_pin(struct drm_gem_object *obj);
141void radeon_gem_prime_unpin(struct drm_gem_object *obj);
142struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
143void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
144void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
145extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
146				    unsigned long arg);
147
148#if defined(CONFIG_DEBUG_FS)
149int radeon_debugfs_init(struct drm_minor *minor);
150void radeon_debugfs_cleanup(struct drm_minor *minor);
151#endif
152
153/* atpx handler */
154#if defined(CONFIG_VGA_SWITCHEROO)
155void radeon_register_atpx_handler(void);
156void radeon_unregister_atpx_handler(void);
157#else
158static inline void radeon_register_atpx_handler(void) {}
159static inline void radeon_unregister_atpx_handler(void) {}
160#endif
161
162int radeon_no_wb;
163int radeon_modeset = -1;
164int radeon_dynclks = -1;
165int radeon_r4xx_atom = 0;
166int radeon_agpmode = 0;
167int radeon_vram_limit = 0;
168int radeon_gart_size = -1; /* auto */
169int radeon_benchmarking = 0;
170int radeon_testing = 0;
171int radeon_connector_table = 0;
172int radeon_tv = 1;
173int radeon_audio = -1;
174int radeon_disp_priority = 0;
175int radeon_hw_i2c = 0;
176int radeon_pcie_gen2 = -1;
177int radeon_msi = -1;
178int radeon_lockup_timeout = 10000;
179int radeon_fastfb = 0;
180int radeon_dpm = -1;
181int radeon_aspm = -1;
182int radeon_runtime_pm = -1;
183int radeon_hard_reset = 0;
184int radeon_vm_size = 8;
185int radeon_vm_block_size = -1;
186int radeon_deep_color = 0;
187int radeon_use_pflipirq = 2;
188int radeon_bapm = -1;
189int radeon_backlight = -1;
190
191MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
192module_param_named(no_wb, radeon_no_wb, int, 0444);
193
194MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
195module_param_named(modeset, radeon_modeset, int, 0400);
196
197MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
198module_param_named(dynclks, radeon_dynclks, int, 0444);
199
200MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
201module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
202
203MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
204module_param_named(vramlimit, radeon_vram_limit, int, 0600);
205
206MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
207module_param_named(agpmode, radeon_agpmode, int, 0444);
208
209MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
210module_param_named(gartsize, radeon_gart_size, int, 0600);
211
212MODULE_PARM_DESC(benchmark, "Run benchmark");
213module_param_named(benchmark, radeon_benchmarking, int, 0444);
214
215MODULE_PARM_DESC(test, "Run tests");
216module_param_named(test, radeon_testing, int, 0444);
217
218MODULE_PARM_DESC(connector_table, "Force connector table");
219module_param_named(connector_table, radeon_connector_table, int, 0444);
220
221MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
222module_param_named(tv, radeon_tv, int, 0444);
223
224MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
225module_param_named(audio, radeon_audio, int, 0444);
226
227MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
228module_param_named(disp_priority, radeon_disp_priority, int, 0444);
229
230MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
231module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
232
233MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
234module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
235
236MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
237module_param_named(msi, radeon_msi, int, 0444);
238
239MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
240module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
241
242MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
243module_param_named(fastfb, radeon_fastfb, int, 0444);
244
245MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
246module_param_named(dpm, radeon_dpm, int, 0444);
247
248MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
249module_param_named(aspm, radeon_aspm, int, 0444);
250
251MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
252module_param_named(runpm, radeon_runtime_pm, int, 0444);
253
254MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
255module_param_named(hard_reset, radeon_hard_reset, int, 0444);
256
257MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
258module_param_named(vm_size, radeon_vm_size, int, 0444);
259
260MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
261module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
262
263MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
264module_param_named(deep_color, radeon_deep_color, int, 0444);
265
266MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
267module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
268
269MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
270module_param_named(bapm, radeon_bapm, int, 0444);
271
272MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
273module_param_named(backlight, radeon_backlight, int, 0444);
274
275static struct pci_device_id pciidlist[] = {
276	radeon_PCI_IDS
277};
278
279MODULE_DEVICE_TABLE(pci, pciidlist);
280
281#ifdef CONFIG_DRM_RADEON_UMS
282
283static int radeon_suspend(struct drm_device *dev, pm_message_t state)
284{
285	drm_radeon_private_t *dev_priv = dev->dev_private;
286
287	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
288		return 0;
289
290	/* Disable *all* interrupts */
291	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
292		RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
293	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
294	return 0;
295}
296
297static int radeon_resume(struct drm_device *dev)
298{
299	drm_radeon_private_t *dev_priv = dev->dev_private;
300
301	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
302		return 0;
303
304	/* Restore interrupt registers */
305	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
306		RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
307	RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
308	return 0;
309}
310
311
312static const struct file_operations radeon_driver_old_fops = {
313	.owner = THIS_MODULE,
314	.open = drm_open,
315	.release = drm_release,
316	.unlocked_ioctl = drm_ioctl,
317	.mmap = drm_legacy_mmap,
318	.poll = drm_poll,
319	.read = drm_read,
320#ifdef CONFIG_COMPAT
321	.compat_ioctl = radeon_compat_ioctl,
322#endif
323	.llseek = noop_llseek,
324};
325
326static struct drm_driver driver_old = {
327	.driver_features =
328	    DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
329	    DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
330	.dev_priv_size = sizeof(drm_radeon_buf_priv_t),
331	.load = radeon_driver_load,
332	.firstopen = radeon_driver_firstopen,
333	.open = radeon_driver_open,
334	.preclose = radeon_driver_preclose,
335	.postclose = radeon_driver_postclose,
336	.lastclose = radeon_driver_lastclose,
337	.set_busid = drm_pci_set_busid,
338	.unload = radeon_driver_unload,
339	.suspend = radeon_suspend,
340	.resume = radeon_resume,
341	.get_vblank_counter = radeon_get_vblank_counter,
342	.enable_vblank = radeon_enable_vblank,
343	.disable_vblank = radeon_disable_vblank,
344	.master_create = radeon_master_create,
345	.master_destroy = radeon_master_destroy,
346	.irq_preinstall = radeon_driver_irq_preinstall,
347	.irq_postinstall = radeon_driver_irq_postinstall,
348	.irq_uninstall = radeon_driver_irq_uninstall,
349	.irq_handler = radeon_driver_irq_handler,
350	.ioctls = radeon_ioctls,
351	.dma_ioctl = radeon_cp_buffers,
352	.fops = &radeon_driver_old_fops,
353	.name = DRIVER_NAME,
354	.desc = DRIVER_DESC,
355	.date = DRIVER_DATE,
356	.major = DRIVER_MAJOR,
357	.minor = DRIVER_MINOR,
358	.patchlevel = DRIVER_PATCHLEVEL,
359};
360
361#endif
362
363static struct drm_driver kms_driver;
364
365static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
366{
367	struct apertures_struct *ap;
368	bool primary = false;
369
370	ap = alloc_apertures(1);
371	if (!ap)
372		return -ENOMEM;
373
374	ap->ranges[0].base = pci_resource_start(pdev, 0);
375	ap->ranges[0].size = pci_resource_len(pdev, 0);
376
377#ifdef CONFIG_X86
378	primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
379#endif
380	remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
381	kfree(ap);
382
383	return 0;
384}
385
386static int radeon_pci_probe(struct pci_dev *pdev,
387			    const struct pci_device_id *ent)
388{
389	int ret;
390
391	/* Get rid of things like offb */
392	ret = radeon_kick_out_firmware_fb(pdev);
393	if (ret)
394		return ret;
395
396	return drm_get_pci_dev(pdev, ent, &kms_driver);
397}
398
399static void
400radeon_pci_remove(struct pci_dev *pdev)
401{
402	struct drm_device *dev = pci_get_drvdata(pdev);
403
404	drm_put_dev(dev);
405}
406
407static int radeon_pmops_suspend(struct device *dev)
408{
409	struct pci_dev *pdev = to_pci_dev(dev);
410	struct drm_device *drm_dev = pci_get_drvdata(pdev);
411	return radeon_suspend_kms(drm_dev, true, true);
412}
413
414static int radeon_pmops_resume(struct device *dev)
415{
416	struct pci_dev *pdev = to_pci_dev(dev);
417	struct drm_device *drm_dev = pci_get_drvdata(pdev);
418	return radeon_resume_kms(drm_dev, true, true);
419}
420
421static int radeon_pmops_freeze(struct device *dev)
422{
423	struct pci_dev *pdev = to_pci_dev(dev);
424	struct drm_device *drm_dev = pci_get_drvdata(pdev);
425	return radeon_suspend_kms(drm_dev, false, true);
426}
427
428static int radeon_pmops_thaw(struct device *dev)
429{
430	struct pci_dev *pdev = to_pci_dev(dev);
431	struct drm_device *drm_dev = pci_get_drvdata(pdev);
432	return radeon_resume_kms(drm_dev, false, true);
433}
434
435static int radeon_pmops_runtime_suspend(struct device *dev)
436{
437	struct pci_dev *pdev = to_pci_dev(dev);
438	struct drm_device *drm_dev = pci_get_drvdata(pdev);
439	int ret;
440
441	if (!radeon_is_px(drm_dev)) {
442		pm_runtime_forbid(dev);
443		return -EBUSY;
444	}
445
446	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
447	drm_kms_helper_poll_disable(drm_dev);
448	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
449
450	ret = radeon_suspend_kms(drm_dev, false, false);
451	pci_save_state(pdev);
452	pci_disable_device(pdev);
453	pci_ignore_hotplug(pdev);
454	pci_set_power_state(pdev, PCI_D3cold);
455	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
456
457	return 0;
458}
459
460static int radeon_pmops_runtime_resume(struct device *dev)
461{
462	struct pci_dev *pdev = to_pci_dev(dev);
463	struct drm_device *drm_dev = pci_get_drvdata(pdev);
464	int ret;
465
466	if (!radeon_is_px(drm_dev))
467		return -EINVAL;
468
469	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
470
471	pci_set_power_state(pdev, PCI_D0);
472	pci_restore_state(pdev);
473	ret = pci_enable_device(pdev);
474	if (ret)
475		return ret;
476	pci_set_master(pdev);
477
478	ret = radeon_resume_kms(drm_dev, false, false);
479	drm_kms_helper_poll_enable(drm_dev);
480	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
481	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
482	return 0;
483}
484
485static int radeon_pmops_runtime_idle(struct device *dev)
486{
487	struct pci_dev *pdev = to_pci_dev(dev);
488	struct drm_device *drm_dev = pci_get_drvdata(pdev);
489	struct drm_crtc *crtc;
490
491	if (!radeon_is_px(drm_dev)) {
492		pm_runtime_forbid(dev);
493		return -EBUSY;
494	}
495
496	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
497		if (crtc->enabled) {
498			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
499			return -EBUSY;
500		}
501	}
502
503	pm_runtime_mark_last_busy(dev);
504	pm_runtime_autosuspend(dev);
505	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
506	return 1;
507}
508
509long radeon_drm_ioctl(struct file *filp,
510		      unsigned int cmd, unsigned long arg)
511{
512	struct drm_file *file_priv = filp->private_data;
513	struct drm_device *dev;
514	long ret;
515	dev = file_priv->minor->dev;
516	ret = pm_runtime_get_sync(dev->dev);
517	if (ret < 0)
518		return ret;
519
520	ret = drm_ioctl(filp, cmd, arg);
521
522	pm_runtime_mark_last_busy(dev->dev);
523	pm_runtime_put_autosuspend(dev->dev);
524	return ret;
525}
526
527static const struct dev_pm_ops radeon_pm_ops = {
528	.suspend = radeon_pmops_suspend,
529	.resume = radeon_pmops_resume,
530	.freeze = radeon_pmops_freeze,
531	.thaw = radeon_pmops_thaw,
532	.poweroff = radeon_pmops_freeze,
533	.restore = radeon_pmops_resume,
534	.runtime_suspend = radeon_pmops_runtime_suspend,
535	.runtime_resume = radeon_pmops_runtime_resume,
536	.runtime_idle = radeon_pmops_runtime_idle,
537};
538
539static const struct file_operations radeon_driver_kms_fops = {
540	.owner = THIS_MODULE,
541	.open = drm_open,
542	.release = drm_release,
543	.unlocked_ioctl = radeon_drm_ioctl,
544	.mmap = radeon_mmap,
545	.poll = drm_poll,
546	.read = drm_read,
547#ifdef CONFIG_COMPAT
548	.compat_ioctl = radeon_kms_compat_ioctl,
549#endif
550};
551
552static struct drm_driver kms_driver = {
553	.driver_features =
554	    DRIVER_USE_AGP |
555	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
556	    DRIVER_PRIME | DRIVER_RENDER,
557	.load = radeon_driver_load_kms,
558	.open = radeon_driver_open_kms,
559	.preclose = radeon_driver_preclose_kms,
560	.postclose = radeon_driver_postclose_kms,
561	.lastclose = radeon_driver_lastclose_kms,
562	.set_busid = drm_pci_set_busid,
563	.unload = radeon_driver_unload_kms,
564	.get_vblank_counter = radeon_get_vblank_counter_kms,
565	.enable_vblank = radeon_enable_vblank_kms,
566	.disable_vblank = radeon_disable_vblank_kms,
567	.get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
568	.get_scanout_position = radeon_get_crtc_scanoutpos,
569#if defined(CONFIG_DEBUG_FS)
570	.debugfs_init = radeon_debugfs_init,
571	.debugfs_cleanup = radeon_debugfs_cleanup,
572#endif
573	.irq_preinstall = radeon_driver_irq_preinstall_kms,
574	.irq_postinstall = radeon_driver_irq_postinstall_kms,
575	.irq_uninstall = radeon_driver_irq_uninstall_kms,
576	.irq_handler = radeon_driver_irq_handler_kms,
577	.ioctls = radeon_ioctls_kms,
578	.gem_free_object = radeon_gem_object_free,
579	.gem_open_object = radeon_gem_object_open,
580	.gem_close_object = radeon_gem_object_close,
581	.dumb_create = radeon_mode_dumb_create,
582	.dumb_map_offset = radeon_mode_dumb_mmap,
583	.dumb_destroy = drm_gem_dumb_destroy,
584	.fops = &radeon_driver_kms_fops,
585
586	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
587	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
588	.gem_prime_export = radeon_gem_prime_export,
589	.gem_prime_import = drm_gem_prime_import,
590	.gem_prime_pin = radeon_gem_prime_pin,
591	.gem_prime_unpin = radeon_gem_prime_unpin,
592	.gem_prime_res_obj = radeon_gem_prime_res_obj,
593	.gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
594	.gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
595	.gem_prime_vmap = radeon_gem_prime_vmap,
596	.gem_prime_vunmap = radeon_gem_prime_vunmap,
597
598	.name = DRIVER_NAME,
599	.desc = DRIVER_DESC,
600	.date = DRIVER_DATE,
601	.major = KMS_DRIVER_MAJOR,
602	.minor = KMS_DRIVER_MINOR,
603	.patchlevel = KMS_DRIVER_PATCHLEVEL,
604};
605
606static struct drm_driver *driver;
607static struct pci_driver *pdriver;
608
609#ifdef CONFIG_DRM_RADEON_UMS
610static struct pci_driver radeon_pci_driver = {
611	.name = DRIVER_NAME,
612	.id_table = pciidlist,
613};
614#endif
615
616static struct pci_driver radeon_kms_pci_driver = {
617	.name = DRIVER_NAME,
618	.id_table = pciidlist,
619	.probe = radeon_pci_probe,
620	.remove = radeon_pci_remove,
621	.driver.pm = &radeon_pm_ops,
622};
623
624static int __init radeon_init(void)
625{
626#ifdef CONFIG_VGA_CONSOLE
627	if (vgacon_text_force() && radeon_modeset == -1) {
628		DRM_INFO("VGACON disable radeon kernel modesetting.\n");
629		radeon_modeset = 0;
630	}
631#endif
632	/* set to modesetting by default if not nomodeset */
633	if (radeon_modeset == -1)
634		radeon_modeset = 1;
635
636	if (radeon_modeset == 1) {
637		DRM_INFO("radeon kernel modesetting enabled.\n");
638		driver = &kms_driver;
639		pdriver = &radeon_kms_pci_driver;
640		driver->driver_features |= DRIVER_MODESET;
641		driver->num_ioctls = radeon_max_kms_ioctl;
642		radeon_register_atpx_handler();
643
644	} else {
645#ifdef CONFIG_DRM_RADEON_UMS
646		DRM_INFO("radeon userspace modesetting enabled.\n");
647		driver = &driver_old;
648		pdriver = &radeon_pci_driver;
649		driver->driver_features &= ~DRIVER_MODESET;
650		driver->num_ioctls = radeon_max_ioctl;
651#else
652		DRM_ERROR("No UMS support in radeon module!\n");
653		return -EINVAL;
654#endif
655	}
656
657	/* let modprobe override vga console setting */
658	return drm_pci_init(driver, pdriver);
659}
660
661static void __exit radeon_exit(void)
662{
663	drm_pci_exit(driver, pdriver);
664	radeon_unregister_atpx_handler();
665}
666
667module_init(radeon_init);
668module_exit(radeon_exit);
669
670MODULE_AUTHOR(DRIVER_AUTHOR);
671MODULE_DESCRIPTION(DRIVER_DESC);
672MODULE_LICENSE("GPL and additional rights");
673