1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <drm/drmP.h> 29#include "radeon.h" 30#include <drm/radeon_drm.h> 31#include "radeon_asic.h" 32 33#include <linux/vga_switcheroo.h> 34#include <linux/slab.h> 35#include <linux/pm_runtime.h> 36 37#if defined(CONFIG_VGA_SWITCHEROO) 38bool radeon_has_atpx(void); 39#else 40static inline bool radeon_has_atpx(void) { return false; } 41#endif 42 43/** 44 * radeon_driver_unload_kms - Main unload function for KMS. 45 * 46 * @dev: drm dev pointer 47 * 48 * This is the main unload function for KMS (all asics). 49 * It calls radeon_modeset_fini() to tear down the 50 * displays, and radeon_device_fini() to tear down 51 * the rest of the device (CP, writeback, etc.). 52 * Returns 0 on success. 53 */ 54int radeon_driver_unload_kms(struct drm_device *dev) 55{ 56 struct radeon_device *rdev = dev->dev_private; 57 58 if (rdev == NULL) 59 return 0; 60 61 if (rdev->rmmio == NULL) 62 goto done_free; 63 64 pm_runtime_get_sync(dev->dev); 65 66 radeon_acpi_fini(rdev); 67 68 radeon_modeset_fini(rdev); 69 radeon_device_fini(rdev); 70 71done_free: 72 kfree(rdev); 73 dev->dev_private = NULL; 74 return 0; 75} 76 77/** 78 * radeon_driver_load_kms - Main load function for KMS. 79 * 80 * @dev: drm dev pointer 81 * @flags: device flags 82 * 83 * This is the main load function for KMS (all asics). 84 * It calls radeon_device_init() to set up the non-display 85 * parts of the chip (asic init, CP, writeback, etc.), and 86 * radeon_modeset_init() to set up the display parts 87 * (crtcs, encoders, hotplug detect, etc.). 88 * Returns 0 on success, error on failure. 89 */ 90int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 91{ 92 struct radeon_device *rdev; 93 int r, acpi_status; 94 95 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 96 if (rdev == NULL) { 97 return -ENOMEM; 98 } 99 dev->dev_private = (void *)rdev; 100 101 /* update BUS flag */ 102 if (drm_pci_device_is_agp(dev)) { 103 flags |= RADEON_IS_AGP; 104 } else if (pci_is_pcie(dev->pdev)) { 105 flags |= RADEON_IS_PCIE; 106 } else { 107 flags |= RADEON_IS_PCI; 108 } 109 110 if ((radeon_runtime_pm != 0) && 111 radeon_has_atpx() && 112 ((flags & RADEON_IS_IGP) == 0)) 113 flags |= RADEON_IS_PX; 114 115 /* radeon_device_init should report only fatal error 116 * like memory allocation failure or iomapping failure, 117 * or memory manager initialization failure, it must 118 * properly initialize the GPU MC controller and permit 119 * VRAM allocation 120 */ 121 r = radeon_device_init(rdev, dev, dev->pdev, flags); 122 if (r) { 123 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 124 goto out; 125 } 126 127 /* Again modeset_init should fail only on fatal error 128 * otherwise it should provide enough functionalities 129 * for shadowfb to run 130 */ 131 r = radeon_modeset_init(rdev); 132 if (r) 133 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 134 135 /* Call ACPI methods: require modeset init 136 * but failure is not fatal 137 */ 138 if (!r) { 139 acpi_status = radeon_acpi_init(rdev); 140 if (acpi_status) 141 dev_dbg(&dev->pdev->dev, 142 "Error during ACPI methods call\n"); 143 } 144 145 if (radeon_is_px(dev)) { 146 pm_runtime_use_autosuspend(dev->dev); 147 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 148 pm_runtime_set_active(dev->dev); 149 pm_runtime_allow(dev->dev); 150 pm_runtime_mark_last_busy(dev->dev); 151 pm_runtime_put_autosuspend(dev->dev); 152 } 153 154out: 155 if (r) 156 radeon_driver_unload_kms(dev); 157 158 159 return r; 160} 161 162/** 163 * radeon_set_filp_rights - Set filp right. 164 * 165 * @dev: drm dev pointer 166 * @owner: drm file 167 * @applier: drm file 168 * @value: value 169 * 170 * Sets the filp rights for the device (all asics). 171 */ 172static void radeon_set_filp_rights(struct drm_device *dev, 173 struct drm_file **owner, 174 struct drm_file *applier, 175 uint32_t *value) 176{ 177 mutex_lock(&dev->struct_mutex); 178 if (*value == 1) { 179 /* wants rights */ 180 if (!*owner) 181 *owner = applier; 182 } else if (*value == 0) { 183 /* revokes rights */ 184 if (*owner == applier) 185 *owner = NULL; 186 } 187 *value = *owner == applier ? 1 : 0; 188 mutex_unlock(&dev->struct_mutex); 189} 190 191/* 192 * Userspace get information ioctl 193 */ 194/** 195 * radeon_info_ioctl - answer a device specific request. 196 * 197 * @rdev: radeon device pointer 198 * @data: request object 199 * @filp: drm filp 200 * 201 * This function is used to pass device specific parameters to the userspace 202 * drivers. Examples include: pci device id, pipeline parms, tiling params, 203 * etc. (all asics). 204 * Returns 0 on success, -EINVAL on failure. 205 */ 206static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 207{ 208 struct radeon_device *rdev = dev->dev_private; 209 struct drm_radeon_info *info = data; 210 struct radeon_mode_info *minfo = &rdev->mode_info; 211 uint32_t *value, value_tmp, *value_ptr, value_size; 212 uint64_t value64; 213 struct drm_crtc *crtc; 214 int i, found; 215 216 value_ptr = (uint32_t *)((unsigned long)info->value); 217 value = &value_tmp; 218 value_size = sizeof(uint32_t); 219 220 switch (info->request) { 221 case RADEON_INFO_DEVICE_ID: 222 *value = dev->pdev->device; 223 break; 224 case RADEON_INFO_NUM_GB_PIPES: 225 *value = rdev->num_gb_pipes; 226 break; 227 case RADEON_INFO_NUM_Z_PIPES: 228 *value = rdev->num_z_pipes; 229 break; 230 case RADEON_INFO_ACCEL_WORKING: 231 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 232 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 233 *value = false; 234 else 235 *value = rdev->accel_working; 236 break; 237 case RADEON_INFO_CRTC_FROM_ID: 238 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 239 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 240 return -EFAULT; 241 } 242 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 243 crtc = (struct drm_crtc *)minfo->crtcs[i]; 244 if (crtc && crtc->base.id == *value) { 245 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 246 *value = radeon_crtc->crtc_id; 247 found = 1; 248 break; 249 } 250 } 251 if (!found) { 252 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 253 return -EINVAL; 254 } 255 break; 256 case RADEON_INFO_ACCEL_WORKING2: 257 if (rdev->family == CHIP_HAWAII) { 258 if (rdev->accel_working) { 259 if (rdev->new_fw) 260 *value = 3; 261 else 262 *value = 2; 263 } else { 264 *value = 0; 265 } 266 } else { 267 *value = rdev->accel_working; 268 } 269 break; 270 case RADEON_INFO_TILING_CONFIG: 271 if (rdev->family >= CHIP_BONAIRE) 272 *value = rdev->config.cik.tile_config; 273 else if (rdev->family >= CHIP_TAHITI) 274 *value = rdev->config.si.tile_config; 275 else if (rdev->family >= CHIP_CAYMAN) 276 *value = rdev->config.cayman.tile_config; 277 else if (rdev->family >= CHIP_CEDAR) 278 *value = rdev->config.evergreen.tile_config; 279 else if (rdev->family >= CHIP_RV770) 280 *value = rdev->config.rv770.tile_config; 281 else if (rdev->family >= CHIP_R600) 282 *value = rdev->config.r600.tile_config; 283 else { 284 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 285 return -EINVAL; 286 } 287 break; 288 case RADEON_INFO_WANT_HYPERZ: 289 /* The "value" here is both an input and output parameter. 290 * If the input value is 1, filp requests hyper-z access. 291 * If the input value is 0, filp revokes its hyper-z access. 292 * 293 * When returning, the value is 1 if filp owns hyper-z access, 294 * 0 otherwise. */ 295 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 296 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 297 return -EFAULT; 298 } 299 if (*value >= 2) { 300 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 301 return -EINVAL; 302 } 303 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 304 break; 305 case RADEON_INFO_WANT_CMASK: 306 /* The same logic as Hyper-Z. */ 307 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 308 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 309 return -EFAULT; 310 } 311 if (*value >= 2) { 312 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 313 return -EINVAL; 314 } 315 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 316 break; 317 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 318 /* return clock value in KHz */ 319 if (rdev->asic->get_xclk) 320 *value = radeon_get_xclk(rdev) * 10; 321 else 322 *value = rdev->clock.spll.reference_freq * 10; 323 break; 324 case RADEON_INFO_NUM_BACKENDS: 325 if (rdev->family >= CHIP_BONAIRE) 326 *value = rdev->config.cik.max_backends_per_se * 327 rdev->config.cik.max_shader_engines; 328 else if (rdev->family >= CHIP_TAHITI) 329 *value = rdev->config.si.max_backends_per_se * 330 rdev->config.si.max_shader_engines; 331 else if (rdev->family >= CHIP_CAYMAN) 332 *value = rdev->config.cayman.max_backends_per_se * 333 rdev->config.cayman.max_shader_engines; 334 else if (rdev->family >= CHIP_CEDAR) 335 *value = rdev->config.evergreen.max_backends; 336 else if (rdev->family >= CHIP_RV770) 337 *value = rdev->config.rv770.max_backends; 338 else if (rdev->family >= CHIP_R600) 339 *value = rdev->config.r600.max_backends; 340 else { 341 return -EINVAL; 342 } 343 break; 344 case RADEON_INFO_NUM_TILE_PIPES: 345 if (rdev->family >= CHIP_BONAIRE) 346 *value = rdev->config.cik.max_tile_pipes; 347 else if (rdev->family >= CHIP_TAHITI) 348 *value = rdev->config.si.max_tile_pipes; 349 else if (rdev->family >= CHIP_CAYMAN) 350 *value = rdev->config.cayman.max_tile_pipes; 351 else if (rdev->family >= CHIP_CEDAR) 352 *value = rdev->config.evergreen.max_tile_pipes; 353 else if (rdev->family >= CHIP_RV770) 354 *value = rdev->config.rv770.max_tile_pipes; 355 else if (rdev->family >= CHIP_R600) 356 *value = rdev->config.r600.max_tile_pipes; 357 else { 358 return -EINVAL; 359 } 360 break; 361 case RADEON_INFO_FUSION_GART_WORKING: 362 *value = 1; 363 break; 364 case RADEON_INFO_BACKEND_MAP: 365 if (rdev->family >= CHIP_BONAIRE) 366 *value = rdev->config.cik.backend_map; 367 else if (rdev->family >= CHIP_TAHITI) 368 *value = rdev->config.si.backend_map; 369 else if (rdev->family >= CHIP_CAYMAN) 370 *value = rdev->config.cayman.backend_map; 371 else if (rdev->family >= CHIP_CEDAR) 372 *value = rdev->config.evergreen.backend_map; 373 else if (rdev->family >= CHIP_RV770) 374 *value = rdev->config.rv770.backend_map; 375 else if (rdev->family >= CHIP_R600) 376 *value = rdev->config.r600.backend_map; 377 else { 378 return -EINVAL; 379 } 380 break; 381 case RADEON_INFO_VA_START: 382 /* this is where we report if vm is supported or not */ 383 if (rdev->family < CHIP_CAYMAN) 384 return -EINVAL; 385 *value = RADEON_VA_RESERVED_SIZE; 386 break; 387 case RADEON_INFO_IB_VM_MAX_SIZE: 388 /* this is where we report if vm is supported or not */ 389 if (rdev->family < CHIP_CAYMAN) 390 return -EINVAL; 391 *value = RADEON_IB_VM_MAX_SIZE; 392 break; 393 case RADEON_INFO_MAX_PIPES: 394 if (rdev->family >= CHIP_BONAIRE) 395 *value = rdev->config.cik.max_cu_per_sh; 396 else if (rdev->family >= CHIP_TAHITI) 397 *value = rdev->config.si.max_cu_per_sh; 398 else if (rdev->family >= CHIP_CAYMAN) 399 *value = rdev->config.cayman.max_pipes_per_simd; 400 else if (rdev->family >= CHIP_CEDAR) 401 *value = rdev->config.evergreen.max_pipes; 402 else if (rdev->family >= CHIP_RV770) 403 *value = rdev->config.rv770.max_pipes; 404 else if (rdev->family >= CHIP_R600) 405 *value = rdev->config.r600.max_pipes; 406 else { 407 return -EINVAL; 408 } 409 break; 410 case RADEON_INFO_TIMESTAMP: 411 if (rdev->family < CHIP_R600) { 412 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 413 return -EINVAL; 414 } 415 value = (uint32_t*)&value64; 416 value_size = sizeof(uint64_t); 417 value64 = radeon_get_gpu_clock_counter(rdev); 418 break; 419 case RADEON_INFO_MAX_SE: 420 if (rdev->family >= CHIP_BONAIRE) 421 *value = rdev->config.cik.max_shader_engines; 422 else if (rdev->family >= CHIP_TAHITI) 423 *value = rdev->config.si.max_shader_engines; 424 else if (rdev->family >= CHIP_CAYMAN) 425 *value = rdev->config.cayman.max_shader_engines; 426 else if (rdev->family >= CHIP_CEDAR) 427 *value = rdev->config.evergreen.num_ses; 428 else 429 *value = 1; 430 break; 431 case RADEON_INFO_MAX_SH_PER_SE: 432 if (rdev->family >= CHIP_BONAIRE) 433 *value = rdev->config.cik.max_sh_per_se; 434 else if (rdev->family >= CHIP_TAHITI) 435 *value = rdev->config.si.max_sh_per_se; 436 else 437 return -EINVAL; 438 break; 439 case RADEON_INFO_FASTFB_WORKING: 440 *value = rdev->fastfb_working; 441 break; 442 case RADEON_INFO_RING_WORKING: 443 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 444 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 445 return -EFAULT; 446 } 447 switch (*value) { 448 case RADEON_CS_RING_GFX: 449 case RADEON_CS_RING_COMPUTE: 450 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 451 break; 452 case RADEON_CS_RING_DMA: 453 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 454 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 455 break; 456 case RADEON_CS_RING_UVD: 457 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 458 break; 459 case RADEON_CS_RING_VCE: 460 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 461 break; 462 default: 463 return -EINVAL; 464 } 465 break; 466 case RADEON_INFO_SI_TILE_MODE_ARRAY: 467 if (rdev->family >= CHIP_BONAIRE) { 468 value = rdev->config.cik.tile_mode_array; 469 value_size = sizeof(uint32_t)*32; 470 } else if (rdev->family >= CHIP_TAHITI) { 471 value = rdev->config.si.tile_mode_array; 472 value_size = sizeof(uint32_t)*32; 473 } else { 474 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 475 return -EINVAL; 476 } 477 break; 478 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 479 if (rdev->family >= CHIP_BONAIRE) { 480 value = rdev->config.cik.macrotile_mode_array; 481 value_size = sizeof(uint32_t)*16; 482 } else { 483 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 484 return -EINVAL; 485 } 486 break; 487 case RADEON_INFO_SI_CP_DMA_COMPUTE: 488 *value = 1; 489 break; 490 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 491 if (rdev->family >= CHIP_BONAIRE) { 492 *value = rdev->config.cik.backend_enable_mask; 493 } else if (rdev->family >= CHIP_TAHITI) { 494 *value = rdev->config.si.backend_enable_mask; 495 } else { 496 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 497 } 498 break; 499 case RADEON_INFO_MAX_SCLK: 500 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 501 rdev->pm.dpm_enabled) 502 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 503 else 504 *value = rdev->pm.default_sclk * 10; 505 break; 506 case RADEON_INFO_VCE_FW_VERSION: 507 *value = rdev->vce.fw_version; 508 break; 509 case RADEON_INFO_VCE_FB_VERSION: 510 *value = rdev->vce.fb_version; 511 break; 512 case RADEON_INFO_NUM_BYTES_MOVED: 513 value = (uint32_t*)&value64; 514 value_size = sizeof(uint64_t); 515 value64 = atomic64_read(&rdev->num_bytes_moved); 516 break; 517 case RADEON_INFO_VRAM_USAGE: 518 value = (uint32_t*)&value64; 519 value_size = sizeof(uint64_t); 520 value64 = atomic64_read(&rdev->vram_usage); 521 break; 522 case RADEON_INFO_GTT_USAGE: 523 value = (uint32_t*)&value64; 524 value_size = sizeof(uint64_t); 525 value64 = atomic64_read(&rdev->gtt_usage); 526 break; 527 case RADEON_INFO_ACTIVE_CU_COUNT: 528 if (rdev->family >= CHIP_BONAIRE) 529 *value = rdev->config.cik.active_cus; 530 else if (rdev->family >= CHIP_TAHITI) 531 *value = rdev->config.si.active_cus; 532 else if (rdev->family >= CHIP_CAYMAN) 533 *value = rdev->config.cayman.active_simds; 534 else if (rdev->family >= CHIP_CEDAR) 535 *value = rdev->config.evergreen.active_simds; 536 else if (rdev->family >= CHIP_RV770) 537 *value = rdev->config.rv770.active_simds; 538 else if (rdev->family >= CHIP_R600) 539 *value = rdev->config.r600.active_simds; 540 else 541 *value = 1; 542 break; 543 default: 544 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 545 return -EINVAL; 546 } 547 if (copy_to_user(value_ptr, (char*)value, value_size)) { 548 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 549 return -EFAULT; 550 } 551 return 0; 552} 553 554 555/* 556 * Outdated mess for old drm with Xorg being in charge (void function now). 557 */ 558/** 559 * radeon_driver_firstopen_kms - drm callback for last close 560 * 561 * @dev: drm dev pointer 562 * 563 * Switch vga switcheroo state after last close (all asics). 564 */ 565void radeon_driver_lastclose_kms(struct drm_device *dev) 566{ 567 vga_switcheroo_process_delayed_switch(); 568} 569 570/** 571 * radeon_driver_open_kms - drm callback for open 572 * 573 * @dev: drm dev pointer 574 * @file_priv: drm file 575 * 576 * On device open, init vm on cayman+ (all asics). 577 * Returns 0 on success, error on failure. 578 */ 579int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 580{ 581 struct radeon_device *rdev = dev->dev_private; 582 int r; 583 584 file_priv->driver_priv = NULL; 585 586 r = pm_runtime_get_sync(dev->dev); 587 if (r < 0) 588 return r; 589 590 /* new gpu have virtual address space support */ 591 if (rdev->family >= CHIP_CAYMAN) { 592 struct radeon_fpriv *fpriv; 593 struct radeon_vm *vm; 594 int r; 595 596 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 597 if (unlikely(!fpriv)) { 598 return -ENOMEM; 599 } 600 601 vm = &fpriv->vm; 602 r = radeon_vm_init(rdev, vm); 603 if (r) { 604 kfree(fpriv); 605 return r; 606 } 607 608 if (rdev->accel_working) { 609 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 610 if (r) { 611 radeon_vm_fini(rdev, vm); 612 kfree(fpriv); 613 return r; 614 } 615 616 /* map the ib pool buffer read only into 617 * virtual address space */ 618 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 619 rdev->ring_tmp_bo.bo); 620 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 621 RADEON_VA_IB_OFFSET, 622 RADEON_VM_PAGE_READABLE | 623 RADEON_VM_PAGE_SNOOPED); 624 625 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 626 if (r) { 627 radeon_vm_fini(rdev, vm); 628 kfree(fpriv); 629 return r; 630 } 631 } 632 file_priv->driver_priv = fpriv; 633 } 634 635 pm_runtime_mark_last_busy(dev->dev); 636 pm_runtime_put_autosuspend(dev->dev); 637 return 0; 638} 639 640/** 641 * radeon_driver_postclose_kms - drm callback for post close 642 * 643 * @dev: drm dev pointer 644 * @file_priv: drm file 645 * 646 * On device post close, tear down vm on cayman+ (all asics). 647 */ 648void radeon_driver_postclose_kms(struct drm_device *dev, 649 struct drm_file *file_priv) 650{ 651 struct radeon_device *rdev = dev->dev_private; 652 653 /* new gpu have virtual address space support */ 654 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 655 struct radeon_fpriv *fpriv = file_priv->driver_priv; 656 struct radeon_vm *vm = &fpriv->vm; 657 int r; 658 659 if (rdev->accel_working) { 660 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 661 if (!r) { 662 if (vm->ib_bo_va) 663 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 664 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 665 } 666 } 667 668 radeon_vm_fini(rdev, vm); 669 kfree(fpriv); 670 file_priv->driver_priv = NULL; 671 } 672} 673 674/** 675 * radeon_driver_preclose_kms - drm callback for pre close 676 * 677 * @dev: drm dev pointer 678 * @file_priv: drm file 679 * 680 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 681 * (all asics). 682 */ 683void radeon_driver_preclose_kms(struct drm_device *dev, 684 struct drm_file *file_priv) 685{ 686 struct radeon_device *rdev = dev->dev_private; 687 if (rdev->hyperz_filp == file_priv) 688 rdev->hyperz_filp = NULL; 689 if (rdev->cmask_filp == file_priv) 690 rdev->cmask_filp = NULL; 691 radeon_uvd_free_handles(rdev, file_priv); 692 radeon_vce_free_handles(rdev, file_priv); 693} 694 695/* 696 * VBlank related functions. 697 */ 698/** 699 * radeon_get_vblank_counter_kms - get frame count 700 * 701 * @dev: drm dev pointer 702 * @crtc: crtc to get the frame count from 703 * 704 * Gets the frame count on the requested crtc (all asics). 705 * Returns frame count on success, -EINVAL on failure. 706 */ 707u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 708{ 709 struct radeon_device *rdev = dev->dev_private; 710 711 if (crtc < 0 || crtc >= rdev->num_crtc) { 712 DRM_ERROR("Invalid crtc %d\n", crtc); 713 return -EINVAL; 714 } 715 716 return radeon_get_vblank_counter(rdev, crtc); 717} 718 719/** 720 * radeon_enable_vblank_kms - enable vblank interrupt 721 * 722 * @dev: drm dev pointer 723 * @crtc: crtc to enable vblank interrupt for 724 * 725 * Enable the interrupt on the requested crtc (all asics). 726 * Returns 0 on success, -EINVAL on failure. 727 */ 728int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 729{ 730 struct radeon_device *rdev = dev->dev_private; 731 unsigned long irqflags; 732 int r; 733 734 if (crtc < 0 || crtc >= rdev->num_crtc) { 735 DRM_ERROR("Invalid crtc %d\n", crtc); 736 return -EINVAL; 737 } 738 739 spin_lock_irqsave(&rdev->irq.lock, irqflags); 740 rdev->irq.crtc_vblank_int[crtc] = true; 741 r = radeon_irq_set(rdev); 742 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 743 return r; 744} 745 746/** 747 * radeon_disable_vblank_kms - disable vblank interrupt 748 * 749 * @dev: drm dev pointer 750 * @crtc: crtc to disable vblank interrupt for 751 * 752 * Disable the interrupt on the requested crtc (all asics). 753 */ 754void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 755{ 756 struct radeon_device *rdev = dev->dev_private; 757 unsigned long irqflags; 758 759 if (crtc < 0 || crtc >= rdev->num_crtc) { 760 DRM_ERROR("Invalid crtc %d\n", crtc); 761 return; 762 } 763 764 spin_lock_irqsave(&rdev->irq.lock, irqflags); 765 rdev->irq.crtc_vblank_int[crtc] = false; 766 radeon_irq_set(rdev); 767 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 768} 769 770/** 771 * radeon_get_vblank_timestamp_kms - get vblank timestamp 772 * 773 * @dev: drm dev pointer 774 * @crtc: crtc to get the timestamp for 775 * @max_error: max error 776 * @vblank_time: time value 777 * @flags: flags passed to the driver 778 * 779 * Gets the timestamp on the requested crtc based on the 780 * scanout position. (all asics). 781 * Returns postive status flags on success, negative error on failure. 782 */ 783int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 784 int *max_error, 785 struct timeval *vblank_time, 786 unsigned flags) 787{ 788 struct drm_crtc *drmcrtc; 789 struct radeon_device *rdev = dev->dev_private; 790 791 if (crtc < 0 || crtc >= dev->num_crtcs) { 792 DRM_ERROR("Invalid crtc %d\n", crtc); 793 return -EINVAL; 794 } 795 796 /* Get associated drm_crtc: */ 797 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 798 if (!drmcrtc) 799 return -EINVAL; 800 801 /* Helper routine in DRM core does all the work: */ 802 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 803 vblank_time, flags, 804 drmcrtc, &drmcrtc->hwmode); 805} 806 807#define KMS_INVALID_IOCTL(name) \ 808static int name(struct drm_device *dev, void *data, struct drm_file \ 809 *file_priv) \ 810{ \ 811 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 812 return -EINVAL; \ 813} 814 815/* 816 * All these ioctls are invalid in kms world. 817 */ 818KMS_INVALID_IOCTL(radeon_cp_init_kms) 819KMS_INVALID_IOCTL(radeon_cp_start_kms) 820KMS_INVALID_IOCTL(radeon_cp_stop_kms) 821KMS_INVALID_IOCTL(radeon_cp_reset_kms) 822KMS_INVALID_IOCTL(radeon_cp_idle_kms) 823KMS_INVALID_IOCTL(radeon_cp_resume_kms) 824KMS_INVALID_IOCTL(radeon_engine_reset_kms) 825KMS_INVALID_IOCTL(radeon_fullscreen_kms) 826KMS_INVALID_IOCTL(radeon_cp_swap_kms) 827KMS_INVALID_IOCTL(radeon_cp_clear_kms) 828KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 829KMS_INVALID_IOCTL(radeon_cp_indices_kms) 830KMS_INVALID_IOCTL(radeon_cp_texture_kms) 831KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 832KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 833KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 834KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 835KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 836KMS_INVALID_IOCTL(radeon_cp_flip_kms) 837KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 838KMS_INVALID_IOCTL(radeon_mem_free_kms) 839KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 840KMS_INVALID_IOCTL(radeon_irq_emit_kms) 841KMS_INVALID_IOCTL(radeon_irq_wait_kms) 842KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 843KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 844KMS_INVALID_IOCTL(radeon_surface_free_kms) 845 846 847const struct drm_ioctl_desc radeon_ioctls_kms[] = { 848 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 849 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 850 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 851 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 852 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 853 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 854 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 855 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 856 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 857 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 858 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 859 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 860 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 861 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 862 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 863 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 864 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 865 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 866 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 867 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 868 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 869 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 870 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 871 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 872 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 873 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 874 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 875 /* KMS */ 876 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 877 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 878 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 879 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 880 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 881 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 882 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 883 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 884 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 885 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 886 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 887 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 888 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 889 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 890 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 891}; 892int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 893