si_dpm.c revision 31f731af513bb9925d0a29dba34bb4f71141bf91
1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include "drmP.h" 25#include "radeon.h" 26#include "sid.h" 27#include "r600_dpm.h" 28#include "si_dpm.h" 29#include "atom.h" 30#include <linux/math64.h> 31#include <linux/seq_file.h> 32 33#define MC_CG_ARB_FREQ_F0 0x0a 34#define MC_CG_ARB_FREQ_F1 0x0b 35#define MC_CG_ARB_FREQ_F2 0x0c 36#define MC_CG_ARB_FREQ_F3 0x0d 37 38#define SMC_RAM_END 0x20000 39 40#define SCLK_MIN_DEEPSLEEP_FREQ 1350 41 42static const struct si_cac_config_reg cac_weights_tahiti[] = 43{ 44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 104 { 0xFFFFFFFF } 105}; 106 107static const struct si_cac_config_reg lcac_tahiti[] = 108{ 109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0xFFFFFFFF } 196 197}; 198 199static const struct si_cac_config_reg cac_override_tahiti[] = 200{ 201 { 0xFFFFFFFF } 202}; 203 204static const struct si_powertune_data powertune_data_tahiti = 205{ 206 ((1 << 16) | 27027), 207 6, 208 0, 209 4, 210 95, 211 { 212 0UL, 213 0UL, 214 4521550UL, 215 309631529UL, 216 -1270850L, 217 4513710L, 218 40 219 }, 220 595000000UL, 221 12, 222 { 223 0, 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0 231 }, 232 true 233}; 234 235static const struct si_dte_data dte_data_tahiti = 236{ 237 { 1159409, 0, 0, 0, 0 }, 238 { 777, 0, 0, 0, 0 }, 239 2, 240 54000, 241 127000, 242 25, 243 2, 244 10, 245 13, 246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 249 85, 250 false 251}; 252 253static const struct si_dte_data dte_data_tahiti_le = 254{ 255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 257 0x5, 258 0xAFC8, 259 0x64, 260 0x32, 261 1, 262 0, 263 0x10, 264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 267 85, 268 true 269}; 270 271static const struct si_dte_data dte_data_tahiti_pro = 272{ 273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 274 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 275 5, 276 45000, 277 100, 278 0xA, 279 1, 280 0, 281 0x10, 282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 285 90, 286 true 287}; 288 289static const struct si_dte_data dte_data_new_zealand = 290{ 291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 293 0x5, 294 0xAFC8, 295 0x69, 296 0x32, 297 1, 298 0, 299 0x10, 300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 303 85, 304 true 305}; 306 307static const struct si_dte_data dte_data_aruba_pro = 308{ 309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 310 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 311 5, 312 45000, 313 100, 314 0xA, 315 1, 316 0, 317 0x10, 318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 321 90, 322 true 323}; 324 325static const struct si_dte_data dte_data_malta = 326{ 327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 328 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 329 5, 330 45000, 331 100, 332 0xA, 333 1, 334 0, 335 0x10, 336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 339 90, 340 true 341}; 342 343struct si_cac_config_reg cac_weights_pitcairn[] = 344{ 345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 405 { 0xFFFFFFFF } 406}; 407 408static const struct si_cac_config_reg lcac_pitcairn[] = 409{ 410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 496 { 0xFFFFFFFF } 497}; 498 499static const struct si_cac_config_reg cac_override_pitcairn[] = 500{ 501 { 0xFFFFFFFF } 502}; 503 504static const struct si_powertune_data powertune_data_pitcairn = 505{ 506 ((1 << 16) | 27027), 507 5, 508 0, 509 6, 510 100, 511 { 512 51600000UL, 513 1800000UL, 514 7194395UL, 515 309631529UL, 516 -1270850L, 517 4513710L, 518 100 519 }, 520 117830498UL, 521 12, 522 { 523 0, 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0 531 }, 532 true 533}; 534 535static const struct si_dte_data dte_data_pitcairn = 536{ 537 { 0, 0, 0, 0, 0 }, 538 { 0, 0, 0, 0, 0 }, 539 0, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 0, 550 false 551}; 552 553static const struct si_dte_data dte_data_curacao_xt = 554{ 555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 556 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 557 5, 558 45000, 559 100, 560 0xA, 561 1, 562 0, 563 0x10, 564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 567 90, 568 true 569}; 570 571static const struct si_dte_data dte_data_curacao_pro = 572{ 573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 574 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 575 5, 576 45000, 577 100, 578 0xA, 579 1, 580 0, 581 0x10, 582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 585 90, 586 true 587}; 588 589static const struct si_dte_data dte_data_neptune_xt = 590{ 591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 592 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 593 5, 594 45000, 595 100, 596 0xA, 597 1, 598 0, 599 0x10, 600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 603 90, 604 true 605}; 606 607static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 608{ 609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 669 { 0xFFFFFFFF } 670}; 671 672static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 673{ 674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 734 { 0xFFFFFFFF } 735}; 736 737static const struct si_cac_config_reg cac_weights_heathrow[] = 738{ 739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 799 { 0xFFFFFFFF } 800}; 801 802static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 803{ 804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 864 { 0xFFFFFFFF } 865}; 866 867static const struct si_cac_config_reg cac_weights_cape_verde[] = 868{ 869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 929 { 0xFFFFFFFF } 930}; 931 932static const struct si_cac_config_reg lcac_cape_verde[] = 933{ 934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0xFFFFFFFF } 989}; 990 991static const struct si_cac_config_reg cac_override_cape_verde[] = 992{ 993 { 0xFFFFFFFF } 994}; 995 996static const struct si_powertune_data powertune_data_cape_verde = 997{ 998 ((1 << 16) | 0x6993), 999 5, 1000 0, 1001 7, 1002 105, 1003 { 1004 0UL, 1005 0UL, 1006 7194395UL, 1007 309631529UL, 1008 -1270850L, 1009 4513710L, 1010 100 1011 }, 1012 117830498UL, 1013 12, 1014 { 1015 0, 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0 1023 }, 1024 true 1025}; 1026 1027static const struct si_dte_data dte_data_cape_verde = 1028{ 1029 { 0, 0, 0, 0, 0 }, 1030 { 0, 0, 0, 0, 0 }, 1031 0, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 0, 1042 false 1043}; 1044 1045static const struct si_dte_data dte_data_venus_xtx = 1046{ 1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1049 5, 1050 55000, 1051 0x69, 1052 0xA, 1053 1, 1054 0, 1055 0x3, 1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 90, 1060 true 1061}; 1062 1063static const struct si_dte_data dte_data_venus_xt = 1064{ 1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1067 5, 1068 55000, 1069 0x69, 1070 0xA, 1071 1, 1072 0, 1073 0x3, 1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 90, 1078 true 1079}; 1080 1081static const struct si_dte_data dte_data_venus_pro = 1082{ 1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1085 5, 1086 55000, 1087 0x69, 1088 0xA, 1089 1, 1090 0, 1091 0x3, 1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 90, 1096 true 1097}; 1098 1099struct si_cac_config_reg cac_weights_oland[] = 1100{ 1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1161 { 0xFFFFFFFF } 1162}; 1163 1164static const struct si_cac_config_reg cac_weights_mars_pro[] = 1165{ 1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1226 { 0xFFFFFFFF } 1227}; 1228 1229static const struct si_cac_config_reg cac_weights_mars_xt[] = 1230{ 1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1291 { 0xFFFFFFFF } 1292}; 1293 1294static const struct si_cac_config_reg cac_weights_oland_pro[] = 1295{ 1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1356 { 0xFFFFFFFF } 1357}; 1358 1359static const struct si_cac_config_reg cac_weights_oland_xt[] = 1360{ 1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1421 { 0xFFFFFFFF } 1422}; 1423 1424static const struct si_cac_config_reg lcac_oland[] = 1425{ 1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0xFFFFFFFF } 1469}; 1470 1471static const struct si_cac_config_reg lcac_mars_pro[] = 1472{ 1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0xFFFFFFFF } 1516}; 1517 1518static const struct si_cac_config_reg cac_override_oland[] = 1519{ 1520 { 0xFFFFFFFF } 1521}; 1522 1523static const struct si_powertune_data powertune_data_oland = 1524{ 1525 ((1 << 16) | 0x6993), 1526 5, 1527 0, 1528 7, 1529 105, 1530 { 1531 0UL, 1532 0UL, 1533 7194395UL, 1534 309631529UL, 1535 -1270850L, 1536 4513710L, 1537 100 1538 }, 1539 117830498UL, 1540 12, 1541 { 1542 0, 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0 1550 }, 1551 true 1552}; 1553 1554static const struct si_powertune_data powertune_data_mars_pro = 1555{ 1556 ((1 << 16) | 0x6993), 1557 5, 1558 0, 1559 7, 1560 105, 1561 { 1562 0UL, 1563 0UL, 1564 7194395UL, 1565 309631529UL, 1566 -1270850L, 1567 4513710L, 1568 100 1569 }, 1570 117830498UL, 1571 12, 1572 { 1573 0, 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0 1581 }, 1582 true 1583}; 1584 1585static const struct si_dte_data dte_data_oland = 1586{ 1587 { 0, 0, 0, 0, 0 }, 1588 { 0, 0, 0, 0, 0 }, 1589 0, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 0, 1600 false 1601}; 1602 1603static const struct si_dte_data dte_data_mars_pro = 1604{ 1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1606 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1607 5, 1608 55000, 1609 105, 1610 0xA, 1611 1, 1612 0, 1613 0x10, 1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1617 90, 1618 true 1619}; 1620 1621static const struct si_dte_data dte_data_sun_xt = 1622{ 1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1624 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1625 5, 1626 55000, 1627 105, 1628 0xA, 1629 1, 1630 0, 1631 0x10, 1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1635 90, 1636 true 1637}; 1638 1639 1640static const struct si_cac_config_reg cac_weights_hainan[] = 1641{ 1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1702 { 0xFFFFFFFF } 1703}; 1704 1705static const struct si_powertune_data powertune_data_hainan = 1706{ 1707 ((1 << 16) | 0x6993), 1708 5, 1709 0, 1710 9, 1711 105, 1712 { 1713 0UL, 1714 0UL, 1715 7194395UL, 1716 309631529UL, 1717 -1270850L, 1718 4513710L, 1719 100 1720 }, 1721 117830498UL, 1722 12, 1723 { 1724 0, 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0 1732 }, 1733 true 1734}; 1735 1736struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1737struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1738struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1739struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1740 1741static int si_populate_voltage_value(struct radeon_device *rdev, 1742 const struct atom_voltage_table *table, 1743 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1744static int si_get_std_voltage_value(struct radeon_device *rdev, 1745 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1746 u16 *std_voltage); 1747static int si_write_smc_soft_register(struct radeon_device *rdev, 1748 u16 reg_offset, u32 value); 1749static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1750 struct rv7xx_pl *pl, 1751 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1752static int si_calculate_sclk_params(struct radeon_device *rdev, 1753 u32 engine_clock, 1754 SISLANDS_SMC_SCLK_VALUE *sclk); 1755 1756static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1757{ 1758 struct si_power_info *pi = rdev->pm.dpm.priv; 1759 1760 return pi; 1761} 1762 1763static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1764 u16 v, s32 t, u32 ileakage, u32 *leakage) 1765{ 1766 s64 kt, kv, leakage_w, i_leakage, vddc; 1767 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1768 s64 tmp; 1769 1770 i_leakage = drm_int2fixp(ileakage) / 100; 1771 vddc = div64_s64(drm_int2fixp(v), 1000); 1772 temperature = div64_s64(drm_int2fixp(t), 1000); 1773 1774 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1775 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1776 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1777 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1778 t_ref = drm_int2fixp(coeff->t_ref); 1779 1780 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1781 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1782 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1783 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1784 1785 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1786 1787 *leakage = drm_fixp2int(leakage_w * 1000); 1788} 1789 1790static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1791 const struct ni_leakage_coeffients *coeff, 1792 u16 v, 1793 s32 t, 1794 u32 i_leakage, 1795 u32 *leakage) 1796{ 1797 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1798} 1799 1800static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1801 const u32 fixed_kt, u16 v, 1802 u32 ileakage, u32 *leakage) 1803{ 1804 s64 kt, kv, leakage_w, i_leakage, vddc; 1805 1806 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1807 vddc = div64_s64(drm_int2fixp(v), 1000); 1808 1809 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1810 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1811 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1812 1813 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1814 1815 *leakage = drm_fixp2int(leakage_w * 1000); 1816} 1817 1818static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1819 const struct ni_leakage_coeffients *coeff, 1820 const u32 fixed_kt, 1821 u16 v, 1822 u32 i_leakage, 1823 u32 *leakage) 1824{ 1825 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1826} 1827 1828 1829static void si_update_dte_from_pl2(struct radeon_device *rdev, 1830 struct si_dte_data *dte_data) 1831{ 1832 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1833 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1834 u32 k = dte_data->k; 1835 u32 t_max = dte_data->max_t; 1836 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1837 u32 t_0 = dte_data->t0; 1838 u32 i; 1839 1840 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1841 dte_data->tdep_count = 3; 1842 1843 for (i = 0; i < k; i++) { 1844 dte_data->r[i] = 1845 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1846 (p_limit2 * (u32)100); 1847 } 1848 1849 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1850 1851 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1852 dte_data->tdep_r[i] = dte_data->r[4]; 1853 } 1854 } else { 1855 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1856 } 1857} 1858 1859static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1860{ 1861 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1862 struct si_power_info *si_pi = si_get_pi(rdev); 1863 bool update_dte_from_pl2 = false; 1864 1865 if (rdev->family == CHIP_TAHITI) { 1866 si_pi->cac_weights = cac_weights_tahiti; 1867 si_pi->lcac_config = lcac_tahiti; 1868 si_pi->cac_override = cac_override_tahiti; 1869 si_pi->powertune_data = &powertune_data_tahiti; 1870 si_pi->dte_data = dte_data_tahiti; 1871 1872 switch (rdev->pdev->device) { 1873 case 0x6798: 1874 si_pi->dte_data.enable_dte_by_default = true; 1875 break; 1876 case 0x6799: 1877 si_pi->dte_data = dte_data_new_zealand; 1878 break; 1879 case 0x6790: 1880 case 0x6791: 1881 case 0x6792: 1882 case 0x679E: 1883 si_pi->dte_data = dte_data_aruba_pro; 1884 update_dte_from_pl2 = true; 1885 break; 1886 case 0x679B: 1887 si_pi->dte_data = dte_data_malta; 1888 update_dte_from_pl2 = true; 1889 break; 1890 case 0x679A: 1891 si_pi->dte_data = dte_data_tahiti_pro; 1892 update_dte_from_pl2 = true; 1893 break; 1894 default: 1895 if (si_pi->dte_data.enable_dte_by_default == true) 1896 DRM_ERROR("DTE is not enabled!\n"); 1897 break; 1898 } 1899 } else if (rdev->family == CHIP_PITCAIRN) { 1900 switch (rdev->pdev->device) { 1901 case 0x6810: 1902 case 0x6818: 1903 si_pi->cac_weights = cac_weights_pitcairn; 1904 si_pi->lcac_config = lcac_pitcairn; 1905 si_pi->cac_override = cac_override_pitcairn; 1906 si_pi->powertune_data = &powertune_data_pitcairn; 1907 si_pi->dte_data = dte_data_curacao_xt; 1908 update_dte_from_pl2 = true; 1909 break; 1910 case 0x6819: 1911 case 0x6811: 1912 si_pi->cac_weights = cac_weights_pitcairn; 1913 si_pi->lcac_config = lcac_pitcairn; 1914 si_pi->cac_override = cac_override_pitcairn; 1915 si_pi->powertune_data = &powertune_data_pitcairn; 1916 si_pi->dte_data = dte_data_curacao_pro; 1917 update_dte_from_pl2 = true; 1918 break; 1919 case 0x6800: 1920 case 0x6806: 1921 si_pi->cac_weights = cac_weights_pitcairn; 1922 si_pi->lcac_config = lcac_pitcairn; 1923 si_pi->cac_override = cac_override_pitcairn; 1924 si_pi->powertune_data = &powertune_data_pitcairn; 1925 si_pi->dte_data = dte_data_neptune_xt; 1926 update_dte_from_pl2 = true; 1927 break; 1928 default: 1929 si_pi->cac_weights = cac_weights_pitcairn; 1930 si_pi->lcac_config = lcac_pitcairn; 1931 si_pi->cac_override = cac_override_pitcairn; 1932 si_pi->powertune_data = &powertune_data_pitcairn; 1933 si_pi->dte_data = dte_data_pitcairn; 1934 break; 1935 } 1936 } else if (rdev->family == CHIP_VERDE) { 1937 si_pi->lcac_config = lcac_cape_verde; 1938 si_pi->cac_override = cac_override_cape_verde; 1939 si_pi->powertune_data = &powertune_data_cape_verde; 1940 1941 switch (rdev->pdev->device) { 1942 case 0x683B: 1943 case 0x683F: 1944 case 0x6829: 1945 case 0x6835: 1946 si_pi->cac_weights = cac_weights_cape_verde_pro; 1947 si_pi->dte_data = dte_data_cape_verde; 1948 break; 1949 case 0x6825: 1950 case 0x6827: 1951 si_pi->cac_weights = cac_weights_heathrow; 1952 si_pi->dte_data = dte_data_cape_verde; 1953 break; 1954 case 0x6824: 1955 case 0x682D: 1956 si_pi->cac_weights = cac_weights_chelsea_xt; 1957 si_pi->dte_data = dte_data_cape_verde; 1958 break; 1959 case 0x682F: 1960 si_pi->cac_weights = cac_weights_chelsea_pro; 1961 si_pi->dte_data = dte_data_cape_verde; 1962 break; 1963 case 0x6820: 1964 si_pi->cac_weights = cac_weights_heathrow; 1965 si_pi->dte_data = dte_data_venus_xtx; 1966 break; 1967 case 0x6821: 1968 si_pi->cac_weights = cac_weights_heathrow; 1969 si_pi->dte_data = dte_data_venus_xt; 1970 break; 1971 case 0x6823: 1972 si_pi->cac_weights = cac_weights_chelsea_pro; 1973 si_pi->dte_data = dte_data_venus_pro; 1974 break; 1975 case 0x682B: 1976 si_pi->cac_weights = cac_weights_chelsea_pro; 1977 si_pi->dte_data = dte_data_venus_pro; 1978 break; 1979 default: 1980 si_pi->cac_weights = cac_weights_cape_verde; 1981 si_pi->dte_data = dte_data_cape_verde; 1982 break; 1983 } 1984 } else if (rdev->family == CHIP_OLAND) { 1985 switch (rdev->pdev->device) { 1986 case 0x6601: 1987 case 0x6621: 1988 case 0x6603: 1989 si_pi->cac_weights = cac_weights_mars_pro; 1990 si_pi->lcac_config = lcac_mars_pro; 1991 si_pi->cac_override = cac_override_oland; 1992 si_pi->powertune_data = &powertune_data_mars_pro; 1993 si_pi->dte_data = dte_data_mars_pro; 1994 update_dte_from_pl2 = true; 1995 break; 1996 case 0x6600: 1997 case 0x6606: 1998 case 0x6620: 1999 si_pi->cac_weights = cac_weights_mars_xt; 2000 si_pi->lcac_config = lcac_mars_pro; 2001 si_pi->cac_override = cac_override_oland; 2002 si_pi->powertune_data = &powertune_data_mars_pro; 2003 si_pi->dte_data = dte_data_mars_pro; 2004 update_dte_from_pl2 = true; 2005 break; 2006 case 0x6611: 2007 si_pi->cac_weights = cac_weights_oland_pro; 2008 si_pi->lcac_config = lcac_mars_pro; 2009 si_pi->cac_override = cac_override_oland; 2010 si_pi->powertune_data = &powertune_data_mars_pro; 2011 si_pi->dte_data = dte_data_mars_pro; 2012 update_dte_from_pl2 = true; 2013 break; 2014 case 0x6610: 2015 si_pi->cac_weights = cac_weights_oland_xt; 2016 si_pi->lcac_config = lcac_mars_pro; 2017 si_pi->cac_override = cac_override_oland; 2018 si_pi->powertune_data = &powertune_data_mars_pro; 2019 si_pi->dte_data = dte_data_mars_pro; 2020 update_dte_from_pl2 = true; 2021 break; 2022 default: 2023 si_pi->cac_weights = cac_weights_oland; 2024 si_pi->lcac_config = lcac_oland; 2025 si_pi->cac_override = cac_override_oland; 2026 si_pi->powertune_data = &powertune_data_oland; 2027 si_pi->dte_data = dte_data_oland; 2028 break; 2029 } 2030 } else if (rdev->family == CHIP_HAINAN) { 2031 si_pi->cac_weights = cac_weights_hainan; 2032 si_pi->lcac_config = lcac_oland; 2033 si_pi->cac_override = cac_override_oland; 2034 si_pi->powertune_data = &powertune_data_hainan; 2035 si_pi->dte_data = dte_data_sun_xt; 2036 update_dte_from_pl2 = true; 2037 } else { 2038 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2039 return; 2040 } 2041 2042 ni_pi->enable_power_containment = false; 2043 ni_pi->enable_cac = false; 2044 ni_pi->enable_sq_ramping = false; 2045 si_pi->enable_dte = false; 2046 2047 /* XXX: fix me */ 2048 if (0/*si_pi->powertune_data->enable_powertune_by_default*/) { 2049 ni_pi->enable_power_containment= true; 2050 ni_pi->enable_cac = true; 2051 if (si_pi->dte_data.enable_dte_by_default) { 2052 si_pi->enable_dte = true; 2053 if (update_dte_from_pl2) 2054 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2055 2056 } 2057 ni_pi->enable_sq_ramping = true; 2058 } 2059 2060 ni_pi->driver_calculate_cac_leakage = true; 2061 ni_pi->cac_configuration_required = true; 2062 2063 if (ni_pi->cac_configuration_required) { 2064 ni_pi->support_cac_long_term_average = true; 2065 si_pi->dyn_powertune_data.l2_lta_window_size = 2066 si_pi->powertune_data->l2_lta_window_size_default; 2067 si_pi->dyn_powertune_data.lts_truncate = 2068 si_pi->powertune_data->lts_truncate_default; 2069 } else { 2070 ni_pi->support_cac_long_term_average = false; 2071 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2072 si_pi->dyn_powertune_data.lts_truncate = 0; 2073 } 2074 2075 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2076} 2077 2078static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2079{ 2080 return 1; 2081} 2082 2083static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2084{ 2085 u32 xclk; 2086 u32 wintime; 2087 u32 cac_window; 2088 u32 cac_window_size; 2089 2090 xclk = radeon_get_xclk(rdev); 2091 2092 if (xclk == 0) 2093 return 0; 2094 2095 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2096 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2097 2098 wintime = (cac_window_size * 100) / xclk; 2099 2100 return wintime; 2101} 2102 2103static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2104{ 2105 return power_in_watts; 2106} 2107 2108static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2109 bool adjust_polarity, 2110 u32 tdp_adjustment, 2111 u32 *tdp_limit, 2112 u32 *near_tdp_limit) 2113{ 2114 u32 adjustment_delta, max_tdp_limit; 2115 2116 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2117 return -EINVAL; 2118 2119 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2120 2121 if (adjust_polarity) { 2122 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2123 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2124 } else { 2125 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2126 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2127 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2128 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2129 else 2130 *near_tdp_limit = 0; 2131 } 2132 2133 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2134 return -EINVAL; 2135 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2136 return -EINVAL; 2137 2138 return 0; 2139} 2140 2141static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2142 struct radeon_ps *radeon_state) 2143{ 2144 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2145 struct si_power_info *si_pi = si_get_pi(rdev); 2146 2147 if (ni_pi->enable_power_containment) { 2148 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2149 PP_SIslands_PAPMParameters *papm_parm; 2150 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2151 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2152 u32 tdp_limit; 2153 u32 near_tdp_limit; 2154 int ret; 2155 2156 if (scaling_factor == 0) 2157 return -EINVAL; 2158 2159 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2160 2161 ret = si_calculate_adjusted_tdp_limits(rdev, 2162 false, /* ??? */ 2163 rdev->pm.dpm.tdp_adjustment, 2164 &tdp_limit, 2165 &near_tdp_limit); 2166 if (ret) 2167 return ret; 2168 2169 smc_table->dpm2Params.TDPLimit = 2170 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2171 smc_table->dpm2Params.NearTDPLimit = 2172 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2173 smc_table->dpm2Params.SafePowerLimit = 2174 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2175 2176 ret = si_copy_bytes_to_smc(rdev, 2177 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2178 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2179 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2180 sizeof(u32) * 3, 2181 si_pi->sram_end); 2182 if (ret) 2183 return ret; 2184 2185 if (si_pi->enable_ppm) { 2186 papm_parm = &si_pi->papm_parm; 2187 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2188 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2189 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2190 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2191 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2192 papm_parm->PlatformPowerLimit = 0xffffffff; 2193 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2194 2195 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2196 (u8 *)papm_parm, 2197 sizeof(PP_SIslands_PAPMParameters), 2198 si_pi->sram_end); 2199 if (ret) 2200 return ret; 2201 } 2202 } 2203 return 0; 2204} 2205 2206static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2207 struct radeon_ps *radeon_state) 2208{ 2209 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2210 struct si_power_info *si_pi = si_get_pi(rdev); 2211 2212 if (ni_pi->enable_power_containment) { 2213 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2214 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2215 int ret; 2216 2217 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2218 2219 smc_table->dpm2Params.NearTDPLimit = 2220 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2221 smc_table->dpm2Params.SafePowerLimit = 2222 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2223 2224 ret = si_copy_bytes_to_smc(rdev, 2225 (si_pi->state_table_start + 2226 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2227 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2228 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2229 sizeof(u32) * 2, 2230 si_pi->sram_end); 2231 if (ret) 2232 return ret; 2233 } 2234 2235 return 0; 2236} 2237 2238static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2239 const u16 prev_std_vddc, 2240 const u16 curr_std_vddc) 2241{ 2242 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2243 u64 prev_vddc = (u64)prev_std_vddc; 2244 u64 curr_vddc = (u64)curr_std_vddc; 2245 u64 pwr_efficiency_ratio, n, d; 2246 2247 if ((prev_vddc == 0) || (curr_vddc == 0)) 2248 return 0; 2249 2250 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2251 d = prev_vddc * prev_vddc; 2252 pwr_efficiency_ratio = div64_u64(n, d); 2253 2254 if (pwr_efficiency_ratio > (u64)0xFFFF) 2255 return 0; 2256 2257 return (u16)pwr_efficiency_ratio; 2258} 2259 2260static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2261 struct radeon_ps *radeon_state) 2262{ 2263 struct si_power_info *si_pi = si_get_pi(rdev); 2264 2265 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2266 radeon_state->vclk && radeon_state->dclk) 2267 return true; 2268 2269 return false; 2270} 2271 2272static int si_populate_power_containment_values(struct radeon_device *rdev, 2273 struct radeon_ps *radeon_state, 2274 SISLANDS_SMC_SWSTATE *smc_state) 2275{ 2276 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2277 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2278 struct ni_ps *state = ni_get_ps(radeon_state); 2279 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2280 u32 prev_sclk; 2281 u32 max_sclk; 2282 u32 min_sclk; 2283 u16 prev_std_vddc; 2284 u16 curr_std_vddc; 2285 int i; 2286 u16 pwr_efficiency_ratio; 2287 u8 max_ps_percent; 2288 bool disable_uvd_power_tune; 2289 int ret; 2290 2291 if (ni_pi->enable_power_containment == false) 2292 return 0; 2293 2294 if (state->performance_level_count == 0) 2295 return -EINVAL; 2296 2297 if (smc_state->levelCount != state->performance_level_count) 2298 return -EINVAL; 2299 2300 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2301 2302 smc_state->levels[0].dpm2.MaxPS = 0; 2303 smc_state->levels[0].dpm2.NearTDPDec = 0; 2304 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2305 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2306 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2307 2308 for (i = 1; i < state->performance_level_count; i++) { 2309 prev_sclk = state->performance_levels[i-1].sclk; 2310 max_sclk = state->performance_levels[i].sclk; 2311 if (i == 1) 2312 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2313 else 2314 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2315 2316 if (prev_sclk > max_sclk) 2317 return -EINVAL; 2318 2319 if ((max_ps_percent == 0) || 2320 (prev_sclk == max_sclk) || 2321 disable_uvd_power_tune) { 2322 min_sclk = max_sclk; 2323 } else if (i == 1) { 2324 min_sclk = prev_sclk; 2325 } else { 2326 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2327 } 2328 2329 if (min_sclk < state->performance_levels[0].sclk) 2330 min_sclk = state->performance_levels[0].sclk; 2331 2332 if (min_sclk == 0) 2333 return -EINVAL; 2334 2335 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2336 state->performance_levels[i-1].vddc, &vddc); 2337 if (ret) 2338 return ret; 2339 2340 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2341 if (ret) 2342 return ret; 2343 2344 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2345 state->performance_levels[i].vddc, &vddc); 2346 if (ret) 2347 return ret; 2348 2349 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2350 if (ret) 2351 return ret; 2352 2353 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2354 prev_std_vddc, curr_std_vddc); 2355 2356 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2357 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2358 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2359 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2360 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2361 } 2362 2363 return 0; 2364} 2365 2366static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2367 struct radeon_ps *radeon_state, 2368 SISLANDS_SMC_SWSTATE *smc_state) 2369{ 2370 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2371 struct ni_ps *state = ni_get_ps(radeon_state); 2372 u32 sq_power_throttle, sq_power_throttle2; 2373 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2374 int i; 2375 2376 if (state->performance_level_count == 0) 2377 return -EINVAL; 2378 2379 if (smc_state->levelCount != state->performance_level_count) 2380 return -EINVAL; 2381 2382 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2383 return -EINVAL; 2384 2385 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2386 enable_sq_ramping = false; 2387 2388 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2389 enable_sq_ramping = false; 2390 2391 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2392 enable_sq_ramping = false; 2393 2394 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2395 enable_sq_ramping = false; 2396 2397 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2398 enable_sq_ramping = false; 2399 2400 for (i = 0; i < state->performance_level_count; i++) { 2401 sq_power_throttle = 0; 2402 sq_power_throttle2 = 0; 2403 2404 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2405 enable_sq_ramping) { 2406 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2407 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2408 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2409 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2410 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2411 } else { 2412 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2413 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2414 } 2415 2416 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2417 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2418 } 2419 2420 return 0; 2421} 2422 2423static int si_enable_power_containment(struct radeon_device *rdev, 2424 struct radeon_ps *radeon_new_state, 2425 bool enable) 2426{ 2427 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2428 PPSMC_Result smc_result; 2429 int ret = 0; 2430 2431 if (ni_pi->enable_power_containment) { 2432 if (enable) { 2433 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2434 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2435 if (smc_result != PPSMC_Result_OK) { 2436 ret = -EINVAL; 2437 ni_pi->pc_enabled = false; 2438 } else { 2439 ni_pi->pc_enabled = true; 2440 } 2441 } 2442 } else { 2443 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2444 if (smc_result != PPSMC_Result_OK) 2445 ret = -EINVAL; 2446 ni_pi->pc_enabled = false; 2447 } 2448 } 2449 2450 return ret; 2451} 2452 2453static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2454{ 2455 struct si_power_info *si_pi = si_get_pi(rdev); 2456 int ret = 0; 2457 struct si_dte_data *dte_data = &si_pi->dte_data; 2458 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2459 u32 table_size; 2460 u8 tdep_count; 2461 u32 i; 2462 2463 if (dte_data == NULL) 2464 si_pi->enable_dte = false; 2465 2466 if (si_pi->enable_dte == false) 2467 return 0; 2468 2469 if (dte_data->k <= 0) 2470 return -EINVAL; 2471 2472 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2473 if (dte_tables == NULL) { 2474 si_pi->enable_dte = false; 2475 return -ENOMEM; 2476 } 2477 2478 table_size = dte_data->k; 2479 2480 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2481 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2482 2483 tdep_count = dte_data->tdep_count; 2484 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2485 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2486 2487 dte_tables->K = cpu_to_be32(table_size); 2488 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2489 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2490 dte_tables->WindowSize = dte_data->window_size; 2491 dte_tables->temp_select = dte_data->temp_select; 2492 dte_tables->DTE_mode = dte_data->dte_mode; 2493 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2494 2495 if (tdep_count > 0) 2496 table_size--; 2497 2498 for (i = 0; i < table_size; i++) { 2499 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2500 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2501 } 2502 2503 dte_tables->Tdep_count = tdep_count; 2504 2505 for (i = 0; i < (u32)tdep_count; i++) { 2506 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2507 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2508 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2509 } 2510 2511 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2512 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2513 kfree(dte_tables); 2514 2515 return ret; 2516} 2517 2518static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2519 u16 *max, u16 *min) 2520{ 2521 struct si_power_info *si_pi = si_get_pi(rdev); 2522 struct radeon_cac_leakage_table *table = 2523 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2524 u32 i; 2525 u32 v0_loadline; 2526 2527 2528 if (table == NULL) 2529 return -EINVAL; 2530 2531 *max = 0; 2532 *min = 0xFFFF; 2533 2534 for (i = 0; i < table->count; i++) { 2535 if (table->entries[i].vddc > *max) 2536 *max = table->entries[i].vddc; 2537 if (table->entries[i].vddc < *min) 2538 *min = table->entries[i].vddc; 2539 } 2540 2541 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2542 return -EINVAL; 2543 2544 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2545 2546 if (v0_loadline > 0xFFFFUL) 2547 return -EINVAL; 2548 2549 *min = (u16)v0_loadline; 2550 2551 if ((*min > *max) || (*max == 0) || (*min == 0)) 2552 return -EINVAL; 2553 2554 return 0; 2555} 2556 2557static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2558{ 2559 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2560 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2561} 2562 2563static int si_init_dte_leakage_table(struct radeon_device *rdev, 2564 PP_SIslands_CacConfig *cac_tables, 2565 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2566 u16 t0, u16 t_step) 2567{ 2568 struct si_power_info *si_pi = si_get_pi(rdev); 2569 u32 leakage; 2570 unsigned int i, j; 2571 s32 t; 2572 u32 smc_leakage; 2573 u32 scaling_factor; 2574 u16 voltage; 2575 2576 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2577 2578 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2579 t = (1000 * (i * t_step + t0)); 2580 2581 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2582 voltage = vddc_max - (vddc_step * j); 2583 2584 si_calculate_leakage_for_v_and_t(rdev, 2585 &si_pi->powertune_data->leakage_coefficients, 2586 voltage, 2587 t, 2588 si_pi->dyn_powertune_data.cac_leakage, 2589 &leakage); 2590 2591 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2592 2593 if (smc_leakage > 0xFFFF) 2594 smc_leakage = 0xFFFF; 2595 2596 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2597 cpu_to_be16((u16)smc_leakage); 2598 } 2599 } 2600 return 0; 2601} 2602 2603static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2604 PP_SIslands_CacConfig *cac_tables, 2605 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2606{ 2607 struct si_power_info *si_pi = si_get_pi(rdev); 2608 u32 leakage; 2609 unsigned int i, j; 2610 u32 smc_leakage; 2611 u32 scaling_factor; 2612 u16 voltage; 2613 2614 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2615 2616 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2617 voltage = vddc_max - (vddc_step * j); 2618 2619 si_calculate_leakage_for_v(rdev, 2620 &si_pi->powertune_data->leakage_coefficients, 2621 si_pi->powertune_data->fixed_kt, 2622 voltage, 2623 si_pi->dyn_powertune_data.cac_leakage, 2624 &leakage); 2625 2626 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2627 2628 if (smc_leakage > 0xFFFF) 2629 smc_leakage = 0xFFFF; 2630 2631 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2632 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2633 cpu_to_be16((u16)smc_leakage); 2634 } 2635 return 0; 2636} 2637 2638static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2639{ 2640 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2641 struct si_power_info *si_pi = si_get_pi(rdev); 2642 PP_SIslands_CacConfig *cac_tables = NULL; 2643 u16 vddc_max, vddc_min, vddc_step; 2644 u16 t0, t_step; 2645 u32 load_line_slope, reg; 2646 int ret = 0; 2647 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2648 2649 if (ni_pi->enable_cac == false) 2650 return 0; 2651 2652 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2653 if (!cac_tables) 2654 return -ENOMEM; 2655 2656 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2657 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2658 WREG32(CG_CAC_CTRL, reg); 2659 2660 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2661 si_pi->dyn_powertune_data.dc_pwr_value = 2662 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2663 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2664 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2665 2666 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2667 2668 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2669 if (ret) 2670 goto done_free; 2671 2672 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2673 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2674 t_step = 4; 2675 t0 = 60; 2676 2677 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2678 ret = si_init_dte_leakage_table(rdev, cac_tables, 2679 vddc_max, vddc_min, vddc_step, 2680 t0, t_step); 2681 else 2682 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2683 vddc_max, vddc_min, vddc_step); 2684 if (ret) 2685 goto done_free; 2686 2687 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2688 2689 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2690 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2691 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2692 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2693 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2694 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2695 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2696 cac_tables->calculation_repeats = cpu_to_be32(2); 2697 cac_tables->dc_cac = cpu_to_be32(0); 2698 cac_tables->log2_PG_LKG_SCALE = 12; 2699 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2700 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2701 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2702 2703 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2704 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2705 2706 if (ret) 2707 goto done_free; 2708 2709 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2710 2711done_free: 2712 if (ret) { 2713 ni_pi->enable_cac = false; 2714 ni_pi->enable_power_containment = false; 2715 } 2716 2717 kfree(cac_tables); 2718 2719 return 0; 2720} 2721 2722static int si_program_cac_config_registers(struct radeon_device *rdev, 2723 const struct si_cac_config_reg *cac_config_regs) 2724{ 2725 const struct si_cac_config_reg *config_regs = cac_config_regs; 2726 u32 data = 0, offset; 2727 2728 if (!config_regs) 2729 return -EINVAL; 2730 2731 while (config_regs->offset != 0xFFFFFFFF) { 2732 switch (config_regs->type) { 2733 case SISLANDS_CACCONFIG_CGIND: 2734 offset = SMC_CG_IND_START + config_regs->offset; 2735 if (offset < SMC_CG_IND_END) 2736 data = RREG32_SMC(offset); 2737 break; 2738 default: 2739 data = RREG32(config_regs->offset << 2); 2740 break; 2741 } 2742 2743 data &= ~config_regs->mask; 2744 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2745 2746 switch (config_regs->type) { 2747 case SISLANDS_CACCONFIG_CGIND: 2748 offset = SMC_CG_IND_START + config_regs->offset; 2749 if (offset < SMC_CG_IND_END) 2750 WREG32_SMC(offset, data); 2751 break; 2752 default: 2753 WREG32(config_regs->offset << 2, data); 2754 break; 2755 } 2756 config_regs++; 2757 } 2758 return 0; 2759} 2760 2761static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2762{ 2763 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2764 struct si_power_info *si_pi = si_get_pi(rdev); 2765 int ret; 2766 2767 if ((ni_pi->enable_cac == false) || 2768 (ni_pi->cac_configuration_required == false)) 2769 return 0; 2770 2771 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2772 if (ret) 2773 return ret; 2774 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2775 if (ret) 2776 return ret; 2777 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2778 if (ret) 2779 return ret; 2780 2781 return 0; 2782} 2783 2784static int si_enable_smc_cac(struct radeon_device *rdev, 2785 struct radeon_ps *radeon_new_state, 2786 bool enable) 2787{ 2788 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2789 struct si_power_info *si_pi = si_get_pi(rdev); 2790 PPSMC_Result smc_result; 2791 int ret = 0; 2792 2793 if (ni_pi->enable_cac) { 2794 if (enable) { 2795 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2796 if (ni_pi->support_cac_long_term_average) { 2797 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2798 if (smc_result != PPSMC_Result_OK) 2799 ni_pi->support_cac_long_term_average = false; 2800 } 2801 2802 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2803 if (smc_result != PPSMC_Result_OK) { 2804 ret = -EINVAL; 2805 ni_pi->cac_enabled = false; 2806 } else { 2807 ni_pi->cac_enabled = true; 2808 } 2809 2810 if (si_pi->enable_dte) { 2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2812 if (smc_result != PPSMC_Result_OK) 2813 ret = -EINVAL; 2814 } 2815 } 2816 } else if (ni_pi->cac_enabled) { 2817 if (si_pi->enable_dte) 2818 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2819 2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2821 2822 ni_pi->cac_enabled = false; 2823 2824 if (ni_pi->support_cac_long_term_average) 2825 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2826 } 2827 } 2828 return ret; 2829} 2830 2831static int si_init_smc_spll_table(struct radeon_device *rdev) 2832{ 2833 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2834 struct si_power_info *si_pi = si_get_pi(rdev); 2835 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2836 SISLANDS_SMC_SCLK_VALUE sclk_params; 2837 u32 fb_div, p_div; 2838 u32 clk_s, clk_v; 2839 u32 sclk = 0; 2840 int ret = 0; 2841 u32 tmp; 2842 int i; 2843 2844 if (si_pi->spll_table_start == 0) 2845 return -EINVAL; 2846 2847 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2848 if (spll_table == NULL) 2849 return -ENOMEM; 2850 2851 for (i = 0; i < 256; i++) { 2852 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2853 if (ret) 2854 break; 2855 2856 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2857 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2858 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2859 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2860 2861 fb_div &= ~0x00001FFF; 2862 fb_div >>= 1; 2863 clk_v >>= 6; 2864 2865 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2866 ret = -EINVAL; 2867 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2868 ret = -EINVAL; 2869 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2870 ret = -EINVAL; 2871 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2872 ret = -EINVAL; 2873 2874 if (ret) 2875 break; 2876 2877 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2878 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2879 spll_table->freq[i] = cpu_to_be32(tmp); 2880 2881 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2882 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2883 spll_table->ss[i] = cpu_to_be32(tmp); 2884 2885 sclk += 512; 2886 } 2887 2888 2889 if (!ret) 2890 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2891 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2892 si_pi->sram_end); 2893 2894 if (ret) 2895 ni_pi->enable_power_containment = false; 2896 2897 kfree(spll_table); 2898 2899 return ret; 2900} 2901 2902static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2903 struct radeon_ps *rps) 2904{ 2905 struct ni_ps *ps = ni_get_ps(rps); 2906 struct radeon_clock_and_voltage_limits *max_limits; 2907 bool disable_mclk_switching; 2908 u32 mclk, sclk; 2909 u16 vddc, vddci; 2910 int i; 2911 2912 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2913 ni_dpm_vblank_too_short(rdev)) 2914 disable_mclk_switching = true; 2915 else 2916 disable_mclk_switching = false; 2917 2918 if (rdev->pm.dpm.ac_power) 2919 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2920 else 2921 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2922 2923 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2924 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2925 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2926 } 2927 if (rdev->pm.dpm.ac_power == false) { 2928 for (i = 0; i < ps->performance_level_count; i++) { 2929 if (ps->performance_levels[i].mclk > max_limits->mclk) 2930 ps->performance_levels[i].mclk = max_limits->mclk; 2931 if (ps->performance_levels[i].sclk > max_limits->sclk) 2932 ps->performance_levels[i].sclk = max_limits->sclk; 2933 if (ps->performance_levels[i].vddc > max_limits->vddc) 2934 ps->performance_levels[i].vddc = max_limits->vddc; 2935 if (ps->performance_levels[i].vddci > max_limits->vddci) 2936 ps->performance_levels[i].vddci = max_limits->vddci; 2937 } 2938 } 2939 2940 /* XXX validate the min clocks required for display */ 2941 2942 if (disable_mclk_switching) { 2943 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2944 sclk = ps->performance_levels[0].sclk; 2945 vddc = ps->performance_levels[0].vddc; 2946 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2947 } else { 2948 sclk = ps->performance_levels[0].sclk; 2949 mclk = ps->performance_levels[0].mclk; 2950 vddc = ps->performance_levels[0].vddc; 2951 vddci = ps->performance_levels[0].vddci; 2952 } 2953 2954 /* adjusted low state */ 2955 ps->performance_levels[0].sclk = sclk; 2956 ps->performance_levels[0].mclk = mclk; 2957 ps->performance_levels[0].vddc = vddc; 2958 ps->performance_levels[0].vddci = vddci; 2959 2960 for (i = 1; i < ps->performance_level_count; i++) { 2961 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2962 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2963 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2964 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2965 } 2966 2967 if (disable_mclk_switching) { 2968 mclk = ps->performance_levels[0].mclk; 2969 for (i = 1; i < ps->performance_level_count; i++) { 2970 if (mclk < ps->performance_levels[i].mclk) 2971 mclk = ps->performance_levels[i].mclk; 2972 } 2973 for (i = 0; i < ps->performance_level_count; i++) { 2974 ps->performance_levels[i].mclk = mclk; 2975 ps->performance_levels[i].vddci = vddci; 2976 } 2977 } else { 2978 for (i = 1; i < ps->performance_level_count; i++) { 2979 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 2980 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 2981 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 2982 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 2983 } 2984 } 2985 2986 for (i = 0; i < ps->performance_level_count; i++) 2987 btc_adjust_clock_combinations(rdev, max_limits, 2988 &ps->performance_levels[i]); 2989 2990 for (i = 0; i < ps->performance_level_count; i++) { 2991 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2992 ps->performance_levels[i].sclk, 2993 max_limits->vddc, &ps->performance_levels[i].vddc); 2994 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2995 ps->performance_levels[i].mclk, 2996 max_limits->vddci, &ps->performance_levels[i].vddci); 2997 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2998 ps->performance_levels[i].mclk, 2999 max_limits->vddc, &ps->performance_levels[i].vddc); 3000 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3001 rdev->clock.current_dispclk, 3002 max_limits->vddc, &ps->performance_levels[i].vddc); 3003 } 3004 3005 for (i = 0; i < ps->performance_level_count; i++) { 3006 btc_apply_voltage_delta_rules(rdev, 3007 max_limits->vddc, max_limits->vddci, 3008 &ps->performance_levels[i].vddc, 3009 &ps->performance_levels[i].vddci); 3010 } 3011 3012 ps->dc_compatible = true; 3013 for (i = 0; i < ps->performance_level_count; i++) { 3014 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3015 ps->dc_compatible = false; 3016 } 3017 3018} 3019 3020#if 0 3021static int si_read_smc_soft_register(struct radeon_device *rdev, 3022 u16 reg_offset, u32 *value) 3023{ 3024 struct si_power_info *si_pi = si_get_pi(rdev); 3025 3026 return si_read_smc_sram_dword(rdev, 3027 si_pi->soft_regs_start + reg_offset, value, 3028 si_pi->sram_end); 3029} 3030#endif 3031 3032static int si_write_smc_soft_register(struct radeon_device *rdev, 3033 u16 reg_offset, u32 value) 3034{ 3035 struct si_power_info *si_pi = si_get_pi(rdev); 3036 3037 return si_write_smc_sram_dword(rdev, 3038 si_pi->soft_regs_start + reg_offset, 3039 value, si_pi->sram_end); 3040} 3041 3042static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3043{ 3044 bool ret = false; 3045 u32 tmp, width, row, column, bank, density; 3046 bool is_memory_gddr5, is_special; 3047 3048 tmp = RREG32(MC_SEQ_MISC0); 3049 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3050 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3051 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3052 3053 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3054 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3055 3056 tmp = RREG32(MC_ARB_RAMCFG); 3057 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3058 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3059 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3060 3061 density = (1 << (row + column - 20 + bank)) * width; 3062 3063 if ((rdev->pdev->device == 0x6819) && 3064 is_memory_gddr5 && is_special && (density == 0x400)) 3065 ret = true; 3066 3067 return ret; 3068} 3069 3070static void si_get_leakage_vddc(struct radeon_device *rdev) 3071{ 3072 struct si_power_info *si_pi = si_get_pi(rdev); 3073 u16 vddc, count = 0; 3074 int i, ret; 3075 3076 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3077 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3078 3079 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3080 si_pi->leakage_voltage.entries[count].voltage = vddc; 3081 si_pi->leakage_voltage.entries[count].leakage_index = 3082 SISLANDS_LEAKAGE_INDEX0 + i; 3083 count++; 3084 } 3085 } 3086 si_pi->leakage_voltage.count = count; 3087} 3088 3089static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3090 u32 index, u16 *leakage_voltage) 3091{ 3092 struct si_power_info *si_pi = si_get_pi(rdev); 3093 int i; 3094 3095 if (leakage_voltage == NULL) 3096 return -EINVAL; 3097 3098 if ((index & 0xff00) != 0xff00) 3099 return -EINVAL; 3100 3101 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3102 return -EINVAL; 3103 3104 if (index < SISLANDS_LEAKAGE_INDEX0) 3105 return -EINVAL; 3106 3107 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3108 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3109 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3110 return 0; 3111 } 3112 } 3113 return -EAGAIN; 3114} 3115 3116static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3117{ 3118 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3119 bool want_thermal_protection; 3120 enum radeon_dpm_event_src dpm_event_src; 3121 3122 switch (sources) { 3123 case 0: 3124 default: 3125 want_thermal_protection = false; 3126 break; 3127 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3128 want_thermal_protection = true; 3129 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3130 break; 3131 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3132 want_thermal_protection = true; 3133 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3134 break; 3135 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3136 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3137 want_thermal_protection = true; 3138 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3139 break; 3140 } 3141 3142 if (want_thermal_protection) { 3143 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3144 if (pi->thermal_protection) 3145 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3146 } else { 3147 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3148 } 3149} 3150 3151static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3152 enum radeon_dpm_auto_throttle_src source, 3153 bool enable) 3154{ 3155 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3156 3157 if (enable) { 3158 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3159 pi->active_auto_throttle_sources |= 1 << source; 3160 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3161 } 3162 } else { 3163 if (pi->active_auto_throttle_sources & (1 << source)) { 3164 pi->active_auto_throttle_sources &= ~(1 << source); 3165 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3166 } 3167 } 3168} 3169 3170static void si_start_dpm(struct radeon_device *rdev) 3171{ 3172 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3173} 3174 3175static void si_stop_dpm(struct radeon_device *rdev) 3176{ 3177 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3178} 3179 3180static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3181{ 3182 if (enable) 3183 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3184 else 3185 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3186 3187} 3188 3189#if 0 3190static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3191 u32 thermal_level) 3192{ 3193 PPSMC_Result ret; 3194 3195 if (thermal_level == 0) { 3196 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3197 if (ret == PPSMC_Result_OK) 3198 return 0; 3199 else 3200 return -EINVAL; 3201 } 3202 return 0; 3203} 3204 3205static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3206{ 3207 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3208} 3209#endif 3210 3211#if 0 3212static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3213{ 3214 if (ac_power) 3215 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3216 0 : -EINVAL; 3217 3218 return 0; 3219} 3220#endif 3221 3222static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3223 PPSMC_Msg msg, u32 parameter) 3224{ 3225 WREG32(SMC_SCRATCH0, parameter); 3226 return si_send_msg_to_smc(rdev, msg); 3227} 3228 3229static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3230{ 3231 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3232 return -EINVAL; 3233 3234 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3235 0 : -EINVAL; 3236} 3237 3238int si_dpm_force_performance_level(struct radeon_device *rdev, 3239 enum radeon_dpm_forced_level level) 3240{ 3241 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3242 struct ni_ps *ps = ni_get_ps(rps); 3243 u32 levels = ps->performance_level_count; 3244 3245 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3246 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3247 return -EINVAL; 3248 3249 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3250 return -EINVAL; 3251 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3252 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3253 return -EINVAL; 3254 3255 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3256 return -EINVAL; 3257 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3258 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3259 return -EINVAL; 3260 3261 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3262 return -EINVAL; 3263 } 3264 3265 rdev->pm.dpm.forced_level = level; 3266 3267 return 0; 3268} 3269 3270static int si_set_boot_state(struct radeon_device *rdev) 3271{ 3272 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3273 0 : -EINVAL; 3274} 3275 3276static int si_set_sw_state(struct radeon_device *rdev) 3277{ 3278 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3279 0 : -EINVAL; 3280} 3281 3282static int si_halt_smc(struct radeon_device *rdev) 3283{ 3284 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3285 return -EINVAL; 3286 3287 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3288 0 : -EINVAL; 3289} 3290 3291static int si_resume_smc(struct radeon_device *rdev) 3292{ 3293 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3294 return -EINVAL; 3295 3296 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3297 0 : -EINVAL; 3298} 3299 3300static void si_dpm_start_smc(struct radeon_device *rdev) 3301{ 3302 si_program_jump_on_start(rdev); 3303 si_start_smc(rdev); 3304 si_start_smc_clock(rdev); 3305} 3306 3307static void si_dpm_stop_smc(struct radeon_device *rdev) 3308{ 3309 si_reset_smc(rdev); 3310 si_stop_smc_clock(rdev); 3311} 3312 3313static int si_process_firmware_header(struct radeon_device *rdev) 3314{ 3315 struct si_power_info *si_pi = si_get_pi(rdev); 3316 u32 tmp; 3317 int ret; 3318 3319 ret = si_read_smc_sram_dword(rdev, 3320 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3321 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3322 &tmp, si_pi->sram_end); 3323 if (ret) 3324 return ret; 3325 3326 si_pi->state_table_start = tmp; 3327 3328 ret = si_read_smc_sram_dword(rdev, 3329 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3330 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3331 &tmp, si_pi->sram_end); 3332 if (ret) 3333 return ret; 3334 3335 si_pi->soft_regs_start = tmp; 3336 3337 ret = si_read_smc_sram_dword(rdev, 3338 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3339 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3340 &tmp, si_pi->sram_end); 3341 if (ret) 3342 return ret; 3343 3344 si_pi->mc_reg_table_start = tmp; 3345 3346 ret = si_read_smc_sram_dword(rdev, 3347 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3348 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3349 &tmp, si_pi->sram_end); 3350 if (ret) 3351 return ret; 3352 3353 si_pi->arb_table_start = tmp; 3354 3355 ret = si_read_smc_sram_dword(rdev, 3356 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3357 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3358 &tmp, si_pi->sram_end); 3359 if (ret) 3360 return ret; 3361 3362 si_pi->cac_table_start = tmp; 3363 3364 ret = si_read_smc_sram_dword(rdev, 3365 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3366 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3367 &tmp, si_pi->sram_end); 3368 if (ret) 3369 return ret; 3370 3371 si_pi->dte_table_start = tmp; 3372 3373 ret = si_read_smc_sram_dword(rdev, 3374 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3375 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3376 &tmp, si_pi->sram_end); 3377 if (ret) 3378 return ret; 3379 3380 si_pi->spll_table_start = tmp; 3381 3382 ret = si_read_smc_sram_dword(rdev, 3383 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3384 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3385 &tmp, si_pi->sram_end); 3386 if (ret) 3387 return ret; 3388 3389 si_pi->papm_cfg_table_start = tmp; 3390 3391 return ret; 3392} 3393 3394static void si_read_clock_registers(struct radeon_device *rdev) 3395{ 3396 struct si_power_info *si_pi = si_get_pi(rdev); 3397 3398 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3399 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3400 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3401 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3402 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3403 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3404 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3405 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3406 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3407 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3408 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3409 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3410 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3411 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3412 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3413} 3414 3415static void si_enable_thermal_protection(struct radeon_device *rdev, 3416 bool enable) 3417{ 3418 if (enable) 3419 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3420 else 3421 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3422} 3423 3424static void si_enable_acpi_power_management(struct radeon_device *rdev) 3425{ 3426 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3427} 3428 3429#if 0 3430static int si_enter_ulp_state(struct radeon_device *rdev) 3431{ 3432 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3433 3434 udelay(25000); 3435 3436 return 0; 3437} 3438 3439static int si_exit_ulp_state(struct radeon_device *rdev) 3440{ 3441 int i; 3442 3443 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3444 3445 udelay(7000); 3446 3447 for (i = 0; i < rdev->usec_timeout; i++) { 3448 if (RREG32(SMC_RESP_0) == 1) 3449 break; 3450 udelay(1000); 3451 } 3452 3453 return 0; 3454} 3455#endif 3456 3457static int si_notify_smc_display_change(struct radeon_device *rdev, 3458 bool has_display) 3459{ 3460 PPSMC_Msg msg = has_display ? 3461 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3462 3463 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3464 0 : -EINVAL; 3465} 3466 3467static void si_program_response_times(struct radeon_device *rdev) 3468{ 3469 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3470 u32 vddc_dly, acpi_dly, vbi_dly; 3471 u32 reference_clock; 3472 3473 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3474 3475 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3476 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3477 3478 if (voltage_response_time == 0) 3479 voltage_response_time = 1000; 3480 3481 acpi_delay_time = 15000; 3482 vbi_time_out = 100000; 3483 3484 reference_clock = radeon_get_xclk(rdev); 3485 3486 vddc_dly = (voltage_response_time * reference_clock) / 100; 3487 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3488 vbi_dly = (vbi_time_out * reference_clock) / 100; 3489 3490 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3491 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3492 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3493 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3494} 3495 3496static void si_program_ds_registers(struct radeon_device *rdev) 3497{ 3498 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3499 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3500 3501 if (eg_pi->sclk_deep_sleep) { 3502 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3503 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3504 ~AUTOSCALE_ON_SS_CLEAR); 3505 } 3506} 3507 3508static void si_program_display_gap(struct radeon_device *rdev) 3509{ 3510 u32 tmp, pipe; 3511 int i; 3512 3513 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3514 if (rdev->pm.dpm.new_active_crtc_count > 0) 3515 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3516 else 3517 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3518 3519 if (rdev->pm.dpm.new_active_crtc_count > 1) 3520 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3521 else 3522 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3523 3524 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3525 3526 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3527 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3528 3529 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3530 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3531 /* find the first active crtc */ 3532 for (i = 0; i < rdev->num_crtc; i++) { 3533 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3534 break; 3535 } 3536 if (i == rdev->num_crtc) 3537 pipe = 0; 3538 else 3539 pipe = i; 3540 3541 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3542 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3543 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3544 } 3545 3546 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3547} 3548 3549static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3550{ 3551 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3552 3553 if (enable) { 3554 if (pi->sclk_ss) 3555 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3556 } else { 3557 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3558 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3559 } 3560} 3561 3562static void si_setup_bsp(struct radeon_device *rdev) 3563{ 3564 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3565 u32 xclk = radeon_get_xclk(rdev); 3566 3567 r600_calculate_u_and_p(pi->asi, 3568 xclk, 3569 16, 3570 &pi->bsp, 3571 &pi->bsu); 3572 3573 r600_calculate_u_and_p(pi->pasi, 3574 xclk, 3575 16, 3576 &pi->pbsp, 3577 &pi->pbsu); 3578 3579 3580 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3581 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3582 3583 WREG32(CG_BSP, pi->dsp); 3584} 3585 3586static void si_program_git(struct radeon_device *rdev) 3587{ 3588 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3589} 3590 3591static void si_program_tp(struct radeon_device *rdev) 3592{ 3593 int i; 3594 enum r600_td td = R600_TD_DFLT; 3595 3596 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3597 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3598 3599 if (td == R600_TD_AUTO) 3600 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3601 else 3602 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3603 3604 if (td == R600_TD_UP) 3605 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3606 3607 if (td == R600_TD_DOWN) 3608 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3609} 3610 3611static void si_program_tpp(struct radeon_device *rdev) 3612{ 3613 WREG32(CG_TPC, R600_TPC_DFLT); 3614} 3615 3616static void si_program_sstp(struct radeon_device *rdev) 3617{ 3618 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3619} 3620 3621static void si_enable_display_gap(struct radeon_device *rdev) 3622{ 3623 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3624 3625 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3626 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3627 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3628 3629 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3630 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3631 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3632 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3633} 3634 3635static void si_program_vc(struct radeon_device *rdev) 3636{ 3637 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3638 3639 WREG32(CG_FTV, pi->vrc); 3640} 3641 3642static void si_clear_vc(struct radeon_device *rdev) 3643{ 3644 WREG32(CG_FTV, 0); 3645} 3646 3647static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3648{ 3649 u8 mc_para_index; 3650 3651 if (memory_clock < 10000) 3652 mc_para_index = 0; 3653 else if (memory_clock >= 80000) 3654 mc_para_index = 0x0f; 3655 else 3656 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3657 return mc_para_index; 3658} 3659 3660static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3661{ 3662 u8 mc_para_index; 3663 3664 if (strobe_mode) { 3665 if (memory_clock < 12500) 3666 mc_para_index = 0x00; 3667 else if (memory_clock > 47500) 3668 mc_para_index = 0x0f; 3669 else 3670 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3671 } else { 3672 if (memory_clock < 65000) 3673 mc_para_index = 0x00; 3674 else if (memory_clock > 135000) 3675 mc_para_index = 0x0f; 3676 else 3677 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3678 } 3679 return mc_para_index; 3680} 3681 3682static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3683{ 3684 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3685 bool strobe_mode = false; 3686 u8 result = 0; 3687 3688 if (mclk <= pi->mclk_strobe_mode_threshold) 3689 strobe_mode = true; 3690 3691 if (pi->mem_gddr5) 3692 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3693 else 3694 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3695 3696 if (strobe_mode) 3697 result |= SISLANDS_SMC_STROBE_ENABLE; 3698 3699 return result; 3700} 3701 3702static int si_upload_firmware(struct radeon_device *rdev) 3703{ 3704 struct si_power_info *si_pi = si_get_pi(rdev); 3705 int ret; 3706 3707 si_reset_smc(rdev); 3708 si_stop_smc_clock(rdev); 3709 3710 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3711 3712 return ret; 3713} 3714 3715static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3716 const struct atom_voltage_table *table, 3717 const struct radeon_phase_shedding_limits_table *limits) 3718{ 3719 u32 data, num_bits, num_levels; 3720 3721 if ((table == NULL) || (limits == NULL)) 3722 return false; 3723 3724 data = table->mask_low; 3725 3726 num_bits = hweight32(data); 3727 3728 if (num_bits == 0) 3729 return false; 3730 3731 num_levels = (1 << num_bits); 3732 3733 if (table->count != num_levels) 3734 return false; 3735 3736 if (limits->count != (num_levels - 1)) 3737 return false; 3738 3739 return true; 3740} 3741 3742static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3743 struct atom_voltage_table *voltage_table) 3744{ 3745 unsigned int i, diff; 3746 3747 if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS) 3748 return; 3749 3750 diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS; 3751 3752 for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++) 3753 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3754 3755 voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS; 3756} 3757 3758static int si_construct_voltage_tables(struct radeon_device *rdev) 3759{ 3760 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3761 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3762 struct si_power_info *si_pi = si_get_pi(rdev); 3763 int ret; 3764 3765 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3766 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3767 if (ret) 3768 return ret; 3769 3770 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3771 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table); 3772 3773 if (eg_pi->vddci_control) { 3774 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3775 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3776 if (ret) 3777 return ret; 3778 3779 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3780 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table); 3781 } 3782 3783 if (pi->mvdd_control) { 3784 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3785 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3786 3787 if (ret) { 3788 pi->mvdd_control = false; 3789 return ret; 3790 } 3791 3792 if (si_pi->mvdd_voltage_table.count == 0) { 3793 pi->mvdd_control = false; 3794 return -EINVAL; 3795 } 3796 3797 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3798 si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table); 3799 } 3800 3801 if (si_pi->vddc_phase_shed_control) { 3802 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3803 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3804 if (ret) 3805 si_pi->vddc_phase_shed_control = false; 3806 3807 if ((si_pi->vddc_phase_shed_table.count == 0) || 3808 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3809 si_pi->vddc_phase_shed_control = false; 3810 } 3811 3812 return 0; 3813} 3814 3815static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3816 const struct atom_voltage_table *voltage_table, 3817 SISLANDS_SMC_STATETABLE *table) 3818{ 3819 unsigned int i; 3820 3821 for (i = 0; i < voltage_table->count; i++) 3822 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3823} 3824 3825static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3826 SISLANDS_SMC_STATETABLE *table) 3827{ 3828 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3829 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3830 struct si_power_info *si_pi = si_get_pi(rdev); 3831 u8 i; 3832 3833 if (eg_pi->vddc_voltage_table.count) { 3834 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3835 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3836 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3837 3838 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3839 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3840 table->maxVDDCIndexInPPTable = i; 3841 break; 3842 } 3843 } 3844 } 3845 3846 if (eg_pi->vddci_voltage_table.count) { 3847 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3848 3849 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3850 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3851 } 3852 3853 3854 if (si_pi->mvdd_voltage_table.count) { 3855 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3856 3857 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3858 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3859 } 3860 3861 if (si_pi->vddc_phase_shed_control) { 3862 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3863 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3864 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3865 3866 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3867 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3868 3869 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3870 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3871 } else { 3872 si_pi->vddc_phase_shed_control = false; 3873 } 3874 } 3875 3876 return 0; 3877} 3878 3879static int si_populate_voltage_value(struct radeon_device *rdev, 3880 const struct atom_voltage_table *table, 3881 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3882{ 3883 unsigned int i; 3884 3885 for (i = 0; i < table->count; i++) { 3886 if (value <= table->entries[i].value) { 3887 voltage->index = (u8)i; 3888 voltage->value = cpu_to_be16(table->entries[i].value); 3889 break; 3890 } 3891 } 3892 3893 if (i >= table->count) 3894 return -EINVAL; 3895 3896 return 0; 3897} 3898 3899static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3900 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3901{ 3902 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3903 struct si_power_info *si_pi = si_get_pi(rdev); 3904 3905 if (pi->mvdd_control) { 3906 if (mclk <= pi->mvdd_split_frequency) 3907 voltage->index = 0; 3908 else 3909 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3910 3911 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 3912 } 3913 return 0; 3914} 3915 3916static int si_get_std_voltage_value(struct radeon_device *rdev, 3917 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 3918 u16 *std_voltage) 3919{ 3920 u16 v_index; 3921 bool voltage_found = false; 3922 *std_voltage = be16_to_cpu(voltage->value); 3923 3924 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 3925 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 3926 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 3927 return -EINVAL; 3928 3929 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3930 if (be16_to_cpu(voltage->value) == 3931 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3932 voltage_found = true; 3933 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3934 *std_voltage = 3935 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3936 else 3937 *std_voltage = 3938 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3939 break; 3940 } 3941 } 3942 3943 if (!voltage_found) { 3944 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3945 if (be16_to_cpu(voltage->value) <= 3946 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3947 voltage_found = true; 3948 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3949 *std_voltage = 3950 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3951 else 3952 *std_voltage = 3953 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3954 break; 3955 } 3956 } 3957 } 3958 } else { 3959 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3960 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 3961 } 3962 } 3963 3964 return 0; 3965} 3966 3967static int si_populate_std_voltage_value(struct radeon_device *rdev, 3968 u16 value, u8 index, 3969 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3970{ 3971 voltage->index = index; 3972 voltage->value = cpu_to_be16(value); 3973 3974 return 0; 3975} 3976 3977static int si_populate_phase_shedding_value(struct radeon_device *rdev, 3978 const struct radeon_phase_shedding_limits_table *limits, 3979 u16 voltage, u32 sclk, u32 mclk, 3980 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 3981{ 3982 unsigned int i; 3983 3984 for (i = 0; i < limits->count; i++) { 3985 if ((voltage <= limits->entries[i].voltage) && 3986 (sclk <= limits->entries[i].sclk) && 3987 (mclk <= limits->entries[i].mclk)) 3988 break; 3989 } 3990 3991 smc_voltage->phase_settings = (u8)i; 3992 3993 return 0; 3994} 3995 3996static int si_init_arb_table_index(struct radeon_device *rdev) 3997{ 3998 struct si_power_info *si_pi = si_get_pi(rdev); 3999 u32 tmp; 4000 int ret; 4001 4002 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4003 if (ret) 4004 return ret; 4005 4006 tmp &= 0x00FFFFFF; 4007 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4008 4009 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4010} 4011 4012static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4013{ 4014 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4015} 4016 4017static int si_reset_to_default(struct radeon_device *rdev) 4018{ 4019 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4020 0 : -EINVAL; 4021} 4022 4023static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4024{ 4025 struct si_power_info *si_pi = si_get_pi(rdev); 4026 u32 tmp; 4027 int ret; 4028 4029 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4030 &tmp, si_pi->sram_end); 4031 if (ret) 4032 return ret; 4033 4034 tmp = (tmp >> 24) & 0xff; 4035 4036 if (tmp == MC_CG_ARB_FREQ_F0) 4037 return 0; 4038 4039 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4040} 4041 4042static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4043 u32 engine_clock) 4044{ 4045 u32 dram_rows; 4046 u32 dram_refresh_rate; 4047 u32 mc_arb_rfsh_rate; 4048 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4049 4050 if (tmp >= 4) 4051 dram_rows = 16384; 4052 else 4053 dram_rows = 1 << (tmp + 10); 4054 4055 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4056 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4057 4058 return mc_arb_rfsh_rate; 4059} 4060 4061static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4062 struct rv7xx_pl *pl, 4063 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4064{ 4065 u32 dram_timing; 4066 u32 dram_timing2; 4067 u32 burst_time; 4068 4069 arb_regs->mc_arb_rfsh_rate = 4070 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4071 4072 radeon_atom_set_engine_dram_timings(rdev, 4073 pl->sclk, 4074 pl->mclk); 4075 4076 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4077 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4078 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4079 4080 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4081 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4082 arb_regs->mc_arb_burst_time = (u8)burst_time; 4083 4084 return 0; 4085} 4086 4087static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4088 struct radeon_ps *radeon_state, 4089 unsigned int first_arb_set) 4090{ 4091 struct si_power_info *si_pi = si_get_pi(rdev); 4092 struct ni_ps *state = ni_get_ps(radeon_state); 4093 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4094 int i, ret = 0; 4095 4096 for (i = 0; i < state->performance_level_count; i++) { 4097 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4098 if (ret) 4099 break; 4100 ret = si_copy_bytes_to_smc(rdev, 4101 si_pi->arb_table_start + 4102 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4103 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4104 (u8 *)&arb_regs, 4105 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4106 si_pi->sram_end); 4107 if (ret) 4108 break; 4109 } 4110 4111 return ret; 4112} 4113 4114static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4115 struct radeon_ps *radeon_new_state) 4116{ 4117 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4118 SISLANDS_DRIVER_STATE_ARB_INDEX); 4119} 4120 4121static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4122 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4123{ 4124 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4125 struct si_power_info *si_pi = si_get_pi(rdev); 4126 4127 if (pi->mvdd_control) 4128 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4129 si_pi->mvdd_bootup_value, voltage); 4130 4131 return 0; 4132} 4133 4134static int si_populate_smc_initial_state(struct radeon_device *rdev, 4135 struct radeon_ps *radeon_initial_state, 4136 SISLANDS_SMC_STATETABLE *table) 4137{ 4138 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4139 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4140 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4141 struct si_power_info *si_pi = si_get_pi(rdev); 4142 u32 reg; 4143 int ret; 4144 4145 table->initialState.levels[0].mclk.vDLL_CNTL = 4146 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4147 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4148 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4149 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4150 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4151 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4152 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4153 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4154 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4155 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4156 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4157 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4158 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4159 table->initialState.levels[0].mclk.vMPLL_SS = 4160 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4161 table->initialState.levels[0].mclk.vMPLL_SS2 = 4162 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4163 4164 table->initialState.levels[0].mclk.mclk_value = 4165 cpu_to_be32(initial_state->performance_levels[0].mclk); 4166 4167 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4168 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4169 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4170 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4171 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4172 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4173 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4174 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4175 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4176 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4177 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4178 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4179 4180 table->initialState.levels[0].sclk.sclk_value = 4181 cpu_to_be32(initial_state->performance_levels[0].sclk); 4182 4183 table->initialState.levels[0].arbRefreshState = 4184 SISLANDS_INITIAL_STATE_ARB_INDEX; 4185 4186 table->initialState.levels[0].ACIndex = 0; 4187 4188 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4189 initial_state->performance_levels[0].vddc, 4190 &table->initialState.levels[0].vddc); 4191 4192 if (!ret) { 4193 u16 std_vddc; 4194 4195 ret = si_get_std_voltage_value(rdev, 4196 &table->initialState.levels[0].vddc, 4197 &std_vddc); 4198 if (!ret) 4199 si_populate_std_voltage_value(rdev, std_vddc, 4200 table->initialState.levels[0].vddc.index, 4201 &table->initialState.levels[0].std_vddc); 4202 } 4203 4204 if (eg_pi->vddci_control) 4205 si_populate_voltage_value(rdev, 4206 &eg_pi->vddci_voltage_table, 4207 initial_state->performance_levels[0].vddci, 4208 &table->initialState.levels[0].vddci); 4209 4210 if (si_pi->vddc_phase_shed_control) 4211 si_populate_phase_shedding_value(rdev, 4212 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4213 initial_state->performance_levels[0].vddc, 4214 initial_state->performance_levels[0].sclk, 4215 initial_state->performance_levels[0].mclk, 4216 &table->initialState.levels[0].vddc); 4217 4218 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4219 4220 reg = CG_R(0xffff) | CG_L(0); 4221 table->initialState.levels[0].aT = cpu_to_be32(reg); 4222 4223 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4224 4225 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4226 4227 if (pi->mem_gddr5) { 4228 table->initialState.levels[0].strobeMode = 4229 si_get_strobe_mode_settings(rdev, 4230 initial_state->performance_levels[0].mclk); 4231 4232 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4233 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4234 else 4235 table->initialState.levels[0].mcFlags = 0; 4236 } 4237 4238 table->initialState.levelCount = 1; 4239 4240 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4241 4242 table->initialState.levels[0].dpm2.MaxPS = 0; 4243 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4244 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4245 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4246 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4247 4248 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4249 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4250 4251 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4252 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4253 4254 return 0; 4255} 4256 4257static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4258 SISLANDS_SMC_STATETABLE *table) 4259{ 4260 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4261 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4262 struct si_power_info *si_pi = si_get_pi(rdev); 4263 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4264 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4265 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4266 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4267 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4268 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4269 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4270 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4271 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4272 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4273 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4274 u32 reg; 4275 int ret; 4276 4277 table->ACPIState = table->initialState; 4278 4279 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4280 4281 if (pi->acpi_vddc) { 4282 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4283 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4284 if (!ret) { 4285 u16 std_vddc; 4286 4287 ret = si_get_std_voltage_value(rdev, 4288 &table->ACPIState.levels[0].vddc, &std_vddc); 4289 if (!ret) 4290 si_populate_std_voltage_value(rdev, std_vddc, 4291 table->ACPIState.levels[0].vddc.index, 4292 &table->ACPIState.levels[0].std_vddc); 4293 } 4294 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4295 4296 if (si_pi->vddc_phase_shed_control) { 4297 si_populate_phase_shedding_value(rdev, 4298 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4299 pi->acpi_vddc, 4300 0, 4301 0, 4302 &table->ACPIState.levels[0].vddc); 4303 } 4304 } else { 4305 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4306 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4307 if (!ret) { 4308 u16 std_vddc; 4309 4310 ret = si_get_std_voltage_value(rdev, 4311 &table->ACPIState.levels[0].vddc, &std_vddc); 4312 4313 if (!ret) 4314 si_populate_std_voltage_value(rdev, std_vddc, 4315 table->ACPIState.levels[0].vddc.index, 4316 &table->ACPIState.levels[0].std_vddc); 4317 } 4318 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4319 si_pi->sys_pcie_mask, 4320 si_pi->boot_pcie_gen, 4321 RADEON_PCIE_GEN1); 4322 4323 if (si_pi->vddc_phase_shed_control) 4324 si_populate_phase_shedding_value(rdev, 4325 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4326 pi->min_vddc_in_table, 4327 0, 4328 0, 4329 &table->ACPIState.levels[0].vddc); 4330 } 4331 4332 if (pi->acpi_vddc) { 4333 if (eg_pi->acpi_vddci) 4334 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4335 eg_pi->acpi_vddci, 4336 &table->ACPIState.levels[0].vddci); 4337 } 4338 4339 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4340 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4341 4342 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4343 4344 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4345 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4346 4347 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4348 cpu_to_be32(dll_cntl); 4349 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4350 cpu_to_be32(mclk_pwrmgt_cntl); 4351 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4352 cpu_to_be32(mpll_ad_func_cntl); 4353 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4354 cpu_to_be32(mpll_dq_func_cntl); 4355 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4356 cpu_to_be32(mpll_func_cntl); 4357 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4358 cpu_to_be32(mpll_func_cntl_1); 4359 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4360 cpu_to_be32(mpll_func_cntl_2); 4361 table->ACPIState.levels[0].mclk.vMPLL_SS = 4362 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4363 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4364 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4365 4366 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4367 cpu_to_be32(spll_func_cntl); 4368 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4369 cpu_to_be32(spll_func_cntl_2); 4370 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4371 cpu_to_be32(spll_func_cntl_3); 4372 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4373 cpu_to_be32(spll_func_cntl_4); 4374 4375 table->ACPIState.levels[0].mclk.mclk_value = 0; 4376 table->ACPIState.levels[0].sclk.sclk_value = 0; 4377 4378 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4379 4380 if (eg_pi->dynamic_ac_timing) 4381 table->ACPIState.levels[0].ACIndex = 0; 4382 4383 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4384 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4385 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4386 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4387 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4388 4389 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4390 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4391 4392 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4393 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4394 4395 return 0; 4396} 4397 4398static int si_populate_ulv_state(struct radeon_device *rdev, 4399 SISLANDS_SMC_SWSTATE *state) 4400{ 4401 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4402 struct si_power_info *si_pi = si_get_pi(rdev); 4403 struct si_ulv_param *ulv = &si_pi->ulv; 4404 u32 sclk_in_sr = 1350; /* ??? */ 4405 int ret; 4406 4407 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4408 &state->levels[0]); 4409 if (!ret) { 4410 if (eg_pi->sclk_deep_sleep) { 4411 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4412 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4413 else 4414 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4415 } 4416 if (ulv->one_pcie_lane_in_ulv) 4417 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4418 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4419 state->levels[0].ACIndex = 1; 4420 state->levels[0].std_vddc = state->levels[0].vddc; 4421 state->levelCount = 1; 4422 4423 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4424 } 4425 4426 return ret; 4427} 4428 4429static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4430{ 4431 struct si_power_info *si_pi = si_get_pi(rdev); 4432 struct si_ulv_param *ulv = &si_pi->ulv; 4433 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4434 int ret; 4435 4436 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4437 &arb_regs); 4438 if (ret) 4439 return ret; 4440 4441 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4442 ulv->volt_change_delay); 4443 4444 ret = si_copy_bytes_to_smc(rdev, 4445 si_pi->arb_table_start + 4446 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4447 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4448 (u8 *)&arb_regs, 4449 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4450 si_pi->sram_end); 4451 4452 return ret; 4453} 4454 4455static void si_get_mvdd_configuration(struct radeon_device *rdev) 4456{ 4457 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4458 4459 pi->mvdd_split_frequency = 30000; 4460} 4461 4462static int si_init_smc_table(struct radeon_device *rdev) 4463{ 4464 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4465 struct si_power_info *si_pi = si_get_pi(rdev); 4466 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4467 const struct si_ulv_param *ulv = &si_pi->ulv; 4468 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4469 int ret; 4470 u32 lane_width; 4471 u32 vr_hot_gpio; 4472 4473 si_populate_smc_voltage_tables(rdev, table); 4474 4475 switch (rdev->pm.int_thermal_type) { 4476 case THERMAL_TYPE_SI: 4477 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4478 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4479 break; 4480 case THERMAL_TYPE_NONE: 4481 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4482 break; 4483 default: 4484 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4485 break; 4486 } 4487 4488 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4489 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4490 4491 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4492 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4493 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4494 } 4495 4496 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4497 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4498 4499 if (pi->mem_gddr5) 4500 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4501 4502 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4503 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4504 4505 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4506 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4507 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4508 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4509 vr_hot_gpio); 4510 } 4511 4512 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4513 if (ret) 4514 return ret; 4515 4516 ret = si_populate_smc_acpi_state(rdev, table); 4517 if (ret) 4518 return ret; 4519 4520 table->driverState = table->initialState; 4521 4522 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4523 SISLANDS_INITIAL_STATE_ARB_INDEX); 4524 if (ret) 4525 return ret; 4526 4527 if (ulv->supported && ulv->pl.vddc) { 4528 ret = si_populate_ulv_state(rdev, &table->ULVState); 4529 if (ret) 4530 return ret; 4531 4532 ret = si_program_ulv_memory_timing_parameters(rdev); 4533 if (ret) 4534 return ret; 4535 4536 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4537 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4538 4539 lane_width = radeon_get_pcie_lanes(rdev); 4540 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4541 } else { 4542 table->ULVState = table->initialState; 4543 } 4544 4545 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4546 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4547 si_pi->sram_end); 4548} 4549 4550static int si_calculate_sclk_params(struct radeon_device *rdev, 4551 u32 engine_clock, 4552 SISLANDS_SMC_SCLK_VALUE *sclk) 4553{ 4554 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4555 struct si_power_info *si_pi = si_get_pi(rdev); 4556 struct atom_clock_dividers dividers; 4557 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4558 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4559 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4560 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4561 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4562 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4563 u64 tmp; 4564 u32 reference_clock = rdev->clock.spll.reference_freq; 4565 u32 reference_divider; 4566 u32 fbdiv; 4567 int ret; 4568 4569 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4570 engine_clock, false, ÷rs); 4571 if (ret) 4572 return ret; 4573 4574 reference_divider = 1 + dividers.ref_div; 4575 4576 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4577 do_div(tmp, reference_clock); 4578 fbdiv = (u32) tmp; 4579 4580 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4581 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4582 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4583 4584 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4585 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4586 4587 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4588 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4589 spll_func_cntl_3 |= SPLL_DITHEN; 4590 4591 if (pi->sclk_ss) { 4592 struct radeon_atom_ss ss; 4593 u32 vco_freq = engine_clock * dividers.post_div; 4594 4595 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4596 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4597 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4598 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4599 4600 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4601 cg_spll_spread_spectrum |= CLK_S(clk_s); 4602 cg_spll_spread_spectrum |= SSEN; 4603 4604 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4605 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4606 } 4607 } 4608 4609 sclk->sclk_value = engine_clock; 4610 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4611 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4612 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4613 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4614 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4615 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4616 4617 return 0; 4618} 4619 4620static int si_populate_sclk_value(struct radeon_device *rdev, 4621 u32 engine_clock, 4622 SISLANDS_SMC_SCLK_VALUE *sclk) 4623{ 4624 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4625 int ret; 4626 4627 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4628 if (!ret) { 4629 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4630 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4631 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4632 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4633 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4634 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4635 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4636 } 4637 4638 return ret; 4639} 4640 4641static int si_populate_mclk_value(struct radeon_device *rdev, 4642 u32 engine_clock, 4643 u32 memory_clock, 4644 SISLANDS_SMC_MCLK_VALUE *mclk, 4645 bool strobe_mode, 4646 bool dll_state_on) 4647{ 4648 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4649 struct si_power_info *si_pi = si_get_pi(rdev); 4650 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4651 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4652 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4653 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4654 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4655 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4656 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4657 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4658 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4659 struct atom_mpll_param mpll_param; 4660 int ret; 4661 4662 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4663 if (ret) 4664 return ret; 4665 4666 mpll_func_cntl &= ~BWCTRL_MASK; 4667 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4668 4669 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4670 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4671 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4672 4673 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4674 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4675 4676 if (pi->mem_gddr5) { 4677 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4678 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4679 YCLK_POST_DIV(mpll_param.post_div); 4680 } 4681 4682 if (pi->mclk_ss) { 4683 struct radeon_atom_ss ss; 4684 u32 freq_nom; 4685 u32 tmp; 4686 u32 reference_clock = rdev->clock.mpll.reference_freq; 4687 4688 if (pi->mem_gddr5) 4689 freq_nom = memory_clock * 4; 4690 else 4691 freq_nom = memory_clock * 2; 4692 4693 tmp = freq_nom / reference_clock; 4694 tmp = tmp * tmp; 4695 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4696 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4697 u32 clks = reference_clock * 5 / ss.rate; 4698 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4699 4700 mpll_ss1 &= ~CLKV_MASK; 4701 mpll_ss1 |= CLKV(clkv); 4702 4703 mpll_ss2 &= ~CLKS_MASK; 4704 mpll_ss2 |= CLKS(clks); 4705 } 4706 } 4707 4708 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4709 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4710 4711 if (dll_state_on) 4712 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4713 else 4714 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4715 4716 mclk->mclk_value = cpu_to_be32(memory_clock); 4717 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4718 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4719 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4720 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4721 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4722 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4723 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4724 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4725 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4726 4727 return 0; 4728} 4729 4730static void si_populate_smc_sp(struct radeon_device *rdev, 4731 struct radeon_ps *radeon_state, 4732 SISLANDS_SMC_SWSTATE *smc_state) 4733{ 4734 struct ni_ps *ps = ni_get_ps(radeon_state); 4735 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4736 int i; 4737 4738 for (i = 0; i < ps->performance_level_count - 1; i++) 4739 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4740 4741 smc_state->levels[ps->performance_level_count - 1].bSP = 4742 cpu_to_be32(pi->psp); 4743} 4744 4745static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4746 struct rv7xx_pl *pl, 4747 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4748{ 4749 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4750 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4751 struct si_power_info *si_pi = si_get_pi(rdev); 4752 int ret; 4753 bool dll_state_on; 4754 u16 std_vddc; 4755 bool gmc_pg = false; 4756 4757 if (eg_pi->pcie_performance_request && 4758 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4759 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4760 else 4761 level->gen2PCIE = (u8)pl->pcie_gen; 4762 4763 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4764 if (ret) 4765 return ret; 4766 4767 level->mcFlags = 0; 4768 4769 if (pi->mclk_stutter_mode_threshold && 4770 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4771 !eg_pi->uvd_enabled && 4772 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4773 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4774 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4775 4776 if (gmc_pg) 4777 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4778 } 4779 4780 if (pi->mem_gddr5) { 4781 if (pl->mclk > pi->mclk_edc_enable_threshold) 4782 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4783 4784 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4785 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4786 4787 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4788 4789 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4790 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4791 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4792 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4793 else 4794 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4795 } else { 4796 dll_state_on = false; 4797 } 4798 } else { 4799 level->strobeMode = si_get_strobe_mode_settings(rdev, 4800 pl->mclk); 4801 4802 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4803 } 4804 4805 ret = si_populate_mclk_value(rdev, 4806 pl->sclk, 4807 pl->mclk, 4808 &level->mclk, 4809 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4810 if (ret) 4811 return ret; 4812 4813 ret = si_populate_voltage_value(rdev, 4814 &eg_pi->vddc_voltage_table, 4815 pl->vddc, &level->vddc); 4816 if (ret) 4817 return ret; 4818 4819 4820 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4821 if (ret) 4822 return ret; 4823 4824 ret = si_populate_std_voltage_value(rdev, std_vddc, 4825 level->vddc.index, &level->std_vddc); 4826 if (ret) 4827 return ret; 4828 4829 if (eg_pi->vddci_control) { 4830 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4831 pl->vddci, &level->vddci); 4832 if (ret) 4833 return ret; 4834 } 4835 4836 if (si_pi->vddc_phase_shed_control) { 4837 ret = si_populate_phase_shedding_value(rdev, 4838 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4839 pl->vddc, 4840 pl->sclk, 4841 pl->mclk, 4842 &level->vddc); 4843 if (ret) 4844 return ret; 4845 } 4846 4847 level->MaxPoweredUpCU = si_pi->max_cu; 4848 4849 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4850 4851 return ret; 4852} 4853 4854static int si_populate_smc_t(struct radeon_device *rdev, 4855 struct radeon_ps *radeon_state, 4856 SISLANDS_SMC_SWSTATE *smc_state) 4857{ 4858 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4859 struct ni_ps *state = ni_get_ps(radeon_state); 4860 u32 a_t; 4861 u32 t_l, t_h; 4862 u32 high_bsp; 4863 int i, ret; 4864 4865 if (state->performance_level_count >= 9) 4866 return -EINVAL; 4867 4868 if (state->performance_level_count < 2) { 4869 a_t = CG_R(0xffff) | CG_L(0); 4870 smc_state->levels[0].aT = cpu_to_be32(a_t); 4871 return 0; 4872 } 4873 4874 smc_state->levels[0].aT = cpu_to_be32(0); 4875 4876 for (i = 0; i <= state->performance_level_count - 2; i++) { 4877 ret = r600_calculate_at( 4878 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4879 100 * R600_AH_DFLT, 4880 state->performance_levels[i + 1].sclk, 4881 state->performance_levels[i].sclk, 4882 &t_l, 4883 &t_h); 4884 4885 if (ret) { 4886 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4887 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4888 } 4889 4890 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4891 a_t |= CG_R(t_l * pi->bsp / 20000); 4892 smc_state->levels[i].aT = cpu_to_be32(a_t); 4893 4894 high_bsp = (i == state->performance_level_count - 2) ? 4895 pi->pbsp : pi->bsp; 4896 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4897 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4898 } 4899 4900 return 0; 4901} 4902 4903static int si_disable_ulv(struct radeon_device *rdev) 4904{ 4905 struct si_power_info *si_pi = si_get_pi(rdev); 4906 struct si_ulv_param *ulv = &si_pi->ulv; 4907 4908 if (ulv->supported) 4909 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4910 0 : -EINVAL; 4911 4912 return 0; 4913} 4914 4915static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 4916 struct radeon_ps *radeon_state) 4917{ 4918 const struct si_power_info *si_pi = si_get_pi(rdev); 4919 const struct si_ulv_param *ulv = &si_pi->ulv; 4920 const struct ni_ps *state = ni_get_ps(radeon_state); 4921 int i; 4922 4923 if (state->performance_levels[0].mclk != ulv->pl.mclk) 4924 return false; 4925 4926 /* XXX validate against display requirements! */ 4927 4928 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 4929 if (rdev->clock.current_dispclk <= 4930 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 4931 if (ulv->pl.vddc < 4932 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 4933 return false; 4934 } 4935 } 4936 4937 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 4938 return false; 4939 4940 return true; 4941} 4942 4943static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 4944 struct radeon_ps *radeon_new_state) 4945{ 4946 const struct si_power_info *si_pi = si_get_pi(rdev); 4947 const struct si_ulv_param *ulv = &si_pi->ulv; 4948 4949 if (ulv->supported) { 4950 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 4951 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 4952 0 : -EINVAL; 4953 } 4954 return 0; 4955} 4956 4957static int si_convert_power_state_to_smc(struct radeon_device *rdev, 4958 struct radeon_ps *radeon_state, 4959 SISLANDS_SMC_SWSTATE *smc_state) 4960{ 4961 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4962 struct ni_power_info *ni_pi = ni_get_pi(rdev); 4963 struct si_power_info *si_pi = si_get_pi(rdev); 4964 struct ni_ps *state = ni_get_ps(radeon_state); 4965 int i, ret; 4966 u32 threshold; 4967 u32 sclk_in_sr = 1350; /* ??? */ 4968 4969 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 4970 return -EINVAL; 4971 4972 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 4973 4974 if (radeon_state->vclk && radeon_state->dclk) { 4975 eg_pi->uvd_enabled = true; 4976 if (eg_pi->smu_uvd_hs) 4977 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 4978 } else { 4979 eg_pi->uvd_enabled = false; 4980 } 4981 4982 if (state->dc_compatible) 4983 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 4984 4985 smc_state->levelCount = 0; 4986 for (i = 0; i < state->performance_level_count; i++) { 4987 if (eg_pi->sclk_deep_sleep) { 4988 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 4989 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4990 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4991 else 4992 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4993 } 4994 } 4995 4996 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 4997 &smc_state->levels[i]); 4998 smc_state->levels[i].arbRefreshState = 4999 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5000 5001 if (ret) 5002 return ret; 5003 5004 if (ni_pi->enable_power_containment) 5005 smc_state->levels[i].displayWatermark = 5006 (state->performance_levels[i].sclk < threshold) ? 5007 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5008 else 5009 smc_state->levels[i].displayWatermark = (i < 2) ? 5010 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5011 5012 if (eg_pi->dynamic_ac_timing) 5013 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5014 else 5015 smc_state->levels[i].ACIndex = 0; 5016 5017 smc_state->levelCount++; 5018 } 5019 5020 si_write_smc_soft_register(rdev, 5021 SI_SMC_SOFT_REGISTER_watermark_threshold, 5022 threshold / 512); 5023 5024 si_populate_smc_sp(rdev, radeon_state, smc_state); 5025 5026 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5027 if (ret) 5028 ni_pi->enable_power_containment = false; 5029 5030 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5031 if (ret) 5032 ni_pi->enable_sq_ramping = false; 5033 5034 return si_populate_smc_t(rdev, radeon_state, smc_state); 5035} 5036 5037static int si_upload_sw_state(struct radeon_device *rdev, 5038 struct radeon_ps *radeon_new_state) 5039{ 5040 struct si_power_info *si_pi = si_get_pi(rdev); 5041 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5042 int ret; 5043 u32 address = si_pi->state_table_start + 5044 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5045 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5046 ((new_state->performance_level_count - 1) * 5047 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5048 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5049 5050 memset(smc_state, 0, state_size); 5051 5052 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5053 if (ret) 5054 return ret; 5055 5056 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5057 state_size, si_pi->sram_end); 5058 5059 return ret; 5060} 5061 5062static int si_upload_ulv_state(struct radeon_device *rdev) 5063{ 5064 struct si_power_info *si_pi = si_get_pi(rdev); 5065 struct si_ulv_param *ulv = &si_pi->ulv; 5066 int ret = 0; 5067 5068 if (ulv->supported && ulv->pl.vddc) { 5069 u32 address = si_pi->state_table_start + 5070 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5071 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5072 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5073 5074 memset(smc_state, 0, state_size); 5075 5076 ret = si_populate_ulv_state(rdev, smc_state); 5077 if (!ret) 5078 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5079 state_size, si_pi->sram_end); 5080 } 5081 5082 return ret; 5083} 5084 5085static int si_upload_smc_data(struct radeon_device *rdev) 5086{ 5087 struct radeon_crtc *radeon_crtc = NULL; 5088 int i; 5089 5090 if (rdev->pm.dpm.new_active_crtc_count == 0) 5091 return 0; 5092 5093 for (i = 0; i < rdev->num_crtc; i++) { 5094 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5095 radeon_crtc = rdev->mode_info.crtcs[i]; 5096 break; 5097 } 5098 } 5099 5100 if (radeon_crtc == NULL) 5101 return 0; 5102 5103 if (radeon_crtc->line_time <= 0) 5104 return 0; 5105 5106 if (si_write_smc_soft_register(rdev, 5107 SI_SMC_SOFT_REGISTER_crtc_index, 5108 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5109 return 0; 5110 5111 if (si_write_smc_soft_register(rdev, 5112 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5113 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5114 return 0; 5115 5116 if (si_write_smc_soft_register(rdev, 5117 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5118 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5119 return 0; 5120 5121 return 0; 5122} 5123 5124static int si_set_mc_special_registers(struct radeon_device *rdev, 5125 struct si_mc_reg_table *table) 5126{ 5127 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5128 u8 i, j, k; 5129 u32 temp_reg; 5130 5131 for (i = 0, j = table->last; i < table->last; i++) { 5132 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5133 return -EINVAL; 5134 switch (table->mc_reg_address[i].s1 << 2) { 5135 case MC_SEQ_MISC1: 5136 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5137 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5138 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5139 for (k = 0; k < table->num_entries; k++) 5140 table->mc_reg_table_entry[k].mc_data[j] = 5141 ((temp_reg & 0xffff0000)) | 5142 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5143 j++; 5144 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5145 return -EINVAL; 5146 5147 temp_reg = RREG32(MC_PMG_CMD_MRS); 5148 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5149 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5150 for (k = 0; k < table->num_entries; k++) { 5151 table->mc_reg_table_entry[k].mc_data[j] = 5152 (temp_reg & 0xffff0000) | 5153 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5154 if (!pi->mem_gddr5) 5155 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5156 } 5157 j++; 5158 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5159 return -EINVAL; 5160 5161 if (!pi->mem_gddr5) { 5162 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5163 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5164 for (k = 0; k < table->num_entries; k++) 5165 table->mc_reg_table_entry[k].mc_data[j] = 5166 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5167 j++; 5168 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5169 return -EINVAL; 5170 } 5171 break; 5172 case MC_SEQ_RESERVE_M: 5173 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5174 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5175 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5176 for(k = 0; k < table->num_entries; k++) 5177 table->mc_reg_table_entry[k].mc_data[j] = 5178 (temp_reg & 0xffff0000) | 5179 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5180 j++; 5181 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5182 return -EINVAL; 5183 break; 5184 default: 5185 break; 5186 } 5187 } 5188 5189 table->last = j; 5190 5191 return 0; 5192} 5193 5194static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5195{ 5196 bool result = true; 5197 5198 switch (in_reg) { 5199 case MC_SEQ_RAS_TIMING >> 2: 5200 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5201 break; 5202 case MC_SEQ_CAS_TIMING >> 2: 5203 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5204 break; 5205 case MC_SEQ_MISC_TIMING >> 2: 5206 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5207 break; 5208 case MC_SEQ_MISC_TIMING2 >> 2: 5209 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5210 break; 5211 case MC_SEQ_RD_CTL_D0 >> 2: 5212 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5213 break; 5214 case MC_SEQ_RD_CTL_D1 >> 2: 5215 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5216 break; 5217 case MC_SEQ_WR_CTL_D0 >> 2: 5218 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5219 break; 5220 case MC_SEQ_WR_CTL_D1 >> 2: 5221 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5222 break; 5223 case MC_PMG_CMD_EMRS >> 2: 5224 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5225 break; 5226 case MC_PMG_CMD_MRS >> 2: 5227 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5228 break; 5229 case MC_PMG_CMD_MRS1 >> 2: 5230 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5231 break; 5232 case MC_SEQ_PMG_TIMING >> 2: 5233 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5234 break; 5235 case MC_PMG_CMD_MRS2 >> 2: 5236 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5237 break; 5238 case MC_SEQ_WR_CTL_2 >> 2: 5239 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5240 break; 5241 default: 5242 result = false; 5243 break; 5244 } 5245 5246 return result; 5247} 5248 5249static void si_set_valid_flag(struct si_mc_reg_table *table) 5250{ 5251 u8 i, j; 5252 5253 for (i = 0; i < table->last; i++) { 5254 for (j = 1; j < table->num_entries; j++) { 5255 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5256 table->valid_flag |= 1 << i; 5257 break; 5258 } 5259 } 5260 } 5261} 5262 5263static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5264{ 5265 u32 i; 5266 u16 address; 5267 5268 for (i = 0; i < table->last; i++) 5269 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5270 address : table->mc_reg_address[i].s1; 5271 5272} 5273 5274static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5275 struct si_mc_reg_table *si_table) 5276{ 5277 u8 i, j; 5278 5279 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5280 return -EINVAL; 5281 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5282 return -EINVAL; 5283 5284 for (i = 0; i < table->last; i++) 5285 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5286 si_table->last = table->last; 5287 5288 for (i = 0; i < table->num_entries; i++) { 5289 si_table->mc_reg_table_entry[i].mclk_max = 5290 table->mc_reg_table_entry[i].mclk_max; 5291 for (j = 0; j < table->last; j++) { 5292 si_table->mc_reg_table_entry[i].mc_data[j] = 5293 table->mc_reg_table_entry[i].mc_data[j]; 5294 } 5295 } 5296 si_table->num_entries = table->num_entries; 5297 5298 return 0; 5299} 5300 5301static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5302{ 5303 struct si_power_info *si_pi = si_get_pi(rdev); 5304 struct atom_mc_reg_table *table; 5305 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5306 u8 module_index = rv770_get_memory_module_index(rdev); 5307 int ret; 5308 5309 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5310 if (!table) 5311 return -ENOMEM; 5312 5313 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5314 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5315 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5316 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5317 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5318 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5319 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5320 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5321 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5322 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5323 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5324 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5325 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5326 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5327 5328 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5329 if (ret) 5330 goto init_mc_done; 5331 5332 ret = si_copy_vbios_mc_reg_table(table, si_table); 5333 if (ret) 5334 goto init_mc_done; 5335 5336 si_set_s0_mc_reg_index(si_table); 5337 5338 ret = si_set_mc_special_registers(rdev, si_table); 5339 if (ret) 5340 goto init_mc_done; 5341 5342 si_set_valid_flag(si_table); 5343 5344init_mc_done: 5345 kfree(table); 5346 5347 return ret; 5348 5349} 5350 5351static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5352 SMC_SIslands_MCRegisters *mc_reg_table) 5353{ 5354 struct si_power_info *si_pi = si_get_pi(rdev); 5355 u32 i, j; 5356 5357 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5358 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5359 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 5360 break; 5361 mc_reg_table->address[i].s0 = 5362 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5363 mc_reg_table->address[i].s1 = 5364 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5365 i++; 5366 } 5367 } 5368 mc_reg_table->last = (u8)i; 5369} 5370 5371static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5372 SMC_SIslands_MCRegisterSet *data, 5373 u32 num_entries, u32 valid_flag) 5374{ 5375 u32 i, j; 5376 5377 for(i = 0, j = 0; j < num_entries; j++) { 5378 if (valid_flag & (1 << j)) { 5379 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5380 i++; 5381 } 5382 } 5383} 5384 5385static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5386 struct rv7xx_pl *pl, 5387 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5388{ 5389 struct si_power_info *si_pi = si_get_pi(rdev); 5390 u32 i = 0; 5391 5392 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5393 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5394 break; 5395 } 5396 5397 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5398 --i; 5399 5400 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5401 mc_reg_table_data, si_pi->mc_reg_table.last, 5402 si_pi->mc_reg_table.valid_flag); 5403} 5404 5405static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5406 struct radeon_ps *radeon_state, 5407 SMC_SIslands_MCRegisters *mc_reg_table) 5408{ 5409 struct ni_ps *state = ni_get_ps(radeon_state); 5410 int i; 5411 5412 for (i = 0; i < state->performance_level_count; i++) { 5413 si_convert_mc_reg_table_entry_to_smc(rdev, 5414 &state->performance_levels[i], 5415 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5416 } 5417} 5418 5419static int si_populate_mc_reg_table(struct radeon_device *rdev, 5420 struct radeon_ps *radeon_boot_state) 5421{ 5422 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5423 struct si_power_info *si_pi = si_get_pi(rdev); 5424 struct si_ulv_param *ulv = &si_pi->ulv; 5425 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5426 5427 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5428 5429 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5430 5431 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5432 5433 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5434 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5435 5436 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5437 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5438 si_pi->mc_reg_table.last, 5439 si_pi->mc_reg_table.valid_flag); 5440 5441 if (ulv->supported && ulv->pl.vddc != 0) 5442 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5443 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5444 else 5445 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5446 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5447 si_pi->mc_reg_table.last, 5448 si_pi->mc_reg_table.valid_flag); 5449 5450 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5451 5452 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5453 (u8 *)smc_mc_reg_table, 5454 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5455} 5456 5457static int si_upload_mc_reg_table(struct radeon_device *rdev, 5458 struct radeon_ps *radeon_new_state) 5459{ 5460 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5461 struct si_power_info *si_pi = si_get_pi(rdev); 5462 u32 address = si_pi->mc_reg_table_start + 5463 offsetof(SMC_SIslands_MCRegisters, 5464 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5465 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5466 5467 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5468 5469 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5470 5471 5472 return si_copy_bytes_to_smc(rdev, address, 5473 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5474 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5475 si_pi->sram_end); 5476 5477} 5478 5479static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5480{ 5481 if (enable) 5482 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5483 else 5484 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5485} 5486 5487static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5488 struct radeon_ps *radeon_state) 5489{ 5490 struct ni_ps *state = ni_get_ps(radeon_state); 5491 int i; 5492 u16 pcie_speed, max_speed = 0; 5493 5494 for (i = 0; i < state->performance_level_count; i++) { 5495 pcie_speed = state->performance_levels[i].pcie_gen; 5496 if (max_speed < pcie_speed) 5497 max_speed = pcie_speed; 5498 } 5499 return max_speed; 5500} 5501 5502static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5503{ 5504 u32 speed_cntl; 5505 5506 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5507 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5508 5509 return (u16)speed_cntl; 5510} 5511 5512static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5513 struct radeon_ps *radeon_new_state, 5514 struct radeon_ps *radeon_current_state) 5515{ 5516 struct si_power_info *si_pi = si_get_pi(rdev); 5517 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5518 enum radeon_pcie_gen current_link_speed; 5519 5520 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5521 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5522 else 5523 current_link_speed = si_pi->force_pcie_gen; 5524 5525 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5526 si_pi->pspp_notify_required = false; 5527 if (target_link_speed > current_link_speed) { 5528 switch (target_link_speed) { 5529#if defined(CONFIG_ACPI) 5530 case RADEON_PCIE_GEN3: 5531 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5532 break; 5533 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5534 if (current_link_speed == RADEON_PCIE_GEN2) 5535 break; 5536 case RADEON_PCIE_GEN2: 5537 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5538 break; 5539#endif 5540 default: 5541 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5542 break; 5543 } 5544 } else { 5545 if (target_link_speed < current_link_speed) 5546 si_pi->pspp_notify_required = true; 5547 } 5548} 5549 5550static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5551 struct radeon_ps *radeon_new_state, 5552 struct radeon_ps *radeon_current_state) 5553{ 5554 struct si_power_info *si_pi = si_get_pi(rdev); 5555 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5556 u8 request; 5557 5558 if (si_pi->pspp_notify_required) { 5559 if (target_link_speed == RADEON_PCIE_GEN3) 5560 request = PCIE_PERF_REQ_PECI_GEN3; 5561 else if (target_link_speed == RADEON_PCIE_GEN2) 5562 request = PCIE_PERF_REQ_PECI_GEN2; 5563 else 5564 request = PCIE_PERF_REQ_PECI_GEN1; 5565 5566 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5567 (si_get_current_pcie_speed(rdev) > 0)) 5568 return; 5569 5570#if defined(CONFIG_ACPI) 5571 radeon_acpi_pcie_performance_request(rdev, request, false); 5572#endif 5573 } 5574} 5575 5576#if 0 5577static int si_ds_request(struct radeon_device *rdev, 5578 bool ds_status_on, u32 count_write) 5579{ 5580 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5581 5582 if (eg_pi->sclk_deep_sleep) { 5583 if (ds_status_on) 5584 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5585 PPSMC_Result_OK) ? 5586 0 : -EINVAL; 5587 else 5588 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5589 PPSMC_Result_OK) ? 0 : -EINVAL; 5590 } 5591 return 0; 5592} 5593#endif 5594 5595static void si_set_max_cu_value(struct radeon_device *rdev) 5596{ 5597 struct si_power_info *si_pi = si_get_pi(rdev); 5598 5599 if (rdev->family == CHIP_VERDE) { 5600 switch (rdev->pdev->device) { 5601 case 0x6820: 5602 case 0x6825: 5603 case 0x6821: 5604 case 0x6823: 5605 case 0x6827: 5606 si_pi->max_cu = 10; 5607 break; 5608 case 0x682D: 5609 case 0x6824: 5610 case 0x682F: 5611 case 0x6826: 5612 si_pi->max_cu = 8; 5613 break; 5614 case 0x6828: 5615 case 0x6830: 5616 case 0x6831: 5617 case 0x6838: 5618 case 0x6839: 5619 case 0x683D: 5620 si_pi->max_cu = 10; 5621 break; 5622 case 0x683B: 5623 case 0x683F: 5624 case 0x6829: 5625 si_pi->max_cu = 8; 5626 break; 5627 default: 5628 si_pi->max_cu = 0; 5629 break; 5630 } 5631 } else { 5632 si_pi->max_cu = 0; 5633 } 5634} 5635 5636static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5637 struct radeon_clock_voltage_dependency_table *table) 5638{ 5639 u32 i; 5640 int j; 5641 u16 leakage_voltage; 5642 5643 if (table) { 5644 for (i = 0; i < table->count; i++) { 5645 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5646 table->entries[i].v, 5647 &leakage_voltage)) { 5648 case 0: 5649 table->entries[i].v = leakage_voltage; 5650 break; 5651 case -EAGAIN: 5652 return -EINVAL; 5653 case -EINVAL: 5654 default: 5655 break; 5656 } 5657 } 5658 5659 for (j = (table->count - 2); j >= 0; j--) { 5660 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5661 table->entries[j].v : table->entries[j + 1].v; 5662 } 5663 } 5664 return 0; 5665} 5666 5667static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5668{ 5669 int ret = 0; 5670 5671 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5672 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5673 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5674 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5675 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5676 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5677 return ret; 5678} 5679 5680static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5681 struct radeon_ps *radeon_new_state, 5682 struct radeon_ps *radeon_current_state) 5683{ 5684 u32 lane_width; 5685 u32 new_lane_width = 5686 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5687 u32 current_lane_width = 5688 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5689 5690 if (new_lane_width != current_lane_width) { 5691 radeon_set_pcie_lanes(rdev, new_lane_width); 5692 lane_width = radeon_get_pcie_lanes(rdev); 5693 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5694 } 5695} 5696 5697void si_dpm_setup_asic(struct radeon_device *rdev) 5698{ 5699 rv770_get_memory_type(rdev); 5700 si_read_clock_registers(rdev); 5701 si_enable_acpi_power_management(rdev); 5702} 5703 5704static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5705 int min_temp, int max_temp) 5706{ 5707 int low_temp = 0 * 1000; 5708 int high_temp = 255 * 1000; 5709 5710 if (low_temp < min_temp) 5711 low_temp = min_temp; 5712 if (high_temp > max_temp) 5713 high_temp = max_temp; 5714 if (high_temp < low_temp) { 5715 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5716 return -EINVAL; 5717 } 5718 5719 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5720 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5721 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5722 5723 rdev->pm.dpm.thermal.min_temp = low_temp; 5724 rdev->pm.dpm.thermal.max_temp = high_temp; 5725 5726 return 0; 5727} 5728 5729int si_dpm_enable(struct radeon_device *rdev) 5730{ 5731 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5732 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5733 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5734 int ret; 5735 5736 if (si_is_smc_running(rdev)) 5737 return -EINVAL; 5738 if (pi->voltage_control) 5739 si_enable_voltage_control(rdev, true); 5740 if (pi->mvdd_control) 5741 si_get_mvdd_configuration(rdev); 5742 if (pi->voltage_control) { 5743 ret = si_construct_voltage_tables(rdev); 5744 if (ret) { 5745 DRM_ERROR("si_construct_voltage_tables failed\n"); 5746 return ret; 5747 } 5748 } 5749 if (eg_pi->dynamic_ac_timing) { 5750 ret = si_initialize_mc_reg_table(rdev); 5751 if (ret) 5752 eg_pi->dynamic_ac_timing = false; 5753 } 5754 if (pi->dynamic_ss) 5755 si_enable_spread_spectrum(rdev, true); 5756 if (pi->thermal_protection) 5757 si_enable_thermal_protection(rdev, true); 5758 si_setup_bsp(rdev); 5759 si_program_git(rdev); 5760 si_program_tp(rdev); 5761 si_program_tpp(rdev); 5762 si_program_sstp(rdev); 5763 si_enable_display_gap(rdev); 5764 si_program_vc(rdev); 5765 ret = si_upload_firmware(rdev); 5766 if (ret) { 5767 DRM_ERROR("si_upload_firmware failed\n"); 5768 return ret; 5769 } 5770 ret = si_process_firmware_header(rdev); 5771 if (ret) { 5772 DRM_ERROR("si_process_firmware_header failed\n"); 5773 return ret; 5774 } 5775 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5776 if (ret) { 5777 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5778 return ret; 5779 } 5780 ret = si_init_smc_table(rdev); 5781 if (ret) { 5782 DRM_ERROR("si_init_smc_table failed\n"); 5783 return ret; 5784 } 5785 ret = si_init_smc_spll_table(rdev); 5786 if (ret) { 5787 DRM_ERROR("si_init_smc_spll_table failed\n"); 5788 return ret; 5789 } 5790 ret = si_init_arb_table_index(rdev); 5791 if (ret) { 5792 DRM_ERROR("si_init_arb_table_index failed\n"); 5793 return ret; 5794 } 5795 if (eg_pi->dynamic_ac_timing) { 5796 ret = si_populate_mc_reg_table(rdev, boot_ps); 5797 if (ret) { 5798 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5799 return ret; 5800 } 5801 } 5802 ret = si_initialize_smc_cac_tables(rdev); 5803 if (ret) { 5804 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5805 return ret; 5806 } 5807 ret = si_initialize_hardware_cac_manager(rdev); 5808 if (ret) { 5809 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5810 return ret; 5811 } 5812 ret = si_initialize_smc_dte_tables(rdev); 5813 if (ret) { 5814 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5815 return ret; 5816 } 5817 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5818 if (ret) { 5819 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5820 return ret; 5821 } 5822 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5823 if (ret) { 5824 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5825 return ret; 5826 } 5827 si_program_response_times(rdev); 5828 si_program_ds_registers(rdev); 5829 si_dpm_start_smc(rdev); 5830 ret = si_notify_smc_display_change(rdev, false); 5831 if (ret) { 5832 DRM_ERROR("si_notify_smc_display_change failed\n"); 5833 return ret; 5834 } 5835 si_enable_sclk_control(rdev, true); 5836 si_start_dpm(rdev); 5837 5838 if (rdev->irq.installed && 5839 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5840 PPSMC_Result result; 5841 5842 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5843 if (ret) 5844 return ret; 5845 rdev->irq.dpm_thermal = true; 5846 radeon_irq_set(rdev); 5847 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5848 5849 if (result != PPSMC_Result_OK) 5850 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5851 } 5852 5853 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5854 5855 ni_update_current_ps(rdev, boot_ps); 5856 5857 return 0; 5858} 5859 5860void si_dpm_disable(struct radeon_device *rdev) 5861{ 5862 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5863 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5864 5865 if (!si_is_smc_running(rdev)) 5866 return; 5867 si_disable_ulv(rdev); 5868 si_clear_vc(rdev); 5869 if (pi->thermal_protection) 5870 si_enable_thermal_protection(rdev, false); 5871 si_enable_power_containment(rdev, boot_ps, false); 5872 si_enable_smc_cac(rdev, boot_ps, false); 5873 si_enable_spread_spectrum(rdev, false); 5874 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5875 si_stop_dpm(rdev); 5876 si_reset_to_default(rdev); 5877 si_dpm_stop_smc(rdev); 5878 si_force_switch_to_arb_f0(rdev); 5879 5880 ni_update_current_ps(rdev, boot_ps); 5881} 5882 5883int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5884{ 5885 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5886 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5887 struct radeon_ps *new_ps = &requested_ps; 5888 5889 ni_update_requested_ps(rdev, new_ps); 5890 5891 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5892 5893 return 0; 5894} 5895 5896static int si_power_control_set_level(struct radeon_device *rdev) 5897{ 5898 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 5899 int ret; 5900 5901 ret = si_restrict_performance_levels_before_switch(rdev); 5902 if (ret) 5903 return ret; 5904 ret = si_halt_smc(rdev); 5905 if (ret) 5906 return ret; 5907 ret = si_populate_smc_tdp_limits(rdev, new_ps); 5908 if (ret) 5909 return ret; 5910 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 5911 if (ret) 5912 return ret; 5913 ret = si_resume_smc(rdev); 5914 if (ret) 5915 return ret; 5916 ret = si_set_sw_state(rdev); 5917 if (ret) 5918 return ret; 5919 return 0; 5920} 5921 5922int si_dpm_set_power_state(struct radeon_device *rdev) 5923{ 5924 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5925 struct radeon_ps *new_ps = &eg_pi->requested_rps; 5926 struct radeon_ps *old_ps = &eg_pi->current_rps; 5927 int ret; 5928 5929 ret = si_disable_ulv(rdev); 5930 if (ret) { 5931 DRM_ERROR("si_disable_ulv failed\n"); 5932 return ret; 5933 } 5934 ret = si_restrict_performance_levels_before_switch(rdev); 5935 if (ret) { 5936 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 5937 return ret; 5938 } 5939 if (eg_pi->pcie_performance_request) 5940 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5941 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 5942 ret = si_enable_power_containment(rdev, new_ps, false); 5943 if (ret) { 5944 DRM_ERROR("si_enable_power_containment failed\n"); 5945 return ret; 5946 } 5947 ret = si_enable_smc_cac(rdev, new_ps, false); 5948 if (ret) { 5949 DRM_ERROR("si_enable_smc_cac failed\n"); 5950 return ret; 5951 } 5952 ret = si_halt_smc(rdev); 5953 if (ret) { 5954 DRM_ERROR("si_halt_smc failed\n"); 5955 return ret; 5956 } 5957 ret = si_upload_sw_state(rdev, new_ps); 5958 if (ret) { 5959 DRM_ERROR("si_upload_sw_state failed\n"); 5960 return ret; 5961 } 5962 ret = si_upload_smc_data(rdev); 5963 if (ret) { 5964 DRM_ERROR("si_upload_smc_data failed\n"); 5965 return ret; 5966 } 5967 ret = si_upload_ulv_state(rdev); 5968 if (ret) { 5969 DRM_ERROR("si_upload_ulv_state failed\n"); 5970 return ret; 5971 } 5972 if (eg_pi->dynamic_ac_timing) { 5973 ret = si_upload_mc_reg_table(rdev, new_ps); 5974 if (ret) { 5975 DRM_ERROR("si_upload_mc_reg_table failed\n"); 5976 return ret; 5977 } 5978 } 5979 ret = si_program_memory_timing_parameters(rdev, new_ps); 5980 if (ret) { 5981 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 5982 return ret; 5983 } 5984 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 5985 5986 ret = si_resume_smc(rdev); 5987 if (ret) { 5988 DRM_ERROR("si_resume_smc failed\n"); 5989 return ret; 5990 } 5991 ret = si_set_sw_state(rdev); 5992 if (ret) { 5993 DRM_ERROR("si_set_sw_state failed\n"); 5994 return ret; 5995 } 5996 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 5997 if (eg_pi->pcie_performance_request) 5998 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 5999 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6000 if (ret) { 6001 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6002 return ret; 6003 } 6004 ret = si_enable_smc_cac(rdev, new_ps, true); 6005 if (ret) { 6006 DRM_ERROR("si_enable_smc_cac failed\n"); 6007 return ret; 6008 } 6009 ret = si_enable_power_containment(rdev, new_ps, true); 6010 if (ret) { 6011 DRM_ERROR("si_enable_power_containment failed\n"); 6012 return ret; 6013 } 6014 6015 ret = si_power_control_set_level(rdev); 6016 if (ret) { 6017 DRM_ERROR("si_power_control_set_level failed\n"); 6018 return ret; 6019 } 6020 6021 ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO); 6022 if (ret) { 6023 DRM_ERROR("si_dpm_force_performance_level failed\n"); 6024 return ret; 6025 } 6026 6027 return 0; 6028} 6029 6030void si_dpm_post_set_power_state(struct radeon_device *rdev) 6031{ 6032 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6033 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6034 6035 ni_update_current_ps(rdev, new_ps); 6036} 6037 6038 6039void si_dpm_reset_asic(struct radeon_device *rdev) 6040{ 6041 si_restrict_performance_levels_before_switch(rdev); 6042 si_disable_ulv(rdev); 6043 si_set_boot_state(rdev); 6044} 6045 6046void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6047{ 6048 si_program_display_gap(rdev); 6049} 6050 6051union power_info { 6052 struct _ATOM_POWERPLAY_INFO info; 6053 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6054 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6055 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6056 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6057 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6058}; 6059 6060union pplib_clock_info { 6061 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6062 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6063 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6064 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6065 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6066}; 6067 6068union pplib_power_state { 6069 struct _ATOM_PPLIB_STATE v1; 6070 struct _ATOM_PPLIB_STATE_V2 v2; 6071}; 6072 6073static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6074 struct radeon_ps *rps, 6075 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6076 u8 table_rev) 6077{ 6078 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6079 rps->class = le16_to_cpu(non_clock_info->usClassification); 6080 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6081 6082 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6083 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6084 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6085 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6086 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6087 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6088 } else { 6089 rps->vclk = 0; 6090 rps->dclk = 0; 6091 } 6092 6093 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6094 rdev->pm.dpm.boot_ps = rps; 6095 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6096 rdev->pm.dpm.uvd_ps = rps; 6097} 6098 6099static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6100 struct radeon_ps *rps, int index, 6101 union pplib_clock_info *clock_info) 6102{ 6103 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6104 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6105 struct si_power_info *si_pi = si_get_pi(rdev); 6106 struct ni_ps *ps = ni_get_ps(rps); 6107 u16 leakage_voltage; 6108 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6109 int ret; 6110 6111 ps->performance_level_count = index + 1; 6112 6113 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6114 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6115 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6116 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6117 6118 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6119 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6120 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6121 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6122 si_pi->sys_pcie_mask, 6123 si_pi->boot_pcie_gen, 6124 clock_info->si.ucPCIEGen); 6125 6126 /* patch up vddc if necessary */ 6127 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6128 &leakage_voltage); 6129 if (ret == 0) 6130 pl->vddc = leakage_voltage; 6131 6132 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6133 pi->acpi_vddc = pl->vddc; 6134 eg_pi->acpi_vddci = pl->vddci; 6135 si_pi->acpi_pcie_gen = pl->pcie_gen; 6136 } 6137 6138 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6139 index == 0) { 6140 /* XXX disable for A0 tahiti */ 6141 si_pi->ulv.supported = true; 6142 si_pi->ulv.pl = *pl; 6143 si_pi->ulv.one_pcie_lane_in_ulv = false; 6144 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6145 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6146 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6147 } 6148 6149 if (pi->min_vddc_in_table > pl->vddc) 6150 pi->min_vddc_in_table = pl->vddc; 6151 6152 if (pi->max_vddc_in_table < pl->vddc) 6153 pi->max_vddc_in_table = pl->vddc; 6154 6155 /* patch up boot state */ 6156 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6157 u16 vddc, vddci, mvdd; 6158 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6159 pl->mclk = rdev->clock.default_mclk; 6160 pl->sclk = rdev->clock.default_sclk; 6161 pl->vddc = vddc; 6162 pl->vddci = vddci; 6163 si_pi->mvdd_bootup_value = mvdd; 6164 } 6165 6166 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6167 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6168 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6169 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6170 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6171 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6172 } 6173} 6174 6175static int si_parse_power_table(struct radeon_device *rdev) 6176{ 6177 struct radeon_mode_info *mode_info = &rdev->mode_info; 6178 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6179 union pplib_power_state *power_state; 6180 int i, j, k, non_clock_array_index, clock_array_index; 6181 union pplib_clock_info *clock_info; 6182 struct _StateArray *state_array; 6183 struct _ClockInfoArray *clock_info_array; 6184 struct _NonClockInfoArray *non_clock_info_array; 6185 union power_info *power_info; 6186 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6187 u16 data_offset; 6188 u8 frev, crev; 6189 u8 *power_state_offset; 6190 struct ni_ps *ps; 6191 6192 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6193 &frev, &crev, &data_offset)) 6194 return -EINVAL; 6195 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6196 6197 state_array = (struct _StateArray *) 6198 (mode_info->atom_context->bios + data_offset + 6199 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6200 clock_info_array = (struct _ClockInfoArray *) 6201 (mode_info->atom_context->bios + data_offset + 6202 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6203 non_clock_info_array = (struct _NonClockInfoArray *) 6204 (mode_info->atom_context->bios + data_offset + 6205 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6206 6207 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6208 state_array->ucNumEntries, GFP_KERNEL); 6209 if (!rdev->pm.dpm.ps) 6210 return -ENOMEM; 6211 power_state_offset = (u8 *)state_array->states; 6212 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 6213 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 6214 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 6215 for (i = 0; i < state_array->ucNumEntries; i++) { 6216 power_state = (union pplib_power_state *)power_state_offset; 6217 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6218 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6219 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6220 if (!rdev->pm.power_state[i].clock_info) 6221 return -EINVAL; 6222 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6223 if (ps == NULL) { 6224 kfree(rdev->pm.dpm.ps); 6225 return -ENOMEM; 6226 } 6227 rdev->pm.dpm.ps[i].ps_priv = ps; 6228 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6229 non_clock_info, 6230 non_clock_info_array->ucEntrySize); 6231 k = 0; 6232 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6233 clock_array_index = power_state->v2.clockInfoIndex[j]; 6234 if (clock_array_index >= clock_info_array->ucNumEntries) 6235 continue; 6236 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6237 break; 6238 clock_info = (union pplib_clock_info *) 6239 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6240 si_parse_pplib_clock_info(rdev, 6241 &rdev->pm.dpm.ps[i], k, 6242 clock_info); 6243 k++; 6244 } 6245 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6246 } 6247 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6248 return 0; 6249} 6250 6251int si_dpm_init(struct radeon_device *rdev) 6252{ 6253 struct rv7xx_power_info *pi; 6254 struct evergreen_power_info *eg_pi; 6255 struct ni_power_info *ni_pi; 6256 struct si_power_info *si_pi; 6257 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 6258 u16 data_offset, size; 6259 u8 frev, crev; 6260 struct atom_clock_dividers dividers; 6261 int ret; 6262 u32 mask; 6263 6264 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6265 if (si_pi == NULL) 6266 return -ENOMEM; 6267 rdev->pm.dpm.priv = si_pi; 6268 ni_pi = &si_pi->ni; 6269 eg_pi = &ni_pi->eg; 6270 pi = &eg_pi->rv7xx; 6271 6272 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6273 if (ret) 6274 si_pi->sys_pcie_mask = 0; 6275 else 6276 si_pi->sys_pcie_mask = mask; 6277 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6278 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6279 6280 si_set_max_cu_value(rdev); 6281 6282 rv770_get_max_vddc(rdev); 6283 si_get_leakage_vddc(rdev); 6284 si_patch_dependency_tables_based_on_leakage(rdev); 6285 6286 pi->acpi_vddc = 0; 6287 eg_pi->acpi_vddci = 0; 6288 pi->min_vddc_in_table = 0; 6289 pi->max_vddc_in_table = 0; 6290 6291 ret = si_parse_power_table(rdev); 6292 if (ret) 6293 return ret; 6294 ret = r600_parse_extended_power_table(rdev); 6295 if (ret) 6296 return ret; 6297 6298 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6299 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6300 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6301 r600_free_extended_power_table(rdev); 6302 return -ENOMEM; 6303 } 6304 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6305 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6306 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6307 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6308 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6309 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6310 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6311 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6312 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6313 6314 if (rdev->pm.dpm.voltage_response_time == 0) 6315 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6316 if (rdev->pm.dpm.backbias_response_time == 0) 6317 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6318 6319 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6320 0, false, ÷rs); 6321 if (ret) 6322 pi->ref_div = dividers.ref_div + 1; 6323 else 6324 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6325 6326 eg_pi->smu_uvd_hs = false; 6327 6328 pi->mclk_strobe_mode_threshold = 40000; 6329 if (si_is_special_1gb_platform(rdev)) 6330 pi->mclk_stutter_mode_threshold = 0; 6331 else 6332 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6333 pi->mclk_edc_enable_threshold = 40000; 6334 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6335 6336 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6337 6338 pi->voltage_control = 6339 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT); 6340 6341 pi->mvdd_control = 6342 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT); 6343 6344 eg_pi->vddci_control = 6345 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT); 6346 6347 si_pi->vddc_phase_shed_control = 6348 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6349 6350 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 6351 &frev, &crev, &data_offset)) { 6352 pi->sclk_ss = true; 6353 pi->mclk_ss = true; 6354 pi->dynamic_ss = true; 6355 } else { 6356 pi->sclk_ss = false; 6357 pi->mclk_ss = false; 6358 pi->dynamic_ss = true; 6359 } 6360 6361 pi->asi = RV770_ASI_DFLT; 6362 pi->pasi = CYPRESS_HASI_DFLT; 6363 pi->vrc = SISLANDS_VRC_DFLT; 6364 6365 pi->gfx_clock_gating = true; 6366 6367 eg_pi->sclk_deep_sleep = true; 6368 si_pi->sclk_deep_sleep_above_low = false; 6369 6370 if (pi->gfx_clock_gating && 6371 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 6372 pi->thermal_protection = true; 6373 else 6374 pi->thermal_protection = false; 6375 6376 eg_pi->dynamic_ac_timing = true; 6377 6378 eg_pi->light_sleep = true; 6379#if defined(CONFIG_ACPI) 6380 eg_pi->pcie_performance_request = 6381 radeon_acpi_is_pcie_performance_request_supported(rdev); 6382#else 6383 eg_pi->pcie_performance_request = false; 6384#endif 6385 6386 si_pi->sram_end = SMC_RAM_END; 6387 6388 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6389 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6390 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6391 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6392 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6393 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6394 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6395 6396 si_initialize_powertune_defaults(rdev); 6397 6398 return 0; 6399} 6400 6401void si_dpm_fini(struct radeon_device *rdev) 6402{ 6403 int i; 6404 6405 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6406 kfree(rdev->pm.dpm.ps[i].ps_priv); 6407 } 6408 kfree(rdev->pm.dpm.ps); 6409 kfree(rdev->pm.dpm.priv); 6410 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6411 r600_free_extended_power_table(rdev); 6412} 6413 6414void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6415 struct seq_file *m) 6416{ 6417 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 6418 struct ni_ps *ps = ni_get_ps(rps); 6419 struct rv7xx_pl *pl; 6420 u32 current_index = 6421 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6422 CURRENT_STATE_INDEX_SHIFT; 6423 6424 if (current_index >= ps->performance_level_count) { 6425 seq_printf(m, "invalid dpm profile %d\n", current_index); 6426 } else { 6427 pl = &ps->performance_levels[current_index]; 6428 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6429 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6430 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6431 } 6432} 6433