si_dpm.c revision bf0936e196ec21b604106578043d4c14831f99e7
1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include "drmP.h" 25#include "radeon.h" 26#include "sid.h" 27#include "r600_dpm.h" 28#include "si_dpm.h" 29#include "atom.h" 30#include <linux/math64.h> 31#include <linux/seq_file.h> 32 33#define MC_CG_ARB_FREQ_F0 0x0a 34#define MC_CG_ARB_FREQ_F1 0x0b 35#define MC_CG_ARB_FREQ_F2 0x0c 36#define MC_CG_ARB_FREQ_F3 0x0d 37 38#define SMC_RAM_END 0x20000 39 40#define DDR3_DRAM_ROWS 0x2000 41 42#define SCLK_MIN_DEEPSLEEP_FREQ 1350 43 44static const struct si_cac_config_reg cac_weights_tahiti[] = 45{ 46 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 47 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 49 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 50 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 56 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 58 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 59 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 61 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 64 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 65 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 67 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 68 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 77 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 81 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 84 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 86 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 106 { 0xFFFFFFFF } 107}; 108 109static const struct si_cac_config_reg lcac_tahiti[] = 110{ 111 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 112 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 114 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 118 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 120 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 134 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 138 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 158 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 162 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 170 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 174 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 184 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 186 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 188 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 196 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 197 { 0xFFFFFFFF } 198 199}; 200 201static const struct si_cac_config_reg cac_override_tahiti[] = 202{ 203 { 0xFFFFFFFF } 204}; 205 206static const struct si_powertune_data powertune_data_tahiti = 207{ 208 ((1 << 16) | 27027), 209 6, 210 0, 211 4, 212 95, 213 { 214 0UL, 215 0UL, 216 4521550UL, 217 309631529UL, 218 -1270850L, 219 4513710L, 220 40 221 }, 222 595000000UL, 223 12, 224 { 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0 233 }, 234 true 235}; 236 237static const struct si_dte_data dte_data_tahiti = 238{ 239 { 1159409, 0, 0, 0, 0 }, 240 { 777, 0, 0, 0, 0 }, 241 2, 242 54000, 243 127000, 244 25, 245 2, 246 10, 247 13, 248 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 249 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 250 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 251 85, 252 false 253}; 254 255static const struct si_dte_data dte_data_tahiti_le = 256{ 257 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 258 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 259 0x5, 260 0xAFC8, 261 0x64, 262 0x32, 263 1, 264 0, 265 0x10, 266 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 267 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 268 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 269 85, 270 true 271}; 272 273static const struct si_dte_data dte_data_tahiti_pro = 274{ 275 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 276 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 277 5, 278 45000, 279 100, 280 0xA, 281 1, 282 0, 283 0x10, 284 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 285 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 286 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 287 90, 288 true 289}; 290 291static const struct si_dte_data dte_data_new_zealand = 292{ 293 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 294 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 295 0x5, 296 0xAFC8, 297 0x69, 298 0x32, 299 1, 300 0, 301 0x10, 302 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 303 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 304 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 305 85, 306 true 307}; 308 309static const struct si_dte_data dte_data_aruba_pro = 310{ 311 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 312 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 313 5, 314 45000, 315 100, 316 0xA, 317 1, 318 0, 319 0x10, 320 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 321 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 322 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 323 90, 324 true 325}; 326 327static const struct si_dte_data dte_data_malta = 328{ 329 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 330 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 331 5, 332 45000, 333 100, 334 0xA, 335 1, 336 0, 337 0x10, 338 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 339 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 340 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 341 90, 342 true 343}; 344 345struct si_cac_config_reg cac_weights_pitcairn[] = 346{ 347 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 348 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 351 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 352 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 356 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 358 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 360 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 361 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 365 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 366 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 367 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 369 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 370 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 373 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 380 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 382 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 383 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 386 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 407 { 0xFFFFFFFF } 408}; 409 410static const struct si_cac_config_reg lcac_pitcairn[] = 411{ 412 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 413 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 484 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 486 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 488 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 490 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 492 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 498 { 0xFFFFFFFF } 499}; 500 501static const struct si_cac_config_reg cac_override_pitcairn[] = 502{ 503 { 0xFFFFFFFF } 504}; 505 506static const struct si_powertune_data powertune_data_pitcairn = 507{ 508 ((1 << 16) | 27027), 509 5, 510 0, 511 6, 512 100, 513 { 514 51600000UL, 515 1800000UL, 516 7194395UL, 517 309631529UL, 518 -1270850L, 519 4513710L, 520 100 521 }, 522 117830498UL, 523 12, 524 { 525 0, 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0 533 }, 534 true 535}; 536 537static const struct si_dte_data dte_data_pitcairn = 538{ 539 { 0, 0, 0, 0, 0 }, 540 { 0, 0, 0, 0, 0 }, 541 0, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 0, 552 false 553}; 554 555static const struct si_dte_data dte_data_curacao_xt = 556{ 557 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 558 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 559 5, 560 45000, 561 100, 562 0xA, 563 1, 564 0, 565 0x10, 566 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 567 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 568 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 569 90, 570 true 571}; 572 573static const struct si_dte_data dte_data_curacao_pro = 574{ 575 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 576 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 577 5, 578 45000, 579 100, 580 0xA, 581 1, 582 0, 583 0x10, 584 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 585 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 586 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 587 90, 588 true 589}; 590 591static const struct si_dte_data dte_data_neptune_xt = 592{ 593 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 594 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 595 5, 596 45000, 597 100, 598 0xA, 599 1, 600 0, 601 0x10, 602 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 603 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 604 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 605 90, 606 true 607}; 608 609static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 610{ 611 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 612 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 613 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 615 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 616 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 620 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 622 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 624 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 625 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 627 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 629 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 630 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 631 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 633 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 634 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 637 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 639 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 643 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 644 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 647 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 649 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 650 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 652 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 671 { 0xFFFFFFFF } 672}; 673 674static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 675{ 676 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 677 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 678 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 680 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 681 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 683 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 685 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 687 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 689 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 690 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 692 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 694 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 695 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 696 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 698 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 699 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 702 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 704 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 708 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 709 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 712 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 714 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 715 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 717 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 736 { 0xFFFFFFFF } 737}; 738 739static const struct si_cac_config_reg cac_weights_heathrow[] = 740{ 741 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 742 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 743 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 745 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 746 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 748 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 750 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 752 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 754 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 755 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 757 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 759 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 760 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 761 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 763 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 764 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 767 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 769 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 773 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 774 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 777 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 779 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 780 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 782 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 801 { 0xFFFFFFFF } 802}; 803 804static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 805{ 806 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 807 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 808 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 810 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 811 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 813 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 815 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 817 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 819 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 820 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 822 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 824 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 825 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 826 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 828 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 829 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 832 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 834 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 838 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 839 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 842 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 844 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 845 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 847 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 866 { 0xFFFFFFFF } 867}; 868 869static const struct si_cac_config_reg cac_weights_cape_verde[] = 870{ 871 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 872 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 873 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 875 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 876 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 878 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 880 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 882 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 884 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 885 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 887 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 889 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 890 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 891 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 893 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 894 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 897 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 899 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 903 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 904 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 907 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 909 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 910 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 912 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 931 { 0xFFFFFFFF } 932}; 933 934static const struct si_cac_config_reg lcac_cape_verde[] = 935{ 936 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 937 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0xFFFFFFFF } 991}; 992 993static const struct si_cac_config_reg cac_override_cape_verde[] = 994{ 995 { 0xFFFFFFFF } 996}; 997 998static const struct si_powertune_data powertune_data_cape_verde = 999{ 1000 ((1 << 16) | 0x6993), 1001 5, 1002 0, 1003 7, 1004 105, 1005 { 1006 0UL, 1007 0UL, 1008 7194395UL, 1009 309631529UL, 1010 -1270850L, 1011 4513710L, 1012 100 1013 }, 1014 117830498UL, 1015 12, 1016 { 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0 1025 }, 1026 true 1027}; 1028 1029static const struct si_dte_data dte_data_cape_verde = 1030{ 1031 { 0, 0, 0, 0, 0 }, 1032 { 0, 0, 0, 0, 0 }, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 0, 1044 false 1045}; 1046 1047static const struct si_dte_data dte_data_venus_xtx = 1048{ 1049 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1050 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1051 5, 1052 55000, 1053 0x69, 1054 0xA, 1055 1, 1056 0, 1057 0x3, 1058 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 90, 1062 true 1063}; 1064 1065static const struct si_dte_data dte_data_venus_xt = 1066{ 1067 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1068 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1069 5, 1070 55000, 1071 0x69, 1072 0xA, 1073 1, 1074 0, 1075 0x3, 1076 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 90, 1080 true 1081}; 1082 1083static const struct si_dte_data dte_data_venus_pro = 1084{ 1085 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1086 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1087 5, 1088 55000, 1089 0x69, 1090 0xA, 1091 1, 1092 0, 1093 0x3, 1094 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 90, 1098 true 1099}; 1100 1101struct si_cac_config_reg cac_weights_oland[] = 1102{ 1103 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1163 { 0xFFFFFFFF } 1164}; 1165 1166static const struct si_cac_config_reg cac_weights_mars_pro[] = 1167{ 1168 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1228 { 0xFFFFFFFF } 1229}; 1230 1231static const struct si_cac_config_reg cac_weights_mars_xt[] = 1232{ 1233 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1293 { 0xFFFFFFFF } 1294}; 1295 1296static const struct si_cac_config_reg cac_weights_oland_pro[] = 1297{ 1298 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1358 { 0xFFFFFFFF } 1359}; 1360 1361static const struct si_cac_config_reg cac_weights_oland_xt[] = 1362{ 1363 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1423 { 0xFFFFFFFF } 1424}; 1425 1426static const struct si_cac_config_reg lcac_oland[] = 1427{ 1428 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0xFFFFFFFF } 1471}; 1472 1473static const struct si_cac_config_reg lcac_mars_pro[] = 1474{ 1475 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0xFFFFFFFF } 1518}; 1519 1520static const struct si_cac_config_reg cac_override_oland[] = 1521{ 1522 { 0xFFFFFFFF } 1523}; 1524 1525static const struct si_powertune_data powertune_data_oland = 1526{ 1527 ((1 << 16) | 0x6993), 1528 5, 1529 0, 1530 7, 1531 105, 1532 { 1533 0UL, 1534 0UL, 1535 7194395UL, 1536 309631529UL, 1537 -1270850L, 1538 4513710L, 1539 100 1540 }, 1541 117830498UL, 1542 12, 1543 { 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0 1552 }, 1553 true 1554}; 1555 1556static const struct si_powertune_data powertune_data_mars_pro = 1557{ 1558 ((1 << 16) | 0x6993), 1559 5, 1560 0, 1561 7, 1562 105, 1563 { 1564 0UL, 1565 0UL, 1566 7194395UL, 1567 309631529UL, 1568 -1270850L, 1569 4513710L, 1570 100 1571 }, 1572 117830498UL, 1573 12, 1574 { 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0 1583 }, 1584 true 1585}; 1586 1587static const struct si_dte_data dte_data_oland = 1588{ 1589 { 0, 0, 0, 0, 0 }, 1590 { 0, 0, 0, 0, 0 }, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 0, 1602 false 1603}; 1604 1605static const struct si_dte_data dte_data_mars_pro = 1606{ 1607 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1608 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1609 5, 1610 55000, 1611 105, 1612 0xA, 1613 1, 1614 0, 1615 0x10, 1616 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1617 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1618 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1619 90, 1620 true 1621}; 1622 1623static const struct si_dte_data dte_data_sun_xt = 1624{ 1625 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1626 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1627 5, 1628 55000, 1629 105, 1630 0xA, 1631 1, 1632 0, 1633 0x10, 1634 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1635 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1636 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1637 90, 1638 true 1639}; 1640 1641 1642static const struct si_cac_config_reg cac_weights_hainan[] = 1643{ 1644 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1704 { 0xFFFFFFFF } 1705}; 1706 1707static const struct si_powertune_data powertune_data_hainan = 1708{ 1709 ((1 << 16) | 0x6993), 1710 5, 1711 0, 1712 9, 1713 105, 1714 { 1715 0UL, 1716 0UL, 1717 7194395UL, 1718 309631529UL, 1719 -1270850L, 1720 4513710L, 1721 100 1722 }, 1723 117830498UL, 1724 12, 1725 { 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0 1734 }, 1735 true 1736}; 1737 1738struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1739struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1740struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1741struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1742 1743static int si_populate_voltage_value(struct radeon_device *rdev, 1744 const struct atom_voltage_table *table, 1745 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1746static int si_get_std_voltage_value(struct radeon_device *rdev, 1747 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1748 u16 *std_voltage); 1749static int si_write_smc_soft_register(struct radeon_device *rdev, 1750 u16 reg_offset, u32 value); 1751static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1752 struct rv7xx_pl *pl, 1753 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1754static int si_calculate_sclk_params(struct radeon_device *rdev, 1755 u32 engine_clock, 1756 SISLANDS_SMC_SCLK_VALUE *sclk); 1757 1758static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1759{ 1760 struct si_power_info *pi = rdev->pm.dpm.priv; 1761 1762 return pi; 1763} 1764 1765static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1766 u16 v, s32 t, u32 ileakage, u32 *leakage) 1767{ 1768 s64 kt, kv, leakage_w, i_leakage, vddc; 1769 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1770 1771 i_leakage = drm_int2fixp(ileakage / 100); 1772 vddc = div64_s64(drm_int2fixp(v), 1000); 1773 temperature = div64_s64(drm_int2fixp(t), 1000); 1774 1775 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1776 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1777 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1778 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1779 t_ref = drm_int2fixp(coeff->t_ref); 1780 1781 kt = drm_fixp_div(drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, temperature)), 1782 drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, t_ref))); 1783 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1784 1785 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1786 1787 *leakage = drm_fixp2int(leakage_w * 1000); 1788} 1789 1790static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1791 const struct ni_leakage_coeffients *coeff, 1792 u16 v, 1793 s32 t, 1794 u32 i_leakage, 1795 u32 *leakage) 1796{ 1797 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1798} 1799 1800static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1801 const u32 fixed_kt, u16 v, 1802 u32 ileakage, u32 *leakage) 1803{ 1804 s64 kt, kv, leakage_w, i_leakage, vddc; 1805 1806 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1807 vddc = div64_s64(drm_int2fixp(v), 1000); 1808 1809 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1810 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1811 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1812 1813 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1814 1815 *leakage = drm_fixp2int(leakage_w * 1000); 1816} 1817 1818static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1819 const struct ni_leakage_coeffients *coeff, 1820 const u32 fixed_kt, 1821 u16 v, 1822 u32 i_leakage, 1823 u32 *leakage) 1824{ 1825 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1826} 1827 1828 1829static void si_update_dte_from_pl2(struct radeon_device *rdev, 1830 struct si_dte_data *dte_data) 1831{ 1832 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1833 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1834 u32 k = dte_data->k; 1835 u32 t_max = dte_data->max_t; 1836 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1837 u32 t_0 = dte_data->t0; 1838 u32 i; 1839 1840 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1841 dte_data->tdep_count = 3; 1842 1843 for (i = 0; i < k; i++) { 1844 dte_data->r[i] = 1845 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1846 (p_limit2 * (u32)100); 1847 } 1848 1849 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1850 1851 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1852 dte_data->tdep_r[i] = dte_data->r[4]; 1853 } 1854 } else { 1855 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1856 } 1857} 1858 1859static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1860{ 1861 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1862 struct si_power_info *si_pi = si_get_pi(rdev); 1863 bool update_dte_from_pl2 = false; 1864 1865 if (rdev->family == CHIP_TAHITI) { 1866 si_pi->cac_weights = cac_weights_tahiti; 1867 si_pi->lcac_config = lcac_tahiti; 1868 si_pi->cac_override = cac_override_tahiti; 1869 si_pi->powertune_data = &powertune_data_tahiti; 1870 si_pi->dte_data = dte_data_tahiti; 1871 1872 switch (rdev->pdev->device) { 1873 case 0x6798: 1874 si_pi->dte_data.enable_dte_by_default = true; 1875 break; 1876 case 0x6799: 1877 si_pi->dte_data = dte_data_new_zealand; 1878 break; 1879 case 0x6790: 1880 case 0x6791: 1881 case 0x6792: 1882 case 0x679E: 1883 si_pi->dte_data = dte_data_aruba_pro; 1884 update_dte_from_pl2 = true; 1885 break; 1886 case 0x679B: 1887 si_pi->dte_data = dte_data_malta; 1888 update_dte_from_pl2 = true; 1889 break; 1890 case 0x679A: 1891 si_pi->dte_data = dte_data_tahiti_pro; 1892 update_dte_from_pl2 = true; 1893 break; 1894 default: 1895 if (si_pi->dte_data.enable_dte_by_default == true) 1896 DRM_ERROR("DTE is not enabled!\n"); 1897 break; 1898 } 1899 } else if (rdev->family == CHIP_PITCAIRN) { 1900 switch (rdev->pdev->device) { 1901 case 0x6810: 1902 case 0x6818: 1903 si_pi->cac_weights = cac_weights_pitcairn; 1904 si_pi->lcac_config = lcac_pitcairn; 1905 si_pi->cac_override = cac_override_pitcairn; 1906 si_pi->powertune_data = &powertune_data_pitcairn; 1907 si_pi->dte_data = dte_data_curacao_xt; 1908 update_dte_from_pl2 = true; 1909 break; 1910 case 0x6819: 1911 case 0x6811: 1912 si_pi->cac_weights = cac_weights_pitcairn; 1913 si_pi->lcac_config = lcac_pitcairn; 1914 si_pi->cac_override = cac_override_pitcairn; 1915 si_pi->powertune_data = &powertune_data_pitcairn; 1916 si_pi->dte_data = dte_data_curacao_pro; 1917 update_dte_from_pl2 = true; 1918 break; 1919 case 0x6800: 1920 case 0x6806: 1921 si_pi->cac_weights = cac_weights_pitcairn; 1922 si_pi->lcac_config = lcac_pitcairn; 1923 si_pi->cac_override = cac_override_pitcairn; 1924 si_pi->powertune_data = &powertune_data_pitcairn; 1925 si_pi->dte_data = dte_data_neptune_xt; 1926 update_dte_from_pl2 = true; 1927 break; 1928 default: 1929 si_pi->cac_weights = cac_weights_pitcairn; 1930 si_pi->lcac_config = lcac_pitcairn; 1931 si_pi->cac_override = cac_override_pitcairn; 1932 si_pi->powertune_data = &powertune_data_pitcairn; 1933 si_pi->dte_data = dte_data_pitcairn; 1934 } 1935 } else if (rdev->family == CHIP_VERDE) { 1936 si_pi->lcac_config = lcac_cape_verde; 1937 si_pi->cac_override = cac_override_cape_verde; 1938 si_pi->powertune_data = &powertune_data_cape_verde; 1939 1940 switch (rdev->pdev->device) { 1941 case 0x683B: 1942 case 0x683F: 1943 case 0x6829: 1944 si_pi->cac_weights = cac_weights_cape_verde_pro; 1945 si_pi->dte_data = dte_data_cape_verde; 1946 break; 1947 case 0x6825: 1948 case 0x6827: 1949 si_pi->cac_weights = cac_weights_heathrow; 1950 si_pi->dte_data = dte_data_cape_verde; 1951 break; 1952 case 0x6824: 1953 case 0x682D: 1954 si_pi->cac_weights = cac_weights_chelsea_xt; 1955 si_pi->dte_data = dte_data_cape_verde; 1956 break; 1957 case 0x682F: 1958 si_pi->cac_weights = cac_weights_chelsea_pro; 1959 si_pi->dte_data = dte_data_cape_verde; 1960 break; 1961 case 0x6820: 1962 si_pi->cac_weights = cac_weights_heathrow; 1963 si_pi->dte_data = dte_data_venus_xtx; 1964 break; 1965 case 0x6821: 1966 si_pi->cac_weights = cac_weights_heathrow; 1967 si_pi->dte_data = dte_data_venus_xt; 1968 break; 1969 case 0x6823: 1970 si_pi->cac_weights = cac_weights_chelsea_pro; 1971 si_pi->dte_data = dte_data_venus_pro; 1972 break; 1973 case 0x682B: 1974 si_pi->cac_weights = cac_weights_chelsea_pro; 1975 si_pi->dte_data = dte_data_venus_pro; 1976 break; 1977 default: 1978 si_pi->cac_weights = cac_weights_cape_verde; 1979 si_pi->dte_data = dte_data_cape_verde; 1980 break; 1981 } 1982 } else if (rdev->family == CHIP_OLAND) { 1983 switch (rdev->pdev->device) { 1984 case 0x6601: 1985 case 0x6621: 1986 case 0x6603: 1987 si_pi->cac_weights = cac_weights_mars_pro; 1988 si_pi->lcac_config = lcac_mars_pro; 1989 si_pi->cac_override = cac_override_oland; 1990 si_pi->powertune_data = &powertune_data_mars_pro; 1991 si_pi->dte_data = dte_data_mars_pro; 1992 update_dte_from_pl2 = true; 1993 break; 1994 case 0x6600: 1995 case 0x6606: 1996 case 0x6620: 1997 si_pi->cac_weights = cac_weights_mars_xt; 1998 si_pi->lcac_config = lcac_mars_pro; 1999 si_pi->cac_override = cac_override_oland; 2000 si_pi->powertune_data = &powertune_data_mars_pro; 2001 si_pi->dte_data = dte_data_mars_pro; 2002 update_dte_from_pl2 = true; 2003 break; 2004 case 0x6611: 2005 si_pi->cac_weights = cac_weights_oland_pro; 2006 si_pi->lcac_config = lcac_mars_pro; 2007 si_pi->cac_override = cac_override_oland; 2008 si_pi->powertune_data = &powertune_data_mars_pro; 2009 si_pi->dte_data = dte_data_mars_pro; 2010 update_dte_from_pl2 = true; 2011 break; 2012 case 0x6610: 2013 si_pi->cac_weights = cac_weights_oland_xt; 2014 si_pi->lcac_config = lcac_mars_pro; 2015 si_pi->cac_override = cac_override_oland; 2016 si_pi->powertune_data = &powertune_data_mars_pro; 2017 si_pi->dte_data = dte_data_mars_pro; 2018 update_dte_from_pl2 = true; 2019 break; 2020 default: 2021 si_pi->cac_weights = cac_weights_oland; 2022 si_pi->lcac_config = lcac_oland; 2023 si_pi->cac_override = cac_override_oland; 2024 si_pi->powertune_data = &powertune_data_oland; 2025 si_pi->dte_data = dte_data_oland; 2026 break; 2027 } 2028 } else if (rdev->family == CHIP_HAINAN) { 2029 si_pi->cac_weights = cac_weights_hainan; 2030 si_pi->lcac_config = lcac_oland; 2031 si_pi->cac_override = cac_override_oland; 2032 si_pi->powertune_data = &powertune_data_hainan; 2033 si_pi->dte_data = dte_data_sun_xt; 2034 update_dte_from_pl2 = true; 2035 } else { 2036 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2037 return; 2038 } 2039 2040 ni_pi->enable_power_containment = false; 2041 ni_pi->enable_cac = false; 2042 ni_pi->enable_sq_ramping = false; 2043 si_pi->enable_dte = false; 2044 2045 if (si_pi->powertune_data->enable_powertune_by_default) { 2046 ni_pi->enable_power_containment= true; 2047 ni_pi->enable_cac = true; 2048 if (si_pi->dte_data.enable_dte_by_default) { 2049 si_pi->enable_dte = true; 2050 if (update_dte_from_pl2) 2051 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2052 2053 } 2054 ni_pi->enable_sq_ramping = true; 2055 } 2056 2057 ni_pi->driver_calculate_cac_leakage = true; 2058 ni_pi->cac_configuration_required = true; 2059 2060 if (ni_pi->cac_configuration_required) { 2061 ni_pi->support_cac_long_term_average = true; 2062 si_pi->dyn_powertune_data.l2_lta_window_size = 2063 si_pi->powertune_data->l2_lta_window_size_default; 2064 si_pi->dyn_powertune_data.lts_truncate = 2065 si_pi->powertune_data->lts_truncate_default; 2066 } else { 2067 ni_pi->support_cac_long_term_average = false; 2068 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2069 si_pi->dyn_powertune_data.lts_truncate = 0; 2070 } 2071 2072 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2073} 2074 2075static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2076{ 2077 return 1; 2078} 2079 2080static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2081{ 2082 u32 xclk; 2083 u32 wintime; 2084 u32 cac_window; 2085 u32 cac_window_size; 2086 2087 xclk = radeon_get_xclk(rdev); 2088 2089 if (xclk == 0) 2090 return 0; 2091 2092 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2093 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2094 2095 wintime = (cac_window_size * 100) / xclk; 2096 2097 return wintime; 2098} 2099 2100static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2101{ 2102 return power_in_watts; 2103} 2104 2105static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2106 bool adjust_polarity, 2107 u32 tdp_adjustment, 2108 u32 *tdp_limit, 2109 u32 *near_tdp_limit) 2110{ 2111 u32 adjustment_delta, max_tdp_limit; 2112 2113 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2114 return -EINVAL; 2115 2116 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2117 2118 if (adjust_polarity) { 2119 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2120 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2121 } else { 2122 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2123 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2124 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2125 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2126 else 2127 *near_tdp_limit = 0; 2128 } 2129 2130 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2131 return -EINVAL; 2132 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2133 return -EINVAL; 2134 2135 return 0; 2136} 2137 2138static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2139 struct radeon_ps *radeon_state) 2140{ 2141 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2142 struct si_power_info *si_pi = si_get_pi(rdev); 2143 2144 if (ni_pi->enable_power_containment) { 2145 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2146 PP_SIslands_PAPMParameters *papm_parm; 2147 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2148 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2149 u32 tdp_limit; 2150 u32 near_tdp_limit; 2151 int ret; 2152 2153 if (scaling_factor == 0) 2154 return -EINVAL; 2155 2156 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2157 2158 ret = si_calculate_adjusted_tdp_limits(rdev, 2159 false, /* ??? */ 2160 rdev->pm.dpm.tdp_adjustment, 2161 &tdp_limit, 2162 &near_tdp_limit); 2163 if (ret) 2164 return ret; 2165 2166 smc_table->dpm2Params.TDPLimit = 2167 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2168 smc_table->dpm2Params.NearTDPLimit = 2169 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2170 smc_table->dpm2Params.SafePowerLimit = 2171 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2172 2173 ret = si_copy_bytes_to_smc(rdev, 2174 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2175 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2176 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2177 sizeof(u32) * 3, 2178 si_pi->sram_end); 2179 if (ret) 2180 return ret; 2181 2182 if (si_pi->enable_ppm) { 2183 papm_parm = &si_pi->papm_parm; 2184 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2185 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2186 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2187 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2188 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2189 papm_parm->PlatformPowerLimit = 0xffffffff; 2190 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2191 2192 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2193 (u8 *)papm_parm, 2194 sizeof(PP_SIslands_PAPMParameters), 2195 si_pi->sram_end); 2196 if (ret) 2197 return ret; 2198 } 2199 } 2200 return 0; 2201} 2202 2203static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2204 struct radeon_ps *radeon_state) 2205{ 2206 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2207 struct si_power_info *si_pi = si_get_pi(rdev); 2208 2209 if (ni_pi->enable_power_containment) { 2210 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2211 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2212 int ret; 2213 2214 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2215 2216 smc_table->dpm2Params.NearTDPLimit = 2217 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2218 smc_table->dpm2Params.SafePowerLimit = 2219 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2220 2221 ret = si_copy_bytes_to_smc(rdev, 2222 (si_pi->state_table_start + 2223 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2224 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2225 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2226 sizeof(u32) * 2, 2227 si_pi->sram_end); 2228 if (ret) 2229 return ret; 2230 } 2231 2232 return 0; 2233} 2234 2235static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2236 const u16 prev_std_vddc, 2237 const u16 curr_std_vddc) 2238{ 2239 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2240 u64 prev_vddc = (u64)prev_std_vddc; 2241 u64 curr_vddc = (u64)curr_std_vddc; 2242 u64 pwr_efficiency_ratio, n, d; 2243 2244 if ((prev_vddc == 0) || (curr_vddc == 0)) 2245 return 0; 2246 2247 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2248 d = prev_vddc * prev_vddc; 2249 pwr_efficiency_ratio = div64_u64(n, d); 2250 2251 if (pwr_efficiency_ratio > (u64)0xFFFF) 2252 return 0; 2253 2254 return (u16)pwr_efficiency_ratio; 2255} 2256 2257static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2258 struct radeon_ps *radeon_state) 2259{ 2260 struct si_power_info *si_pi = si_get_pi(rdev); 2261 2262 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2263 radeon_state->vclk && radeon_state->dclk) 2264 return true; 2265 2266 return false; 2267} 2268 2269static int si_populate_power_containment_values(struct radeon_device *rdev, 2270 struct radeon_ps *radeon_state, 2271 SISLANDS_SMC_SWSTATE *smc_state) 2272{ 2273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2274 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2275 struct ni_ps *state = ni_get_ps(radeon_state); 2276 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2277 u32 prev_sclk; 2278 u32 max_sclk; 2279 u32 min_sclk; 2280 u16 prev_std_vddc; 2281 u16 curr_std_vddc; 2282 int i; 2283 u16 pwr_efficiency_ratio; 2284 u8 max_ps_percent; 2285 bool disable_uvd_power_tune; 2286 int ret; 2287 2288 if (ni_pi->enable_power_containment == false) 2289 return 0; 2290 2291 if (state->performance_level_count == 0) 2292 return -EINVAL; 2293 2294 if (smc_state->levelCount != state->performance_level_count) 2295 return -EINVAL; 2296 2297 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2298 2299 smc_state->levels[0].dpm2.MaxPS = 0; 2300 smc_state->levels[0].dpm2.NearTDPDec = 0; 2301 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2302 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2303 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2304 2305 for (i = 1; i < state->performance_level_count; i++) { 2306 prev_sclk = state->performance_levels[i-1].sclk; 2307 max_sclk = state->performance_levels[i].sclk; 2308 if (i == 1) 2309 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2310 else 2311 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2312 2313 if (prev_sclk > max_sclk) 2314 return -EINVAL; 2315 2316 if ((max_ps_percent == 0) || 2317 (prev_sclk == max_sclk) || 2318 disable_uvd_power_tune) { 2319 min_sclk = max_sclk; 2320 } else if (i == 1) { 2321 min_sclk = prev_sclk; 2322 } else { 2323 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2324 } 2325 2326 if (min_sclk < state->performance_levels[0].sclk) 2327 min_sclk = state->performance_levels[0].sclk; 2328 2329 if (min_sclk == 0) 2330 return -EINVAL; 2331 2332 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2333 state->performance_levels[i-1].vddc, &vddc); 2334 if (ret) 2335 return ret; 2336 2337 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2338 if (ret) 2339 return ret; 2340 2341 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2342 state->performance_levels[i].vddc, &vddc); 2343 if (ret) 2344 return ret; 2345 2346 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2347 if (ret) 2348 return ret; 2349 2350 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2351 prev_std_vddc, curr_std_vddc); 2352 2353 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2354 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2355 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2356 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2357 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2358 } 2359 2360 return 0; 2361} 2362 2363static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2364 struct radeon_ps *radeon_state, 2365 SISLANDS_SMC_SWSTATE *smc_state) 2366{ 2367 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2368 struct ni_ps *state = ni_get_ps(radeon_state); 2369 u32 sq_power_throttle, sq_power_throttle2; 2370 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2371 int i; 2372 2373 if (state->performance_level_count == 0) 2374 return -EINVAL; 2375 2376 if (smc_state->levelCount != state->performance_level_count) 2377 return -EINVAL; 2378 2379 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2380 return -EINVAL; 2381 2382 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2383 enable_sq_ramping = false; 2384 2385 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2386 enable_sq_ramping = false; 2387 2388 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2389 enable_sq_ramping = false; 2390 2391 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2392 enable_sq_ramping = false; 2393 2394 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2395 enable_sq_ramping = false; 2396 2397 for (i = 0; i < state->performance_level_count; i++) { 2398 sq_power_throttle = 0; 2399 sq_power_throttle2 = 0; 2400 2401 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2402 enable_sq_ramping) { 2403 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2404 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2405 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2406 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2407 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2408 } else { 2409 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2410 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2411 } 2412 2413 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2414 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2415 } 2416 2417 return 0; 2418} 2419 2420static int si_enable_power_containment(struct radeon_device *rdev, 2421 struct radeon_ps *radeon_new_state, 2422 bool enable) 2423{ 2424 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2425 PPSMC_Result smc_result; 2426 int ret = 0; 2427 2428 if (ni_pi->enable_power_containment) { 2429 if (enable) { 2430 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2431 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2432 if (smc_result != PPSMC_Result_OK) { 2433 ret = -EINVAL; 2434 ni_pi->pc_enabled = false; 2435 } else { 2436 ni_pi->pc_enabled = true; 2437 } 2438 } 2439 } else { 2440 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2441 if (smc_result != PPSMC_Result_OK) 2442 ret = -EINVAL; 2443 ni_pi->pc_enabled = false; 2444 } 2445 } 2446 2447 return ret; 2448} 2449 2450static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2451{ 2452 struct si_power_info *si_pi = si_get_pi(rdev); 2453 int ret = 0; 2454 struct si_dte_data *dte_data = &si_pi->dte_data; 2455 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2456 u32 table_size; 2457 u8 tdep_count; 2458 u32 i; 2459 2460 if (dte_data == NULL) 2461 si_pi->enable_dte = false; 2462 2463 if (si_pi->enable_dte == false) 2464 return 0; 2465 2466 if (dte_data->k <= 0) 2467 return -EINVAL; 2468 2469 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2470 if (dte_tables == NULL) { 2471 si_pi->enable_dte = false; 2472 return -ENOMEM; 2473 } 2474 2475 table_size = dte_data->k; 2476 2477 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2478 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2479 2480 tdep_count = dte_data->tdep_count; 2481 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2482 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2483 2484 dte_tables->K = cpu_to_be32(table_size); 2485 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2486 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2487 dte_tables->WindowSize = dte_data->window_size; 2488 dte_tables->temp_select = dte_data->temp_select; 2489 dte_tables->DTE_mode = dte_data->dte_mode; 2490 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2491 2492 if (tdep_count > 0) 2493 table_size--; 2494 2495 for (i = 0; i < table_size; i++) { 2496 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2497 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2498 } 2499 2500 dte_tables->Tdep_count = tdep_count; 2501 2502 for (i = 0; i < (u32)tdep_count; i++) { 2503 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2504 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2505 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2506 } 2507 2508 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2509 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2510 kfree(dte_tables); 2511 2512 return ret; 2513} 2514 2515static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2516 u16 *max, u16 *min) 2517{ 2518 struct si_power_info *si_pi = si_get_pi(rdev); 2519 struct radeon_cac_leakage_table *table = 2520 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2521 u32 i; 2522 u32 v0_loadline; 2523 2524 2525 if (table == NULL) 2526 return -EINVAL; 2527 2528 *max = 0; 2529 *min = 0xFFFF; 2530 2531 for (i = 0; i < table->count; i++) { 2532 if (table->entries[i].vddc > *max) 2533 *max = table->entries[i].vddc; 2534 if (table->entries[i].vddc < *min) 2535 *min = table->entries[i].vddc; 2536 } 2537 2538 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2539 return -EINVAL; 2540 2541 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2542 2543 if (v0_loadline > 0xFFFFUL) 2544 return -EINVAL; 2545 2546 *min = (u16)v0_loadline; 2547 2548 if ((*min > *max) || (*max == 0) || (*min == 0)) 2549 return -EINVAL; 2550 2551 return 0; 2552} 2553 2554static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2555{ 2556 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2557 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2558} 2559 2560static int si_init_dte_leakage_table(struct radeon_device *rdev, 2561 PP_SIslands_CacConfig *cac_tables, 2562 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2563 u16 t0, u16 t_step) 2564{ 2565 struct si_power_info *si_pi = si_get_pi(rdev); 2566 u32 leakage; 2567 unsigned int i, j; 2568 s32 t; 2569 u32 smc_leakage; 2570 u32 scaling_factor; 2571 u16 voltage; 2572 2573 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2574 2575 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2576 t = (1000 * (i * t_step + t0)); 2577 2578 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2579 voltage = vddc_max - (vddc_step * j); 2580 2581 si_calculate_leakage_for_v_and_t(rdev, 2582 &si_pi->powertune_data->leakage_coefficients, 2583 voltage, 2584 t, 2585 si_pi->dyn_powertune_data.cac_leakage, 2586 &leakage); 2587 2588 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2589 2590 if (smc_leakage > 0xFFFF) 2591 smc_leakage = 0xFFFF; 2592 2593 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2594 cpu_to_be16((u16)smc_leakage); 2595 } 2596 } 2597 return 0; 2598} 2599 2600static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2601 PP_SIslands_CacConfig *cac_tables, 2602 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2603{ 2604 struct si_power_info *si_pi = si_get_pi(rdev); 2605 u32 leakage; 2606 unsigned int i, j; 2607 u32 smc_leakage; 2608 u32 scaling_factor; 2609 u16 voltage; 2610 2611 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2612 2613 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2614 voltage = vddc_max - (vddc_step * j); 2615 2616 si_calculate_leakage_for_v(rdev, 2617 &si_pi->powertune_data->leakage_coefficients, 2618 si_pi->powertune_data->fixed_kt, 2619 voltage, 2620 si_pi->dyn_powertune_data.cac_leakage, 2621 &leakage); 2622 2623 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2624 2625 if (smc_leakage > 0xFFFF) 2626 smc_leakage = 0xFFFF; 2627 2628 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2629 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2630 cpu_to_be16((u16)smc_leakage); 2631 } 2632 return 0; 2633} 2634 2635static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2636{ 2637 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2638 struct si_power_info *si_pi = si_get_pi(rdev); 2639 PP_SIslands_CacConfig *cac_tables = NULL; 2640 u16 vddc_max, vddc_min, vddc_step; 2641 u16 t0, t_step; 2642 u32 load_line_slope, reg; 2643 int ret = 0; 2644 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2645 2646 if (ni_pi->enable_cac == false) 2647 return 0; 2648 2649 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2650 if (!cac_tables) 2651 return -ENOMEM; 2652 2653 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2654 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2655 WREG32(CG_CAC_CTRL, reg); 2656 2657 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2658 si_pi->dyn_powertune_data.dc_pwr_value = 2659 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2660 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2661 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2662 2663 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2664 2665 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2666 if (ret) 2667 goto done_free; 2668 2669 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2670 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2671 t_step = 4; 2672 t0 = 60; 2673 2674 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2675 ret = si_init_dte_leakage_table(rdev, cac_tables, 2676 vddc_max, vddc_min, vddc_step, 2677 t0, t_step); 2678 else 2679 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2680 vddc_max, vddc_min, vddc_step); 2681 if (ret) 2682 goto done_free; 2683 2684 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2685 2686 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2687 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2688 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2689 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2690 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2691 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2692 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2693 cac_tables->calculation_repeats = cpu_to_be32(2); 2694 cac_tables->dc_cac = cpu_to_be32(0); 2695 cac_tables->log2_PG_LKG_SCALE = 12; 2696 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2697 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2698 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2699 2700 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2701 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2702 2703 if (ret) 2704 goto done_free; 2705 2706 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2707 2708done_free: 2709 if (ret) { 2710 ni_pi->enable_cac = false; 2711 ni_pi->enable_power_containment = false; 2712 } 2713 2714 kfree(cac_tables); 2715 2716 return 0; 2717} 2718 2719static int si_program_cac_config_registers(struct radeon_device *rdev, 2720 const struct si_cac_config_reg *cac_config_regs) 2721{ 2722 const struct si_cac_config_reg *config_regs = cac_config_regs; 2723 u32 data = 0, offset; 2724 2725 if (!config_regs) 2726 return -EINVAL; 2727 2728 while (config_regs->offset != 0xFFFFFFFF) { 2729 switch (config_regs->type) { 2730 case SISLANDS_CACCONFIG_CGIND: 2731 offset = SMC_CG_IND_START + config_regs->offset; 2732 if (offset < SMC_CG_IND_END) 2733 data = RREG32_SMC(offset); 2734 break; 2735 default: 2736 data = RREG32(config_regs->offset << 2); 2737 break; 2738 } 2739 2740 data &= ~config_regs->mask; 2741 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2742 2743 switch (config_regs->type) { 2744 case SISLANDS_CACCONFIG_CGIND: 2745 offset = SMC_CG_IND_START + config_regs->offset; 2746 if (offset < SMC_CG_IND_END) 2747 WREG32_SMC(offset, data); 2748 break; 2749 default: 2750 WREG32(config_regs->offset << 2, data); 2751 break; 2752 } 2753 config_regs++; 2754 } 2755 return 0; 2756} 2757 2758static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2759{ 2760 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2761 struct si_power_info *si_pi = si_get_pi(rdev); 2762 int ret; 2763 2764 if ((ni_pi->enable_cac == false) || 2765 (ni_pi->cac_configuration_required == false)) 2766 return 0; 2767 2768 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2769 if (ret) 2770 return ret; 2771 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2772 if (ret) 2773 return ret; 2774 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2775 if (ret) 2776 return ret; 2777 2778 return 0; 2779} 2780 2781static int si_enable_smc_cac(struct radeon_device *rdev, 2782 struct radeon_ps *radeon_new_state, 2783 bool enable) 2784{ 2785 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2786 struct si_power_info *si_pi = si_get_pi(rdev); 2787 PPSMC_Result smc_result; 2788 int ret = 0; 2789 2790 if (ni_pi->enable_cac) { 2791 if (enable) { 2792 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2793 if (ni_pi->support_cac_long_term_average) { 2794 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2795 if (smc_result != PPSMC_Result_OK) 2796 ni_pi->support_cac_long_term_average = false; 2797 } 2798 2799 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2800 if (smc_result != PPSMC_Result_OK) { 2801 ret = -EINVAL; 2802 ni_pi->cac_enabled = false; 2803 } else { 2804 ni_pi->cac_enabled = true; 2805 } 2806 2807 if (si_pi->enable_dte) { 2808 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2809 if (smc_result != PPSMC_Result_OK) 2810 ret = -EINVAL; 2811 } 2812 } 2813 } else if (ni_pi->cac_enabled) { 2814 if (si_pi->enable_dte) 2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2816 2817 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2818 2819 ni_pi->cac_enabled = false; 2820 2821 if (ni_pi->support_cac_long_term_average) 2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2823 } 2824 } 2825 return ret; 2826} 2827 2828static int si_init_smc_spll_table(struct radeon_device *rdev) 2829{ 2830 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2831 struct si_power_info *si_pi = si_get_pi(rdev); 2832 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2833 SISLANDS_SMC_SCLK_VALUE sclk_params; 2834 u32 fb_div, p_div; 2835 u32 clk_s, clk_v; 2836 u32 sclk = 0; 2837 int ret = 0; 2838 u32 tmp; 2839 int i; 2840 2841 if (si_pi->spll_table_start == 0) 2842 return -EINVAL; 2843 2844 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2845 if (spll_table == NULL) 2846 return -ENOMEM; 2847 2848 for (i = 0; i < 256; i++) { 2849 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2850 if (ret) 2851 break; 2852 2853 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2854 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2855 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2856 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2857 2858 fb_div &= ~0x00001FFF; 2859 fb_div >>= 1; 2860 clk_v >>= 6; 2861 2862 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2863 ret = -EINVAL; 2864 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2865 ret = -EINVAL; 2866 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2867 ret = -EINVAL; 2868 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2869 ret = -EINVAL; 2870 2871 if (ret) 2872 break; 2873 2874 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2875 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2876 spll_table->freq[i] = cpu_to_be32(tmp); 2877 2878 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2879 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2880 spll_table->ss[i] = cpu_to_be32(tmp); 2881 2882 sclk += 512; 2883 } 2884 2885 2886 if (!ret) 2887 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2888 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2889 si_pi->sram_end); 2890 2891 if (ret) 2892 ni_pi->enable_power_containment = false; 2893 2894 kfree(spll_table); 2895 2896 return ret; 2897} 2898 2899static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2900 struct radeon_ps *rps) 2901{ 2902 struct ni_ps *ps = ni_get_ps(rps); 2903 struct radeon_clock_and_voltage_limits *max_limits; 2904 bool disable_mclk_switching; 2905 u32 mclk, sclk; 2906 u16 vddc, vddci; 2907 int i; 2908 2909 if (rdev->pm.dpm.new_active_crtc_count > 1) 2910 disable_mclk_switching = true; 2911 else 2912 disable_mclk_switching = false; 2913 2914 if (rdev->pm.dpm.ac_power) 2915 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2916 else 2917 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2918 2919 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2920 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2921 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2922 } 2923 if (rdev->pm.dpm.ac_power == false) { 2924 for (i = 0; i < ps->performance_level_count; i++) { 2925 if (ps->performance_levels[i].mclk > max_limits->mclk) 2926 ps->performance_levels[i].mclk = max_limits->mclk; 2927 if (ps->performance_levels[i].sclk > max_limits->sclk) 2928 ps->performance_levels[i].sclk = max_limits->sclk; 2929 if (ps->performance_levels[i].vddc > max_limits->vddc) 2930 ps->performance_levels[i].vddc = max_limits->vddc; 2931 if (ps->performance_levels[i].vddci > max_limits->vddci) 2932 ps->performance_levels[i].vddci = max_limits->vddci; 2933 } 2934 } 2935 2936 /* XXX validate the min clocks required for display */ 2937 2938 if (disable_mclk_switching) { 2939 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2940 sclk = ps->performance_levels[0].sclk; 2941 vddc = ps->performance_levels[0].vddc; 2942 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2943 } else { 2944 sclk = ps->performance_levels[0].sclk; 2945 mclk = ps->performance_levels[0].mclk; 2946 vddc = ps->performance_levels[0].vddc; 2947 vddci = ps->performance_levels[0].vddci; 2948 } 2949 2950 /* adjusted low state */ 2951 ps->performance_levels[0].sclk = sclk; 2952 ps->performance_levels[0].mclk = mclk; 2953 ps->performance_levels[0].vddc = vddc; 2954 ps->performance_levels[0].vddci = vddci; 2955 2956 for (i = 1; i < ps->performance_level_count; i++) { 2957 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2958 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2959 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2960 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2961 } 2962 2963 if (disable_mclk_switching) { 2964 mclk = ps->performance_levels[0].mclk; 2965 for (i = 1; i < ps->performance_level_count; i++) { 2966 if (mclk < ps->performance_levels[i].mclk) 2967 mclk = ps->performance_levels[i].mclk; 2968 } 2969 for (i = 0; i < ps->performance_level_count; i++) { 2970 ps->performance_levels[i].mclk = mclk; 2971 ps->performance_levels[i].vddci = vddci; 2972 } 2973 } else { 2974 for (i = 1; i < ps->performance_level_count; i++) { 2975 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 2976 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 2977 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 2978 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 2979 } 2980 } 2981 2982 for (i = 0; i < ps->performance_level_count; i++) 2983 btc_adjust_clock_combinations(rdev, max_limits, 2984 &ps->performance_levels[i]); 2985 2986 for (i = 0; i < ps->performance_level_count; i++) { 2987 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2988 ps->performance_levels[i].sclk, 2989 max_limits->vddc, &ps->performance_levels[i].vddc); 2990 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2991 ps->performance_levels[i].mclk, 2992 max_limits->vddci, &ps->performance_levels[i].vddci); 2993 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2994 ps->performance_levels[i].mclk, 2995 max_limits->vddc, &ps->performance_levels[i].vddc); 2996 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 2997 rdev->clock.current_dispclk, 2998 max_limits->vddc, &ps->performance_levels[i].vddc); 2999 } 3000 3001 for (i = 0; i < ps->performance_level_count; i++) { 3002 btc_apply_voltage_delta_rules(rdev, 3003 max_limits->vddc, max_limits->vddci, 3004 &ps->performance_levels[i].vddc, 3005 &ps->performance_levels[i].vddci); 3006 } 3007 3008 ps->dc_compatible = true; 3009 for (i = 0; i < ps->performance_level_count; i++) { 3010 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3011 ps->dc_compatible = false; 3012 } 3013 3014} 3015 3016#if 0 3017static int si_read_smc_soft_register(struct radeon_device *rdev, 3018 u16 reg_offset, u32 *value) 3019{ 3020 struct si_power_info *si_pi = si_get_pi(rdev); 3021 3022 return si_read_smc_sram_dword(rdev, 3023 si_pi->soft_regs_start + reg_offset, value, 3024 si_pi->sram_end); 3025} 3026#endif 3027 3028static int si_write_smc_soft_register(struct radeon_device *rdev, 3029 u16 reg_offset, u32 value) 3030{ 3031 struct si_power_info *si_pi = si_get_pi(rdev); 3032 3033 return si_write_smc_sram_dword(rdev, 3034 si_pi->soft_regs_start + reg_offset, 3035 value, si_pi->sram_end); 3036} 3037 3038static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3039{ 3040 bool ret = false; 3041 u32 tmp, width, row, column, bank, density; 3042 bool is_memory_gddr5, is_special; 3043 3044 tmp = RREG32(MC_SEQ_MISC0); 3045 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3046 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3047 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3048 3049 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3050 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3051 3052 tmp = RREG32(MC_ARB_RAMCFG); 3053 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3054 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3055 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3056 3057 density = (1 << (row + column - 20 + bank)) * width; 3058 3059 if ((rdev->pdev->device == 0x6819) && 3060 is_memory_gddr5 && is_special && (density == 0x400)) 3061 ret = true; 3062 3063 return ret; 3064} 3065 3066static void si_get_leakage_vddc(struct radeon_device *rdev) 3067{ 3068 struct si_power_info *si_pi = si_get_pi(rdev); 3069 u16 vddc, count = 0; 3070 int i, ret; 3071 3072 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3073 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3074 3075 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3076 si_pi->leakage_voltage.entries[count].voltage = vddc; 3077 si_pi->leakage_voltage.entries[count].leakage_index = 3078 SISLANDS_LEAKAGE_INDEX0 + i; 3079 count++; 3080 } 3081 } 3082 si_pi->leakage_voltage.count = count; 3083} 3084 3085static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3086 u32 index, u16 *leakage_voltage) 3087{ 3088 struct si_power_info *si_pi = si_get_pi(rdev); 3089 int i; 3090 3091 if (leakage_voltage == NULL) 3092 return -EINVAL; 3093 3094 if ((index & 0xff00) != 0xff00) 3095 return -EINVAL; 3096 3097 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3098 return -EINVAL; 3099 3100 if (index < SISLANDS_LEAKAGE_INDEX0) 3101 return -EINVAL; 3102 3103 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3104 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3105 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3106 return 0; 3107 } 3108 } 3109 return -EAGAIN; 3110} 3111 3112static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3113{ 3114 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3115 bool want_thermal_protection; 3116 enum radeon_dpm_event_src dpm_event_src; 3117 3118 switch (sources) { 3119 case 0: 3120 default: 3121 want_thermal_protection = false; 3122 break; 3123 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3124 want_thermal_protection = true; 3125 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3126 break; 3127 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3128 want_thermal_protection = true; 3129 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3130 break; 3131 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3132 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3133 want_thermal_protection = true; 3134 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3135 break; 3136 } 3137 3138 if (want_thermal_protection) { 3139 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3140 if (pi->thermal_protection) 3141 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3142 } else { 3143 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3144 } 3145} 3146 3147static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3148 enum radeon_dpm_auto_throttle_src source, 3149 bool enable) 3150{ 3151 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3152 3153 if (enable) { 3154 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3155 pi->active_auto_throttle_sources |= 1 << source; 3156 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3157 } 3158 } else { 3159 if (pi->active_auto_throttle_sources & (1 << source)) { 3160 pi->active_auto_throttle_sources &= ~(1 << source); 3161 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3162 } 3163 } 3164} 3165 3166static void si_start_dpm(struct radeon_device *rdev) 3167{ 3168 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3169} 3170 3171static void si_stop_dpm(struct radeon_device *rdev) 3172{ 3173 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3174} 3175 3176static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3177{ 3178 if (enable) 3179 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3180 else 3181 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3182 3183} 3184 3185#if 0 3186static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3187 u32 thermal_level) 3188{ 3189 PPSMC_Result ret; 3190 3191 if (thermal_level == 0) { 3192 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3193 if (ret == PPSMC_Result_OK) 3194 return 0; 3195 else 3196 return -EINVAL; 3197 } 3198 return 0; 3199} 3200 3201static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3202{ 3203 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3204} 3205#endif 3206 3207#if 0 3208static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3209{ 3210 if (ac_power) 3211 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3212 0 : -EINVAL; 3213 3214 return 0; 3215} 3216#endif 3217 3218static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3219 PPSMC_Msg msg, u32 parameter) 3220{ 3221 WREG32(SMC_SCRATCH0, parameter); 3222 return si_send_msg_to_smc(rdev, msg); 3223} 3224 3225static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3226{ 3227 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3228 return -EINVAL; 3229 3230 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3231 0 : -EINVAL; 3232} 3233 3234#if 0 3235static int si_unrestrict_performance_levels_after_switch(struct radeon_device *rdev) 3236{ 3237 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3238 return -EINVAL; 3239 3240 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) == PPSMC_Result_OK) ? 3241 0 : -EINVAL; 3242} 3243#endif 3244 3245static int si_set_boot_state(struct radeon_device *rdev) 3246{ 3247 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3248 0 : -EINVAL; 3249} 3250 3251static int si_set_sw_state(struct radeon_device *rdev) 3252{ 3253 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3254 0 : -EINVAL; 3255} 3256 3257static int si_halt_smc(struct radeon_device *rdev) 3258{ 3259 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3260 return -EINVAL; 3261 3262 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3263 0 : -EINVAL; 3264} 3265 3266static int si_resume_smc(struct radeon_device *rdev) 3267{ 3268 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3269 return -EINVAL; 3270 3271 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3272 0 : -EINVAL; 3273} 3274 3275static void si_dpm_start_smc(struct radeon_device *rdev) 3276{ 3277 si_program_jump_on_start(rdev); 3278 si_start_smc(rdev); 3279 si_start_smc_clock(rdev); 3280} 3281 3282static void si_dpm_stop_smc(struct radeon_device *rdev) 3283{ 3284 si_reset_smc(rdev); 3285 si_stop_smc_clock(rdev); 3286} 3287 3288static int si_process_firmware_header(struct radeon_device *rdev) 3289{ 3290 struct si_power_info *si_pi = si_get_pi(rdev); 3291 u32 tmp; 3292 int ret; 3293 3294 ret = si_read_smc_sram_dword(rdev, 3295 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3296 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3297 &tmp, si_pi->sram_end); 3298 if (ret) 3299 return ret; 3300 3301 si_pi->state_table_start = tmp; 3302 3303 ret = si_read_smc_sram_dword(rdev, 3304 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3305 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3306 &tmp, si_pi->sram_end); 3307 if (ret) 3308 return ret; 3309 3310 si_pi->soft_regs_start = tmp; 3311 3312 ret = si_read_smc_sram_dword(rdev, 3313 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3314 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3315 &tmp, si_pi->sram_end); 3316 if (ret) 3317 return ret; 3318 3319 si_pi->mc_reg_table_start = tmp; 3320 3321 ret = si_read_smc_sram_dword(rdev, 3322 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3323 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3324 &tmp, si_pi->sram_end); 3325 if (ret) 3326 return ret; 3327 3328 si_pi->arb_table_start = tmp; 3329 3330 ret = si_read_smc_sram_dword(rdev, 3331 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3332 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3333 &tmp, si_pi->sram_end); 3334 if (ret) 3335 return ret; 3336 3337 si_pi->cac_table_start = tmp; 3338 3339 ret = si_read_smc_sram_dword(rdev, 3340 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3341 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3342 &tmp, si_pi->sram_end); 3343 if (ret) 3344 return ret; 3345 3346 si_pi->dte_table_start = tmp; 3347 3348 ret = si_read_smc_sram_dword(rdev, 3349 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3350 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3351 &tmp, si_pi->sram_end); 3352 if (ret) 3353 return ret; 3354 3355 si_pi->spll_table_start = tmp; 3356 3357 ret = si_read_smc_sram_dword(rdev, 3358 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3359 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3360 &tmp, si_pi->sram_end); 3361 if (ret) 3362 return ret; 3363 3364 si_pi->papm_cfg_table_start = tmp; 3365 3366 return ret; 3367} 3368 3369static void si_read_clock_registers(struct radeon_device *rdev) 3370{ 3371 struct si_power_info *si_pi = si_get_pi(rdev); 3372 3373 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3374 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3375 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3376 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3377 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3378 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3379 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3380 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3381 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3382 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3383 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3384 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3385 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3386 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3387 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3388} 3389 3390static void si_enable_thermal_protection(struct radeon_device *rdev, 3391 bool enable) 3392{ 3393 if (enable) 3394 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3395 else 3396 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3397} 3398 3399static void si_enable_acpi_power_management(struct radeon_device *rdev) 3400{ 3401 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3402} 3403 3404#if 0 3405static int si_enter_ulp_state(struct radeon_device *rdev) 3406{ 3407 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3408 3409 udelay(25000); 3410 3411 return 0; 3412} 3413 3414static int si_exit_ulp_state(struct radeon_device *rdev) 3415{ 3416 int i; 3417 3418 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3419 3420 udelay(7000); 3421 3422 for (i = 0; i < rdev->usec_timeout; i++) { 3423 if (RREG32(SMC_RESP_0) == 1) 3424 break; 3425 udelay(1000); 3426 } 3427 3428 return 0; 3429} 3430#endif 3431 3432static int si_notify_smc_display_change(struct radeon_device *rdev, 3433 bool has_display) 3434{ 3435 PPSMC_Msg msg = has_display ? 3436 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3437 3438 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3439 0 : -EINVAL; 3440} 3441 3442static void si_program_response_times(struct radeon_device *rdev) 3443{ 3444 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3445 u32 vddc_dly, acpi_dly, vbi_dly; 3446 u32 reference_clock; 3447 3448 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3449 3450 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3451 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3452 3453 if (voltage_response_time == 0) 3454 voltage_response_time = 1000; 3455 3456 acpi_delay_time = 15000; 3457 vbi_time_out = 100000; 3458 3459 reference_clock = radeon_get_xclk(rdev); 3460 3461 vddc_dly = (voltage_response_time * reference_clock) / 100; 3462 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3463 vbi_dly = (vbi_time_out * reference_clock) / 100; 3464 3465 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3466 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3467 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3468 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3469} 3470 3471static void si_program_ds_registers(struct radeon_device *rdev) 3472{ 3473 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3474 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3475 3476 if (eg_pi->sclk_deep_sleep) { 3477 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3478 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3479 ~AUTOSCALE_ON_SS_CLEAR); 3480 } 3481} 3482 3483static void si_program_display_gap(struct radeon_device *rdev) 3484{ 3485 u32 tmp, pipe; 3486 int i; 3487 3488 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3489 if (rdev->pm.dpm.new_active_crtc_count > 0) 3490 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3491 else 3492 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3493 3494 if (rdev->pm.dpm.new_active_crtc_count > 1) 3495 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3496 else 3497 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3498 3499 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3500 3501 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3502 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3503 3504 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3505 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3506 /* find the first active crtc */ 3507 for (i = 0; i < rdev->num_crtc; i++) { 3508 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3509 break; 3510 } 3511 if (i == rdev->num_crtc) 3512 pipe = 0; 3513 else 3514 pipe = i; 3515 3516 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3517 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3518 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3519 } 3520 3521 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3522} 3523 3524static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3525{ 3526 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3527 3528 if (enable) { 3529 if (pi->sclk_ss) 3530 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3531 } else { 3532 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3533 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3534 } 3535} 3536 3537static void si_setup_bsp(struct radeon_device *rdev) 3538{ 3539 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3540 u32 xclk = radeon_get_xclk(rdev); 3541 3542 r600_calculate_u_and_p(pi->asi, 3543 xclk, 3544 16, 3545 &pi->bsp, 3546 &pi->bsu); 3547 3548 r600_calculate_u_and_p(pi->pasi, 3549 xclk, 3550 16, 3551 &pi->pbsp, 3552 &pi->pbsu); 3553 3554 3555 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3556 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3557 3558 WREG32(CG_BSP, pi->dsp); 3559} 3560 3561static void si_program_git(struct radeon_device *rdev) 3562{ 3563 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3564} 3565 3566static void si_program_tp(struct radeon_device *rdev) 3567{ 3568 int i; 3569 enum r600_td td = R600_TD_DFLT; 3570 3571 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3572 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3573 3574 if (td == R600_TD_AUTO) 3575 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3576 else 3577 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3578 3579 if (td == R600_TD_UP) 3580 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3581 3582 if (td == R600_TD_DOWN) 3583 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3584} 3585 3586static void si_program_tpp(struct radeon_device *rdev) 3587{ 3588 WREG32(CG_TPC, R600_TPC_DFLT); 3589} 3590 3591static void si_program_sstp(struct radeon_device *rdev) 3592{ 3593 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3594} 3595 3596static void si_enable_display_gap(struct radeon_device *rdev) 3597{ 3598 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3599 3600 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3601 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) | 3602 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3603 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3604} 3605 3606static void si_program_vc(struct radeon_device *rdev) 3607{ 3608 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3609 3610 WREG32(CG_FTV, pi->vrc); 3611} 3612 3613static void si_clear_vc(struct radeon_device *rdev) 3614{ 3615 WREG32(CG_FTV, 0); 3616} 3617 3618static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3619{ 3620 u8 mc_para_index; 3621 3622 if (memory_clock < 10000) 3623 mc_para_index = 0; 3624 else if (memory_clock >= 80000) 3625 mc_para_index = 0x0f; 3626 else 3627 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3628 return mc_para_index; 3629} 3630 3631static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3632{ 3633 u8 mc_para_index; 3634 3635 if (strobe_mode) { 3636 if (memory_clock < 12500) 3637 mc_para_index = 0x00; 3638 else if (memory_clock > 47500) 3639 mc_para_index = 0x0f; 3640 else 3641 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3642 } else { 3643 if (memory_clock < 65000) 3644 mc_para_index = 0x00; 3645 else if (memory_clock > 135000) 3646 mc_para_index = 0x0f; 3647 else 3648 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3649 } 3650 return mc_para_index; 3651} 3652 3653static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3654{ 3655 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3656 bool strobe_mode = false; 3657 u8 result = 0; 3658 3659 if (mclk <= pi->mclk_strobe_mode_threshold) 3660 strobe_mode = true; 3661 3662 if (pi->mem_gddr5) 3663 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3664 else 3665 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3666 3667 if (strobe_mode) 3668 result |= SISLANDS_SMC_STROBE_ENABLE; 3669 3670 return result; 3671} 3672 3673static int si_upload_firmware(struct radeon_device *rdev) 3674{ 3675 struct si_power_info *si_pi = si_get_pi(rdev); 3676 int ret; 3677 3678 si_reset_smc(rdev); 3679 si_stop_smc_clock(rdev); 3680 3681 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3682 3683 return ret; 3684} 3685 3686static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3687 const struct atom_voltage_table *table, 3688 const struct radeon_phase_shedding_limits_table *limits) 3689{ 3690 u32 data, num_bits, num_levels; 3691 3692 if ((table == NULL) || (limits == NULL)) 3693 return false; 3694 3695 data = table->mask_low; 3696 3697 num_bits = hweight32(data); 3698 3699 if (num_bits == 0) 3700 return false; 3701 3702 num_levels = (1 << num_bits); 3703 3704 if (table->count != num_levels) 3705 return false; 3706 3707 if (limits->count != (num_levels - 1)) 3708 return false; 3709 3710 return true; 3711} 3712 3713static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3714 struct atom_voltage_table *voltage_table) 3715{ 3716 unsigned int i, diff; 3717 3718 if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS) 3719 return; 3720 3721 diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS; 3722 3723 for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++) 3724 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3725 3726 voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS; 3727} 3728 3729static int si_construct_voltage_tables(struct radeon_device *rdev) 3730{ 3731 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3732 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3733 struct si_power_info *si_pi = si_get_pi(rdev); 3734 int ret; 3735 3736 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3737 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3738 if (ret) 3739 return ret; 3740 3741 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3742 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table); 3743 3744 if (eg_pi->vddci_control) { 3745 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3746 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3747 if (ret) 3748 return ret; 3749 3750 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3751 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table); 3752 } 3753 3754 if (pi->mvdd_control) { 3755 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3756 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3757 3758 if (ret) { 3759 pi->mvdd_control = false; 3760 return ret; 3761 } 3762 3763 if (si_pi->mvdd_voltage_table.count == 0) { 3764 pi->mvdd_control = false; 3765 return -EINVAL; 3766 } 3767 3768 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3769 si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table); 3770 } 3771 3772 if (si_pi->vddc_phase_shed_control) { 3773 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3774 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3775 if (ret) 3776 si_pi->vddc_phase_shed_control = false; 3777 3778 if ((si_pi->vddc_phase_shed_table.count == 0) || 3779 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3780 si_pi->vddc_phase_shed_control = false; 3781 } 3782 3783 return 0; 3784} 3785 3786static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3787 const struct atom_voltage_table *voltage_table, 3788 SISLANDS_SMC_STATETABLE *table) 3789{ 3790 unsigned int i; 3791 3792 for (i = 0; i < voltage_table->count; i++) 3793 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3794} 3795 3796static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3797 SISLANDS_SMC_STATETABLE *table) 3798{ 3799 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3800 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3801 struct si_power_info *si_pi = si_get_pi(rdev); 3802 u8 i; 3803 3804 if (eg_pi->vddc_voltage_table.count) { 3805 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3806 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3807 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3808 3809 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3810 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3811 table->maxVDDCIndexInPPTable = i; 3812 break; 3813 } 3814 } 3815 } 3816 3817 if (eg_pi->vddci_voltage_table.count) { 3818 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3819 3820 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3821 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3822 } 3823 3824 3825 if (si_pi->mvdd_voltage_table.count) { 3826 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3827 3828 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3829 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3830 } 3831 3832 if (si_pi->vddc_phase_shed_control) { 3833 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3834 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3835 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3836 3837 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3838 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3839 3840 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3841 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3842 } else { 3843 si_pi->vddc_phase_shed_control = false; 3844 } 3845 } 3846 3847 return 0; 3848} 3849 3850static int si_populate_voltage_value(struct radeon_device *rdev, 3851 const struct atom_voltage_table *table, 3852 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3853{ 3854 unsigned int i; 3855 3856 for (i = 0; i < table->count; i++) { 3857 if (value <= table->entries[i].value) { 3858 voltage->index = (u8)i; 3859 voltage->value = cpu_to_be16(table->entries[i].value); 3860 break; 3861 } 3862 } 3863 3864 if (i >= table->count) 3865 return -EINVAL; 3866 3867 return 0; 3868} 3869 3870static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3871 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3872{ 3873 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3874 struct si_power_info *si_pi = si_get_pi(rdev); 3875 3876 if (pi->mvdd_control) { 3877 if (mclk <= pi->mvdd_split_frequency) 3878 voltage->index = 0; 3879 else 3880 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3881 3882 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 3883 } 3884 return 0; 3885} 3886 3887static int si_get_std_voltage_value(struct radeon_device *rdev, 3888 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 3889 u16 *std_voltage) 3890{ 3891 u16 v_index; 3892 bool voltage_found = false; 3893 *std_voltage = be16_to_cpu(voltage->value); 3894 3895 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 3896 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 3897 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 3898 return -EINVAL; 3899 3900 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3901 if (be16_to_cpu(voltage->value) == 3902 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3903 voltage_found = true; 3904 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3905 *std_voltage = 3906 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3907 else 3908 *std_voltage = 3909 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3910 break; 3911 } 3912 } 3913 3914 if (!voltage_found) { 3915 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3916 if (be16_to_cpu(voltage->value) <= 3917 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3918 voltage_found = true; 3919 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3920 *std_voltage = 3921 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3922 else 3923 *std_voltage = 3924 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3925 break; 3926 } 3927 } 3928 } 3929 } else { 3930 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3931 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 3932 } 3933 } 3934 3935 return 0; 3936} 3937 3938static int si_populate_std_voltage_value(struct radeon_device *rdev, 3939 u16 value, u8 index, 3940 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3941{ 3942 voltage->index = index; 3943 voltage->value = cpu_to_be16(value); 3944 3945 return 0; 3946} 3947 3948static int si_populate_phase_shedding_value(struct radeon_device *rdev, 3949 const struct radeon_phase_shedding_limits_table *limits, 3950 u16 voltage, u32 sclk, u32 mclk, 3951 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 3952{ 3953 unsigned int i; 3954 3955 for (i = 0; i < limits->count; i++) { 3956 if ((voltage <= limits->entries[i].voltage) && 3957 (sclk <= limits->entries[i].sclk) && 3958 (mclk <= limits->entries[i].mclk)) 3959 break; 3960 } 3961 3962 smc_voltage->phase_settings = (u8)i; 3963 3964 return 0; 3965} 3966 3967static int si_init_arb_table_index(struct radeon_device *rdev) 3968{ 3969 struct si_power_info *si_pi = si_get_pi(rdev); 3970 u32 tmp; 3971 int ret; 3972 3973 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 3974 if (ret) 3975 return ret; 3976 3977 tmp &= 0x00FFFFFF; 3978 tmp |= MC_CG_ARB_FREQ_F1 << 24; 3979 3980 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 3981} 3982 3983static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 3984{ 3985 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 3986} 3987 3988static int si_reset_to_default(struct radeon_device *rdev) 3989{ 3990 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 3991 0 : -EINVAL; 3992} 3993 3994static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 3995{ 3996 struct si_power_info *si_pi = si_get_pi(rdev); 3997 u32 tmp; 3998 int ret; 3999 4000 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4001 &tmp, si_pi->sram_end); 4002 if (ret) 4003 return ret; 4004 4005 tmp = (tmp >> 24) & 0xff; 4006 4007 if (tmp == MC_CG_ARB_FREQ_F0) 4008 return 0; 4009 4010 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4011} 4012 4013static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4014 u32 engine_clock) 4015{ 4016 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4017 u32 dram_rows; 4018 u32 dram_refresh_rate; 4019 u32 mc_arb_rfsh_rate; 4020 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4021 4022 if (pi->mem_gddr5) 4023 dram_rows = 1 << (tmp + 10); 4024 else 4025 dram_rows = DDR3_DRAM_ROWS; 4026 4027 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4028 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4029 4030 return mc_arb_rfsh_rate; 4031} 4032 4033static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4034 struct rv7xx_pl *pl, 4035 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4036{ 4037 u32 dram_timing; 4038 u32 dram_timing2; 4039 u32 burst_time; 4040 4041 arb_regs->mc_arb_rfsh_rate = 4042 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4043 4044 radeon_atom_set_engine_dram_timings(rdev, 4045 pl->sclk, 4046 pl->mclk); 4047 4048 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4049 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4050 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4051 4052 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4053 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4054 arb_regs->mc_arb_burst_time = (u8)burst_time; 4055 4056 return 0; 4057} 4058 4059static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4060 struct radeon_ps *radeon_state, 4061 unsigned int first_arb_set) 4062{ 4063 struct si_power_info *si_pi = si_get_pi(rdev); 4064 struct ni_ps *state = ni_get_ps(radeon_state); 4065 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4066 int i, ret = 0; 4067 4068 for (i = 0; i < state->performance_level_count; i++) { 4069 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4070 if (ret) 4071 break; 4072 ret = si_copy_bytes_to_smc(rdev, 4073 si_pi->arb_table_start + 4074 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4075 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4076 (u8 *)&arb_regs, 4077 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4078 si_pi->sram_end); 4079 if (ret) 4080 break; 4081 } 4082 4083 return ret; 4084} 4085 4086static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4087 struct radeon_ps *radeon_new_state) 4088{ 4089 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4090 SISLANDS_DRIVER_STATE_ARB_INDEX); 4091} 4092 4093static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4094 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4095{ 4096 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4097 struct si_power_info *si_pi = si_get_pi(rdev); 4098 4099 if (pi->mvdd_control) 4100 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4101 si_pi->mvdd_bootup_value, voltage); 4102 4103 return 0; 4104} 4105 4106static int si_populate_smc_initial_state(struct radeon_device *rdev, 4107 struct radeon_ps *radeon_initial_state, 4108 SISLANDS_SMC_STATETABLE *table) 4109{ 4110 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4111 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4112 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4113 struct si_power_info *si_pi = si_get_pi(rdev); 4114 u32 reg; 4115 int ret; 4116 4117 table->initialState.levels[0].mclk.vDLL_CNTL = 4118 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4119 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4120 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4121 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4122 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4123 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4124 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4125 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4126 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4127 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4128 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4129 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4130 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4131 table->initialState.levels[0].mclk.vMPLL_SS = 4132 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4133 table->initialState.levels[0].mclk.vMPLL_SS2 = 4134 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4135 4136 table->initialState.levels[0].mclk.mclk_value = 4137 cpu_to_be32(initial_state->performance_levels[0].mclk); 4138 4139 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4140 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4141 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4142 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4143 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4144 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4145 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4146 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4147 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4148 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4149 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4150 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4151 4152 table->initialState.levels[0].sclk.sclk_value = 4153 cpu_to_be32(initial_state->performance_levels[0].sclk); 4154 4155 table->initialState.levels[0].arbRefreshState = 4156 SISLANDS_INITIAL_STATE_ARB_INDEX; 4157 4158 table->initialState.levels[0].ACIndex = 0; 4159 4160 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4161 initial_state->performance_levels[0].vddc, 4162 &table->initialState.levels[0].vddc); 4163 4164 if (!ret) { 4165 u16 std_vddc; 4166 4167 ret = si_get_std_voltage_value(rdev, 4168 &table->initialState.levels[0].vddc, 4169 &std_vddc); 4170 if (!ret) 4171 si_populate_std_voltage_value(rdev, std_vddc, 4172 table->initialState.levels[0].vddc.index, 4173 &table->initialState.levels[0].std_vddc); 4174 } 4175 4176 if (eg_pi->vddci_control) 4177 si_populate_voltage_value(rdev, 4178 &eg_pi->vddci_voltage_table, 4179 initial_state->performance_levels[0].vddci, 4180 &table->initialState.levels[0].vddci); 4181 4182 if (si_pi->vddc_phase_shed_control) 4183 si_populate_phase_shedding_value(rdev, 4184 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4185 initial_state->performance_levels[0].vddc, 4186 initial_state->performance_levels[0].sclk, 4187 initial_state->performance_levels[0].mclk, 4188 &table->initialState.levels[0].vddc); 4189 4190 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4191 4192 reg = CG_R(0xffff) | CG_L(0); 4193 table->initialState.levels[0].aT = cpu_to_be32(reg); 4194 4195 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4196 4197 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4198 4199 if (pi->mem_gddr5) { 4200 table->initialState.levels[0].strobeMode = 4201 si_get_strobe_mode_settings(rdev, 4202 initial_state->performance_levels[0].mclk); 4203 4204 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4205 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4206 else 4207 table->initialState.levels[0].mcFlags = 0; 4208 } 4209 4210 table->initialState.levelCount = 1; 4211 4212 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4213 4214 table->initialState.levels[0].dpm2.MaxPS = 0; 4215 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4216 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4217 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4218 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4219 4220 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4221 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4222 4223 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4224 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4225 4226 return 0; 4227} 4228 4229static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4230 SISLANDS_SMC_STATETABLE *table) 4231{ 4232 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4233 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4234 struct si_power_info *si_pi = si_get_pi(rdev); 4235 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4236 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4237 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4238 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4239 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4240 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4241 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4242 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4243 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4244 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4245 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4246 u32 reg; 4247 int ret; 4248 4249 table->ACPIState = table->initialState; 4250 4251 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4252 4253 if (pi->acpi_vddc) { 4254 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4255 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4256 if (!ret) { 4257 u16 std_vddc; 4258 4259 ret = si_get_std_voltage_value(rdev, 4260 &table->ACPIState.levels[0].vddc, &std_vddc); 4261 if (!ret) 4262 si_populate_std_voltage_value(rdev, std_vddc, 4263 table->ACPIState.levels[0].vddc.index, 4264 &table->ACPIState.levels[0].std_vddc); 4265 } 4266 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4267 4268 if (si_pi->vddc_phase_shed_control) { 4269 si_populate_phase_shedding_value(rdev, 4270 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4271 pi->acpi_vddc, 4272 0, 4273 0, 4274 &table->ACPIState.levels[0].vddc); 4275 } 4276 } else { 4277 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4278 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4279 if (!ret) { 4280 u16 std_vddc; 4281 4282 ret = si_get_std_voltage_value(rdev, 4283 &table->ACPIState.levels[0].vddc, &std_vddc); 4284 4285 if (!ret) 4286 si_populate_std_voltage_value(rdev, std_vddc, 4287 table->ACPIState.levels[0].vddc.index, 4288 &table->ACPIState.levels[0].std_vddc); 4289 } 4290 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4291 si_pi->sys_pcie_mask, 4292 si_pi->boot_pcie_gen, 4293 RADEON_PCIE_GEN1); 4294 4295 if (si_pi->vddc_phase_shed_control) 4296 si_populate_phase_shedding_value(rdev, 4297 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4298 pi->min_vddc_in_table, 4299 0, 4300 0, 4301 &table->ACPIState.levels[0].vddc); 4302 } 4303 4304 if (pi->acpi_vddc) { 4305 if (eg_pi->acpi_vddci) 4306 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4307 eg_pi->acpi_vddci, 4308 &table->ACPIState.levels[0].vddci); 4309 } 4310 4311 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4312 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4313 4314 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4315 4316 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4317 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4318 4319 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4320 cpu_to_be32(dll_cntl); 4321 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4322 cpu_to_be32(mclk_pwrmgt_cntl); 4323 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4324 cpu_to_be32(mpll_ad_func_cntl); 4325 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4326 cpu_to_be32(mpll_dq_func_cntl); 4327 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4328 cpu_to_be32(mpll_func_cntl); 4329 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4330 cpu_to_be32(mpll_func_cntl_1); 4331 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4332 cpu_to_be32(mpll_func_cntl_2); 4333 table->ACPIState.levels[0].mclk.vMPLL_SS = 4334 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4335 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4336 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4337 4338 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4339 cpu_to_be32(spll_func_cntl); 4340 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4341 cpu_to_be32(spll_func_cntl_2); 4342 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4343 cpu_to_be32(spll_func_cntl_3); 4344 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4345 cpu_to_be32(spll_func_cntl_4); 4346 4347 table->ACPIState.levels[0].mclk.mclk_value = 0; 4348 table->ACPIState.levels[0].sclk.sclk_value = 0; 4349 4350 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4351 4352 if (eg_pi->dynamic_ac_timing) 4353 table->ACPIState.levels[0].ACIndex = 0; 4354 4355 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4356 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4357 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4358 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4359 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4360 4361 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4362 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4363 4364 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4365 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4366 4367 return 0; 4368} 4369 4370static int si_populate_ulv_state(struct radeon_device *rdev, 4371 SISLANDS_SMC_SWSTATE *state) 4372{ 4373 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4374 struct si_power_info *si_pi = si_get_pi(rdev); 4375 struct si_ulv_param *ulv = &si_pi->ulv; 4376 u32 sclk_in_sr = 1350; /* ??? */ 4377 int ret; 4378 4379 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4380 &state->levels[0]); 4381 if (!ret) { 4382 if (eg_pi->sclk_deep_sleep) { 4383 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4384 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4385 else 4386 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4387 } 4388 if (ulv->one_pcie_lane_in_ulv) 4389 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4390 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4391 state->levels[0].ACIndex = 1; 4392 state->levels[0].std_vddc = state->levels[0].vddc; 4393 state->levelCount = 1; 4394 4395 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4396 } 4397 4398 return ret; 4399} 4400 4401static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4402{ 4403 struct si_power_info *si_pi = si_get_pi(rdev); 4404 struct si_ulv_param *ulv = &si_pi->ulv; 4405 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4406 int ret; 4407 4408 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4409 &arb_regs); 4410 if (ret) 4411 return ret; 4412 4413 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4414 ulv->volt_change_delay); 4415 4416 ret = si_copy_bytes_to_smc(rdev, 4417 si_pi->arb_table_start + 4418 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4419 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4420 (u8 *)&arb_regs, 4421 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4422 si_pi->sram_end); 4423 4424 return ret; 4425} 4426 4427static void si_get_mvdd_configuration(struct radeon_device *rdev) 4428{ 4429 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4430 4431 pi->mvdd_split_frequency = 30000; 4432} 4433 4434static int si_init_smc_table(struct radeon_device *rdev) 4435{ 4436 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4437 struct si_power_info *si_pi = si_get_pi(rdev); 4438 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4439 const struct si_ulv_param *ulv = &si_pi->ulv; 4440 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4441 int ret; 4442 u32 lane_width; 4443 u32 vr_hot_gpio; 4444 4445 si_populate_smc_voltage_tables(rdev, table); 4446 4447 switch (rdev->pm.int_thermal_type) { 4448 case THERMAL_TYPE_SI: 4449 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4450 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4451 break; 4452 case THERMAL_TYPE_NONE: 4453 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4454 break; 4455 default: 4456 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4457 break; 4458 } 4459 4460 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4461 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4462 4463 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4464 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4465 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4466 } 4467 4468 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4469 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4470 4471 if (pi->mem_gddr5) 4472 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4473 4474 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4475 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4476 4477 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4478 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4479 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4480 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4481 vr_hot_gpio); 4482 } 4483 4484 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4485 if (ret) 4486 return ret; 4487 4488 ret = si_populate_smc_acpi_state(rdev, table); 4489 if (ret) 4490 return ret; 4491 4492 table->driverState = table->initialState; 4493 4494 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4495 SISLANDS_INITIAL_STATE_ARB_INDEX); 4496 if (ret) 4497 return ret; 4498 4499 if (ulv->supported && ulv->pl.vddc) { 4500 ret = si_populate_ulv_state(rdev, &table->ULVState); 4501 if (ret) 4502 return ret; 4503 4504 ret = si_program_ulv_memory_timing_parameters(rdev); 4505 if (ret) 4506 return ret; 4507 4508 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4509 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4510 4511 lane_width = radeon_get_pcie_lanes(rdev); 4512 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4513 } else { 4514 table->ULVState = table->initialState; 4515 } 4516 4517 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4518 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4519 si_pi->sram_end); 4520} 4521 4522static int si_calculate_sclk_params(struct radeon_device *rdev, 4523 u32 engine_clock, 4524 SISLANDS_SMC_SCLK_VALUE *sclk) 4525{ 4526 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4527 struct si_power_info *si_pi = si_get_pi(rdev); 4528 struct atom_clock_dividers dividers; 4529 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4530 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4531 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4532 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4533 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4534 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4535 u64 tmp; 4536 u32 reference_clock = rdev->clock.spll.reference_freq; 4537 u32 reference_divider; 4538 u32 fbdiv; 4539 int ret; 4540 4541 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4542 engine_clock, false, ÷rs); 4543 if (ret) 4544 return ret; 4545 4546 reference_divider = 1 + dividers.ref_div; 4547 4548 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4549 do_div(tmp, reference_clock); 4550 fbdiv = (u32) tmp; 4551 4552 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4553 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4554 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4555 4556 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4557 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4558 4559 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4560 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4561 spll_func_cntl_3 |= SPLL_DITHEN; 4562 4563 if (pi->sclk_ss) { 4564 struct radeon_atom_ss ss; 4565 u32 vco_freq = engine_clock * dividers.post_div; 4566 4567 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4568 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4569 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4570 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4571 4572 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4573 cg_spll_spread_spectrum |= CLK_S(clk_s); 4574 cg_spll_spread_spectrum |= SSEN; 4575 4576 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4577 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4578 } 4579 } 4580 4581 sclk->sclk_value = engine_clock; 4582 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4583 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4584 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4585 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4586 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4587 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4588 4589 return 0; 4590} 4591 4592static int si_populate_sclk_value(struct radeon_device *rdev, 4593 u32 engine_clock, 4594 SISLANDS_SMC_SCLK_VALUE *sclk) 4595{ 4596 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4597 int ret; 4598 4599 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4600 if (!ret) { 4601 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4602 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4603 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4604 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4605 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4606 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4607 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4608 } 4609 4610 return ret; 4611} 4612 4613static int si_populate_mclk_value(struct radeon_device *rdev, 4614 u32 engine_clock, 4615 u32 memory_clock, 4616 SISLANDS_SMC_MCLK_VALUE *mclk, 4617 bool strobe_mode, 4618 bool dll_state_on) 4619{ 4620 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4621 struct si_power_info *si_pi = si_get_pi(rdev); 4622 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4623 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4624 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4625 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4626 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4627 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4628 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4629 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4630 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4631 struct atom_mpll_param mpll_param; 4632 int ret; 4633 4634 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4635 if (ret) 4636 return ret; 4637 4638 mpll_func_cntl &= ~BWCTRL_MASK; 4639 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4640 4641 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4642 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4643 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4644 4645 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4646 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4647 4648 if (pi->mem_gddr5) { 4649 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4650 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4651 YCLK_POST_DIV(mpll_param.post_div); 4652 } 4653 4654 if (pi->mclk_ss) { 4655 struct radeon_atom_ss ss; 4656 u32 freq_nom; 4657 u32 tmp; 4658 u32 reference_clock = rdev->clock.mpll.reference_freq; 4659 4660 if (pi->mem_gddr5) 4661 freq_nom = memory_clock * 4; 4662 else 4663 freq_nom = memory_clock * 2; 4664 4665 tmp = freq_nom / reference_clock; 4666 tmp = tmp * tmp; 4667 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4668 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4669 u32 clks = reference_clock * 5 / ss.rate; 4670 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4671 4672 mpll_ss1 &= ~CLKV_MASK; 4673 mpll_ss1 |= CLKV(clkv); 4674 4675 mpll_ss2 &= ~CLKS_MASK; 4676 mpll_ss2 |= CLKS(clks); 4677 } 4678 } 4679 4680 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4681 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4682 4683 if (dll_state_on) 4684 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4685 else 4686 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4687 4688 mclk->mclk_value = cpu_to_be32(memory_clock); 4689 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4690 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4691 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4692 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4693 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4694 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4695 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4696 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4697 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4698 4699 return 0; 4700} 4701 4702static void si_populate_smc_sp(struct radeon_device *rdev, 4703 struct radeon_ps *radeon_state, 4704 SISLANDS_SMC_SWSTATE *smc_state) 4705{ 4706 struct ni_ps *ps = ni_get_ps(radeon_state); 4707 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4708 int i; 4709 4710 for (i = 0; i < ps->performance_level_count - 1; i++) 4711 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4712 4713 smc_state->levels[ps->performance_level_count - 1].bSP = 4714 cpu_to_be32(pi->psp); 4715} 4716 4717static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4718 struct rv7xx_pl *pl, 4719 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4720{ 4721 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4722 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4723 struct si_power_info *si_pi = si_get_pi(rdev); 4724 int ret; 4725 bool dll_state_on; 4726 u16 std_vddc; 4727 bool gmc_pg = false; 4728 4729 if (eg_pi->pcie_performance_request && 4730 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4731 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4732 else 4733 level->gen2PCIE = (u8)pl->pcie_gen; 4734 4735 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4736 if (ret) 4737 return ret; 4738 4739 level->mcFlags = 0; 4740 4741 if (pi->mclk_stutter_mode_threshold && 4742 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4743 !eg_pi->uvd_enabled && 4744 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4745 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4746 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4747 4748 if (gmc_pg) 4749 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4750 } 4751 4752 if (pi->mem_gddr5) { 4753 if (pl->mclk > pi->mclk_edc_enable_threshold) 4754 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4755 4756 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4757 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4758 4759 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4760 4761 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4762 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4763 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4764 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4765 else 4766 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4767 } else { 4768 dll_state_on = false; 4769 } 4770 } else { 4771 level->strobeMode = si_get_strobe_mode_settings(rdev, 4772 pl->mclk); 4773 4774 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4775 } 4776 4777 ret = si_populate_mclk_value(rdev, 4778 pl->sclk, 4779 pl->mclk, 4780 &level->mclk, 4781 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4782 if (ret) 4783 return ret; 4784 4785 ret = si_populate_voltage_value(rdev, 4786 &eg_pi->vddc_voltage_table, 4787 pl->vddc, &level->vddc); 4788 if (ret) 4789 return ret; 4790 4791 4792 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4793 if (ret) 4794 return ret; 4795 4796 ret = si_populate_std_voltage_value(rdev, std_vddc, 4797 level->vddc.index, &level->std_vddc); 4798 if (ret) 4799 return ret; 4800 4801 if (eg_pi->vddci_control) { 4802 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4803 pl->vddci, &level->vddci); 4804 if (ret) 4805 return ret; 4806 } 4807 4808 if (si_pi->vddc_phase_shed_control) { 4809 ret = si_populate_phase_shedding_value(rdev, 4810 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4811 pl->vddc, 4812 pl->sclk, 4813 pl->mclk, 4814 &level->vddc); 4815 if (ret) 4816 return ret; 4817 } 4818 4819 level->MaxPoweredUpCU = si_pi->max_cu; 4820 4821 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4822 4823 return ret; 4824} 4825 4826static int si_populate_smc_t(struct radeon_device *rdev, 4827 struct radeon_ps *radeon_state, 4828 SISLANDS_SMC_SWSTATE *smc_state) 4829{ 4830 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4831 struct ni_ps *state = ni_get_ps(radeon_state); 4832 u32 a_t; 4833 u32 t_l, t_h; 4834 u32 high_bsp; 4835 int i, ret; 4836 4837 if (state->performance_level_count >= 9) 4838 return -EINVAL; 4839 4840 if (state->performance_level_count < 2) { 4841 a_t = CG_R(0xffff) | CG_L(0); 4842 smc_state->levels[0].aT = cpu_to_be32(a_t); 4843 return 0; 4844 } 4845 4846 smc_state->levels[0].aT = cpu_to_be32(0); 4847 4848 for (i = 0; i <= state->performance_level_count - 2; i++) { 4849 ret = r600_calculate_at( 4850 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4851 100 * R600_AH_DFLT, 4852 state->performance_levels[i + 1].sclk, 4853 state->performance_levels[i].sclk, 4854 &t_l, 4855 &t_h); 4856 4857 if (ret) { 4858 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4859 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4860 } 4861 4862 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4863 a_t |= CG_R(t_l * pi->bsp / 20000); 4864 smc_state->levels[i].aT = cpu_to_be32(a_t); 4865 4866 high_bsp = (i == state->performance_level_count - 2) ? 4867 pi->pbsp : pi->bsp; 4868 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4869 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4870 } 4871 4872 return 0; 4873} 4874 4875static int si_disable_ulv(struct radeon_device *rdev) 4876{ 4877 struct si_power_info *si_pi = si_get_pi(rdev); 4878 struct si_ulv_param *ulv = &si_pi->ulv; 4879 4880 if (ulv->supported) 4881 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4882 0 : -EINVAL; 4883 4884 return 0; 4885} 4886 4887static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 4888 struct radeon_ps *radeon_state) 4889{ 4890 const struct si_power_info *si_pi = si_get_pi(rdev); 4891 const struct si_ulv_param *ulv = &si_pi->ulv; 4892 const struct ni_ps *state = ni_get_ps(radeon_state); 4893 int i; 4894 4895 if (state->performance_levels[0].mclk != ulv->pl.mclk) 4896 return false; 4897 4898 /* XXX validate against display requirements! */ 4899 4900 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 4901 if (rdev->clock.current_dispclk <= 4902 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 4903 if (ulv->pl.vddc < 4904 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 4905 return false; 4906 } 4907 } 4908 4909 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 4910 return false; 4911 4912 return true; 4913} 4914 4915static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 4916 struct radeon_ps *radeon_new_state) 4917{ 4918 const struct si_power_info *si_pi = si_get_pi(rdev); 4919 const struct si_ulv_param *ulv = &si_pi->ulv; 4920 4921 if (ulv->supported) { 4922 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 4923 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 4924 0 : -EINVAL; 4925 } 4926 return 0; 4927} 4928 4929static int si_convert_power_state_to_smc(struct radeon_device *rdev, 4930 struct radeon_ps *radeon_state, 4931 SISLANDS_SMC_SWSTATE *smc_state) 4932{ 4933 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4934 struct ni_power_info *ni_pi = ni_get_pi(rdev); 4935 struct si_power_info *si_pi = si_get_pi(rdev); 4936 struct ni_ps *state = ni_get_ps(radeon_state); 4937 int i, ret; 4938 u32 threshold; 4939 u32 sclk_in_sr = 1350; /* ??? */ 4940 4941 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 4942 return -EINVAL; 4943 4944 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 4945 4946 if (radeon_state->vclk && radeon_state->dclk) { 4947 eg_pi->uvd_enabled = true; 4948 if (eg_pi->smu_uvd_hs) 4949 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 4950 } else { 4951 eg_pi->uvd_enabled = false; 4952 } 4953 4954 if (state->dc_compatible) 4955 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 4956 4957 smc_state->levelCount = 0; 4958 for (i = 0; i < state->performance_level_count; i++) { 4959 if (eg_pi->sclk_deep_sleep) { 4960 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 4961 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4962 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4963 else 4964 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4965 } 4966 } 4967 4968 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 4969 &smc_state->levels[i]); 4970 smc_state->levels[i].arbRefreshState = 4971 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 4972 4973 if (ret) 4974 return ret; 4975 4976 if (ni_pi->enable_power_containment) 4977 smc_state->levels[i].displayWatermark = 4978 (state->performance_levels[i].sclk < threshold) ? 4979 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 4980 else 4981 smc_state->levels[i].displayWatermark = (i < 2) ? 4982 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 4983 4984 if (eg_pi->dynamic_ac_timing) 4985 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 4986 else 4987 smc_state->levels[i].ACIndex = 0; 4988 4989 smc_state->levelCount++; 4990 } 4991 4992 si_write_smc_soft_register(rdev, 4993 SI_SMC_SOFT_REGISTER_watermark_threshold, 4994 threshold / 512); 4995 4996 si_populate_smc_sp(rdev, radeon_state, smc_state); 4997 4998 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 4999 if (ret) 5000 ni_pi->enable_power_containment = false; 5001 5002 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5003 if (ret) 5004 ni_pi->enable_sq_ramping = false; 5005 5006 return si_populate_smc_t(rdev, radeon_state, smc_state); 5007} 5008 5009static int si_upload_sw_state(struct radeon_device *rdev, 5010 struct radeon_ps *radeon_new_state) 5011{ 5012 struct si_power_info *si_pi = si_get_pi(rdev); 5013 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5014 int ret; 5015 u32 address = si_pi->state_table_start + 5016 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5017 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5018 ((new_state->performance_level_count - 1) * 5019 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5020 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5021 5022 memset(smc_state, 0, state_size); 5023 5024 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5025 if (ret) 5026 return ret; 5027 5028 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5029 state_size, si_pi->sram_end); 5030 5031 return ret; 5032} 5033 5034static int si_upload_ulv_state(struct radeon_device *rdev) 5035{ 5036 struct si_power_info *si_pi = si_get_pi(rdev); 5037 struct si_ulv_param *ulv = &si_pi->ulv; 5038 int ret = 0; 5039 5040 if (ulv->supported && ulv->pl.vddc) { 5041 u32 address = si_pi->state_table_start + 5042 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5043 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5044 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5045 5046 memset(smc_state, 0, state_size); 5047 5048 ret = si_populate_ulv_state(rdev, smc_state); 5049 if (!ret) 5050 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5051 state_size, si_pi->sram_end); 5052 } 5053 5054 return ret; 5055} 5056 5057static int si_upload_smc_data(struct radeon_device *rdev) 5058{ 5059 struct radeon_crtc *radeon_crtc = NULL; 5060 int i; 5061 5062 if (rdev->pm.dpm.new_active_crtc_count == 0) 5063 return 0; 5064 5065 for (i = 0; i < rdev->num_crtc; i++) { 5066 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5067 radeon_crtc = rdev->mode_info.crtcs[i]; 5068 break; 5069 } 5070 } 5071 5072 if (radeon_crtc == NULL) 5073 return 0; 5074 5075 if (radeon_crtc->line_time <= 0) 5076 return 0; 5077 5078 if (si_write_smc_soft_register(rdev, 5079 SI_SMC_SOFT_REGISTER_crtc_index, 5080 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5081 return 0; 5082 5083 if (si_write_smc_soft_register(rdev, 5084 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5085 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5086 return 0; 5087 5088 if (si_write_smc_soft_register(rdev, 5089 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5090 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5091 return 0; 5092 5093 return 0; 5094} 5095 5096static int si_set_mc_special_registers(struct radeon_device *rdev, 5097 struct si_mc_reg_table *table) 5098{ 5099 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5100 u8 i, j, k; 5101 u32 temp_reg; 5102 5103 for (i = 0, j = table->last; i < table->last; i++) { 5104 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5105 return -EINVAL; 5106 switch (table->mc_reg_address[i].s1 << 2) { 5107 case MC_SEQ_MISC1: 5108 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5109 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5110 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5111 for (k = 0; k < table->num_entries; k++) 5112 table->mc_reg_table_entry[k].mc_data[j] = 5113 ((temp_reg & 0xffff0000)) | 5114 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5115 j++; 5116 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5117 return -EINVAL; 5118 5119 temp_reg = RREG32(MC_PMG_CMD_MRS); 5120 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5121 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5122 for (k = 0; k < table->num_entries; k++) { 5123 table->mc_reg_table_entry[k].mc_data[j] = 5124 (temp_reg & 0xffff0000) | 5125 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5126 if (!pi->mem_gddr5) 5127 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5128 } 5129 j++; 5130 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5131 return -EINVAL; 5132 5133 if (!pi->mem_gddr5) { 5134 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5135 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5136 for (k = 0; k < table->num_entries; k++) 5137 table->mc_reg_table_entry[k].mc_data[j] = 5138 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5139 j++; 5140 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5141 return -EINVAL; 5142 } 5143 break; 5144 case MC_SEQ_RESERVE_M: 5145 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5146 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5147 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5148 for(k = 0; k < table->num_entries; k++) 5149 table->mc_reg_table_entry[k].mc_data[j] = 5150 (temp_reg & 0xffff0000) | 5151 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5152 j++; 5153 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5154 return -EINVAL; 5155 break; 5156 default: 5157 break; 5158 } 5159 } 5160 5161 table->last = j; 5162 5163 return 0; 5164} 5165 5166static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5167{ 5168 bool result = true; 5169 5170 switch (in_reg) { 5171 case MC_SEQ_RAS_TIMING >> 2: 5172 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5173 break; 5174 case MC_SEQ_CAS_TIMING >> 2: 5175 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5176 break; 5177 case MC_SEQ_MISC_TIMING >> 2: 5178 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5179 break; 5180 case MC_SEQ_MISC_TIMING2 >> 2: 5181 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5182 break; 5183 case MC_SEQ_RD_CTL_D0 >> 2: 5184 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5185 break; 5186 case MC_SEQ_RD_CTL_D1 >> 2: 5187 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5188 break; 5189 case MC_SEQ_WR_CTL_D0 >> 2: 5190 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5191 break; 5192 case MC_SEQ_WR_CTL_D1 >> 2: 5193 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5194 break; 5195 case MC_PMG_CMD_EMRS >> 2: 5196 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5197 break; 5198 case MC_PMG_CMD_MRS >> 2: 5199 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5200 break; 5201 case MC_PMG_CMD_MRS1 >> 2: 5202 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5203 break; 5204 case MC_SEQ_PMG_TIMING >> 2: 5205 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5206 break; 5207 case MC_PMG_CMD_MRS2 >> 2: 5208 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5209 break; 5210 case MC_SEQ_WR_CTL_2 >> 2: 5211 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5212 break; 5213 default: 5214 result = false; 5215 break; 5216 } 5217 5218 return result; 5219} 5220 5221static void si_set_valid_flag(struct si_mc_reg_table *table) 5222{ 5223 u8 i, j; 5224 5225 for (i = 0; i < table->last; i++) { 5226 for (j = 1; j < table->num_entries; j++) { 5227 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5228 table->valid_flag |= 1 << i; 5229 break; 5230 } 5231 } 5232 } 5233} 5234 5235static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5236{ 5237 u32 i; 5238 u16 address; 5239 5240 for (i = 0; i < table->last; i++) 5241 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5242 address : table->mc_reg_address[i].s1; 5243 5244} 5245 5246static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5247 struct si_mc_reg_table *si_table) 5248{ 5249 u8 i, j; 5250 5251 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5252 return -EINVAL; 5253 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5254 return -EINVAL; 5255 5256 for (i = 0; i < table->last; i++) 5257 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5258 si_table->last = table->last; 5259 5260 for (i = 0; i < table->num_entries; i++) { 5261 si_table->mc_reg_table_entry[i].mclk_max = 5262 table->mc_reg_table_entry[i].mclk_max; 5263 for (j = 0; j < table->last; j++) { 5264 si_table->mc_reg_table_entry[i].mc_data[j] = 5265 table->mc_reg_table_entry[i].mc_data[j]; 5266 } 5267 } 5268 si_table->num_entries = table->num_entries; 5269 5270 return 0; 5271} 5272 5273static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5274{ 5275 struct si_power_info *si_pi = si_get_pi(rdev); 5276 struct atom_mc_reg_table *table; 5277 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5278 u8 module_index = rv770_get_memory_module_index(rdev); 5279 int ret; 5280 5281 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5282 if (!table) 5283 return -ENOMEM; 5284 5285 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5286 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5287 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5288 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5289 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5290 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5291 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5292 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5293 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5294 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5295 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5296 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5297 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5298 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5299 5300 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5301 if (ret) 5302 goto init_mc_done; 5303 5304 ret = si_copy_vbios_mc_reg_table(table, si_table); 5305 if (ret) 5306 goto init_mc_done; 5307 5308 si_set_s0_mc_reg_index(si_table); 5309 5310 ret = si_set_mc_special_registers(rdev, si_table); 5311 if (ret) 5312 goto init_mc_done; 5313 5314 si_set_valid_flag(si_table); 5315 5316init_mc_done: 5317 kfree(table); 5318 5319 return ret; 5320 5321} 5322 5323static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5324 SMC_SIslands_MCRegisters *mc_reg_table) 5325{ 5326 struct si_power_info *si_pi = si_get_pi(rdev); 5327 u32 i, j; 5328 5329 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5330 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5331 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 5332 break; 5333 mc_reg_table->address[i].s0 = 5334 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5335 mc_reg_table->address[i].s1 = 5336 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5337 i++; 5338 } 5339 } 5340 mc_reg_table->last = (u8)i; 5341} 5342 5343static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5344 SMC_SIslands_MCRegisterSet *data, 5345 u32 num_entries, u32 valid_flag) 5346{ 5347 u32 i, j; 5348 5349 for(i = 0, j = 0; j < num_entries; j++) { 5350 if (valid_flag & (1 << j)) { 5351 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5352 i++; 5353 } 5354 } 5355} 5356 5357static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5358 struct rv7xx_pl *pl, 5359 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5360{ 5361 struct si_power_info *si_pi = si_get_pi(rdev); 5362 u32 i = 0; 5363 5364 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5365 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5366 break; 5367 } 5368 5369 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5370 --i; 5371 5372 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5373 mc_reg_table_data, si_pi->mc_reg_table.last, 5374 si_pi->mc_reg_table.valid_flag); 5375} 5376 5377static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5378 struct radeon_ps *radeon_state, 5379 SMC_SIslands_MCRegisters *mc_reg_table) 5380{ 5381 struct ni_ps *state = ni_get_ps(radeon_state); 5382 int i; 5383 5384 for (i = 0; i < state->performance_level_count; i++) { 5385 si_convert_mc_reg_table_entry_to_smc(rdev, 5386 &state->performance_levels[i], 5387 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5388 } 5389} 5390 5391static int si_populate_mc_reg_table(struct radeon_device *rdev, 5392 struct radeon_ps *radeon_boot_state) 5393{ 5394 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5395 struct si_power_info *si_pi = si_get_pi(rdev); 5396 struct si_ulv_param *ulv = &si_pi->ulv; 5397 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5398 5399 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5400 5401 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5402 5403 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5404 5405 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5406 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5407 5408 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5409 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5410 si_pi->mc_reg_table.last, 5411 si_pi->mc_reg_table.valid_flag); 5412 5413 if (ulv->supported && ulv->pl.vddc != 0) 5414 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5415 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5416 else 5417 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5418 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5419 si_pi->mc_reg_table.last, 5420 si_pi->mc_reg_table.valid_flag); 5421 5422 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5423 5424 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5425 (u8 *)smc_mc_reg_table, 5426 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5427} 5428 5429static int si_upload_mc_reg_table(struct radeon_device *rdev, 5430 struct radeon_ps *radeon_new_state) 5431{ 5432 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5433 struct si_power_info *si_pi = si_get_pi(rdev); 5434 u32 address = si_pi->mc_reg_table_start + 5435 offsetof(SMC_SIslands_MCRegisters, 5436 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5437 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5438 5439 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5440 5441 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5442 5443 5444 return si_copy_bytes_to_smc(rdev, address, 5445 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5446 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5447 si_pi->sram_end); 5448 5449} 5450 5451static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5452{ 5453 if (enable) 5454 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5455 else 5456 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5457} 5458 5459static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5460 struct radeon_ps *radeon_state) 5461{ 5462 struct ni_ps *state = ni_get_ps(radeon_state); 5463 int i; 5464 u16 pcie_speed, max_speed = 0; 5465 5466 for (i = 0; i < state->performance_level_count; i++) { 5467 pcie_speed = state->performance_levels[i].pcie_gen; 5468 if (max_speed < pcie_speed) 5469 max_speed = pcie_speed; 5470 } 5471 return max_speed; 5472} 5473 5474static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5475{ 5476 u32 speed_cntl; 5477 5478 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5479 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5480 5481 return (u16)speed_cntl; 5482} 5483 5484static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5485 struct radeon_ps *radeon_new_state, 5486 struct radeon_ps *radeon_current_state) 5487{ 5488 struct si_power_info *si_pi = si_get_pi(rdev); 5489 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5490 enum radeon_pcie_gen current_link_speed; 5491 5492 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5493 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5494 else 5495 current_link_speed = si_pi->force_pcie_gen; 5496 5497 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5498 si_pi->pspp_notify_required = false; 5499 if (target_link_speed > current_link_speed) { 5500 switch (target_link_speed) { 5501#if defined(CONFIG_ACPI) 5502 case RADEON_PCIE_GEN3: 5503 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5504 break; 5505 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5506 if (current_link_speed == RADEON_PCIE_GEN2) 5507 break; 5508 case RADEON_PCIE_GEN2: 5509 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5510 break; 5511#endif 5512 default: 5513 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5514 break; 5515 } 5516 } else { 5517 if (target_link_speed < current_link_speed) 5518 si_pi->pspp_notify_required = true; 5519 } 5520} 5521 5522static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5523 struct radeon_ps *radeon_new_state, 5524 struct radeon_ps *radeon_current_state) 5525{ 5526 struct si_power_info *si_pi = si_get_pi(rdev); 5527 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5528 u8 request; 5529 5530 if (si_pi->pspp_notify_required) { 5531 if (target_link_speed == RADEON_PCIE_GEN3) 5532 request = PCIE_PERF_REQ_PECI_GEN3; 5533 else if (target_link_speed == RADEON_PCIE_GEN2) 5534 request = PCIE_PERF_REQ_PECI_GEN2; 5535 else 5536 request = PCIE_PERF_REQ_PECI_GEN1; 5537 5538 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5539 (si_get_current_pcie_speed(rdev) > 0)) 5540 return; 5541 5542#if defined(CONFIG_ACPI) 5543 radeon_acpi_pcie_performance_request(rdev, request, false); 5544#endif 5545 } 5546} 5547 5548#if 0 5549static int si_ds_request(struct radeon_device *rdev, 5550 bool ds_status_on, u32 count_write) 5551{ 5552 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5553 5554 if (eg_pi->sclk_deep_sleep) { 5555 if (ds_status_on) 5556 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5557 PPSMC_Result_OK) ? 5558 0 : -EINVAL; 5559 else 5560 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5561 PPSMC_Result_OK) ? 0 : -EINVAL; 5562 } 5563 return 0; 5564} 5565#endif 5566 5567static void si_set_max_cu_value(struct radeon_device *rdev) 5568{ 5569 struct si_power_info *si_pi = si_get_pi(rdev); 5570 5571 if (rdev->family == CHIP_VERDE) { 5572 switch (rdev->pdev->device) { 5573 case 0x6820: 5574 case 0x6825: 5575 case 0x6821: 5576 case 0x6823: 5577 case 0x6827: 5578 si_pi->max_cu = 10; 5579 break; 5580 case 0x682D: 5581 case 0x6824: 5582 case 0x682F: 5583 case 0x6826: 5584 si_pi->max_cu = 8; 5585 break; 5586 case 0x6828: 5587 case 0x6830: 5588 case 0x6831: 5589 case 0x6838: 5590 case 0x6839: 5591 case 0x683D: 5592 si_pi->max_cu = 10; 5593 break; 5594 case 0x683B: 5595 case 0x683F: 5596 case 0x6829: 5597 si_pi->max_cu = 8; 5598 break; 5599 default: 5600 si_pi->max_cu = 0; 5601 break; 5602 } 5603 } else { 5604 si_pi->max_cu = 0; 5605 } 5606} 5607 5608static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5609 struct radeon_clock_voltage_dependency_table *table) 5610{ 5611 u32 i; 5612 int j; 5613 u16 leakage_voltage; 5614 5615 if (table) { 5616 for (i = 0; i < table->count; i++) { 5617 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5618 table->entries[i].v, 5619 &leakage_voltage)) { 5620 case 0: 5621 table->entries[i].v = leakage_voltage; 5622 break; 5623 case -EAGAIN: 5624 return -EINVAL; 5625 case -EINVAL: 5626 default: 5627 break; 5628 } 5629 } 5630 5631 for (j = (table->count - 2); j >= 0; j--) { 5632 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5633 table->entries[j].v : table->entries[j + 1].v; 5634 } 5635 } 5636 return 0; 5637} 5638 5639static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5640{ 5641 int ret = 0; 5642 5643 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5644 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5645 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5646 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5647 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5648 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5649 return ret; 5650} 5651 5652static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5653 struct radeon_ps *radeon_new_state, 5654 struct radeon_ps *radeon_current_state) 5655{ 5656 u32 lane_width; 5657 u32 new_lane_width = 5658 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5659 u32 current_lane_width = 5660 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5661 5662 if (new_lane_width != current_lane_width) { 5663 radeon_set_pcie_lanes(rdev, new_lane_width); 5664 lane_width = radeon_get_pcie_lanes(rdev); 5665 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5666 } 5667} 5668 5669void si_dpm_setup_asic(struct radeon_device *rdev) 5670{ 5671 rv770_get_memory_type(rdev); 5672 si_read_clock_registers(rdev); 5673 si_enable_acpi_power_management(rdev); 5674} 5675 5676static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5677 int min_temp, int max_temp) 5678{ 5679 int low_temp = 0 * 1000; 5680 int high_temp = 255 * 1000; 5681 5682 if (low_temp < min_temp) 5683 low_temp = min_temp; 5684 if (high_temp > max_temp) 5685 high_temp = max_temp; 5686 if (high_temp < low_temp) { 5687 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5688 return -EINVAL; 5689 } 5690 5691 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5692 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5693 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5694 5695 rdev->pm.dpm.thermal.min_temp = low_temp; 5696 rdev->pm.dpm.thermal.max_temp = high_temp; 5697 5698 return 0; 5699} 5700 5701int si_dpm_enable(struct radeon_device *rdev) 5702{ 5703 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5704 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5705 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5706 int ret; 5707 5708 if (si_is_smc_running(rdev)) 5709 return -EINVAL; 5710 if (pi->voltage_control) 5711 si_enable_voltage_control(rdev, true); 5712 if (pi->mvdd_control) 5713 si_get_mvdd_configuration(rdev); 5714 if (pi->voltage_control) { 5715 ret = si_construct_voltage_tables(rdev); 5716 if (ret) { 5717 DRM_ERROR("si_construct_voltage_tables failed\n"); 5718 return ret; 5719 } 5720 } 5721 if (eg_pi->dynamic_ac_timing) { 5722 ret = si_initialize_mc_reg_table(rdev); 5723 if (ret) 5724 eg_pi->dynamic_ac_timing = false; 5725 } 5726 if (pi->dynamic_ss) 5727 si_enable_spread_spectrum(rdev, true); 5728 if (pi->thermal_protection) 5729 si_enable_thermal_protection(rdev, true); 5730 si_setup_bsp(rdev); 5731 si_program_git(rdev); 5732 si_program_tp(rdev); 5733 si_program_tpp(rdev); 5734 si_program_sstp(rdev); 5735 si_enable_display_gap(rdev); 5736 si_program_vc(rdev); 5737 ret = si_upload_firmware(rdev); 5738 if (ret) { 5739 DRM_ERROR("si_upload_firmware failed\n"); 5740 return ret; 5741 } 5742 ret = si_process_firmware_header(rdev); 5743 if (ret) { 5744 DRM_ERROR("si_process_firmware_header failed\n"); 5745 return ret; 5746 } 5747 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5748 if (ret) { 5749 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5750 return ret; 5751 } 5752 ret = si_init_smc_table(rdev); 5753 if (ret) { 5754 DRM_ERROR("si_init_smc_table failed\n"); 5755 return ret; 5756 } 5757 ret = si_init_smc_spll_table(rdev); 5758 if (ret) { 5759 DRM_ERROR("si_init_smc_spll_table failed\n"); 5760 return ret; 5761 } 5762 ret = si_init_arb_table_index(rdev); 5763 if (ret) { 5764 DRM_ERROR("si_init_arb_table_index failed\n"); 5765 return ret; 5766 } 5767 if (eg_pi->dynamic_ac_timing) { 5768 ret = si_populate_mc_reg_table(rdev, boot_ps); 5769 if (ret) { 5770 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5771 return ret; 5772 } 5773 } 5774 ret = si_initialize_smc_cac_tables(rdev); 5775 if (ret) { 5776 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5777 return ret; 5778 } 5779 ret = si_initialize_hardware_cac_manager(rdev); 5780 if (ret) { 5781 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5782 return ret; 5783 } 5784 ret = si_initialize_smc_dte_tables(rdev); 5785 if (ret) { 5786 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5787 return ret; 5788 } 5789 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5790 if (ret) { 5791 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5792 return ret; 5793 } 5794 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5795 if (ret) { 5796 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5797 return ret; 5798 } 5799 si_program_response_times(rdev); 5800 si_program_ds_registers(rdev); 5801 si_dpm_start_smc(rdev); 5802 ret = si_notify_smc_display_change(rdev, false); 5803 if (ret) { 5804 DRM_ERROR("si_notify_smc_display_change failed\n"); 5805 return ret; 5806 } 5807 si_enable_sclk_control(rdev, true); 5808 si_start_dpm(rdev); 5809 5810 if (rdev->irq.installed && 5811 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5812 PPSMC_Result result; 5813 5814 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5815 if (ret) 5816 return ret; 5817 rdev->irq.dpm_thermal = true; 5818 radeon_irq_set(rdev); 5819 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5820 5821 if (result != PPSMC_Result_OK) 5822 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5823 } 5824 5825 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5826 5827 ni_update_current_ps(rdev, boot_ps); 5828 5829 return 0; 5830} 5831 5832void si_dpm_disable(struct radeon_device *rdev) 5833{ 5834 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5835 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5836 5837 if (!si_is_smc_running(rdev)) 5838 return; 5839 si_disable_ulv(rdev); 5840 si_clear_vc(rdev); 5841 if (pi->thermal_protection) 5842 si_enable_thermal_protection(rdev, false); 5843 si_enable_power_containment(rdev, boot_ps, false); 5844 si_enable_smc_cac(rdev, boot_ps, false); 5845 si_enable_spread_spectrum(rdev, false); 5846 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5847 si_stop_dpm(rdev); 5848 si_reset_to_default(rdev); 5849 si_dpm_stop_smc(rdev); 5850 si_force_switch_to_arb_f0(rdev); 5851 5852 ni_update_current_ps(rdev, boot_ps); 5853} 5854 5855int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5856{ 5857 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5858 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5859 struct radeon_ps *new_ps = &requested_ps; 5860 5861 ni_update_requested_ps(rdev, new_ps); 5862 5863 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5864 5865 return 0; 5866} 5867 5868static int si_power_control_set_level(struct radeon_device *rdev) 5869{ 5870 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 5871 int ret; 5872 5873 ret = si_restrict_performance_levels_before_switch(rdev); 5874 if (ret) 5875 return ret; 5876 ret = si_halt_smc(rdev); 5877 if (ret) 5878 return ret; 5879 ret = si_populate_smc_tdp_limits(rdev, new_ps); 5880 if (ret) 5881 return ret; 5882 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 5883 if (ret) 5884 return ret; 5885 ret = si_resume_smc(rdev); 5886 if (ret) 5887 return ret; 5888 ret = si_set_sw_state(rdev); 5889 if (ret) 5890 return ret; 5891 return 0; 5892} 5893 5894int si_dpm_set_power_state(struct radeon_device *rdev) 5895{ 5896 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5897 struct radeon_ps *new_ps = &eg_pi->requested_rps; 5898 struct radeon_ps *old_ps = &eg_pi->current_rps; 5899 int ret; 5900 5901 ret = si_disable_ulv(rdev); 5902 if (ret) { 5903 DRM_ERROR("si_disable_ulv failed\n"); 5904 return ret; 5905 } 5906 ret = si_restrict_performance_levels_before_switch(rdev); 5907 if (ret) { 5908 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 5909 return ret; 5910 } 5911 if (eg_pi->pcie_performance_request) 5912 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5913 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 5914 ret = si_enable_power_containment(rdev, new_ps, false); 5915 if (ret) { 5916 DRM_ERROR("si_enable_power_containment failed\n"); 5917 return ret; 5918 } 5919 ret = si_enable_smc_cac(rdev, new_ps, false); 5920 if (ret) { 5921 DRM_ERROR("si_enable_smc_cac failed\n"); 5922 return ret; 5923 } 5924 ret = si_halt_smc(rdev); 5925 if (ret) { 5926 DRM_ERROR("si_halt_smc failed\n"); 5927 return ret; 5928 } 5929 ret = si_upload_sw_state(rdev, new_ps); 5930 if (ret) { 5931 DRM_ERROR("si_upload_sw_state failed\n"); 5932 return ret; 5933 } 5934 ret = si_upload_smc_data(rdev); 5935 if (ret) { 5936 DRM_ERROR("si_upload_smc_data failed\n"); 5937 return ret; 5938 } 5939 ret = si_upload_ulv_state(rdev); 5940 if (ret) { 5941 DRM_ERROR("si_upload_ulv_state failed\n"); 5942 return ret; 5943 } 5944 if (eg_pi->dynamic_ac_timing) { 5945 ret = si_upload_mc_reg_table(rdev, new_ps); 5946 if (ret) { 5947 DRM_ERROR("si_upload_mc_reg_table failed\n"); 5948 return ret; 5949 } 5950 } 5951 ret = si_program_memory_timing_parameters(rdev, new_ps); 5952 if (ret) { 5953 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 5954 return ret; 5955 } 5956 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 5957 5958 ret = si_resume_smc(rdev); 5959 if (ret) { 5960 DRM_ERROR("si_resume_smc failed\n"); 5961 return ret; 5962 } 5963 ret = si_set_sw_state(rdev); 5964 if (ret) { 5965 DRM_ERROR("si_set_sw_state failed\n"); 5966 return ret; 5967 } 5968 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 5969 if (eg_pi->pcie_performance_request) 5970 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 5971 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 5972 if (ret) { 5973 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 5974 return ret; 5975 } 5976 ret = si_enable_smc_cac(rdev, new_ps, true); 5977 if (ret) { 5978 DRM_ERROR("si_enable_smc_cac failed\n"); 5979 return ret; 5980 } 5981 ret = si_enable_power_containment(rdev, new_ps, true); 5982 if (ret) { 5983 DRM_ERROR("si_enable_power_containment failed\n"); 5984 return ret; 5985 } 5986 5987 ret = si_power_control_set_level(rdev); 5988 if (ret) { 5989 DRM_ERROR("si_power_control_set_level failed\n"); 5990 return ret; 5991 } 5992 5993#if 0 5994 /* XXX */ 5995 ret = si_unrestrict_performance_levels_after_switch(rdev); 5996 if (ret) { 5997 DRM_ERROR("si_unrestrict_performance_levels_after_switch failed\n"); 5998 return ret; 5999 } 6000#endif 6001 6002 return 0; 6003} 6004 6005void si_dpm_post_set_power_state(struct radeon_device *rdev) 6006{ 6007 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6008 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6009 6010 ni_update_current_ps(rdev, new_ps); 6011} 6012 6013 6014void si_dpm_reset_asic(struct radeon_device *rdev) 6015{ 6016 si_restrict_performance_levels_before_switch(rdev); 6017 si_disable_ulv(rdev); 6018 si_set_boot_state(rdev); 6019} 6020 6021void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6022{ 6023 si_program_display_gap(rdev); 6024} 6025 6026union power_info { 6027 struct _ATOM_POWERPLAY_INFO info; 6028 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6029 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6030 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6031 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6032 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6033}; 6034 6035union pplib_clock_info { 6036 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6037 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6038 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6039 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6040 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6041}; 6042 6043union pplib_power_state { 6044 struct _ATOM_PPLIB_STATE v1; 6045 struct _ATOM_PPLIB_STATE_V2 v2; 6046}; 6047 6048static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6049 struct radeon_ps *rps, 6050 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6051 u8 table_rev) 6052{ 6053 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6054 rps->class = le16_to_cpu(non_clock_info->usClassification); 6055 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6056 6057 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6058 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6059 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6060 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6061 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6062 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6063 } else { 6064 rps->vclk = 0; 6065 rps->dclk = 0; 6066 } 6067 6068 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6069 rdev->pm.dpm.boot_ps = rps; 6070 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6071 rdev->pm.dpm.uvd_ps = rps; 6072} 6073 6074static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6075 struct radeon_ps *rps, int index, 6076 union pplib_clock_info *clock_info) 6077{ 6078 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6079 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6080 struct si_power_info *si_pi = si_get_pi(rdev); 6081 struct ni_ps *ps = ni_get_ps(rps); 6082 u16 leakage_voltage; 6083 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6084 int ret; 6085 6086 ps->performance_level_count = index + 1; 6087 6088 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6089 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6090 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6091 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6092 6093 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6094 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6095 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6096 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6097 si_pi->sys_pcie_mask, 6098 si_pi->boot_pcie_gen, 6099 clock_info->si.ucPCIEGen); 6100 6101 /* patch up vddc if necessary */ 6102 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6103 &leakage_voltage); 6104 if (ret == 0) 6105 pl->vddc = leakage_voltage; 6106 6107 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6108 pi->acpi_vddc = pl->vddc; 6109 eg_pi->acpi_vddci = pl->vddci; 6110 si_pi->acpi_pcie_gen = pl->pcie_gen; 6111 } 6112 6113 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6114 index == 0) { 6115 /* XXX disable for A0 tahiti */ 6116 si_pi->ulv.supported = true; 6117 si_pi->ulv.pl = *pl; 6118 si_pi->ulv.one_pcie_lane_in_ulv = false; 6119 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6120 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6121 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6122 } 6123 6124 if (pi->min_vddc_in_table > pl->vddc) 6125 pi->min_vddc_in_table = pl->vddc; 6126 6127 if (pi->max_vddc_in_table < pl->vddc) 6128 pi->max_vddc_in_table = pl->vddc; 6129 6130 /* patch up boot state */ 6131 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6132 u16 vddc, vddci, mvdd; 6133 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6134 pl->mclk = rdev->clock.default_mclk; 6135 pl->sclk = rdev->clock.default_sclk; 6136 pl->vddc = vddc; 6137 pl->vddci = vddci; 6138 si_pi->mvdd_bootup_value = mvdd; 6139 } 6140 6141 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6142 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6143 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6144 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6145 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6146 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6147 } 6148} 6149 6150static int si_parse_power_table(struct radeon_device *rdev) 6151{ 6152 struct radeon_mode_info *mode_info = &rdev->mode_info; 6153 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6154 union pplib_power_state *power_state; 6155 int i, j, k, non_clock_array_index, clock_array_index; 6156 union pplib_clock_info *clock_info; 6157 struct _StateArray *state_array; 6158 struct _ClockInfoArray *clock_info_array; 6159 struct _NonClockInfoArray *non_clock_info_array; 6160 union power_info *power_info; 6161 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6162 u16 data_offset; 6163 u8 frev, crev; 6164 u8 *power_state_offset; 6165 struct ni_ps *ps; 6166 6167 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6168 &frev, &crev, &data_offset)) 6169 return -EINVAL; 6170 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6171 6172 state_array = (struct _StateArray *) 6173 (mode_info->atom_context->bios + data_offset + 6174 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6175 clock_info_array = (struct _ClockInfoArray *) 6176 (mode_info->atom_context->bios + data_offset + 6177 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6178 non_clock_info_array = (struct _NonClockInfoArray *) 6179 (mode_info->atom_context->bios + data_offset + 6180 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6181 6182 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6183 state_array->ucNumEntries, GFP_KERNEL); 6184 if (!rdev->pm.dpm.ps) 6185 return -ENOMEM; 6186 power_state_offset = (u8 *)state_array->states; 6187 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 6188 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 6189 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 6190 for (i = 0; i < state_array->ucNumEntries; i++) { 6191 power_state = (union pplib_power_state *)power_state_offset; 6192 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6193 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6194 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6195 if (!rdev->pm.power_state[i].clock_info) 6196 return -EINVAL; 6197 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6198 if (ps == NULL) { 6199 kfree(rdev->pm.dpm.ps); 6200 return -ENOMEM; 6201 } 6202 rdev->pm.dpm.ps[i].ps_priv = ps; 6203 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6204 non_clock_info, 6205 non_clock_info_array->ucEntrySize); 6206 k = 0; 6207 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6208 clock_array_index = power_state->v2.clockInfoIndex[j]; 6209 if (clock_array_index >= clock_info_array->ucNumEntries) 6210 continue; 6211 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6212 break; 6213 clock_info = (union pplib_clock_info *) 6214 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6215 si_parse_pplib_clock_info(rdev, 6216 &rdev->pm.dpm.ps[i], k, 6217 clock_info); 6218 k++; 6219 } 6220 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6221 } 6222 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6223 return 0; 6224} 6225 6226int si_dpm_init(struct radeon_device *rdev) 6227{ 6228 struct rv7xx_power_info *pi; 6229 struct evergreen_power_info *eg_pi; 6230 struct ni_power_info *ni_pi; 6231 struct si_power_info *si_pi; 6232 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 6233 u16 data_offset, size; 6234 u8 frev, crev; 6235 struct atom_clock_dividers dividers; 6236 int ret; 6237 u32 mask; 6238 6239 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6240 if (si_pi == NULL) 6241 return -ENOMEM; 6242 rdev->pm.dpm.priv = si_pi; 6243 ni_pi = &si_pi->ni; 6244 eg_pi = &ni_pi->eg; 6245 pi = &eg_pi->rv7xx; 6246 6247 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6248 if (ret) 6249 si_pi->sys_pcie_mask = 0; 6250 else 6251 si_pi->sys_pcie_mask = mask; 6252 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6253 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6254 6255 si_set_max_cu_value(rdev); 6256 6257 rv770_get_max_vddc(rdev); 6258 si_get_leakage_vddc(rdev); 6259 si_patch_dependency_tables_based_on_leakage(rdev); 6260 6261 pi->acpi_vddc = 0; 6262 eg_pi->acpi_vddci = 0; 6263 pi->min_vddc_in_table = 0; 6264 pi->max_vddc_in_table = 0; 6265 6266 ret = si_parse_power_table(rdev); 6267 if (ret) 6268 return ret; 6269 ret = r600_parse_extended_power_table(rdev); 6270 if (ret) 6271 return ret; 6272 6273 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6274 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6275 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6276 r600_free_extended_power_table(rdev); 6277 return -ENOMEM; 6278 } 6279 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6280 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6281 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6282 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6283 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6284 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6285 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6286 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6287 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6288 6289 if (rdev->pm.dpm.voltage_response_time == 0) 6290 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6291 if (rdev->pm.dpm.backbias_response_time == 0) 6292 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6293 6294 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6295 0, false, ÷rs); 6296 if (ret) 6297 pi->ref_div = dividers.ref_div + 1; 6298 else 6299 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6300 6301 eg_pi->smu_uvd_hs = false; 6302 6303 pi->mclk_strobe_mode_threshold = 40000; 6304 if (si_is_special_1gb_platform(rdev)) 6305 pi->mclk_stutter_mode_threshold = 0; 6306 else 6307 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6308 pi->mclk_edc_enable_threshold = 40000; 6309 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6310 6311 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6312 6313 pi->voltage_control = 6314 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT); 6315 6316 pi->mvdd_control = 6317 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT); 6318 6319 eg_pi->vddci_control = 6320 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT); 6321 6322 si_pi->vddc_phase_shed_control = 6323 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6324 6325 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 6326 &frev, &crev, &data_offset)) { 6327 pi->sclk_ss = true; 6328 pi->mclk_ss = true; 6329 pi->dynamic_ss = true; 6330 } else { 6331 pi->sclk_ss = false; 6332 pi->mclk_ss = false; 6333 pi->dynamic_ss = true; 6334 } 6335 6336 pi->asi = RV770_ASI_DFLT; 6337 pi->pasi = CYPRESS_HASI_DFLT; 6338 pi->vrc = SISLANDS_VRC_DFLT; 6339 6340 pi->gfx_clock_gating = true; 6341 6342 eg_pi->sclk_deep_sleep = true; 6343 si_pi->sclk_deep_sleep_above_low = false; 6344 6345 if (pi->gfx_clock_gating && 6346 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 6347 pi->thermal_protection = true; 6348 else 6349 pi->thermal_protection = false; 6350 6351 eg_pi->dynamic_ac_timing = true; 6352 6353 eg_pi->light_sleep = true; 6354#if defined(CONFIG_ACPI) 6355 eg_pi->pcie_performance_request = 6356 radeon_acpi_is_pcie_performance_request_supported(rdev); 6357#else 6358 eg_pi->pcie_performance_request = false; 6359#endif 6360 6361 si_pi->sram_end = SMC_RAM_END; 6362 6363 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6364 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6365 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6366 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6367 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6368 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6369 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6370 6371 si_initialize_powertune_defaults(rdev); 6372 6373 return 0; 6374} 6375 6376void si_dpm_fini(struct radeon_device *rdev) 6377{ 6378 int i; 6379 6380 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6381 kfree(rdev->pm.dpm.ps[i].ps_priv); 6382 } 6383 kfree(rdev->pm.dpm.ps); 6384 kfree(rdev->pm.dpm.priv); 6385 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6386 r600_free_extended_power_table(rdev); 6387} 6388 6389void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6390 struct seq_file *m) 6391{ 6392 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 6393 struct ni_ps *ps = ni_get_ps(rps); 6394 struct rv7xx_pl *pl; 6395 u32 current_index = 6396 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6397 CURRENT_STATE_INDEX_SHIFT; 6398 6399 if (current_index >= ps->performance_level_count) { 6400 seq_printf(m, "invalid dpm profile %d\n", current_index); 6401 } else { 6402 pl = &ps->performance_levels[current_index]; 6403 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6404 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6405 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6406 } 6407} 6408