si_dpm.c revision f44a0120ef07cc9a1f36ab86751ec2b0598d7a2b
1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include "drmP.h" 25#include "radeon.h" 26#include "sid.h" 27#include "r600_dpm.h" 28#include "si_dpm.h" 29#include "atom.h" 30#include <linux/math64.h> 31#include <linux/seq_file.h> 32 33#define MC_CG_ARB_FREQ_F0 0x0a 34#define MC_CG_ARB_FREQ_F1 0x0b 35#define MC_CG_ARB_FREQ_F2 0x0c 36#define MC_CG_ARB_FREQ_F3 0x0d 37 38#define SMC_RAM_END 0x20000 39 40#define SCLK_MIN_DEEPSLEEP_FREQ 1350 41 42static const struct si_cac_config_reg cac_weights_tahiti[] = 43{ 44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 104 { 0xFFFFFFFF } 105}; 106 107static const struct si_cac_config_reg lcac_tahiti[] = 108{ 109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0xFFFFFFFF } 196 197}; 198 199static const struct si_cac_config_reg cac_override_tahiti[] = 200{ 201 { 0xFFFFFFFF } 202}; 203 204static const struct si_powertune_data powertune_data_tahiti = 205{ 206 ((1 << 16) | 27027), 207 6, 208 0, 209 4, 210 95, 211 { 212 0UL, 213 0UL, 214 4521550UL, 215 309631529UL, 216 -1270850L, 217 4513710L, 218 40 219 }, 220 595000000UL, 221 12, 222 { 223 0, 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0 231 }, 232 true 233}; 234 235static const struct si_dte_data dte_data_tahiti = 236{ 237 { 1159409, 0, 0, 0, 0 }, 238 { 777, 0, 0, 0, 0 }, 239 2, 240 54000, 241 127000, 242 25, 243 2, 244 10, 245 13, 246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 249 85, 250 false 251}; 252 253static const struct si_dte_data dte_data_tahiti_le = 254{ 255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 257 0x5, 258 0xAFC8, 259 0x64, 260 0x32, 261 1, 262 0, 263 0x10, 264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 267 85, 268 true 269}; 270 271static const struct si_dte_data dte_data_tahiti_pro = 272{ 273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 274 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 275 5, 276 45000, 277 100, 278 0xA, 279 1, 280 0, 281 0x10, 282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 285 90, 286 true 287}; 288 289static const struct si_dte_data dte_data_new_zealand = 290{ 291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 293 0x5, 294 0xAFC8, 295 0x69, 296 0x32, 297 1, 298 0, 299 0x10, 300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 303 85, 304 true 305}; 306 307static const struct si_dte_data dte_data_aruba_pro = 308{ 309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 310 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 311 5, 312 45000, 313 100, 314 0xA, 315 1, 316 0, 317 0x10, 318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 321 90, 322 true 323}; 324 325static const struct si_dte_data dte_data_malta = 326{ 327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 328 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 329 5, 330 45000, 331 100, 332 0xA, 333 1, 334 0, 335 0x10, 336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 339 90, 340 true 341}; 342 343struct si_cac_config_reg cac_weights_pitcairn[] = 344{ 345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 405 { 0xFFFFFFFF } 406}; 407 408static const struct si_cac_config_reg lcac_pitcairn[] = 409{ 410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 496 { 0xFFFFFFFF } 497}; 498 499static const struct si_cac_config_reg cac_override_pitcairn[] = 500{ 501 { 0xFFFFFFFF } 502}; 503 504static const struct si_powertune_data powertune_data_pitcairn = 505{ 506 ((1 << 16) | 27027), 507 5, 508 0, 509 6, 510 100, 511 { 512 51600000UL, 513 1800000UL, 514 7194395UL, 515 309631529UL, 516 -1270850L, 517 4513710L, 518 100 519 }, 520 117830498UL, 521 12, 522 { 523 0, 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0 531 }, 532 true 533}; 534 535static const struct si_dte_data dte_data_pitcairn = 536{ 537 { 0, 0, 0, 0, 0 }, 538 { 0, 0, 0, 0, 0 }, 539 0, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 0, 550 false 551}; 552 553static const struct si_dte_data dte_data_curacao_xt = 554{ 555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 556 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 557 5, 558 45000, 559 100, 560 0xA, 561 1, 562 0, 563 0x10, 564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 567 90, 568 true 569}; 570 571static const struct si_dte_data dte_data_curacao_pro = 572{ 573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 574 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 575 5, 576 45000, 577 100, 578 0xA, 579 1, 580 0, 581 0x10, 582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 585 90, 586 true 587}; 588 589static const struct si_dte_data dte_data_neptune_xt = 590{ 591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 592 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 593 5, 594 45000, 595 100, 596 0xA, 597 1, 598 0, 599 0x10, 600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 603 90, 604 true 605}; 606 607static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 608{ 609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 669 { 0xFFFFFFFF } 670}; 671 672static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 673{ 674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 734 { 0xFFFFFFFF } 735}; 736 737static const struct si_cac_config_reg cac_weights_heathrow[] = 738{ 739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 799 { 0xFFFFFFFF } 800}; 801 802static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 803{ 804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 864 { 0xFFFFFFFF } 865}; 866 867static const struct si_cac_config_reg cac_weights_cape_verde[] = 868{ 869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 929 { 0xFFFFFFFF } 930}; 931 932static const struct si_cac_config_reg lcac_cape_verde[] = 933{ 934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0xFFFFFFFF } 989}; 990 991static const struct si_cac_config_reg cac_override_cape_verde[] = 992{ 993 { 0xFFFFFFFF } 994}; 995 996static const struct si_powertune_data powertune_data_cape_verde = 997{ 998 ((1 << 16) | 0x6993), 999 5, 1000 0, 1001 7, 1002 105, 1003 { 1004 0UL, 1005 0UL, 1006 7194395UL, 1007 309631529UL, 1008 -1270850L, 1009 4513710L, 1010 100 1011 }, 1012 117830498UL, 1013 12, 1014 { 1015 0, 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0 1023 }, 1024 true 1025}; 1026 1027static const struct si_dte_data dte_data_cape_verde = 1028{ 1029 { 0, 0, 0, 0, 0 }, 1030 { 0, 0, 0, 0, 0 }, 1031 0, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 0, 1042 false 1043}; 1044 1045static const struct si_dte_data dte_data_venus_xtx = 1046{ 1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1049 5, 1050 55000, 1051 0x69, 1052 0xA, 1053 1, 1054 0, 1055 0x3, 1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 90, 1060 true 1061}; 1062 1063static const struct si_dte_data dte_data_venus_xt = 1064{ 1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1067 5, 1068 55000, 1069 0x69, 1070 0xA, 1071 1, 1072 0, 1073 0x3, 1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 90, 1078 true 1079}; 1080 1081static const struct si_dte_data dte_data_venus_pro = 1082{ 1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1085 5, 1086 55000, 1087 0x69, 1088 0xA, 1089 1, 1090 0, 1091 0x3, 1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 90, 1096 true 1097}; 1098 1099struct si_cac_config_reg cac_weights_oland[] = 1100{ 1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1161 { 0xFFFFFFFF } 1162}; 1163 1164static const struct si_cac_config_reg cac_weights_mars_pro[] = 1165{ 1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1226 { 0xFFFFFFFF } 1227}; 1228 1229static const struct si_cac_config_reg cac_weights_mars_xt[] = 1230{ 1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1291 { 0xFFFFFFFF } 1292}; 1293 1294static const struct si_cac_config_reg cac_weights_oland_pro[] = 1295{ 1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1356 { 0xFFFFFFFF } 1357}; 1358 1359static const struct si_cac_config_reg cac_weights_oland_xt[] = 1360{ 1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1421 { 0xFFFFFFFF } 1422}; 1423 1424static const struct si_cac_config_reg lcac_oland[] = 1425{ 1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0xFFFFFFFF } 1469}; 1470 1471static const struct si_cac_config_reg lcac_mars_pro[] = 1472{ 1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0xFFFFFFFF } 1516}; 1517 1518static const struct si_cac_config_reg cac_override_oland[] = 1519{ 1520 { 0xFFFFFFFF } 1521}; 1522 1523static const struct si_powertune_data powertune_data_oland = 1524{ 1525 ((1 << 16) | 0x6993), 1526 5, 1527 0, 1528 7, 1529 105, 1530 { 1531 0UL, 1532 0UL, 1533 7194395UL, 1534 309631529UL, 1535 -1270850L, 1536 4513710L, 1537 100 1538 }, 1539 117830498UL, 1540 12, 1541 { 1542 0, 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0 1550 }, 1551 true 1552}; 1553 1554static const struct si_powertune_data powertune_data_mars_pro = 1555{ 1556 ((1 << 16) | 0x6993), 1557 5, 1558 0, 1559 7, 1560 105, 1561 { 1562 0UL, 1563 0UL, 1564 7194395UL, 1565 309631529UL, 1566 -1270850L, 1567 4513710L, 1568 100 1569 }, 1570 117830498UL, 1571 12, 1572 { 1573 0, 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0 1581 }, 1582 true 1583}; 1584 1585static const struct si_dte_data dte_data_oland = 1586{ 1587 { 0, 0, 0, 0, 0 }, 1588 { 0, 0, 0, 0, 0 }, 1589 0, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 0, 1600 false 1601}; 1602 1603static const struct si_dte_data dte_data_mars_pro = 1604{ 1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1606 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1607 5, 1608 55000, 1609 105, 1610 0xA, 1611 1, 1612 0, 1613 0x10, 1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1617 90, 1618 true 1619}; 1620 1621static const struct si_dte_data dte_data_sun_xt = 1622{ 1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1624 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1625 5, 1626 55000, 1627 105, 1628 0xA, 1629 1, 1630 0, 1631 0x10, 1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1635 90, 1636 true 1637}; 1638 1639 1640static const struct si_cac_config_reg cac_weights_hainan[] = 1641{ 1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1702 { 0xFFFFFFFF } 1703}; 1704 1705static const struct si_powertune_data powertune_data_hainan = 1706{ 1707 ((1 << 16) | 0x6993), 1708 5, 1709 0, 1710 9, 1711 105, 1712 { 1713 0UL, 1714 0UL, 1715 7194395UL, 1716 309631529UL, 1717 -1270850L, 1718 4513710L, 1719 100 1720 }, 1721 117830498UL, 1722 12, 1723 { 1724 0, 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0 1732 }, 1733 true 1734}; 1735 1736struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1737struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1738struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1739struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1740 1741static int si_populate_voltage_value(struct radeon_device *rdev, 1742 const struct atom_voltage_table *table, 1743 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1744static int si_get_std_voltage_value(struct radeon_device *rdev, 1745 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1746 u16 *std_voltage); 1747static int si_write_smc_soft_register(struct radeon_device *rdev, 1748 u16 reg_offset, u32 value); 1749static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1750 struct rv7xx_pl *pl, 1751 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1752static int si_calculate_sclk_params(struct radeon_device *rdev, 1753 u32 engine_clock, 1754 SISLANDS_SMC_SCLK_VALUE *sclk); 1755 1756static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1757{ 1758 struct si_power_info *pi = rdev->pm.dpm.priv; 1759 1760 return pi; 1761} 1762 1763static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1764 u16 v, s32 t, u32 ileakage, u32 *leakage) 1765{ 1766 s64 kt, kv, leakage_w, i_leakage, vddc; 1767 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1768 1769 i_leakage = drm_int2fixp(ileakage / 100); 1770 vddc = div64_s64(drm_int2fixp(v), 1000); 1771 temperature = div64_s64(drm_int2fixp(t), 1000); 1772 1773 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1774 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1775 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1776 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1777 t_ref = drm_int2fixp(coeff->t_ref); 1778 1779 kt = drm_fixp_div(drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, temperature)), 1780 drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, t_ref))); 1781 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1782 1783 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1784 1785 *leakage = drm_fixp2int(leakage_w * 1000); 1786} 1787 1788static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1789 const struct ni_leakage_coeffients *coeff, 1790 u16 v, 1791 s32 t, 1792 u32 i_leakage, 1793 u32 *leakage) 1794{ 1795 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1796} 1797 1798static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1799 const u32 fixed_kt, u16 v, 1800 u32 ileakage, u32 *leakage) 1801{ 1802 s64 kt, kv, leakage_w, i_leakage, vddc; 1803 1804 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1805 vddc = div64_s64(drm_int2fixp(v), 1000); 1806 1807 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1808 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1809 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1810 1811 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1812 1813 *leakage = drm_fixp2int(leakage_w * 1000); 1814} 1815 1816static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1817 const struct ni_leakage_coeffients *coeff, 1818 const u32 fixed_kt, 1819 u16 v, 1820 u32 i_leakage, 1821 u32 *leakage) 1822{ 1823 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1824} 1825 1826 1827static void si_update_dte_from_pl2(struct radeon_device *rdev, 1828 struct si_dte_data *dte_data) 1829{ 1830 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1831 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1832 u32 k = dte_data->k; 1833 u32 t_max = dte_data->max_t; 1834 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1835 u32 t_0 = dte_data->t0; 1836 u32 i; 1837 1838 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1839 dte_data->tdep_count = 3; 1840 1841 for (i = 0; i < k; i++) { 1842 dte_data->r[i] = 1843 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1844 (p_limit2 * (u32)100); 1845 } 1846 1847 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1848 1849 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1850 dte_data->tdep_r[i] = dte_data->r[4]; 1851 } 1852 } else { 1853 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1854 } 1855} 1856 1857static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1858{ 1859 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1860 struct si_power_info *si_pi = si_get_pi(rdev); 1861 bool update_dte_from_pl2 = false; 1862 1863 if (rdev->family == CHIP_TAHITI) { 1864 si_pi->cac_weights = cac_weights_tahiti; 1865 si_pi->lcac_config = lcac_tahiti; 1866 si_pi->cac_override = cac_override_tahiti; 1867 si_pi->powertune_data = &powertune_data_tahiti; 1868 si_pi->dte_data = dte_data_tahiti; 1869 1870 switch (rdev->pdev->device) { 1871 case 0x6798: 1872 si_pi->dte_data.enable_dte_by_default = true; 1873 break; 1874 case 0x6799: 1875 si_pi->dte_data = dte_data_new_zealand; 1876 break; 1877 case 0x6790: 1878 case 0x6791: 1879 case 0x6792: 1880 case 0x679E: 1881 si_pi->dte_data = dte_data_aruba_pro; 1882 update_dte_from_pl2 = true; 1883 break; 1884 case 0x679B: 1885 si_pi->dte_data = dte_data_malta; 1886 update_dte_from_pl2 = true; 1887 break; 1888 case 0x679A: 1889 si_pi->dte_data = dte_data_tahiti_pro; 1890 update_dte_from_pl2 = true; 1891 break; 1892 default: 1893 if (si_pi->dte_data.enable_dte_by_default == true) 1894 DRM_ERROR("DTE is not enabled!\n"); 1895 break; 1896 } 1897 } else if (rdev->family == CHIP_PITCAIRN) { 1898 switch (rdev->pdev->device) { 1899 case 0x6810: 1900 case 0x6818: 1901 si_pi->cac_weights = cac_weights_pitcairn; 1902 si_pi->lcac_config = lcac_pitcairn; 1903 si_pi->cac_override = cac_override_pitcairn; 1904 si_pi->powertune_data = &powertune_data_pitcairn; 1905 si_pi->dte_data = dte_data_curacao_xt; 1906 update_dte_from_pl2 = true; 1907 break; 1908 case 0x6819: 1909 case 0x6811: 1910 si_pi->cac_weights = cac_weights_pitcairn; 1911 si_pi->lcac_config = lcac_pitcairn; 1912 si_pi->cac_override = cac_override_pitcairn; 1913 si_pi->powertune_data = &powertune_data_pitcairn; 1914 si_pi->dte_data = dte_data_curacao_pro; 1915 update_dte_from_pl2 = true; 1916 break; 1917 case 0x6800: 1918 case 0x6806: 1919 si_pi->cac_weights = cac_weights_pitcairn; 1920 si_pi->lcac_config = lcac_pitcairn; 1921 si_pi->cac_override = cac_override_pitcairn; 1922 si_pi->powertune_data = &powertune_data_pitcairn; 1923 si_pi->dte_data = dte_data_neptune_xt; 1924 update_dte_from_pl2 = true; 1925 break; 1926 default: 1927 si_pi->cac_weights = cac_weights_pitcairn; 1928 si_pi->lcac_config = lcac_pitcairn; 1929 si_pi->cac_override = cac_override_pitcairn; 1930 si_pi->powertune_data = &powertune_data_pitcairn; 1931 si_pi->dte_data = dte_data_pitcairn; 1932 } 1933 } else if (rdev->family == CHIP_VERDE) { 1934 si_pi->lcac_config = lcac_cape_verde; 1935 si_pi->cac_override = cac_override_cape_verde; 1936 si_pi->powertune_data = &powertune_data_cape_verde; 1937 1938 switch (rdev->pdev->device) { 1939 case 0x683B: 1940 case 0x683F: 1941 case 0x6829: 1942 si_pi->cac_weights = cac_weights_cape_verde_pro; 1943 si_pi->dte_data = dte_data_cape_verde; 1944 break; 1945 case 0x6825: 1946 case 0x6827: 1947 si_pi->cac_weights = cac_weights_heathrow; 1948 si_pi->dte_data = dte_data_cape_verde; 1949 break; 1950 case 0x6824: 1951 case 0x682D: 1952 si_pi->cac_weights = cac_weights_chelsea_xt; 1953 si_pi->dte_data = dte_data_cape_verde; 1954 break; 1955 case 0x682F: 1956 si_pi->cac_weights = cac_weights_chelsea_pro; 1957 si_pi->dte_data = dte_data_cape_verde; 1958 break; 1959 case 0x6820: 1960 si_pi->cac_weights = cac_weights_heathrow; 1961 si_pi->dte_data = dte_data_venus_xtx; 1962 break; 1963 case 0x6821: 1964 si_pi->cac_weights = cac_weights_heathrow; 1965 si_pi->dte_data = dte_data_venus_xt; 1966 break; 1967 case 0x6823: 1968 si_pi->cac_weights = cac_weights_chelsea_pro; 1969 si_pi->dte_data = dte_data_venus_pro; 1970 break; 1971 case 0x682B: 1972 si_pi->cac_weights = cac_weights_chelsea_pro; 1973 si_pi->dte_data = dte_data_venus_pro; 1974 break; 1975 default: 1976 si_pi->cac_weights = cac_weights_cape_verde; 1977 si_pi->dte_data = dte_data_cape_verde; 1978 break; 1979 } 1980 } else if (rdev->family == CHIP_OLAND) { 1981 switch (rdev->pdev->device) { 1982 case 0x6601: 1983 case 0x6621: 1984 case 0x6603: 1985 si_pi->cac_weights = cac_weights_mars_pro; 1986 si_pi->lcac_config = lcac_mars_pro; 1987 si_pi->cac_override = cac_override_oland; 1988 si_pi->powertune_data = &powertune_data_mars_pro; 1989 si_pi->dte_data = dte_data_mars_pro; 1990 update_dte_from_pl2 = true; 1991 break; 1992 case 0x6600: 1993 case 0x6606: 1994 case 0x6620: 1995 si_pi->cac_weights = cac_weights_mars_xt; 1996 si_pi->lcac_config = lcac_mars_pro; 1997 si_pi->cac_override = cac_override_oland; 1998 si_pi->powertune_data = &powertune_data_mars_pro; 1999 si_pi->dte_data = dte_data_mars_pro; 2000 update_dte_from_pl2 = true; 2001 break; 2002 case 0x6611: 2003 si_pi->cac_weights = cac_weights_oland_pro; 2004 si_pi->lcac_config = lcac_mars_pro; 2005 si_pi->cac_override = cac_override_oland; 2006 si_pi->powertune_data = &powertune_data_mars_pro; 2007 si_pi->dte_data = dte_data_mars_pro; 2008 update_dte_from_pl2 = true; 2009 break; 2010 case 0x6610: 2011 si_pi->cac_weights = cac_weights_oland_xt; 2012 si_pi->lcac_config = lcac_mars_pro; 2013 si_pi->cac_override = cac_override_oland; 2014 si_pi->powertune_data = &powertune_data_mars_pro; 2015 si_pi->dte_data = dte_data_mars_pro; 2016 update_dte_from_pl2 = true; 2017 break; 2018 default: 2019 si_pi->cac_weights = cac_weights_oland; 2020 si_pi->lcac_config = lcac_oland; 2021 si_pi->cac_override = cac_override_oland; 2022 si_pi->powertune_data = &powertune_data_oland; 2023 si_pi->dte_data = dte_data_oland; 2024 break; 2025 } 2026 } else if (rdev->family == CHIP_HAINAN) { 2027 si_pi->cac_weights = cac_weights_hainan; 2028 si_pi->lcac_config = lcac_oland; 2029 si_pi->cac_override = cac_override_oland; 2030 si_pi->powertune_data = &powertune_data_hainan; 2031 si_pi->dte_data = dte_data_sun_xt; 2032 update_dte_from_pl2 = true; 2033 } else { 2034 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2035 return; 2036 } 2037 2038 ni_pi->enable_power_containment = false; 2039 ni_pi->enable_cac = false; 2040 ni_pi->enable_sq_ramping = false; 2041 si_pi->enable_dte = false; 2042 2043 if (si_pi->powertune_data->enable_powertune_by_default) { 2044 ni_pi->enable_power_containment= true; 2045 ni_pi->enable_cac = true; 2046 if (si_pi->dte_data.enable_dte_by_default) { 2047 si_pi->enable_dte = true; 2048 if (update_dte_from_pl2) 2049 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2050 2051 } 2052 ni_pi->enable_sq_ramping = true; 2053 } 2054 2055 ni_pi->driver_calculate_cac_leakage = true; 2056 ni_pi->cac_configuration_required = true; 2057 2058 if (ni_pi->cac_configuration_required) { 2059 ni_pi->support_cac_long_term_average = true; 2060 si_pi->dyn_powertune_data.l2_lta_window_size = 2061 si_pi->powertune_data->l2_lta_window_size_default; 2062 si_pi->dyn_powertune_data.lts_truncate = 2063 si_pi->powertune_data->lts_truncate_default; 2064 } else { 2065 ni_pi->support_cac_long_term_average = false; 2066 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2067 si_pi->dyn_powertune_data.lts_truncate = 0; 2068 } 2069 2070 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2071} 2072 2073static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2074{ 2075 return 1; 2076} 2077 2078static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2079{ 2080 u32 xclk; 2081 u32 wintime; 2082 u32 cac_window; 2083 u32 cac_window_size; 2084 2085 xclk = radeon_get_xclk(rdev); 2086 2087 if (xclk == 0) 2088 return 0; 2089 2090 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2091 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2092 2093 wintime = (cac_window_size * 100) / xclk; 2094 2095 return wintime; 2096} 2097 2098static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2099{ 2100 return power_in_watts; 2101} 2102 2103static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2104 bool adjust_polarity, 2105 u32 tdp_adjustment, 2106 u32 *tdp_limit, 2107 u32 *near_tdp_limit) 2108{ 2109 u32 adjustment_delta, max_tdp_limit; 2110 2111 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2112 return -EINVAL; 2113 2114 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2115 2116 if (adjust_polarity) { 2117 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2118 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2119 } else { 2120 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2121 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2122 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2123 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2124 else 2125 *near_tdp_limit = 0; 2126 } 2127 2128 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2129 return -EINVAL; 2130 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2131 return -EINVAL; 2132 2133 return 0; 2134} 2135 2136static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2137 struct radeon_ps *radeon_state) 2138{ 2139 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2140 struct si_power_info *si_pi = si_get_pi(rdev); 2141 2142 if (ni_pi->enable_power_containment) { 2143 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2144 PP_SIslands_PAPMParameters *papm_parm; 2145 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2146 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2147 u32 tdp_limit; 2148 u32 near_tdp_limit; 2149 int ret; 2150 2151 if (scaling_factor == 0) 2152 return -EINVAL; 2153 2154 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2155 2156 ret = si_calculate_adjusted_tdp_limits(rdev, 2157 false, /* ??? */ 2158 rdev->pm.dpm.tdp_adjustment, 2159 &tdp_limit, 2160 &near_tdp_limit); 2161 if (ret) 2162 return ret; 2163 2164 smc_table->dpm2Params.TDPLimit = 2165 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2166 smc_table->dpm2Params.NearTDPLimit = 2167 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2168 smc_table->dpm2Params.SafePowerLimit = 2169 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2170 2171 ret = si_copy_bytes_to_smc(rdev, 2172 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2173 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2174 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2175 sizeof(u32) * 3, 2176 si_pi->sram_end); 2177 if (ret) 2178 return ret; 2179 2180 if (si_pi->enable_ppm) { 2181 papm_parm = &si_pi->papm_parm; 2182 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2183 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2184 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2185 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2186 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2187 papm_parm->PlatformPowerLimit = 0xffffffff; 2188 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2189 2190 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2191 (u8 *)papm_parm, 2192 sizeof(PP_SIslands_PAPMParameters), 2193 si_pi->sram_end); 2194 if (ret) 2195 return ret; 2196 } 2197 } 2198 return 0; 2199} 2200 2201static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2202 struct radeon_ps *radeon_state) 2203{ 2204 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2205 struct si_power_info *si_pi = si_get_pi(rdev); 2206 2207 if (ni_pi->enable_power_containment) { 2208 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2209 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2210 int ret; 2211 2212 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2213 2214 smc_table->dpm2Params.NearTDPLimit = 2215 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2216 smc_table->dpm2Params.SafePowerLimit = 2217 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2218 2219 ret = si_copy_bytes_to_smc(rdev, 2220 (si_pi->state_table_start + 2221 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2222 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2223 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2224 sizeof(u32) * 2, 2225 si_pi->sram_end); 2226 if (ret) 2227 return ret; 2228 } 2229 2230 return 0; 2231} 2232 2233static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2234 const u16 prev_std_vddc, 2235 const u16 curr_std_vddc) 2236{ 2237 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2238 u64 prev_vddc = (u64)prev_std_vddc; 2239 u64 curr_vddc = (u64)curr_std_vddc; 2240 u64 pwr_efficiency_ratio, n, d; 2241 2242 if ((prev_vddc == 0) || (curr_vddc == 0)) 2243 return 0; 2244 2245 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2246 d = prev_vddc * prev_vddc; 2247 pwr_efficiency_ratio = div64_u64(n, d); 2248 2249 if (pwr_efficiency_ratio > (u64)0xFFFF) 2250 return 0; 2251 2252 return (u16)pwr_efficiency_ratio; 2253} 2254 2255static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2256 struct radeon_ps *radeon_state) 2257{ 2258 struct si_power_info *si_pi = si_get_pi(rdev); 2259 2260 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2261 radeon_state->vclk && radeon_state->dclk) 2262 return true; 2263 2264 return false; 2265} 2266 2267static int si_populate_power_containment_values(struct radeon_device *rdev, 2268 struct radeon_ps *radeon_state, 2269 SISLANDS_SMC_SWSTATE *smc_state) 2270{ 2271 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2272 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2273 struct ni_ps *state = ni_get_ps(radeon_state); 2274 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2275 u32 prev_sclk; 2276 u32 max_sclk; 2277 u32 min_sclk; 2278 u16 prev_std_vddc; 2279 u16 curr_std_vddc; 2280 int i; 2281 u16 pwr_efficiency_ratio; 2282 u8 max_ps_percent; 2283 bool disable_uvd_power_tune; 2284 int ret; 2285 2286 if (ni_pi->enable_power_containment == false) 2287 return 0; 2288 2289 if (state->performance_level_count == 0) 2290 return -EINVAL; 2291 2292 if (smc_state->levelCount != state->performance_level_count) 2293 return -EINVAL; 2294 2295 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2296 2297 smc_state->levels[0].dpm2.MaxPS = 0; 2298 smc_state->levels[0].dpm2.NearTDPDec = 0; 2299 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2300 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2301 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2302 2303 for (i = 1; i < state->performance_level_count; i++) { 2304 prev_sclk = state->performance_levels[i-1].sclk; 2305 max_sclk = state->performance_levels[i].sclk; 2306 if (i == 1) 2307 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2308 else 2309 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2310 2311 if (prev_sclk > max_sclk) 2312 return -EINVAL; 2313 2314 if ((max_ps_percent == 0) || 2315 (prev_sclk == max_sclk) || 2316 disable_uvd_power_tune) { 2317 min_sclk = max_sclk; 2318 } else if (i == 1) { 2319 min_sclk = prev_sclk; 2320 } else { 2321 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2322 } 2323 2324 if (min_sclk < state->performance_levels[0].sclk) 2325 min_sclk = state->performance_levels[0].sclk; 2326 2327 if (min_sclk == 0) 2328 return -EINVAL; 2329 2330 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2331 state->performance_levels[i-1].vddc, &vddc); 2332 if (ret) 2333 return ret; 2334 2335 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2336 if (ret) 2337 return ret; 2338 2339 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2340 state->performance_levels[i].vddc, &vddc); 2341 if (ret) 2342 return ret; 2343 2344 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2345 if (ret) 2346 return ret; 2347 2348 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2349 prev_std_vddc, curr_std_vddc); 2350 2351 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2352 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2353 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2354 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2355 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2356 } 2357 2358 return 0; 2359} 2360 2361static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2362 struct radeon_ps *radeon_state, 2363 SISLANDS_SMC_SWSTATE *smc_state) 2364{ 2365 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2366 struct ni_ps *state = ni_get_ps(radeon_state); 2367 u32 sq_power_throttle, sq_power_throttle2; 2368 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2369 int i; 2370 2371 if (state->performance_level_count == 0) 2372 return -EINVAL; 2373 2374 if (smc_state->levelCount != state->performance_level_count) 2375 return -EINVAL; 2376 2377 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2378 return -EINVAL; 2379 2380 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2381 enable_sq_ramping = false; 2382 2383 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2384 enable_sq_ramping = false; 2385 2386 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2387 enable_sq_ramping = false; 2388 2389 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2390 enable_sq_ramping = false; 2391 2392 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2393 enable_sq_ramping = false; 2394 2395 for (i = 0; i < state->performance_level_count; i++) { 2396 sq_power_throttle = 0; 2397 sq_power_throttle2 = 0; 2398 2399 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2400 enable_sq_ramping) { 2401 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2402 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2403 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2404 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2405 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2406 } else { 2407 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2408 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2409 } 2410 2411 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2412 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2413 } 2414 2415 return 0; 2416} 2417 2418static int si_enable_power_containment(struct radeon_device *rdev, 2419 struct radeon_ps *radeon_new_state, 2420 bool enable) 2421{ 2422 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2423 PPSMC_Result smc_result; 2424 int ret = 0; 2425 2426 if (ni_pi->enable_power_containment) { 2427 if (enable) { 2428 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2429 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2430 if (smc_result != PPSMC_Result_OK) { 2431 ret = -EINVAL; 2432 ni_pi->pc_enabled = false; 2433 } else { 2434 ni_pi->pc_enabled = true; 2435 } 2436 } 2437 } else { 2438 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2439 if (smc_result != PPSMC_Result_OK) 2440 ret = -EINVAL; 2441 ni_pi->pc_enabled = false; 2442 } 2443 } 2444 2445 return ret; 2446} 2447 2448static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2449{ 2450 struct si_power_info *si_pi = si_get_pi(rdev); 2451 int ret = 0; 2452 struct si_dte_data *dte_data = &si_pi->dte_data; 2453 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2454 u32 table_size; 2455 u8 tdep_count; 2456 u32 i; 2457 2458 if (dte_data == NULL) 2459 si_pi->enable_dte = false; 2460 2461 if (si_pi->enable_dte == false) 2462 return 0; 2463 2464 if (dte_data->k <= 0) 2465 return -EINVAL; 2466 2467 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2468 if (dte_tables == NULL) { 2469 si_pi->enable_dte = false; 2470 return -ENOMEM; 2471 } 2472 2473 table_size = dte_data->k; 2474 2475 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2476 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2477 2478 tdep_count = dte_data->tdep_count; 2479 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2480 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2481 2482 dte_tables->K = cpu_to_be32(table_size); 2483 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2484 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2485 dte_tables->WindowSize = dte_data->window_size; 2486 dte_tables->temp_select = dte_data->temp_select; 2487 dte_tables->DTE_mode = dte_data->dte_mode; 2488 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2489 2490 if (tdep_count > 0) 2491 table_size--; 2492 2493 for (i = 0; i < table_size; i++) { 2494 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2495 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2496 } 2497 2498 dte_tables->Tdep_count = tdep_count; 2499 2500 for (i = 0; i < (u32)tdep_count; i++) { 2501 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2502 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2503 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2504 } 2505 2506 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2507 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2508 kfree(dte_tables); 2509 2510 return ret; 2511} 2512 2513static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2514 u16 *max, u16 *min) 2515{ 2516 struct si_power_info *si_pi = si_get_pi(rdev); 2517 struct radeon_cac_leakage_table *table = 2518 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2519 u32 i; 2520 u32 v0_loadline; 2521 2522 2523 if (table == NULL) 2524 return -EINVAL; 2525 2526 *max = 0; 2527 *min = 0xFFFF; 2528 2529 for (i = 0; i < table->count; i++) { 2530 if (table->entries[i].vddc > *max) 2531 *max = table->entries[i].vddc; 2532 if (table->entries[i].vddc < *min) 2533 *min = table->entries[i].vddc; 2534 } 2535 2536 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2537 return -EINVAL; 2538 2539 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2540 2541 if (v0_loadline > 0xFFFFUL) 2542 return -EINVAL; 2543 2544 *min = (u16)v0_loadline; 2545 2546 if ((*min > *max) || (*max == 0) || (*min == 0)) 2547 return -EINVAL; 2548 2549 return 0; 2550} 2551 2552static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2553{ 2554 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2555 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2556} 2557 2558static int si_init_dte_leakage_table(struct radeon_device *rdev, 2559 PP_SIslands_CacConfig *cac_tables, 2560 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2561 u16 t0, u16 t_step) 2562{ 2563 struct si_power_info *si_pi = si_get_pi(rdev); 2564 u32 leakage; 2565 unsigned int i, j; 2566 s32 t; 2567 u32 smc_leakage; 2568 u32 scaling_factor; 2569 u16 voltage; 2570 2571 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2572 2573 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2574 t = (1000 * (i * t_step + t0)); 2575 2576 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2577 voltage = vddc_max - (vddc_step * j); 2578 2579 si_calculate_leakage_for_v_and_t(rdev, 2580 &si_pi->powertune_data->leakage_coefficients, 2581 voltage, 2582 t, 2583 si_pi->dyn_powertune_data.cac_leakage, 2584 &leakage); 2585 2586 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2587 2588 if (smc_leakage > 0xFFFF) 2589 smc_leakage = 0xFFFF; 2590 2591 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2592 cpu_to_be16((u16)smc_leakage); 2593 } 2594 } 2595 return 0; 2596} 2597 2598static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2599 PP_SIslands_CacConfig *cac_tables, 2600 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2601{ 2602 struct si_power_info *si_pi = si_get_pi(rdev); 2603 u32 leakage; 2604 unsigned int i, j; 2605 u32 smc_leakage; 2606 u32 scaling_factor; 2607 u16 voltage; 2608 2609 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2610 2611 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2612 voltage = vddc_max - (vddc_step * j); 2613 2614 si_calculate_leakage_for_v(rdev, 2615 &si_pi->powertune_data->leakage_coefficients, 2616 si_pi->powertune_data->fixed_kt, 2617 voltage, 2618 si_pi->dyn_powertune_data.cac_leakage, 2619 &leakage); 2620 2621 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2622 2623 if (smc_leakage > 0xFFFF) 2624 smc_leakage = 0xFFFF; 2625 2626 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2627 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2628 cpu_to_be16((u16)smc_leakage); 2629 } 2630 return 0; 2631} 2632 2633static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2634{ 2635 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2636 struct si_power_info *si_pi = si_get_pi(rdev); 2637 PP_SIslands_CacConfig *cac_tables = NULL; 2638 u16 vddc_max, vddc_min, vddc_step; 2639 u16 t0, t_step; 2640 u32 load_line_slope, reg; 2641 int ret = 0; 2642 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2643 2644 if (ni_pi->enable_cac == false) 2645 return 0; 2646 2647 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2648 if (!cac_tables) 2649 return -ENOMEM; 2650 2651 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2652 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2653 WREG32(CG_CAC_CTRL, reg); 2654 2655 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2656 si_pi->dyn_powertune_data.dc_pwr_value = 2657 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2658 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2659 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2660 2661 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2662 2663 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2664 if (ret) 2665 goto done_free; 2666 2667 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2668 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2669 t_step = 4; 2670 t0 = 60; 2671 2672 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2673 ret = si_init_dte_leakage_table(rdev, cac_tables, 2674 vddc_max, vddc_min, vddc_step, 2675 t0, t_step); 2676 else 2677 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2678 vddc_max, vddc_min, vddc_step); 2679 if (ret) 2680 goto done_free; 2681 2682 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2683 2684 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2685 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2686 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2687 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2688 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2689 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2690 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2691 cac_tables->calculation_repeats = cpu_to_be32(2); 2692 cac_tables->dc_cac = cpu_to_be32(0); 2693 cac_tables->log2_PG_LKG_SCALE = 12; 2694 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2695 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2696 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2697 2698 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2699 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2700 2701 if (ret) 2702 goto done_free; 2703 2704 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2705 2706done_free: 2707 if (ret) { 2708 ni_pi->enable_cac = false; 2709 ni_pi->enable_power_containment = false; 2710 } 2711 2712 kfree(cac_tables); 2713 2714 return 0; 2715} 2716 2717static int si_program_cac_config_registers(struct radeon_device *rdev, 2718 const struct si_cac_config_reg *cac_config_regs) 2719{ 2720 const struct si_cac_config_reg *config_regs = cac_config_regs; 2721 u32 data = 0, offset; 2722 2723 if (!config_regs) 2724 return -EINVAL; 2725 2726 while (config_regs->offset != 0xFFFFFFFF) { 2727 switch (config_regs->type) { 2728 case SISLANDS_CACCONFIG_CGIND: 2729 offset = SMC_CG_IND_START + config_regs->offset; 2730 if (offset < SMC_CG_IND_END) 2731 data = RREG32_SMC(offset); 2732 break; 2733 default: 2734 data = RREG32(config_regs->offset << 2); 2735 break; 2736 } 2737 2738 data &= ~config_regs->mask; 2739 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2740 2741 switch (config_regs->type) { 2742 case SISLANDS_CACCONFIG_CGIND: 2743 offset = SMC_CG_IND_START + config_regs->offset; 2744 if (offset < SMC_CG_IND_END) 2745 WREG32_SMC(offset, data); 2746 break; 2747 default: 2748 WREG32(config_regs->offset << 2, data); 2749 break; 2750 } 2751 config_regs++; 2752 } 2753 return 0; 2754} 2755 2756static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2757{ 2758 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2759 struct si_power_info *si_pi = si_get_pi(rdev); 2760 int ret; 2761 2762 if ((ni_pi->enable_cac == false) || 2763 (ni_pi->cac_configuration_required == false)) 2764 return 0; 2765 2766 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2767 if (ret) 2768 return ret; 2769 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2770 if (ret) 2771 return ret; 2772 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2773 if (ret) 2774 return ret; 2775 2776 return 0; 2777} 2778 2779static int si_enable_smc_cac(struct radeon_device *rdev, 2780 struct radeon_ps *radeon_new_state, 2781 bool enable) 2782{ 2783 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2784 struct si_power_info *si_pi = si_get_pi(rdev); 2785 PPSMC_Result smc_result; 2786 int ret = 0; 2787 2788 if (ni_pi->enable_cac) { 2789 if (enable) { 2790 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2791 if (ni_pi->support_cac_long_term_average) { 2792 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2793 if (smc_result != PPSMC_Result_OK) 2794 ni_pi->support_cac_long_term_average = false; 2795 } 2796 2797 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2798 if (smc_result != PPSMC_Result_OK) { 2799 ret = -EINVAL; 2800 ni_pi->cac_enabled = false; 2801 } else { 2802 ni_pi->cac_enabled = true; 2803 } 2804 2805 if (si_pi->enable_dte) { 2806 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2807 if (smc_result != PPSMC_Result_OK) 2808 ret = -EINVAL; 2809 } 2810 } 2811 } else if (ni_pi->cac_enabled) { 2812 if (si_pi->enable_dte) 2813 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2814 2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2816 2817 ni_pi->cac_enabled = false; 2818 2819 if (ni_pi->support_cac_long_term_average) 2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2821 } 2822 } 2823 return ret; 2824} 2825 2826static int si_init_smc_spll_table(struct radeon_device *rdev) 2827{ 2828 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2829 struct si_power_info *si_pi = si_get_pi(rdev); 2830 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2831 SISLANDS_SMC_SCLK_VALUE sclk_params; 2832 u32 fb_div, p_div; 2833 u32 clk_s, clk_v; 2834 u32 sclk = 0; 2835 int ret = 0; 2836 u32 tmp; 2837 int i; 2838 2839 if (si_pi->spll_table_start == 0) 2840 return -EINVAL; 2841 2842 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2843 if (spll_table == NULL) 2844 return -ENOMEM; 2845 2846 for (i = 0; i < 256; i++) { 2847 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2848 if (ret) 2849 break; 2850 2851 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2852 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2853 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2854 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2855 2856 fb_div &= ~0x00001FFF; 2857 fb_div >>= 1; 2858 clk_v >>= 6; 2859 2860 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2861 ret = -EINVAL; 2862 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2863 ret = -EINVAL; 2864 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2865 ret = -EINVAL; 2866 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2867 ret = -EINVAL; 2868 2869 if (ret) 2870 break; 2871 2872 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2873 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2874 spll_table->freq[i] = cpu_to_be32(tmp); 2875 2876 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2877 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2878 spll_table->ss[i] = cpu_to_be32(tmp); 2879 2880 sclk += 512; 2881 } 2882 2883 2884 if (!ret) 2885 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2886 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2887 si_pi->sram_end); 2888 2889 if (ret) 2890 ni_pi->enable_power_containment = false; 2891 2892 kfree(spll_table); 2893 2894 return ret; 2895} 2896 2897static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2898 struct radeon_ps *rps) 2899{ 2900 struct ni_ps *ps = ni_get_ps(rps); 2901 struct radeon_clock_and_voltage_limits *max_limits; 2902 bool disable_mclk_switching; 2903 u32 mclk, sclk; 2904 u16 vddc, vddci; 2905 int i; 2906 2907 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2908 ni_dpm_vblank_too_short(rdev)) 2909 disable_mclk_switching = true; 2910 else 2911 disable_mclk_switching = false; 2912 2913 if (rdev->pm.dpm.ac_power) 2914 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2915 else 2916 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2917 2918 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2919 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2920 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2921 } 2922 if (rdev->pm.dpm.ac_power == false) { 2923 for (i = 0; i < ps->performance_level_count; i++) { 2924 if (ps->performance_levels[i].mclk > max_limits->mclk) 2925 ps->performance_levels[i].mclk = max_limits->mclk; 2926 if (ps->performance_levels[i].sclk > max_limits->sclk) 2927 ps->performance_levels[i].sclk = max_limits->sclk; 2928 if (ps->performance_levels[i].vddc > max_limits->vddc) 2929 ps->performance_levels[i].vddc = max_limits->vddc; 2930 if (ps->performance_levels[i].vddci > max_limits->vddci) 2931 ps->performance_levels[i].vddci = max_limits->vddci; 2932 } 2933 } 2934 2935 /* XXX validate the min clocks required for display */ 2936 2937 if (disable_mclk_switching) { 2938 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2939 sclk = ps->performance_levels[0].sclk; 2940 vddc = ps->performance_levels[0].vddc; 2941 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2942 } else { 2943 sclk = ps->performance_levels[0].sclk; 2944 mclk = ps->performance_levels[0].mclk; 2945 vddc = ps->performance_levels[0].vddc; 2946 vddci = ps->performance_levels[0].vddci; 2947 } 2948 2949 /* adjusted low state */ 2950 ps->performance_levels[0].sclk = sclk; 2951 ps->performance_levels[0].mclk = mclk; 2952 ps->performance_levels[0].vddc = vddc; 2953 ps->performance_levels[0].vddci = vddci; 2954 2955 for (i = 1; i < ps->performance_level_count; i++) { 2956 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2957 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2958 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2959 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2960 } 2961 2962 if (disable_mclk_switching) { 2963 mclk = ps->performance_levels[0].mclk; 2964 for (i = 1; i < ps->performance_level_count; i++) { 2965 if (mclk < ps->performance_levels[i].mclk) 2966 mclk = ps->performance_levels[i].mclk; 2967 } 2968 for (i = 0; i < ps->performance_level_count; i++) { 2969 ps->performance_levels[i].mclk = mclk; 2970 ps->performance_levels[i].vddci = vddci; 2971 } 2972 } else { 2973 for (i = 1; i < ps->performance_level_count; i++) { 2974 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 2975 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 2976 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 2977 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 2978 } 2979 } 2980 2981 for (i = 0; i < ps->performance_level_count; i++) 2982 btc_adjust_clock_combinations(rdev, max_limits, 2983 &ps->performance_levels[i]); 2984 2985 for (i = 0; i < ps->performance_level_count; i++) { 2986 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2987 ps->performance_levels[i].sclk, 2988 max_limits->vddc, &ps->performance_levels[i].vddc); 2989 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2990 ps->performance_levels[i].mclk, 2991 max_limits->vddci, &ps->performance_levels[i].vddci); 2992 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2993 ps->performance_levels[i].mclk, 2994 max_limits->vddc, &ps->performance_levels[i].vddc); 2995 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 2996 rdev->clock.current_dispclk, 2997 max_limits->vddc, &ps->performance_levels[i].vddc); 2998 } 2999 3000 for (i = 0; i < ps->performance_level_count; i++) { 3001 btc_apply_voltage_delta_rules(rdev, 3002 max_limits->vddc, max_limits->vddci, 3003 &ps->performance_levels[i].vddc, 3004 &ps->performance_levels[i].vddci); 3005 } 3006 3007 ps->dc_compatible = true; 3008 for (i = 0; i < ps->performance_level_count; i++) { 3009 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3010 ps->dc_compatible = false; 3011 } 3012 3013} 3014 3015#if 0 3016static int si_read_smc_soft_register(struct radeon_device *rdev, 3017 u16 reg_offset, u32 *value) 3018{ 3019 struct si_power_info *si_pi = si_get_pi(rdev); 3020 3021 return si_read_smc_sram_dword(rdev, 3022 si_pi->soft_regs_start + reg_offset, value, 3023 si_pi->sram_end); 3024} 3025#endif 3026 3027static int si_write_smc_soft_register(struct radeon_device *rdev, 3028 u16 reg_offset, u32 value) 3029{ 3030 struct si_power_info *si_pi = si_get_pi(rdev); 3031 3032 return si_write_smc_sram_dword(rdev, 3033 si_pi->soft_regs_start + reg_offset, 3034 value, si_pi->sram_end); 3035} 3036 3037static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3038{ 3039 bool ret = false; 3040 u32 tmp, width, row, column, bank, density; 3041 bool is_memory_gddr5, is_special; 3042 3043 tmp = RREG32(MC_SEQ_MISC0); 3044 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3045 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3046 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3047 3048 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3049 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3050 3051 tmp = RREG32(MC_ARB_RAMCFG); 3052 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3053 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3054 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3055 3056 density = (1 << (row + column - 20 + bank)) * width; 3057 3058 if ((rdev->pdev->device == 0x6819) && 3059 is_memory_gddr5 && is_special && (density == 0x400)) 3060 ret = true; 3061 3062 return ret; 3063} 3064 3065static void si_get_leakage_vddc(struct radeon_device *rdev) 3066{ 3067 struct si_power_info *si_pi = si_get_pi(rdev); 3068 u16 vddc, count = 0; 3069 int i, ret; 3070 3071 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3072 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3073 3074 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3075 si_pi->leakage_voltage.entries[count].voltage = vddc; 3076 si_pi->leakage_voltage.entries[count].leakage_index = 3077 SISLANDS_LEAKAGE_INDEX0 + i; 3078 count++; 3079 } 3080 } 3081 si_pi->leakage_voltage.count = count; 3082} 3083 3084static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3085 u32 index, u16 *leakage_voltage) 3086{ 3087 struct si_power_info *si_pi = si_get_pi(rdev); 3088 int i; 3089 3090 if (leakage_voltage == NULL) 3091 return -EINVAL; 3092 3093 if ((index & 0xff00) != 0xff00) 3094 return -EINVAL; 3095 3096 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3097 return -EINVAL; 3098 3099 if (index < SISLANDS_LEAKAGE_INDEX0) 3100 return -EINVAL; 3101 3102 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3103 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3104 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3105 return 0; 3106 } 3107 } 3108 return -EAGAIN; 3109} 3110 3111static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3112{ 3113 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3114 bool want_thermal_protection; 3115 enum radeon_dpm_event_src dpm_event_src; 3116 3117 switch (sources) { 3118 case 0: 3119 default: 3120 want_thermal_protection = false; 3121 break; 3122 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3123 want_thermal_protection = true; 3124 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3125 break; 3126 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3127 want_thermal_protection = true; 3128 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3129 break; 3130 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3131 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3132 want_thermal_protection = true; 3133 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3134 break; 3135 } 3136 3137 if (want_thermal_protection) { 3138 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3139 if (pi->thermal_protection) 3140 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3141 } else { 3142 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3143 } 3144} 3145 3146static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3147 enum radeon_dpm_auto_throttle_src source, 3148 bool enable) 3149{ 3150 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3151 3152 if (enable) { 3153 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3154 pi->active_auto_throttle_sources |= 1 << source; 3155 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3156 } 3157 } else { 3158 if (pi->active_auto_throttle_sources & (1 << source)) { 3159 pi->active_auto_throttle_sources &= ~(1 << source); 3160 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3161 } 3162 } 3163} 3164 3165static void si_start_dpm(struct radeon_device *rdev) 3166{ 3167 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3168} 3169 3170static void si_stop_dpm(struct radeon_device *rdev) 3171{ 3172 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3173} 3174 3175static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3176{ 3177 if (enable) 3178 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3179 else 3180 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3181 3182} 3183 3184#if 0 3185static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3186 u32 thermal_level) 3187{ 3188 PPSMC_Result ret; 3189 3190 if (thermal_level == 0) { 3191 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3192 if (ret == PPSMC_Result_OK) 3193 return 0; 3194 else 3195 return -EINVAL; 3196 } 3197 return 0; 3198} 3199 3200static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3201{ 3202 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3203} 3204#endif 3205 3206#if 0 3207static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3208{ 3209 if (ac_power) 3210 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3211 0 : -EINVAL; 3212 3213 return 0; 3214} 3215#endif 3216 3217static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3218 PPSMC_Msg msg, u32 parameter) 3219{ 3220 WREG32(SMC_SCRATCH0, parameter); 3221 return si_send_msg_to_smc(rdev, msg); 3222} 3223 3224static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3225{ 3226 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3227 return -EINVAL; 3228 3229 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3230 0 : -EINVAL; 3231} 3232 3233int si_dpm_force_performance_level(struct radeon_device *rdev, 3234 enum radeon_dpm_forced_level level) 3235{ 3236 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3237 struct ni_ps *ps = ni_get_ps(rps); 3238 u32 levels; 3239 3240 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3241 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 3242 return -EINVAL; 3243 3244 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3245 return -EINVAL; 3246 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3247 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3248 return -EINVAL; 3249 3250 levels = ps->performance_level_count - 1; 3251 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3252 return -EINVAL; 3253 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3254 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3255 return -EINVAL; 3256 3257 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 3258 return -EINVAL; 3259 } 3260 3261 rdev->pm.dpm.forced_level = level; 3262 3263 return 0; 3264} 3265 3266static int si_set_boot_state(struct radeon_device *rdev) 3267{ 3268 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3269 0 : -EINVAL; 3270} 3271 3272static int si_set_sw_state(struct radeon_device *rdev) 3273{ 3274 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3275 0 : -EINVAL; 3276} 3277 3278static int si_halt_smc(struct radeon_device *rdev) 3279{ 3280 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3281 return -EINVAL; 3282 3283 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3284 0 : -EINVAL; 3285} 3286 3287static int si_resume_smc(struct radeon_device *rdev) 3288{ 3289 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3290 return -EINVAL; 3291 3292 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3293 0 : -EINVAL; 3294} 3295 3296static void si_dpm_start_smc(struct radeon_device *rdev) 3297{ 3298 si_program_jump_on_start(rdev); 3299 si_start_smc(rdev); 3300 si_start_smc_clock(rdev); 3301} 3302 3303static void si_dpm_stop_smc(struct radeon_device *rdev) 3304{ 3305 si_reset_smc(rdev); 3306 si_stop_smc_clock(rdev); 3307} 3308 3309static int si_process_firmware_header(struct radeon_device *rdev) 3310{ 3311 struct si_power_info *si_pi = si_get_pi(rdev); 3312 u32 tmp; 3313 int ret; 3314 3315 ret = si_read_smc_sram_dword(rdev, 3316 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3317 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3318 &tmp, si_pi->sram_end); 3319 if (ret) 3320 return ret; 3321 3322 si_pi->state_table_start = tmp; 3323 3324 ret = si_read_smc_sram_dword(rdev, 3325 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3326 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3327 &tmp, si_pi->sram_end); 3328 if (ret) 3329 return ret; 3330 3331 si_pi->soft_regs_start = tmp; 3332 3333 ret = si_read_smc_sram_dword(rdev, 3334 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3335 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3336 &tmp, si_pi->sram_end); 3337 if (ret) 3338 return ret; 3339 3340 si_pi->mc_reg_table_start = tmp; 3341 3342 ret = si_read_smc_sram_dword(rdev, 3343 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3344 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3345 &tmp, si_pi->sram_end); 3346 if (ret) 3347 return ret; 3348 3349 si_pi->arb_table_start = tmp; 3350 3351 ret = si_read_smc_sram_dword(rdev, 3352 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3353 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3354 &tmp, si_pi->sram_end); 3355 if (ret) 3356 return ret; 3357 3358 si_pi->cac_table_start = tmp; 3359 3360 ret = si_read_smc_sram_dword(rdev, 3361 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3362 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3363 &tmp, si_pi->sram_end); 3364 if (ret) 3365 return ret; 3366 3367 si_pi->dte_table_start = tmp; 3368 3369 ret = si_read_smc_sram_dword(rdev, 3370 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3371 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3372 &tmp, si_pi->sram_end); 3373 if (ret) 3374 return ret; 3375 3376 si_pi->spll_table_start = tmp; 3377 3378 ret = si_read_smc_sram_dword(rdev, 3379 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3380 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3381 &tmp, si_pi->sram_end); 3382 if (ret) 3383 return ret; 3384 3385 si_pi->papm_cfg_table_start = tmp; 3386 3387 return ret; 3388} 3389 3390static void si_read_clock_registers(struct radeon_device *rdev) 3391{ 3392 struct si_power_info *si_pi = si_get_pi(rdev); 3393 3394 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3395 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3396 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3397 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3398 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3399 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3400 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3401 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3402 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3403 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3404 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3405 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3406 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3407 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3408 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3409} 3410 3411static void si_enable_thermal_protection(struct radeon_device *rdev, 3412 bool enable) 3413{ 3414 if (enable) 3415 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3416 else 3417 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3418} 3419 3420static void si_enable_acpi_power_management(struct radeon_device *rdev) 3421{ 3422 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3423} 3424 3425#if 0 3426static int si_enter_ulp_state(struct radeon_device *rdev) 3427{ 3428 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3429 3430 udelay(25000); 3431 3432 return 0; 3433} 3434 3435static int si_exit_ulp_state(struct radeon_device *rdev) 3436{ 3437 int i; 3438 3439 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3440 3441 udelay(7000); 3442 3443 for (i = 0; i < rdev->usec_timeout; i++) { 3444 if (RREG32(SMC_RESP_0) == 1) 3445 break; 3446 udelay(1000); 3447 } 3448 3449 return 0; 3450} 3451#endif 3452 3453static int si_notify_smc_display_change(struct radeon_device *rdev, 3454 bool has_display) 3455{ 3456 PPSMC_Msg msg = has_display ? 3457 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3458 3459 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3460 0 : -EINVAL; 3461} 3462 3463static void si_program_response_times(struct radeon_device *rdev) 3464{ 3465 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3466 u32 vddc_dly, acpi_dly, vbi_dly; 3467 u32 reference_clock; 3468 3469 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3470 3471 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3472 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3473 3474 if (voltage_response_time == 0) 3475 voltage_response_time = 1000; 3476 3477 acpi_delay_time = 15000; 3478 vbi_time_out = 100000; 3479 3480 reference_clock = radeon_get_xclk(rdev); 3481 3482 vddc_dly = (voltage_response_time * reference_clock) / 100; 3483 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3484 vbi_dly = (vbi_time_out * reference_clock) / 100; 3485 3486 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3487 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3488 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3489 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3490} 3491 3492static void si_program_ds_registers(struct radeon_device *rdev) 3493{ 3494 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3495 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3496 3497 if (eg_pi->sclk_deep_sleep) { 3498 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3499 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3500 ~AUTOSCALE_ON_SS_CLEAR); 3501 } 3502} 3503 3504static void si_program_display_gap(struct radeon_device *rdev) 3505{ 3506 u32 tmp, pipe; 3507 int i; 3508 3509 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3510 if (rdev->pm.dpm.new_active_crtc_count > 0) 3511 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3512 else 3513 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3514 3515 if (rdev->pm.dpm.new_active_crtc_count > 1) 3516 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3517 else 3518 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3519 3520 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3521 3522 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3523 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3524 3525 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3526 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3527 /* find the first active crtc */ 3528 for (i = 0; i < rdev->num_crtc; i++) { 3529 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3530 break; 3531 } 3532 if (i == rdev->num_crtc) 3533 pipe = 0; 3534 else 3535 pipe = i; 3536 3537 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3538 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3539 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3540 } 3541 3542 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3543} 3544 3545static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3546{ 3547 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3548 3549 if (enable) { 3550 if (pi->sclk_ss) 3551 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3552 } else { 3553 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3554 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3555 } 3556} 3557 3558static void si_setup_bsp(struct radeon_device *rdev) 3559{ 3560 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3561 u32 xclk = radeon_get_xclk(rdev); 3562 3563 r600_calculate_u_and_p(pi->asi, 3564 xclk, 3565 16, 3566 &pi->bsp, 3567 &pi->bsu); 3568 3569 r600_calculate_u_and_p(pi->pasi, 3570 xclk, 3571 16, 3572 &pi->pbsp, 3573 &pi->pbsu); 3574 3575 3576 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3577 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3578 3579 WREG32(CG_BSP, pi->dsp); 3580} 3581 3582static void si_program_git(struct radeon_device *rdev) 3583{ 3584 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3585} 3586 3587static void si_program_tp(struct radeon_device *rdev) 3588{ 3589 int i; 3590 enum r600_td td = R600_TD_DFLT; 3591 3592 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3593 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3594 3595 if (td == R600_TD_AUTO) 3596 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3597 else 3598 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3599 3600 if (td == R600_TD_UP) 3601 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3602 3603 if (td == R600_TD_DOWN) 3604 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3605} 3606 3607static void si_program_tpp(struct radeon_device *rdev) 3608{ 3609 WREG32(CG_TPC, R600_TPC_DFLT); 3610} 3611 3612static void si_program_sstp(struct radeon_device *rdev) 3613{ 3614 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3615} 3616 3617static void si_enable_display_gap(struct radeon_device *rdev) 3618{ 3619 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3620 3621 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3622 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3623 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3624 3625 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3626 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3627 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3628 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3629} 3630 3631static void si_program_vc(struct radeon_device *rdev) 3632{ 3633 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3634 3635 WREG32(CG_FTV, pi->vrc); 3636} 3637 3638static void si_clear_vc(struct radeon_device *rdev) 3639{ 3640 WREG32(CG_FTV, 0); 3641} 3642 3643static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3644{ 3645 u8 mc_para_index; 3646 3647 if (memory_clock < 10000) 3648 mc_para_index = 0; 3649 else if (memory_clock >= 80000) 3650 mc_para_index = 0x0f; 3651 else 3652 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3653 return mc_para_index; 3654} 3655 3656static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3657{ 3658 u8 mc_para_index; 3659 3660 if (strobe_mode) { 3661 if (memory_clock < 12500) 3662 mc_para_index = 0x00; 3663 else if (memory_clock > 47500) 3664 mc_para_index = 0x0f; 3665 else 3666 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3667 } else { 3668 if (memory_clock < 65000) 3669 mc_para_index = 0x00; 3670 else if (memory_clock > 135000) 3671 mc_para_index = 0x0f; 3672 else 3673 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3674 } 3675 return mc_para_index; 3676} 3677 3678static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3679{ 3680 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3681 bool strobe_mode = false; 3682 u8 result = 0; 3683 3684 if (mclk <= pi->mclk_strobe_mode_threshold) 3685 strobe_mode = true; 3686 3687 if (pi->mem_gddr5) 3688 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3689 else 3690 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3691 3692 if (strobe_mode) 3693 result |= SISLANDS_SMC_STROBE_ENABLE; 3694 3695 return result; 3696} 3697 3698static int si_upload_firmware(struct radeon_device *rdev) 3699{ 3700 struct si_power_info *si_pi = si_get_pi(rdev); 3701 int ret; 3702 3703 si_reset_smc(rdev); 3704 si_stop_smc_clock(rdev); 3705 3706 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3707 3708 return ret; 3709} 3710 3711static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3712 const struct atom_voltage_table *table, 3713 const struct radeon_phase_shedding_limits_table *limits) 3714{ 3715 u32 data, num_bits, num_levels; 3716 3717 if ((table == NULL) || (limits == NULL)) 3718 return false; 3719 3720 data = table->mask_low; 3721 3722 num_bits = hweight32(data); 3723 3724 if (num_bits == 0) 3725 return false; 3726 3727 num_levels = (1 << num_bits); 3728 3729 if (table->count != num_levels) 3730 return false; 3731 3732 if (limits->count != (num_levels - 1)) 3733 return false; 3734 3735 return true; 3736} 3737 3738static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3739 struct atom_voltage_table *voltage_table) 3740{ 3741 unsigned int i, diff; 3742 3743 if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS) 3744 return; 3745 3746 diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS; 3747 3748 for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++) 3749 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3750 3751 voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS; 3752} 3753 3754static int si_construct_voltage_tables(struct radeon_device *rdev) 3755{ 3756 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3757 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3758 struct si_power_info *si_pi = si_get_pi(rdev); 3759 int ret; 3760 3761 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3762 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3763 if (ret) 3764 return ret; 3765 3766 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3767 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table); 3768 3769 if (eg_pi->vddci_control) { 3770 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3771 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3772 if (ret) 3773 return ret; 3774 3775 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3776 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table); 3777 } 3778 3779 if (pi->mvdd_control) { 3780 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3781 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3782 3783 if (ret) { 3784 pi->mvdd_control = false; 3785 return ret; 3786 } 3787 3788 if (si_pi->mvdd_voltage_table.count == 0) { 3789 pi->mvdd_control = false; 3790 return -EINVAL; 3791 } 3792 3793 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3794 si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table); 3795 } 3796 3797 if (si_pi->vddc_phase_shed_control) { 3798 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3799 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3800 if (ret) 3801 si_pi->vddc_phase_shed_control = false; 3802 3803 if ((si_pi->vddc_phase_shed_table.count == 0) || 3804 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3805 si_pi->vddc_phase_shed_control = false; 3806 } 3807 3808 return 0; 3809} 3810 3811static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3812 const struct atom_voltage_table *voltage_table, 3813 SISLANDS_SMC_STATETABLE *table) 3814{ 3815 unsigned int i; 3816 3817 for (i = 0; i < voltage_table->count; i++) 3818 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3819} 3820 3821static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3822 SISLANDS_SMC_STATETABLE *table) 3823{ 3824 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3825 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3826 struct si_power_info *si_pi = si_get_pi(rdev); 3827 u8 i; 3828 3829 if (eg_pi->vddc_voltage_table.count) { 3830 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3831 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3832 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3833 3834 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3835 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3836 table->maxVDDCIndexInPPTable = i; 3837 break; 3838 } 3839 } 3840 } 3841 3842 if (eg_pi->vddci_voltage_table.count) { 3843 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3844 3845 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3846 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3847 } 3848 3849 3850 if (si_pi->mvdd_voltage_table.count) { 3851 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3852 3853 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3854 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3855 } 3856 3857 if (si_pi->vddc_phase_shed_control) { 3858 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3859 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3860 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3861 3862 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3863 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3864 3865 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3866 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3867 } else { 3868 si_pi->vddc_phase_shed_control = false; 3869 } 3870 } 3871 3872 return 0; 3873} 3874 3875static int si_populate_voltage_value(struct radeon_device *rdev, 3876 const struct atom_voltage_table *table, 3877 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3878{ 3879 unsigned int i; 3880 3881 for (i = 0; i < table->count; i++) { 3882 if (value <= table->entries[i].value) { 3883 voltage->index = (u8)i; 3884 voltage->value = cpu_to_be16(table->entries[i].value); 3885 break; 3886 } 3887 } 3888 3889 if (i >= table->count) 3890 return -EINVAL; 3891 3892 return 0; 3893} 3894 3895static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3896 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3897{ 3898 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3899 struct si_power_info *si_pi = si_get_pi(rdev); 3900 3901 if (pi->mvdd_control) { 3902 if (mclk <= pi->mvdd_split_frequency) 3903 voltage->index = 0; 3904 else 3905 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3906 3907 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 3908 } 3909 return 0; 3910} 3911 3912static int si_get_std_voltage_value(struct radeon_device *rdev, 3913 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 3914 u16 *std_voltage) 3915{ 3916 u16 v_index; 3917 bool voltage_found = false; 3918 *std_voltage = be16_to_cpu(voltage->value); 3919 3920 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 3921 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 3922 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 3923 return -EINVAL; 3924 3925 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3926 if (be16_to_cpu(voltage->value) == 3927 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3928 voltage_found = true; 3929 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3930 *std_voltage = 3931 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3932 else 3933 *std_voltage = 3934 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3935 break; 3936 } 3937 } 3938 3939 if (!voltage_found) { 3940 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3941 if (be16_to_cpu(voltage->value) <= 3942 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3943 voltage_found = true; 3944 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3945 *std_voltage = 3946 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3947 else 3948 *std_voltage = 3949 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3950 break; 3951 } 3952 } 3953 } 3954 } else { 3955 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3956 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 3957 } 3958 } 3959 3960 return 0; 3961} 3962 3963static int si_populate_std_voltage_value(struct radeon_device *rdev, 3964 u16 value, u8 index, 3965 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3966{ 3967 voltage->index = index; 3968 voltage->value = cpu_to_be16(value); 3969 3970 return 0; 3971} 3972 3973static int si_populate_phase_shedding_value(struct radeon_device *rdev, 3974 const struct radeon_phase_shedding_limits_table *limits, 3975 u16 voltage, u32 sclk, u32 mclk, 3976 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 3977{ 3978 unsigned int i; 3979 3980 for (i = 0; i < limits->count; i++) { 3981 if ((voltage <= limits->entries[i].voltage) && 3982 (sclk <= limits->entries[i].sclk) && 3983 (mclk <= limits->entries[i].mclk)) 3984 break; 3985 } 3986 3987 smc_voltage->phase_settings = (u8)i; 3988 3989 return 0; 3990} 3991 3992static int si_init_arb_table_index(struct radeon_device *rdev) 3993{ 3994 struct si_power_info *si_pi = si_get_pi(rdev); 3995 u32 tmp; 3996 int ret; 3997 3998 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 3999 if (ret) 4000 return ret; 4001 4002 tmp &= 0x00FFFFFF; 4003 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4004 4005 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4006} 4007 4008static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4009{ 4010 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4011} 4012 4013static int si_reset_to_default(struct radeon_device *rdev) 4014{ 4015 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4016 0 : -EINVAL; 4017} 4018 4019static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4020{ 4021 struct si_power_info *si_pi = si_get_pi(rdev); 4022 u32 tmp; 4023 int ret; 4024 4025 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4026 &tmp, si_pi->sram_end); 4027 if (ret) 4028 return ret; 4029 4030 tmp = (tmp >> 24) & 0xff; 4031 4032 if (tmp == MC_CG_ARB_FREQ_F0) 4033 return 0; 4034 4035 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4036} 4037 4038static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4039 u32 engine_clock) 4040{ 4041 u32 dram_rows; 4042 u32 dram_refresh_rate; 4043 u32 mc_arb_rfsh_rate; 4044 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4045 4046 if (tmp >= 4) 4047 dram_rows = 16384; 4048 else 4049 dram_rows = 1 << (tmp + 10); 4050 4051 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4052 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4053 4054 return mc_arb_rfsh_rate; 4055} 4056 4057static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4058 struct rv7xx_pl *pl, 4059 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4060{ 4061 u32 dram_timing; 4062 u32 dram_timing2; 4063 u32 burst_time; 4064 4065 arb_regs->mc_arb_rfsh_rate = 4066 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4067 4068 radeon_atom_set_engine_dram_timings(rdev, 4069 pl->sclk, 4070 pl->mclk); 4071 4072 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4073 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4074 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4075 4076 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4077 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4078 arb_regs->mc_arb_burst_time = (u8)burst_time; 4079 4080 return 0; 4081} 4082 4083static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4084 struct radeon_ps *radeon_state, 4085 unsigned int first_arb_set) 4086{ 4087 struct si_power_info *si_pi = si_get_pi(rdev); 4088 struct ni_ps *state = ni_get_ps(radeon_state); 4089 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4090 int i, ret = 0; 4091 4092 for (i = 0; i < state->performance_level_count; i++) { 4093 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4094 if (ret) 4095 break; 4096 ret = si_copy_bytes_to_smc(rdev, 4097 si_pi->arb_table_start + 4098 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4099 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4100 (u8 *)&arb_regs, 4101 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4102 si_pi->sram_end); 4103 if (ret) 4104 break; 4105 } 4106 4107 return ret; 4108} 4109 4110static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4111 struct radeon_ps *radeon_new_state) 4112{ 4113 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4114 SISLANDS_DRIVER_STATE_ARB_INDEX); 4115} 4116 4117static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4118 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4119{ 4120 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4121 struct si_power_info *si_pi = si_get_pi(rdev); 4122 4123 if (pi->mvdd_control) 4124 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4125 si_pi->mvdd_bootup_value, voltage); 4126 4127 return 0; 4128} 4129 4130static int si_populate_smc_initial_state(struct radeon_device *rdev, 4131 struct radeon_ps *radeon_initial_state, 4132 SISLANDS_SMC_STATETABLE *table) 4133{ 4134 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4135 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4136 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4137 struct si_power_info *si_pi = si_get_pi(rdev); 4138 u32 reg; 4139 int ret; 4140 4141 table->initialState.levels[0].mclk.vDLL_CNTL = 4142 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4143 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4144 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4145 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4146 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4147 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4148 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4149 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4150 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4151 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4152 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4153 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4154 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4155 table->initialState.levels[0].mclk.vMPLL_SS = 4156 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4157 table->initialState.levels[0].mclk.vMPLL_SS2 = 4158 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4159 4160 table->initialState.levels[0].mclk.mclk_value = 4161 cpu_to_be32(initial_state->performance_levels[0].mclk); 4162 4163 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4164 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4165 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4166 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4167 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4168 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4169 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4170 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4171 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4172 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4173 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4174 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4175 4176 table->initialState.levels[0].sclk.sclk_value = 4177 cpu_to_be32(initial_state->performance_levels[0].sclk); 4178 4179 table->initialState.levels[0].arbRefreshState = 4180 SISLANDS_INITIAL_STATE_ARB_INDEX; 4181 4182 table->initialState.levels[0].ACIndex = 0; 4183 4184 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4185 initial_state->performance_levels[0].vddc, 4186 &table->initialState.levels[0].vddc); 4187 4188 if (!ret) { 4189 u16 std_vddc; 4190 4191 ret = si_get_std_voltage_value(rdev, 4192 &table->initialState.levels[0].vddc, 4193 &std_vddc); 4194 if (!ret) 4195 si_populate_std_voltage_value(rdev, std_vddc, 4196 table->initialState.levels[0].vddc.index, 4197 &table->initialState.levels[0].std_vddc); 4198 } 4199 4200 if (eg_pi->vddci_control) 4201 si_populate_voltage_value(rdev, 4202 &eg_pi->vddci_voltage_table, 4203 initial_state->performance_levels[0].vddci, 4204 &table->initialState.levels[0].vddci); 4205 4206 if (si_pi->vddc_phase_shed_control) 4207 si_populate_phase_shedding_value(rdev, 4208 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4209 initial_state->performance_levels[0].vddc, 4210 initial_state->performance_levels[0].sclk, 4211 initial_state->performance_levels[0].mclk, 4212 &table->initialState.levels[0].vddc); 4213 4214 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4215 4216 reg = CG_R(0xffff) | CG_L(0); 4217 table->initialState.levels[0].aT = cpu_to_be32(reg); 4218 4219 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4220 4221 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4222 4223 if (pi->mem_gddr5) { 4224 table->initialState.levels[0].strobeMode = 4225 si_get_strobe_mode_settings(rdev, 4226 initial_state->performance_levels[0].mclk); 4227 4228 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4229 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4230 else 4231 table->initialState.levels[0].mcFlags = 0; 4232 } 4233 4234 table->initialState.levelCount = 1; 4235 4236 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4237 4238 table->initialState.levels[0].dpm2.MaxPS = 0; 4239 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4240 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4241 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4242 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4243 4244 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4245 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4246 4247 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4248 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4249 4250 return 0; 4251} 4252 4253static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4254 SISLANDS_SMC_STATETABLE *table) 4255{ 4256 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4257 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4258 struct si_power_info *si_pi = si_get_pi(rdev); 4259 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4260 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4261 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4262 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4263 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4264 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4265 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4266 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4267 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4268 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4269 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4270 u32 reg; 4271 int ret; 4272 4273 table->ACPIState = table->initialState; 4274 4275 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4276 4277 if (pi->acpi_vddc) { 4278 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4279 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4280 if (!ret) { 4281 u16 std_vddc; 4282 4283 ret = si_get_std_voltage_value(rdev, 4284 &table->ACPIState.levels[0].vddc, &std_vddc); 4285 if (!ret) 4286 si_populate_std_voltage_value(rdev, std_vddc, 4287 table->ACPIState.levels[0].vddc.index, 4288 &table->ACPIState.levels[0].std_vddc); 4289 } 4290 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4291 4292 if (si_pi->vddc_phase_shed_control) { 4293 si_populate_phase_shedding_value(rdev, 4294 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4295 pi->acpi_vddc, 4296 0, 4297 0, 4298 &table->ACPIState.levels[0].vddc); 4299 } 4300 } else { 4301 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4302 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4303 if (!ret) { 4304 u16 std_vddc; 4305 4306 ret = si_get_std_voltage_value(rdev, 4307 &table->ACPIState.levels[0].vddc, &std_vddc); 4308 4309 if (!ret) 4310 si_populate_std_voltage_value(rdev, std_vddc, 4311 table->ACPIState.levels[0].vddc.index, 4312 &table->ACPIState.levels[0].std_vddc); 4313 } 4314 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4315 si_pi->sys_pcie_mask, 4316 si_pi->boot_pcie_gen, 4317 RADEON_PCIE_GEN1); 4318 4319 if (si_pi->vddc_phase_shed_control) 4320 si_populate_phase_shedding_value(rdev, 4321 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4322 pi->min_vddc_in_table, 4323 0, 4324 0, 4325 &table->ACPIState.levels[0].vddc); 4326 } 4327 4328 if (pi->acpi_vddc) { 4329 if (eg_pi->acpi_vddci) 4330 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4331 eg_pi->acpi_vddci, 4332 &table->ACPIState.levels[0].vddci); 4333 } 4334 4335 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4336 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4337 4338 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4339 4340 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4341 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4342 4343 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4344 cpu_to_be32(dll_cntl); 4345 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4346 cpu_to_be32(mclk_pwrmgt_cntl); 4347 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4348 cpu_to_be32(mpll_ad_func_cntl); 4349 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4350 cpu_to_be32(mpll_dq_func_cntl); 4351 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4352 cpu_to_be32(mpll_func_cntl); 4353 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4354 cpu_to_be32(mpll_func_cntl_1); 4355 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4356 cpu_to_be32(mpll_func_cntl_2); 4357 table->ACPIState.levels[0].mclk.vMPLL_SS = 4358 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4359 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4360 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4361 4362 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4363 cpu_to_be32(spll_func_cntl); 4364 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4365 cpu_to_be32(spll_func_cntl_2); 4366 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4367 cpu_to_be32(spll_func_cntl_3); 4368 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4369 cpu_to_be32(spll_func_cntl_4); 4370 4371 table->ACPIState.levels[0].mclk.mclk_value = 0; 4372 table->ACPIState.levels[0].sclk.sclk_value = 0; 4373 4374 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4375 4376 if (eg_pi->dynamic_ac_timing) 4377 table->ACPIState.levels[0].ACIndex = 0; 4378 4379 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4380 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4381 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4382 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4383 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4384 4385 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4386 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4387 4388 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4389 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4390 4391 return 0; 4392} 4393 4394static int si_populate_ulv_state(struct radeon_device *rdev, 4395 SISLANDS_SMC_SWSTATE *state) 4396{ 4397 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4398 struct si_power_info *si_pi = si_get_pi(rdev); 4399 struct si_ulv_param *ulv = &si_pi->ulv; 4400 u32 sclk_in_sr = 1350; /* ??? */ 4401 int ret; 4402 4403 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4404 &state->levels[0]); 4405 if (!ret) { 4406 if (eg_pi->sclk_deep_sleep) { 4407 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4408 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4409 else 4410 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4411 } 4412 if (ulv->one_pcie_lane_in_ulv) 4413 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4414 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4415 state->levels[0].ACIndex = 1; 4416 state->levels[0].std_vddc = state->levels[0].vddc; 4417 state->levelCount = 1; 4418 4419 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4420 } 4421 4422 return ret; 4423} 4424 4425static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4426{ 4427 struct si_power_info *si_pi = si_get_pi(rdev); 4428 struct si_ulv_param *ulv = &si_pi->ulv; 4429 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4430 int ret; 4431 4432 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4433 &arb_regs); 4434 if (ret) 4435 return ret; 4436 4437 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4438 ulv->volt_change_delay); 4439 4440 ret = si_copy_bytes_to_smc(rdev, 4441 si_pi->arb_table_start + 4442 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4443 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4444 (u8 *)&arb_regs, 4445 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4446 si_pi->sram_end); 4447 4448 return ret; 4449} 4450 4451static void si_get_mvdd_configuration(struct radeon_device *rdev) 4452{ 4453 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4454 4455 pi->mvdd_split_frequency = 30000; 4456} 4457 4458static int si_init_smc_table(struct radeon_device *rdev) 4459{ 4460 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4461 struct si_power_info *si_pi = si_get_pi(rdev); 4462 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4463 const struct si_ulv_param *ulv = &si_pi->ulv; 4464 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4465 int ret; 4466 u32 lane_width; 4467 u32 vr_hot_gpio; 4468 4469 si_populate_smc_voltage_tables(rdev, table); 4470 4471 switch (rdev->pm.int_thermal_type) { 4472 case THERMAL_TYPE_SI: 4473 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4474 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4475 break; 4476 case THERMAL_TYPE_NONE: 4477 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4478 break; 4479 default: 4480 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4481 break; 4482 } 4483 4484 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4485 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4486 4487 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4488 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4489 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4490 } 4491 4492 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4493 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4494 4495 if (pi->mem_gddr5) 4496 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4497 4498 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4499 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4500 4501 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4502 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4503 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4504 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4505 vr_hot_gpio); 4506 } 4507 4508 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4509 if (ret) 4510 return ret; 4511 4512 ret = si_populate_smc_acpi_state(rdev, table); 4513 if (ret) 4514 return ret; 4515 4516 table->driverState = table->initialState; 4517 4518 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4519 SISLANDS_INITIAL_STATE_ARB_INDEX); 4520 if (ret) 4521 return ret; 4522 4523 if (ulv->supported && ulv->pl.vddc) { 4524 ret = si_populate_ulv_state(rdev, &table->ULVState); 4525 if (ret) 4526 return ret; 4527 4528 ret = si_program_ulv_memory_timing_parameters(rdev); 4529 if (ret) 4530 return ret; 4531 4532 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4533 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4534 4535 lane_width = radeon_get_pcie_lanes(rdev); 4536 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4537 } else { 4538 table->ULVState = table->initialState; 4539 } 4540 4541 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4542 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4543 si_pi->sram_end); 4544} 4545 4546static int si_calculate_sclk_params(struct radeon_device *rdev, 4547 u32 engine_clock, 4548 SISLANDS_SMC_SCLK_VALUE *sclk) 4549{ 4550 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4551 struct si_power_info *si_pi = si_get_pi(rdev); 4552 struct atom_clock_dividers dividers; 4553 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4554 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4555 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4556 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4557 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4558 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4559 u64 tmp; 4560 u32 reference_clock = rdev->clock.spll.reference_freq; 4561 u32 reference_divider; 4562 u32 fbdiv; 4563 int ret; 4564 4565 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4566 engine_clock, false, ÷rs); 4567 if (ret) 4568 return ret; 4569 4570 reference_divider = 1 + dividers.ref_div; 4571 4572 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4573 do_div(tmp, reference_clock); 4574 fbdiv = (u32) tmp; 4575 4576 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4577 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4578 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4579 4580 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4581 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4582 4583 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4584 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4585 spll_func_cntl_3 |= SPLL_DITHEN; 4586 4587 if (pi->sclk_ss) { 4588 struct radeon_atom_ss ss; 4589 u32 vco_freq = engine_clock * dividers.post_div; 4590 4591 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4592 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4593 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4594 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4595 4596 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4597 cg_spll_spread_spectrum |= CLK_S(clk_s); 4598 cg_spll_spread_spectrum |= SSEN; 4599 4600 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4601 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4602 } 4603 } 4604 4605 sclk->sclk_value = engine_clock; 4606 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4607 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4608 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4609 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4610 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4611 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4612 4613 return 0; 4614} 4615 4616static int si_populate_sclk_value(struct radeon_device *rdev, 4617 u32 engine_clock, 4618 SISLANDS_SMC_SCLK_VALUE *sclk) 4619{ 4620 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4621 int ret; 4622 4623 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4624 if (!ret) { 4625 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4626 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4627 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4628 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4629 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4630 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4631 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4632 } 4633 4634 return ret; 4635} 4636 4637static int si_populate_mclk_value(struct radeon_device *rdev, 4638 u32 engine_clock, 4639 u32 memory_clock, 4640 SISLANDS_SMC_MCLK_VALUE *mclk, 4641 bool strobe_mode, 4642 bool dll_state_on) 4643{ 4644 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4645 struct si_power_info *si_pi = si_get_pi(rdev); 4646 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4647 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4648 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4649 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4650 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4651 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4652 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4653 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4654 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4655 struct atom_mpll_param mpll_param; 4656 int ret; 4657 4658 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4659 if (ret) 4660 return ret; 4661 4662 mpll_func_cntl &= ~BWCTRL_MASK; 4663 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4664 4665 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4666 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4667 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4668 4669 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4670 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4671 4672 if (pi->mem_gddr5) { 4673 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4674 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4675 YCLK_POST_DIV(mpll_param.post_div); 4676 } 4677 4678 if (pi->mclk_ss) { 4679 struct radeon_atom_ss ss; 4680 u32 freq_nom; 4681 u32 tmp; 4682 u32 reference_clock = rdev->clock.mpll.reference_freq; 4683 4684 if (pi->mem_gddr5) 4685 freq_nom = memory_clock * 4; 4686 else 4687 freq_nom = memory_clock * 2; 4688 4689 tmp = freq_nom / reference_clock; 4690 tmp = tmp * tmp; 4691 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4692 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4693 u32 clks = reference_clock * 5 / ss.rate; 4694 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4695 4696 mpll_ss1 &= ~CLKV_MASK; 4697 mpll_ss1 |= CLKV(clkv); 4698 4699 mpll_ss2 &= ~CLKS_MASK; 4700 mpll_ss2 |= CLKS(clks); 4701 } 4702 } 4703 4704 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4705 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4706 4707 if (dll_state_on) 4708 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4709 else 4710 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4711 4712 mclk->mclk_value = cpu_to_be32(memory_clock); 4713 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4714 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4715 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4716 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4717 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4718 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4719 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4720 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4721 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4722 4723 return 0; 4724} 4725 4726static void si_populate_smc_sp(struct radeon_device *rdev, 4727 struct radeon_ps *radeon_state, 4728 SISLANDS_SMC_SWSTATE *smc_state) 4729{ 4730 struct ni_ps *ps = ni_get_ps(radeon_state); 4731 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4732 int i; 4733 4734 for (i = 0; i < ps->performance_level_count - 1; i++) 4735 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4736 4737 smc_state->levels[ps->performance_level_count - 1].bSP = 4738 cpu_to_be32(pi->psp); 4739} 4740 4741static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4742 struct rv7xx_pl *pl, 4743 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4744{ 4745 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4746 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4747 struct si_power_info *si_pi = si_get_pi(rdev); 4748 int ret; 4749 bool dll_state_on; 4750 u16 std_vddc; 4751 bool gmc_pg = false; 4752 4753 if (eg_pi->pcie_performance_request && 4754 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4755 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4756 else 4757 level->gen2PCIE = (u8)pl->pcie_gen; 4758 4759 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4760 if (ret) 4761 return ret; 4762 4763 level->mcFlags = 0; 4764 4765 if (pi->mclk_stutter_mode_threshold && 4766 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4767 !eg_pi->uvd_enabled && 4768 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4769 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4770 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4771 4772 if (gmc_pg) 4773 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4774 } 4775 4776 if (pi->mem_gddr5) { 4777 if (pl->mclk > pi->mclk_edc_enable_threshold) 4778 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4779 4780 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4781 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4782 4783 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4784 4785 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4786 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4787 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4788 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4789 else 4790 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4791 } else { 4792 dll_state_on = false; 4793 } 4794 } else { 4795 level->strobeMode = si_get_strobe_mode_settings(rdev, 4796 pl->mclk); 4797 4798 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4799 } 4800 4801 ret = si_populate_mclk_value(rdev, 4802 pl->sclk, 4803 pl->mclk, 4804 &level->mclk, 4805 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4806 if (ret) 4807 return ret; 4808 4809 ret = si_populate_voltage_value(rdev, 4810 &eg_pi->vddc_voltage_table, 4811 pl->vddc, &level->vddc); 4812 if (ret) 4813 return ret; 4814 4815 4816 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4817 if (ret) 4818 return ret; 4819 4820 ret = si_populate_std_voltage_value(rdev, std_vddc, 4821 level->vddc.index, &level->std_vddc); 4822 if (ret) 4823 return ret; 4824 4825 if (eg_pi->vddci_control) { 4826 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4827 pl->vddci, &level->vddci); 4828 if (ret) 4829 return ret; 4830 } 4831 4832 if (si_pi->vddc_phase_shed_control) { 4833 ret = si_populate_phase_shedding_value(rdev, 4834 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4835 pl->vddc, 4836 pl->sclk, 4837 pl->mclk, 4838 &level->vddc); 4839 if (ret) 4840 return ret; 4841 } 4842 4843 level->MaxPoweredUpCU = si_pi->max_cu; 4844 4845 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4846 4847 return ret; 4848} 4849 4850static int si_populate_smc_t(struct radeon_device *rdev, 4851 struct radeon_ps *radeon_state, 4852 SISLANDS_SMC_SWSTATE *smc_state) 4853{ 4854 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4855 struct ni_ps *state = ni_get_ps(radeon_state); 4856 u32 a_t; 4857 u32 t_l, t_h; 4858 u32 high_bsp; 4859 int i, ret; 4860 4861 if (state->performance_level_count >= 9) 4862 return -EINVAL; 4863 4864 if (state->performance_level_count < 2) { 4865 a_t = CG_R(0xffff) | CG_L(0); 4866 smc_state->levels[0].aT = cpu_to_be32(a_t); 4867 return 0; 4868 } 4869 4870 smc_state->levels[0].aT = cpu_to_be32(0); 4871 4872 for (i = 0; i <= state->performance_level_count - 2; i++) { 4873 ret = r600_calculate_at( 4874 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4875 100 * R600_AH_DFLT, 4876 state->performance_levels[i + 1].sclk, 4877 state->performance_levels[i].sclk, 4878 &t_l, 4879 &t_h); 4880 4881 if (ret) { 4882 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4883 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4884 } 4885 4886 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4887 a_t |= CG_R(t_l * pi->bsp / 20000); 4888 smc_state->levels[i].aT = cpu_to_be32(a_t); 4889 4890 high_bsp = (i == state->performance_level_count - 2) ? 4891 pi->pbsp : pi->bsp; 4892 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4893 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4894 } 4895 4896 return 0; 4897} 4898 4899static int si_disable_ulv(struct radeon_device *rdev) 4900{ 4901 struct si_power_info *si_pi = si_get_pi(rdev); 4902 struct si_ulv_param *ulv = &si_pi->ulv; 4903 4904 if (ulv->supported) 4905 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4906 0 : -EINVAL; 4907 4908 return 0; 4909} 4910 4911static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 4912 struct radeon_ps *radeon_state) 4913{ 4914 const struct si_power_info *si_pi = si_get_pi(rdev); 4915 const struct si_ulv_param *ulv = &si_pi->ulv; 4916 const struct ni_ps *state = ni_get_ps(radeon_state); 4917 int i; 4918 4919 if (state->performance_levels[0].mclk != ulv->pl.mclk) 4920 return false; 4921 4922 /* XXX validate against display requirements! */ 4923 4924 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 4925 if (rdev->clock.current_dispclk <= 4926 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 4927 if (ulv->pl.vddc < 4928 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 4929 return false; 4930 } 4931 } 4932 4933 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 4934 return false; 4935 4936 return true; 4937} 4938 4939static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 4940 struct radeon_ps *radeon_new_state) 4941{ 4942 const struct si_power_info *si_pi = si_get_pi(rdev); 4943 const struct si_ulv_param *ulv = &si_pi->ulv; 4944 4945 if (ulv->supported) { 4946 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 4947 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 4948 0 : -EINVAL; 4949 } 4950 return 0; 4951} 4952 4953static int si_convert_power_state_to_smc(struct radeon_device *rdev, 4954 struct radeon_ps *radeon_state, 4955 SISLANDS_SMC_SWSTATE *smc_state) 4956{ 4957 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4958 struct ni_power_info *ni_pi = ni_get_pi(rdev); 4959 struct si_power_info *si_pi = si_get_pi(rdev); 4960 struct ni_ps *state = ni_get_ps(radeon_state); 4961 int i, ret; 4962 u32 threshold; 4963 u32 sclk_in_sr = 1350; /* ??? */ 4964 4965 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 4966 return -EINVAL; 4967 4968 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 4969 4970 if (radeon_state->vclk && radeon_state->dclk) { 4971 eg_pi->uvd_enabled = true; 4972 if (eg_pi->smu_uvd_hs) 4973 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 4974 } else { 4975 eg_pi->uvd_enabled = false; 4976 } 4977 4978 if (state->dc_compatible) 4979 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 4980 4981 smc_state->levelCount = 0; 4982 for (i = 0; i < state->performance_level_count; i++) { 4983 if (eg_pi->sclk_deep_sleep) { 4984 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 4985 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4986 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4987 else 4988 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4989 } 4990 } 4991 4992 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 4993 &smc_state->levels[i]); 4994 smc_state->levels[i].arbRefreshState = 4995 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 4996 4997 if (ret) 4998 return ret; 4999 5000 if (ni_pi->enable_power_containment) 5001 smc_state->levels[i].displayWatermark = 5002 (state->performance_levels[i].sclk < threshold) ? 5003 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5004 else 5005 smc_state->levels[i].displayWatermark = (i < 2) ? 5006 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5007 5008 if (eg_pi->dynamic_ac_timing) 5009 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5010 else 5011 smc_state->levels[i].ACIndex = 0; 5012 5013 smc_state->levelCount++; 5014 } 5015 5016 si_write_smc_soft_register(rdev, 5017 SI_SMC_SOFT_REGISTER_watermark_threshold, 5018 threshold / 512); 5019 5020 si_populate_smc_sp(rdev, radeon_state, smc_state); 5021 5022 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5023 if (ret) 5024 ni_pi->enable_power_containment = false; 5025 5026 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5027 if (ret) 5028 ni_pi->enable_sq_ramping = false; 5029 5030 return si_populate_smc_t(rdev, radeon_state, smc_state); 5031} 5032 5033static int si_upload_sw_state(struct radeon_device *rdev, 5034 struct radeon_ps *radeon_new_state) 5035{ 5036 struct si_power_info *si_pi = si_get_pi(rdev); 5037 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5038 int ret; 5039 u32 address = si_pi->state_table_start + 5040 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5041 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5042 ((new_state->performance_level_count - 1) * 5043 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5044 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5045 5046 memset(smc_state, 0, state_size); 5047 5048 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5049 if (ret) 5050 return ret; 5051 5052 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5053 state_size, si_pi->sram_end); 5054 5055 return ret; 5056} 5057 5058static int si_upload_ulv_state(struct radeon_device *rdev) 5059{ 5060 struct si_power_info *si_pi = si_get_pi(rdev); 5061 struct si_ulv_param *ulv = &si_pi->ulv; 5062 int ret = 0; 5063 5064 if (ulv->supported && ulv->pl.vddc) { 5065 u32 address = si_pi->state_table_start + 5066 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5067 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5068 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5069 5070 memset(smc_state, 0, state_size); 5071 5072 ret = si_populate_ulv_state(rdev, smc_state); 5073 if (!ret) 5074 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5075 state_size, si_pi->sram_end); 5076 } 5077 5078 return ret; 5079} 5080 5081static int si_upload_smc_data(struct radeon_device *rdev) 5082{ 5083 struct radeon_crtc *radeon_crtc = NULL; 5084 int i; 5085 5086 if (rdev->pm.dpm.new_active_crtc_count == 0) 5087 return 0; 5088 5089 for (i = 0; i < rdev->num_crtc; i++) { 5090 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5091 radeon_crtc = rdev->mode_info.crtcs[i]; 5092 break; 5093 } 5094 } 5095 5096 if (radeon_crtc == NULL) 5097 return 0; 5098 5099 if (radeon_crtc->line_time <= 0) 5100 return 0; 5101 5102 if (si_write_smc_soft_register(rdev, 5103 SI_SMC_SOFT_REGISTER_crtc_index, 5104 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5105 return 0; 5106 5107 if (si_write_smc_soft_register(rdev, 5108 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5109 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5110 return 0; 5111 5112 if (si_write_smc_soft_register(rdev, 5113 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5114 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5115 return 0; 5116 5117 return 0; 5118} 5119 5120static int si_set_mc_special_registers(struct radeon_device *rdev, 5121 struct si_mc_reg_table *table) 5122{ 5123 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5124 u8 i, j, k; 5125 u32 temp_reg; 5126 5127 for (i = 0, j = table->last; i < table->last; i++) { 5128 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5129 return -EINVAL; 5130 switch (table->mc_reg_address[i].s1 << 2) { 5131 case MC_SEQ_MISC1: 5132 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5133 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5134 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5135 for (k = 0; k < table->num_entries; k++) 5136 table->mc_reg_table_entry[k].mc_data[j] = 5137 ((temp_reg & 0xffff0000)) | 5138 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5139 j++; 5140 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5141 return -EINVAL; 5142 5143 temp_reg = RREG32(MC_PMG_CMD_MRS); 5144 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5145 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5146 for (k = 0; k < table->num_entries; k++) { 5147 table->mc_reg_table_entry[k].mc_data[j] = 5148 (temp_reg & 0xffff0000) | 5149 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5150 if (!pi->mem_gddr5) 5151 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5152 } 5153 j++; 5154 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5155 return -EINVAL; 5156 5157 if (!pi->mem_gddr5) { 5158 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5159 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5160 for (k = 0; k < table->num_entries; k++) 5161 table->mc_reg_table_entry[k].mc_data[j] = 5162 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5163 j++; 5164 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5165 return -EINVAL; 5166 } 5167 break; 5168 case MC_SEQ_RESERVE_M: 5169 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5170 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5171 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5172 for(k = 0; k < table->num_entries; k++) 5173 table->mc_reg_table_entry[k].mc_data[j] = 5174 (temp_reg & 0xffff0000) | 5175 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5176 j++; 5177 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5178 return -EINVAL; 5179 break; 5180 default: 5181 break; 5182 } 5183 } 5184 5185 table->last = j; 5186 5187 return 0; 5188} 5189 5190static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5191{ 5192 bool result = true; 5193 5194 switch (in_reg) { 5195 case MC_SEQ_RAS_TIMING >> 2: 5196 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5197 break; 5198 case MC_SEQ_CAS_TIMING >> 2: 5199 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5200 break; 5201 case MC_SEQ_MISC_TIMING >> 2: 5202 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5203 break; 5204 case MC_SEQ_MISC_TIMING2 >> 2: 5205 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5206 break; 5207 case MC_SEQ_RD_CTL_D0 >> 2: 5208 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5209 break; 5210 case MC_SEQ_RD_CTL_D1 >> 2: 5211 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5212 break; 5213 case MC_SEQ_WR_CTL_D0 >> 2: 5214 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5215 break; 5216 case MC_SEQ_WR_CTL_D1 >> 2: 5217 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5218 break; 5219 case MC_PMG_CMD_EMRS >> 2: 5220 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5221 break; 5222 case MC_PMG_CMD_MRS >> 2: 5223 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5224 break; 5225 case MC_PMG_CMD_MRS1 >> 2: 5226 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5227 break; 5228 case MC_SEQ_PMG_TIMING >> 2: 5229 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5230 break; 5231 case MC_PMG_CMD_MRS2 >> 2: 5232 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5233 break; 5234 case MC_SEQ_WR_CTL_2 >> 2: 5235 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5236 break; 5237 default: 5238 result = false; 5239 break; 5240 } 5241 5242 return result; 5243} 5244 5245static void si_set_valid_flag(struct si_mc_reg_table *table) 5246{ 5247 u8 i, j; 5248 5249 for (i = 0; i < table->last; i++) { 5250 for (j = 1; j < table->num_entries; j++) { 5251 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5252 table->valid_flag |= 1 << i; 5253 break; 5254 } 5255 } 5256 } 5257} 5258 5259static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5260{ 5261 u32 i; 5262 u16 address; 5263 5264 for (i = 0; i < table->last; i++) 5265 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5266 address : table->mc_reg_address[i].s1; 5267 5268} 5269 5270static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5271 struct si_mc_reg_table *si_table) 5272{ 5273 u8 i, j; 5274 5275 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5276 return -EINVAL; 5277 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5278 return -EINVAL; 5279 5280 for (i = 0; i < table->last; i++) 5281 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5282 si_table->last = table->last; 5283 5284 for (i = 0; i < table->num_entries; i++) { 5285 si_table->mc_reg_table_entry[i].mclk_max = 5286 table->mc_reg_table_entry[i].mclk_max; 5287 for (j = 0; j < table->last; j++) { 5288 si_table->mc_reg_table_entry[i].mc_data[j] = 5289 table->mc_reg_table_entry[i].mc_data[j]; 5290 } 5291 } 5292 si_table->num_entries = table->num_entries; 5293 5294 return 0; 5295} 5296 5297static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5298{ 5299 struct si_power_info *si_pi = si_get_pi(rdev); 5300 struct atom_mc_reg_table *table; 5301 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5302 u8 module_index = rv770_get_memory_module_index(rdev); 5303 int ret; 5304 5305 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5306 if (!table) 5307 return -ENOMEM; 5308 5309 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5310 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5311 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5312 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5313 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5314 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5315 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5316 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5317 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5318 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5319 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5320 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5321 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5322 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5323 5324 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5325 if (ret) 5326 goto init_mc_done; 5327 5328 ret = si_copy_vbios_mc_reg_table(table, si_table); 5329 if (ret) 5330 goto init_mc_done; 5331 5332 si_set_s0_mc_reg_index(si_table); 5333 5334 ret = si_set_mc_special_registers(rdev, si_table); 5335 if (ret) 5336 goto init_mc_done; 5337 5338 si_set_valid_flag(si_table); 5339 5340init_mc_done: 5341 kfree(table); 5342 5343 return ret; 5344 5345} 5346 5347static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5348 SMC_SIslands_MCRegisters *mc_reg_table) 5349{ 5350 struct si_power_info *si_pi = si_get_pi(rdev); 5351 u32 i, j; 5352 5353 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5354 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5355 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 5356 break; 5357 mc_reg_table->address[i].s0 = 5358 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5359 mc_reg_table->address[i].s1 = 5360 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5361 i++; 5362 } 5363 } 5364 mc_reg_table->last = (u8)i; 5365} 5366 5367static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5368 SMC_SIslands_MCRegisterSet *data, 5369 u32 num_entries, u32 valid_flag) 5370{ 5371 u32 i, j; 5372 5373 for(i = 0, j = 0; j < num_entries; j++) { 5374 if (valid_flag & (1 << j)) { 5375 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5376 i++; 5377 } 5378 } 5379} 5380 5381static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5382 struct rv7xx_pl *pl, 5383 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5384{ 5385 struct si_power_info *si_pi = si_get_pi(rdev); 5386 u32 i = 0; 5387 5388 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5389 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5390 break; 5391 } 5392 5393 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5394 --i; 5395 5396 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5397 mc_reg_table_data, si_pi->mc_reg_table.last, 5398 si_pi->mc_reg_table.valid_flag); 5399} 5400 5401static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5402 struct radeon_ps *radeon_state, 5403 SMC_SIslands_MCRegisters *mc_reg_table) 5404{ 5405 struct ni_ps *state = ni_get_ps(radeon_state); 5406 int i; 5407 5408 for (i = 0; i < state->performance_level_count; i++) { 5409 si_convert_mc_reg_table_entry_to_smc(rdev, 5410 &state->performance_levels[i], 5411 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5412 } 5413} 5414 5415static int si_populate_mc_reg_table(struct radeon_device *rdev, 5416 struct radeon_ps *radeon_boot_state) 5417{ 5418 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5419 struct si_power_info *si_pi = si_get_pi(rdev); 5420 struct si_ulv_param *ulv = &si_pi->ulv; 5421 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5422 5423 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5424 5425 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5426 5427 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5428 5429 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5430 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5431 5432 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5433 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5434 si_pi->mc_reg_table.last, 5435 si_pi->mc_reg_table.valid_flag); 5436 5437 if (ulv->supported && ulv->pl.vddc != 0) 5438 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5439 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5440 else 5441 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5442 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5443 si_pi->mc_reg_table.last, 5444 si_pi->mc_reg_table.valid_flag); 5445 5446 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5447 5448 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5449 (u8 *)smc_mc_reg_table, 5450 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5451} 5452 5453static int si_upload_mc_reg_table(struct radeon_device *rdev, 5454 struct radeon_ps *radeon_new_state) 5455{ 5456 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5457 struct si_power_info *si_pi = si_get_pi(rdev); 5458 u32 address = si_pi->mc_reg_table_start + 5459 offsetof(SMC_SIslands_MCRegisters, 5460 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5461 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5462 5463 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5464 5465 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5466 5467 5468 return si_copy_bytes_to_smc(rdev, address, 5469 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5470 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5471 si_pi->sram_end); 5472 5473} 5474 5475static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5476{ 5477 if (enable) 5478 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5479 else 5480 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5481} 5482 5483static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5484 struct radeon_ps *radeon_state) 5485{ 5486 struct ni_ps *state = ni_get_ps(radeon_state); 5487 int i; 5488 u16 pcie_speed, max_speed = 0; 5489 5490 for (i = 0; i < state->performance_level_count; i++) { 5491 pcie_speed = state->performance_levels[i].pcie_gen; 5492 if (max_speed < pcie_speed) 5493 max_speed = pcie_speed; 5494 } 5495 return max_speed; 5496} 5497 5498static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5499{ 5500 u32 speed_cntl; 5501 5502 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5503 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5504 5505 return (u16)speed_cntl; 5506} 5507 5508static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5509 struct radeon_ps *radeon_new_state, 5510 struct radeon_ps *radeon_current_state) 5511{ 5512 struct si_power_info *si_pi = si_get_pi(rdev); 5513 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5514 enum radeon_pcie_gen current_link_speed; 5515 5516 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5517 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5518 else 5519 current_link_speed = si_pi->force_pcie_gen; 5520 5521 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5522 si_pi->pspp_notify_required = false; 5523 if (target_link_speed > current_link_speed) { 5524 switch (target_link_speed) { 5525#if defined(CONFIG_ACPI) 5526 case RADEON_PCIE_GEN3: 5527 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5528 break; 5529 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5530 if (current_link_speed == RADEON_PCIE_GEN2) 5531 break; 5532 case RADEON_PCIE_GEN2: 5533 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5534 break; 5535#endif 5536 default: 5537 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5538 break; 5539 } 5540 } else { 5541 if (target_link_speed < current_link_speed) 5542 si_pi->pspp_notify_required = true; 5543 } 5544} 5545 5546static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5547 struct radeon_ps *radeon_new_state, 5548 struct radeon_ps *radeon_current_state) 5549{ 5550 struct si_power_info *si_pi = si_get_pi(rdev); 5551 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5552 u8 request; 5553 5554 if (si_pi->pspp_notify_required) { 5555 if (target_link_speed == RADEON_PCIE_GEN3) 5556 request = PCIE_PERF_REQ_PECI_GEN3; 5557 else if (target_link_speed == RADEON_PCIE_GEN2) 5558 request = PCIE_PERF_REQ_PECI_GEN2; 5559 else 5560 request = PCIE_PERF_REQ_PECI_GEN1; 5561 5562 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5563 (si_get_current_pcie_speed(rdev) > 0)) 5564 return; 5565 5566#if defined(CONFIG_ACPI) 5567 radeon_acpi_pcie_performance_request(rdev, request, false); 5568#endif 5569 } 5570} 5571 5572#if 0 5573static int si_ds_request(struct radeon_device *rdev, 5574 bool ds_status_on, u32 count_write) 5575{ 5576 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5577 5578 if (eg_pi->sclk_deep_sleep) { 5579 if (ds_status_on) 5580 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5581 PPSMC_Result_OK) ? 5582 0 : -EINVAL; 5583 else 5584 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5585 PPSMC_Result_OK) ? 0 : -EINVAL; 5586 } 5587 return 0; 5588} 5589#endif 5590 5591static void si_set_max_cu_value(struct radeon_device *rdev) 5592{ 5593 struct si_power_info *si_pi = si_get_pi(rdev); 5594 5595 if (rdev->family == CHIP_VERDE) { 5596 switch (rdev->pdev->device) { 5597 case 0x6820: 5598 case 0x6825: 5599 case 0x6821: 5600 case 0x6823: 5601 case 0x6827: 5602 si_pi->max_cu = 10; 5603 break; 5604 case 0x682D: 5605 case 0x6824: 5606 case 0x682F: 5607 case 0x6826: 5608 si_pi->max_cu = 8; 5609 break; 5610 case 0x6828: 5611 case 0x6830: 5612 case 0x6831: 5613 case 0x6838: 5614 case 0x6839: 5615 case 0x683D: 5616 si_pi->max_cu = 10; 5617 break; 5618 case 0x683B: 5619 case 0x683F: 5620 case 0x6829: 5621 si_pi->max_cu = 8; 5622 break; 5623 default: 5624 si_pi->max_cu = 0; 5625 break; 5626 } 5627 } else { 5628 si_pi->max_cu = 0; 5629 } 5630} 5631 5632static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5633 struct radeon_clock_voltage_dependency_table *table) 5634{ 5635 u32 i; 5636 int j; 5637 u16 leakage_voltage; 5638 5639 if (table) { 5640 for (i = 0; i < table->count; i++) { 5641 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5642 table->entries[i].v, 5643 &leakage_voltage)) { 5644 case 0: 5645 table->entries[i].v = leakage_voltage; 5646 break; 5647 case -EAGAIN: 5648 return -EINVAL; 5649 case -EINVAL: 5650 default: 5651 break; 5652 } 5653 } 5654 5655 for (j = (table->count - 2); j >= 0; j--) { 5656 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5657 table->entries[j].v : table->entries[j + 1].v; 5658 } 5659 } 5660 return 0; 5661} 5662 5663static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5664{ 5665 int ret = 0; 5666 5667 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5668 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5669 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5670 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5671 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5672 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5673 return ret; 5674} 5675 5676static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5677 struct radeon_ps *radeon_new_state, 5678 struct radeon_ps *radeon_current_state) 5679{ 5680 u32 lane_width; 5681 u32 new_lane_width = 5682 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5683 u32 current_lane_width = 5684 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5685 5686 if (new_lane_width != current_lane_width) { 5687 radeon_set_pcie_lanes(rdev, new_lane_width); 5688 lane_width = radeon_get_pcie_lanes(rdev); 5689 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5690 } 5691} 5692 5693void si_dpm_setup_asic(struct radeon_device *rdev) 5694{ 5695 rv770_get_memory_type(rdev); 5696 si_read_clock_registers(rdev); 5697 si_enable_acpi_power_management(rdev); 5698} 5699 5700static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5701 int min_temp, int max_temp) 5702{ 5703 int low_temp = 0 * 1000; 5704 int high_temp = 255 * 1000; 5705 5706 if (low_temp < min_temp) 5707 low_temp = min_temp; 5708 if (high_temp > max_temp) 5709 high_temp = max_temp; 5710 if (high_temp < low_temp) { 5711 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5712 return -EINVAL; 5713 } 5714 5715 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5716 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5717 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5718 5719 rdev->pm.dpm.thermal.min_temp = low_temp; 5720 rdev->pm.dpm.thermal.max_temp = high_temp; 5721 5722 return 0; 5723} 5724 5725int si_dpm_enable(struct radeon_device *rdev) 5726{ 5727 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5728 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5729 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5730 int ret; 5731 5732 if (si_is_smc_running(rdev)) 5733 return -EINVAL; 5734 if (pi->voltage_control) 5735 si_enable_voltage_control(rdev, true); 5736 if (pi->mvdd_control) 5737 si_get_mvdd_configuration(rdev); 5738 if (pi->voltage_control) { 5739 ret = si_construct_voltage_tables(rdev); 5740 if (ret) { 5741 DRM_ERROR("si_construct_voltage_tables failed\n"); 5742 return ret; 5743 } 5744 } 5745 if (eg_pi->dynamic_ac_timing) { 5746 ret = si_initialize_mc_reg_table(rdev); 5747 if (ret) 5748 eg_pi->dynamic_ac_timing = false; 5749 } 5750 if (pi->dynamic_ss) 5751 si_enable_spread_spectrum(rdev, true); 5752 if (pi->thermal_protection) 5753 si_enable_thermal_protection(rdev, true); 5754 si_setup_bsp(rdev); 5755 si_program_git(rdev); 5756 si_program_tp(rdev); 5757 si_program_tpp(rdev); 5758 si_program_sstp(rdev); 5759 si_enable_display_gap(rdev); 5760 si_program_vc(rdev); 5761 ret = si_upload_firmware(rdev); 5762 if (ret) { 5763 DRM_ERROR("si_upload_firmware failed\n"); 5764 return ret; 5765 } 5766 ret = si_process_firmware_header(rdev); 5767 if (ret) { 5768 DRM_ERROR("si_process_firmware_header failed\n"); 5769 return ret; 5770 } 5771 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5772 if (ret) { 5773 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5774 return ret; 5775 } 5776 ret = si_init_smc_table(rdev); 5777 if (ret) { 5778 DRM_ERROR("si_init_smc_table failed\n"); 5779 return ret; 5780 } 5781 ret = si_init_smc_spll_table(rdev); 5782 if (ret) { 5783 DRM_ERROR("si_init_smc_spll_table failed\n"); 5784 return ret; 5785 } 5786 ret = si_init_arb_table_index(rdev); 5787 if (ret) { 5788 DRM_ERROR("si_init_arb_table_index failed\n"); 5789 return ret; 5790 } 5791 if (eg_pi->dynamic_ac_timing) { 5792 ret = si_populate_mc_reg_table(rdev, boot_ps); 5793 if (ret) { 5794 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5795 return ret; 5796 } 5797 } 5798 ret = si_initialize_smc_cac_tables(rdev); 5799 if (ret) { 5800 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5801 return ret; 5802 } 5803 ret = si_initialize_hardware_cac_manager(rdev); 5804 if (ret) { 5805 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5806 return ret; 5807 } 5808 ret = si_initialize_smc_dte_tables(rdev); 5809 if (ret) { 5810 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5811 return ret; 5812 } 5813 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5814 if (ret) { 5815 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5816 return ret; 5817 } 5818 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5819 if (ret) { 5820 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5821 return ret; 5822 } 5823 si_program_response_times(rdev); 5824 si_program_ds_registers(rdev); 5825 si_dpm_start_smc(rdev); 5826 ret = si_notify_smc_display_change(rdev, false); 5827 if (ret) { 5828 DRM_ERROR("si_notify_smc_display_change failed\n"); 5829 return ret; 5830 } 5831 si_enable_sclk_control(rdev, true); 5832 si_start_dpm(rdev); 5833 5834 if (rdev->irq.installed && 5835 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5836 PPSMC_Result result; 5837 5838 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5839 if (ret) 5840 return ret; 5841 rdev->irq.dpm_thermal = true; 5842 radeon_irq_set(rdev); 5843 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5844 5845 if (result != PPSMC_Result_OK) 5846 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5847 } 5848 5849 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5850 5851 ni_update_current_ps(rdev, boot_ps); 5852 5853 return 0; 5854} 5855 5856void si_dpm_disable(struct radeon_device *rdev) 5857{ 5858 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5859 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5860 5861 if (!si_is_smc_running(rdev)) 5862 return; 5863 si_disable_ulv(rdev); 5864 si_clear_vc(rdev); 5865 if (pi->thermal_protection) 5866 si_enable_thermal_protection(rdev, false); 5867 si_enable_power_containment(rdev, boot_ps, false); 5868 si_enable_smc_cac(rdev, boot_ps, false); 5869 si_enable_spread_spectrum(rdev, false); 5870 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5871 si_stop_dpm(rdev); 5872 si_reset_to_default(rdev); 5873 si_dpm_stop_smc(rdev); 5874 si_force_switch_to_arb_f0(rdev); 5875 5876 ni_update_current_ps(rdev, boot_ps); 5877} 5878 5879int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5880{ 5881 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5882 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5883 struct radeon_ps *new_ps = &requested_ps; 5884 5885 ni_update_requested_ps(rdev, new_ps); 5886 5887 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5888 5889 return 0; 5890} 5891 5892static int si_power_control_set_level(struct radeon_device *rdev) 5893{ 5894 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 5895 int ret; 5896 5897 ret = si_restrict_performance_levels_before_switch(rdev); 5898 if (ret) 5899 return ret; 5900 ret = si_halt_smc(rdev); 5901 if (ret) 5902 return ret; 5903 ret = si_populate_smc_tdp_limits(rdev, new_ps); 5904 if (ret) 5905 return ret; 5906 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 5907 if (ret) 5908 return ret; 5909 ret = si_resume_smc(rdev); 5910 if (ret) 5911 return ret; 5912 ret = si_set_sw_state(rdev); 5913 if (ret) 5914 return ret; 5915 return 0; 5916} 5917 5918int si_dpm_set_power_state(struct radeon_device *rdev) 5919{ 5920 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5921 struct radeon_ps *new_ps = &eg_pi->requested_rps; 5922 struct radeon_ps *old_ps = &eg_pi->current_rps; 5923 int ret; 5924 5925 ret = si_disable_ulv(rdev); 5926 if (ret) { 5927 DRM_ERROR("si_disable_ulv failed\n"); 5928 return ret; 5929 } 5930 ret = si_restrict_performance_levels_before_switch(rdev); 5931 if (ret) { 5932 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 5933 return ret; 5934 } 5935 if (eg_pi->pcie_performance_request) 5936 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5937 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 5938 ret = si_enable_power_containment(rdev, new_ps, false); 5939 if (ret) { 5940 DRM_ERROR("si_enable_power_containment failed\n"); 5941 return ret; 5942 } 5943 ret = si_enable_smc_cac(rdev, new_ps, false); 5944 if (ret) { 5945 DRM_ERROR("si_enable_smc_cac failed\n"); 5946 return ret; 5947 } 5948 ret = si_halt_smc(rdev); 5949 if (ret) { 5950 DRM_ERROR("si_halt_smc failed\n"); 5951 return ret; 5952 } 5953 ret = si_upload_sw_state(rdev, new_ps); 5954 if (ret) { 5955 DRM_ERROR("si_upload_sw_state failed\n"); 5956 return ret; 5957 } 5958 ret = si_upload_smc_data(rdev); 5959 if (ret) { 5960 DRM_ERROR("si_upload_smc_data failed\n"); 5961 return ret; 5962 } 5963 ret = si_upload_ulv_state(rdev); 5964 if (ret) { 5965 DRM_ERROR("si_upload_ulv_state failed\n"); 5966 return ret; 5967 } 5968 if (eg_pi->dynamic_ac_timing) { 5969 ret = si_upload_mc_reg_table(rdev, new_ps); 5970 if (ret) { 5971 DRM_ERROR("si_upload_mc_reg_table failed\n"); 5972 return ret; 5973 } 5974 } 5975 ret = si_program_memory_timing_parameters(rdev, new_ps); 5976 if (ret) { 5977 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 5978 return ret; 5979 } 5980 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 5981 5982 ret = si_resume_smc(rdev); 5983 if (ret) { 5984 DRM_ERROR("si_resume_smc failed\n"); 5985 return ret; 5986 } 5987 ret = si_set_sw_state(rdev); 5988 if (ret) { 5989 DRM_ERROR("si_set_sw_state failed\n"); 5990 return ret; 5991 } 5992 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 5993 if (eg_pi->pcie_performance_request) 5994 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 5995 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 5996 if (ret) { 5997 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 5998 return ret; 5999 } 6000 ret = si_enable_smc_cac(rdev, new_ps, true); 6001 if (ret) { 6002 DRM_ERROR("si_enable_smc_cac failed\n"); 6003 return ret; 6004 } 6005 ret = si_enable_power_containment(rdev, new_ps, true); 6006 if (ret) { 6007 DRM_ERROR("si_enable_power_containment failed\n"); 6008 return ret; 6009 } 6010 6011 ret = si_power_control_set_level(rdev); 6012 if (ret) { 6013 DRM_ERROR("si_power_control_set_level failed\n"); 6014 return ret; 6015 } 6016 6017#if 0 6018 /* XXX */ 6019 ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO); 6020 if (ret) { 6021 DRM_ERROR("si_dpm_force_performance_level failed\n"); 6022 return ret; 6023 } 6024#else 6025 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 6026#endif 6027 6028 return 0; 6029} 6030 6031void si_dpm_post_set_power_state(struct radeon_device *rdev) 6032{ 6033 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6034 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6035 6036 ni_update_current_ps(rdev, new_ps); 6037} 6038 6039 6040void si_dpm_reset_asic(struct radeon_device *rdev) 6041{ 6042 si_restrict_performance_levels_before_switch(rdev); 6043 si_disable_ulv(rdev); 6044 si_set_boot_state(rdev); 6045} 6046 6047void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6048{ 6049 si_program_display_gap(rdev); 6050} 6051 6052union power_info { 6053 struct _ATOM_POWERPLAY_INFO info; 6054 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6055 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6056 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6057 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6058 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6059}; 6060 6061union pplib_clock_info { 6062 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6063 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6064 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6065 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6066 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6067}; 6068 6069union pplib_power_state { 6070 struct _ATOM_PPLIB_STATE v1; 6071 struct _ATOM_PPLIB_STATE_V2 v2; 6072}; 6073 6074static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6075 struct radeon_ps *rps, 6076 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6077 u8 table_rev) 6078{ 6079 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6080 rps->class = le16_to_cpu(non_clock_info->usClassification); 6081 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6082 6083 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6084 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6085 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6086 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6087 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6088 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6089 } else { 6090 rps->vclk = 0; 6091 rps->dclk = 0; 6092 } 6093 6094 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6095 rdev->pm.dpm.boot_ps = rps; 6096 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6097 rdev->pm.dpm.uvd_ps = rps; 6098} 6099 6100static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6101 struct radeon_ps *rps, int index, 6102 union pplib_clock_info *clock_info) 6103{ 6104 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6105 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6106 struct si_power_info *si_pi = si_get_pi(rdev); 6107 struct ni_ps *ps = ni_get_ps(rps); 6108 u16 leakage_voltage; 6109 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6110 int ret; 6111 6112 ps->performance_level_count = index + 1; 6113 6114 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6115 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6116 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6117 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6118 6119 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6120 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6121 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6122 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6123 si_pi->sys_pcie_mask, 6124 si_pi->boot_pcie_gen, 6125 clock_info->si.ucPCIEGen); 6126 6127 /* patch up vddc if necessary */ 6128 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6129 &leakage_voltage); 6130 if (ret == 0) 6131 pl->vddc = leakage_voltage; 6132 6133 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6134 pi->acpi_vddc = pl->vddc; 6135 eg_pi->acpi_vddci = pl->vddci; 6136 si_pi->acpi_pcie_gen = pl->pcie_gen; 6137 } 6138 6139 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6140 index == 0) { 6141 /* XXX disable for A0 tahiti */ 6142 si_pi->ulv.supported = true; 6143 si_pi->ulv.pl = *pl; 6144 si_pi->ulv.one_pcie_lane_in_ulv = false; 6145 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6146 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6147 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6148 } 6149 6150 if (pi->min_vddc_in_table > pl->vddc) 6151 pi->min_vddc_in_table = pl->vddc; 6152 6153 if (pi->max_vddc_in_table < pl->vddc) 6154 pi->max_vddc_in_table = pl->vddc; 6155 6156 /* patch up boot state */ 6157 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6158 u16 vddc, vddci, mvdd; 6159 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6160 pl->mclk = rdev->clock.default_mclk; 6161 pl->sclk = rdev->clock.default_sclk; 6162 pl->vddc = vddc; 6163 pl->vddci = vddci; 6164 si_pi->mvdd_bootup_value = mvdd; 6165 } 6166 6167 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6168 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6169 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6170 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6171 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6172 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6173 } 6174} 6175 6176static int si_parse_power_table(struct radeon_device *rdev) 6177{ 6178 struct radeon_mode_info *mode_info = &rdev->mode_info; 6179 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6180 union pplib_power_state *power_state; 6181 int i, j, k, non_clock_array_index, clock_array_index; 6182 union pplib_clock_info *clock_info; 6183 struct _StateArray *state_array; 6184 struct _ClockInfoArray *clock_info_array; 6185 struct _NonClockInfoArray *non_clock_info_array; 6186 union power_info *power_info; 6187 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6188 u16 data_offset; 6189 u8 frev, crev; 6190 u8 *power_state_offset; 6191 struct ni_ps *ps; 6192 6193 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6194 &frev, &crev, &data_offset)) 6195 return -EINVAL; 6196 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6197 6198 state_array = (struct _StateArray *) 6199 (mode_info->atom_context->bios + data_offset + 6200 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6201 clock_info_array = (struct _ClockInfoArray *) 6202 (mode_info->atom_context->bios + data_offset + 6203 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6204 non_clock_info_array = (struct _NonClockInfoArray *) 6205 (mode_info->atom_context->bios + data_offset + 6206 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6207 6208 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6209 state_array->ucNumEntries, GFP_KERNEL); 6210 if (!rdev->pm.dpm.ps) 6211 return -ENOMEM; 6212 power_state_offset = (u8 *)state_array->states; 6213 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 6214 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 6215 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 6216 for (i = 0; i < state_array->ucNumEntries; i++) { 6217 power_state = (union pplib_power_state *)power_state_offset; 6218 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6219 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6220 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6221 if (!rdev->pm.power_state[i].clock_info) 6222 return -EINVAL; 6223 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6224 if (ps == NULL) { 6225 kfree(rdev->pm.dpm.ps); 6226 return -ENOMEM; 6227 } 6228 rdev->pm.dpm.ps[i].ps_priv = ps; 6229 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6230 non_clock_info, 6231 non_clock_info_array->ucEntrySize); 6232 k = 0; 6233 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6234 clock_array_index = power_state->v2.clockInfoIndex[j]; 6235 if (clock_array_index >= clock_info_array->ucNumEntries) 6236 continue; 6237 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6238 break; 6239 clock_info = (union pplib_clock_info *) 6240 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6241 si_parse_pplib_clock_info(rdev, 6242 &rdev->pm.dpm.ps[i], k, 6243 clock_info); 6244 k++; 6245 } 6246 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6247 } 6248 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6249 return 0; 6250} 6251 6252int si_dpm_init(struct radeon_device *rdev) 6253{ 6254 struct rv7xx_power_info *pi; 6255 struct evergreen_power_info *eg_pi; 6256 struct ni_power_info *ni_pi; 6257 struct si_power_info *si_pi; 6258 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 6259 u16 data_offset, size; 6260 u8 frev, crev; 6261 struct atom_clock_dividers dividers; 6262 int ret; 6263 u32 mask; 6264 6265 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6266 if (si_pi == NULL) 6267 return -ENOMEM; 6268 rdev->pm.dpm.priv = si_pi; 6269 ni_pi = &si_pi->ni; 6270 eg_pi = &ni_pi->eg; 6271 pi = &eg_pi->rv7xx; 6272 6273 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6274 if (ret) 6275 si_pi->sys_pcie_mask = 0; 6276 else 6277 si_pi->sys_pcie_mask = mask; 6278 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6279 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6280 6281 si_set_max_cu_value(rdev); 6282 6283 rv770_get_max_vddc(rdev); 6284 si_get_leakage_vddc(rdev); 6285 si_patch_dependency_tables_based_on_leakage(rdev); 6286 6287 pi->acpi_vddc = 0; 6288 eg_pi->acpi_vddci = 0; 6289 pi->min_vddc_in_table = 0; 6290 pi->max_vddc_in_table = 0; 6291 6292 ret = si_parse_power_table(rdev); 6293 if (ret) 6294 return ret; 6295 ret = r600_parse_extended_power_table(rdev); 6296 if (ret) 6297 return ret; 6298 6299 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6300 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6301 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6302 r600_free_extended_power_table(rdev); 6303 return -ENOMEM; 6304 } 6305 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6306 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6307 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6308 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6309 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6310 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6311 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6312 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6313 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6314 6315 if (rdev->pm.dpm.voltage_response_time == 0) 6316 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6317 if (rdev->pm.dpm.backbias_response_time == 0) 6318 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6319 6320 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6321 0, false, ÷rs); 6322 if (ret) 6323 pi->ref_div = dividers.ref_div + 1; 6324 else 6325 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6326 6327 eg_pi->smu_uvd_hs = false; 6328 6329 pi->mclk_strobe_mode_threshold = 40000; 6330 if (si_is_special_1gb_platform(rdev)) 6331 pi->mclk_stutter_mode_threshold = 0; 6332 else 6333 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6334 pi->mclk_edc_enable_threshold = 40000; 6335 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6336 6337 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6338 6339 pi->voltage_control = 6340 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT); 6341 6342 pi->mvdd_control = 6343 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT); 6344 6345 eg_pi->vddci_control = 6346 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT); 6347 6348 si_pi->vddc_phase_shed_control = 6349 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6350 6351 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 6352 &frev, &crev, &data_offset)) { 6353 pi->sclk_ss = true; 6354 pi->mclk_ss = true; 6355 pi->dynamic_ss = true; 6356 } else { 6357 pi->sclk_ss = false; 6358 pi->mclk_ss = false; 6359 pi->dynamic_ss = true; 6360 } 6361 6362 pi->asi = RV770_ASI_DFLT; 6363 pi->pasi = CYPRESS_HASI_DFLT; 6364 pi->vrc = SISLANDS_VRC_DFLT; 6365 6366 pi->gfx_clock_gating = true; 6367 6368 eg_pi->sclk_deep_sleep = true; 6369 si_pi->sclk_deep_sleep_above_low = false; 6370 6371 if (pi->gfx_clock_gating && 6372 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 6373 pi->thermal_protection = true; 6374 else 6375 pi->thermal_protection = false; 6376 6377 eg_pi->dynamic_ac_timing = true; 6378 6379 eg_pi->light_sleep = true; 6380#if defined(CONFIG_ACPI) 6381 eg_pi->pcie_performance_request = 6382 radeon_acpi_is_pcie_performance_request_supported(rdev); 6383#else 6384 eg_pi->pcie_performance_request = false; 6385#endif 6386 6387 si_pi->sram_end = SMC_RAM_END; 6388 6389 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6390 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6391 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6392 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6393 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6394 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6395 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6396 6397 si_initialize_powertune_defaults(rdev); 6398 6399 return 0; 6400} 6401 6402void si_dpm_fini(struct radeon_device *rdev) 6403{ 6404 int i; 6405 6406 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6407 kfree(rdev->pm.dpm.ps[i].ps_priv); 6408 } 6409 kfree(rdev->pm.dpm.ps); 6410 kfree(rdev->pm.dpm.priv); 6411 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6412 r600_free_extended_power_table(rdev); 6413} 6414 6415void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6416 struct seq_file *m) 6417{ 6418 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 6419 struct ni_ps *ps = ni_get_ps(rps); 6420 struct rv7xx_pl *pl; 6421 u32 current_index = 6422 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6423 CURRENT_STATE_INDEX_SHIFT; 6424 6425 if (current_index >= ps->performance_level_count) { 6426 seq_printf(m, "invalid dpm profile %d\n", current_index); 6427 } else { 6428 pl = &ps->performance_levels[current_index]; 6429 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6430 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6431 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6432 } 6433} 6434