alim15x3.c revision a345c7856e52bf8b21a5ae6a24fb824bfedefbe9
1/* 2 * Copyright (C) 1998-2000 Michel Aubry, Maintainer 3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer 4 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer 5 * 6 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org) 7 * May be copied or modified under the terms of the GNU General Public License 8 * Copyright (C) 2002 Alan Cox 9 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw> 10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> 11 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz 12 * 13 * (U)DMA capable version of ali 1533/1543(C), 1535(D) 14 * 15 ********************************************************************** 16 * 9/7/99 --Parts from the above author are included and need to be 17 * converted into standard interface, once I finish the thought. 18 * 19 * Recent changes 20 * Don't use LBA48 mode on ALi <= 0xC4 21 * Don't poke 0x79 with a non ALi northbridge 22 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang) 23 * Allow UDMA6 on revisions > 0xC4 24 * 25 * Documentation 26 * Chipset documentation available under NDA only 27 * 28 */ 29 30#include <linux/module.h> 31#include <linux/types.h> 32#include <linux/kernel.h> 33#include <linux/pci.h> 34#include <linux/ide.h> 35#include <linux/init.h> 36#include <linux/dmi.h> 37 38#include <asm/io.h> 39 40#define DRV_NAME "alim15x3" 41 42/* 43 * ALi devices are not plug in. Otherwise these static values would 44 * need to go. They ought to go away anyway 45 */ 46 47static u8 m5229_revision; 48static u8 chip_is_1543c_e; 49static struct pci_dev *isa_dev; 50 51static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on) 52{ 53 struct pci_dev *pdev = to_pci_dev(hwif->dev); 54 int pio_fifo = 0x54 + hwif->channel; 55 u8 fifo; 56 int shift = 4 * (drive->dn & 1); 57 58 pci_read_config_byte(pdev, pio_fifo, &fifo); 59 fifo &= ~(0x0F << shift); 60 fifo |= (on << shift); 61 pci_write_config_byte(pdev, pio_fifo, fifo); 62} 63 64static void ali_program_timings(ide_hwif_t *hwif, ide_drive_t *drive, 65 struct ide_timing *t) 66{ 67 struct pci_dev *dev = to_pci_dev(hwif->dev); 68 int port = hwif->channel ? 0x5c : 0x58; 69 u8 unit = drive->dn & 1; 70 71 t->setup = clamp_val(t->setup, 1, 8) & 7; 72 t->act8b = clamp_val(t->act8b, 1, 8) & 7; 73 t->rec8b = clamp_val(t->rec8b, 1, 16) & 15; 74 t->active = clamp_val(t->active, 1, 8) & 7; 75 t->recover = clamp_val(t->recover, 1, 16) & 15; 76 77 pci_write_config_byte(dev, port, t->setup); 78 pci_write_config_byte(dev, port + 1, (t->act8b << 4) | t->rec8b); 79 pci_write_config_byte(dev, port + unit + 2, 80 (t->active << 4) | t->recover); 81} 82 83/** 84 * ali_set_pio_mode - set host controller for PIO mode 85 * @hwif: port 86 * @drive: drive 87 * 88 * Program the controller for the given PIO mode. 89 */ 90 91static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 92{ 93 ide_drive_t *pair = ide_get_pair_dev(drive); 94 int bus_speed = ide_pci_clk ? ide_pci_clk : 33; 95 unsigned long T = 1000000 / bus_speed; /* PCI clock based */ 96 struct ide_timing t; 97 98 ide_timing_compute(drive, drive->pio_mode, &t, T, 1); 99 if (pair) { 100 struct ide_timing p; 101 102 ide_timing_compute(pair, pair->pio_mode, &p, T, 1); 103 ide_timing_merge(&p, &t, &t, 104 IDE_TIMING_SETUP | IDE_TIMING_8BIT); 105 if (pair->dma_mode) { 106 ide_timing_compute(pair, pair->dma_mode, &p, T, 1); 107 ide_timing_merge(&p, &t, &t, 108 IDE_TIMING_SETUP | IDE_TIMING_8BIT); 109 } 110 } 111 112 /* 113 * PIO mode => ATA FIFO on, ATAPI FIFO off 114 */ 115 ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00); 116 117 ali_program_timings(hwif, drive, &t); 118} 119 120/** 121 * ali_udma_filter - compute UDMA mask 122 * @drive: IDE device 123 * 124 * Return available UDMA modes. 125 * 126 * The actual rules for the ALi are: 127 * No UDMA on revisions <= 0x20 128 * Disk only for revisions < 0xC2 129 * Not WDC drives on M1543C-E (?) 130 */ 131 132static u8 ali_udma_filter(ide_drive_t *drive) 133{ 134 if (m5229_revision > 0x20 && m5229_revision < 0xC2) { 135 if (drive->media != ide_disk) 136 return 0; 137 if (chip_is_1543c_e && 138 strstr((char *)&drive->id[ATA_ID_PROD], "WDC ")) 139 return 0; 140 } 141 142 return drive->hwif->ultra_mask; 143} 144 145/** 146 * ali_set_dma_mode - set host controller for DMA mode 147 * @hwif: port 148 * @drive: drive 149 * 150 * Configure the hardware for the desired IDE transfer mode. 151 */ 152 153static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 154{ 155 struct pci_dev *dev = to_pci_dev(hwif->dev); 156 ide_drive_t *pair = ide_get_pair_dev(drive); 157 int bus_speed = ide_pci_clk ? ide_pci_clk : 33; 158 unsigned long T = 1000000 / bus_speed; /* PCI clock based */ 159 const u8 speed = drive->dma_mode; 160 u8 speed1 = speed; 161 u8 unit = drive->dn & 1; 162 u8 tmpbyte = 0x00; 163 int m5229_udma = (hwif->channel) ? 0x57 : 0x56; 164 struct ide_timing t; 165 166 if (speed == XFER_UDMA_6) 167 speed1 = 0x47; 168 169 if (speed < XFER_UDMA_0) { 170 u8 ultra_enable = (unit) ? 0x7f : 0xf7; 171 /* 172 * clear "ultra enable" bit 173 */ 174 pci_read_config_byte(dev, m5229_udma, &tmpbyte); 175 tmpbyte &= ultra_enable; 176 pci_write_config_byte(dev, m5229_udma, tmpbyte); 177 178 ide_timing_compute(drive, drive->dma_mode, &t, T, 1); 179 if (pair) { 180 struct ide_timing p; 181 182 ide_timing_compute(pair, pair->pio_mode, &p, T, 1); 183 ide_timing_merge(&p, &t, &t, 184 IDE_TIMING_SETUP | IDE_TIMING_8BIT); 185 if (pair->dma_mode) { 186 ide_timing_compute(pair, pair->dma_mode, 187 &p, T, 1); 188 ide_timing_merge(&p, &t, &t, 189 IDE_TIMING_SETUP | IDE_TIMING_8BIT); 190 } 191 } 192 ali_program_timings(hwif, drive, &t); 193 } else { 194 pci_read_config_byte(dev, m5229_udma, &tmpbyte); 195 tmpbyte &= (0x0f << ((1-unit) << 2)); 196 /* 197 * enable ultra dma and set timing 198 */ 199 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2)); 200 pci_write_config_byte(dev, m5229_udma, tmpbyte); 201 if (speed >= XFER_UDMA_3) { 202 pci_read_config_byte(dev, 0x4b, &tmpbyte); 203 tmpbyte |= 1; 204 pci_write_config_byte(dev, 0x4b, tmpbyte); 205 } 206 } 207} 208 209/** 210 * ali_dma_check - DMA check 211 * @drive: target device 212 * @cmd: command 213 * 214 * Returns 1 if the DMA cannot be performed, zero on success. 215 */ 216 217static int ali_dma_check(ide_drive_t *drive, struct ide_cmd *cmd) 218{ 219 if (m5229_revision < 0xC2 && drive->media != ide_disk) { 220 if (cmd->tf_flags & IDE_TFLAG_WRITE) 221 return 1; /* try PIO instead of DMA */ 222 } 223 return 0; 224} 225 226/** 227 * init_chipset_ali15x3 - Initialise an ALi IDE controller 228 * @dev: PCI device 229 * 230 * This function initializes the ALI IDE controller and where 231 * appropriate also sets up the 1533 southbridge. 232 */ 233 234static int init_chipset_ali15x3(struct pci_dev *dev) 235{ 236 unsigned long flags; 237 u8 tmpbyte; 238 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0)); 239 240 m5229_revision = dev->revision; 241 242 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL); 243 244 local_irq_save(flags); 245 246 if (m5229_revision < 0xC2) { 247 /* 248 * revision 0x20 (1543-E, 1543-F) 249 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E) 250 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7 251 */ 252 pci_read_config_byte(dev, 0x4b, &tmpbyte); 253 /* 254 * clear bit 7 255 */ 256 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); 257 /* 258 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010 259 */ 260 if (m5229_revision >= 0x20 && isa_dev) { 261 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte); 262 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0; 263 } 264 goto out; 265 } 266 267 /* 268 * 1543C-B?, 1535, 1535D, 1553 269 * Note 1: not all "motherboard" support this detection 270 * Note 2: if no udma 66 device, the detection may "error". 271 * but in this case, we will not set the device to 272 * ultra 66, the detection result is not important 273 */ 274 275 /* 276 * enable "Cable Detection", m5229, 0x4b, bit3 277 */ 278 pci_read_config_byte(dev, 0x4b, &tmpbyte); 279 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08); 280 281 /* 282 * We should only tune the 1533 enable if we are using an ALi 283 * North bridge. We might have no north found on some zany 284 * box without a device at 0:0.0. The ALi bridge will be at 285 * 0:0.0 so if we didn't find one we know what is cooking. 286 */ 287 if (north && north->vendor != PCI_VENDOR_ID_AL) 288 goto out; 289 290 if (m5229_revision < 0xC5 && isa_dev) 291 { 292 /* 293 * set south-bridge's enable bit, m1533, 0x79 294 */ 295 296 pci_read_config_byte(isa_dev, 0x79, &tmpbyte); 297 if (m5229_revision == 0xC2) { 298 /* 299 * 1543C-B0 (m1533, 0x79, bit 2) 300 */ 301 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04); 302 } else if (m5229_revision >= 0xC3) { 303 /* 304 * 1553/1535 (m1533, 0x79, bit 1) 305 */ 306 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); 307 } 308 } 309 310out: 311 /* 312 * CD_ROM DMA on (m5229, 0x53, bit0) 313 * Enable this bit even if we want to use PIO. 314 * PIO FIFO off (m5229, 0x53, bit1) 315 * The hardware will use 0x54h and 0x55h to control PIO FIFO. 316 * (Not on later devices it seems) 317 * 318 * 0x53 changes meaning on later revs - we must no touch 319 * bit 1 on them. Need to check if 0x20 is the right break. 320 */ 321 if (m5229_revision >= 0x20) { 322 pci_read_config_byte(dev, 0x53, &tmpbyte); 323 324 if (m5229_revision <= 0x20) 325 tmpbyte = (tmpbyte & (~0x02)) | 0x01; 326 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8) 327 tmpbyte |= 0x03; 328 else 329 tmpbyte |= 0x01; 330 331 pci_write_config_byte(dev, 0x53, tmpbyte); 332 } 333 pci_dev_put(north); 334 pci_dev_put(isa_dev); 335 local_irq_restore(flags); 336 return 0; 337} 338 339/* 340 * Cable special cases 341 */ 342 343static const struct dmi_system_id cable_dmi_table[] = { 344 { 345 .ident = "HP Pavilion N5430", 346 .matches = { 347 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 348 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 349 }, 350 }, 351 { 352 .ident = "Toshiba Satellite S1800-814", 353 .matches = { 354 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 355 DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"), 356 }, 357 }, 358 { } 359}; 360 361static int ali_cable_override(struct pci_dev *pdev) 362{ 363 /* Fujitsu P2000 */ 364 if (pdev->subsystem_vendor == 0x10CF && 365 pdev->subsystem_device == 0x10AF) 366 return 1; 367 368 /* Mitac 8317 (Winbook-A) and relatives */ 369 if (pdev->subsystem_vendor == 0x1071 && 370 pdev->subsystem_device == 0x8317) 371 return 1; 372 373 /* Systems by DMI */ 374 if (dmi_check_system(cable_dmi_table)) 375 return 1; 376 377 return 0; 378} 379 380/** 381 * ali_cable_detect - cable detection 382 * @hwif: IDE interface 383 * 384 * This checks if the controller and the cable are capable 385 * of UDMA66 transfers. It doesn't check the drives. 386 */ 387 388static u8 ali_cable_detect(ide_hwif_t *hwif) 389{ 390 struct pci_dev *dev = to_pci_dev(hwif->dev); 391 u8 cbl = ATA_CBL_PATA40, tmpbyte; 392 393 if (m5229_revision >= 0xC2) { 394 /* 395 * m5229 80-pin cable detection (from Host View) 396 * 397 * 0x4a bit0 is 0 => primary channel has 80-pin 398 * 0x4a bit1 is 0 => secondary channel has 80-pin 399 * 400 * Certain laptops use short but suitable cables 401 * and don't implement the detect logic. 402 */ 403 if (ali_cable_override(dev)) 404 cbl = ATA_CBL_PATA40_SHORT; 405 else { 406 pci_read_config_byte(dev, 0x4a, &tmpbyte); 407 if ((tmpbyte & (1 << hwif->channel)) == 0) 408 cbl = ATA_CBL_PATA80; 409 } 410 } 411 412 return cbl; 413} 414 415#ifndef CONFIG_SPARC64 416/** 417 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff 418 * @hwif: interface to configure 419 * 420 * Obtain the IRQ tables for an ALi based IDE solution on the PC 421 * class platforms. This part of the code isn't applicable to the 422 * Sparc systems. 423 */ 424 425static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif) 426{ 427 u8 ideic, inmir; 428 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6, 429 1, 11, 0, 12, 0, 14, 0, 15 }; 430 int irq = -1; 431 432 if (isa_dev) { 433 /* 434 * read IDE interface control 435 */ 436 pci_read_config_byte(isa_dev, 0x58, &ideic); 437 438 /* bit0, bit1 */ 439 ideic = ideic & 0x03; 440 441 /* get IRQ for IDE Controller */ 442 if ((hwif->channel && ideic == 0x03) || 443 (!hwif->channel && !ideic)) { 444 /* 445 * get SIRQ1 routing table 446 */ 447 pci_read_config_byte(isa_dev, 0x44, &inmir); 448 inmir = inmir & 0x0f; 449 irq = irq_routing_table[inmir]; 450 } else if (hwif->channel && !(ideic & 0x01)) { 451 /* 452 * get SIRQ2 routing table 453 */ 454 pci_read_config_byte(isa_dev, 0x75, &inmir); 455 inmir = inmir & 0x0f; 456 irq = irq_routing_table[inmir]; 457 } 458 if(irq >= 0) 459 hwif->irq = irq; 460 } 461} 462#else 463#define init_hwif_ali15x3 NULL 464#endif /* CONFIG_SPARC64 */ 465 466/** 467 * init_dma_ali15x3 - set up DMA on ALi15x3 468 * @hwif: IDE interface 469 * @d: IDE port info 470 * 471 * Set up the DMA functionality on the ALi 15x3. 472 */ 473 474static int __devinit init_dma_ali15x3(ide_hwif_t *hwif, 475 const struct ide_port_info *d) 476{ 477 struct pci_dev *dev = to_pci_dev(hwif->dev); 478 unsigned long base = ide_pci_dma_base(hwif, d); 479 480 if (base == 0) 481 return -1; 482 483 hwif->dma_base = base; 484 485 if (ide_pci_check_simplex(hwif, d) < 0) 486 return -1; 487 488 if (ide_pci_set_master(dev, d->name) < 0) 489 return -1; 490 491 if (!hwif->channel) 492 outb(inb(base + 2) & 0x60, base + 2); 493 494 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", 495 hwif->name, base, base + 7); 496 497 if (ide_allocate_dma_engine(hwif)) 498 return -1; 499 500 return 0; 501} 502 503static const struct ide_port_ops ali_port_ops = { 504 .set_pio_mode = ali_set_pio_mode, 505 .set_dma_mode = ali_set_dma_mode, 506 .udma_filter = ali_udma_filter, 507 .cable_detect = ali_cable_detect, 508}; 509 510static const struct ide_dma_ops ali_dma_ops = { 511 .dma_host_set = ide_dma_host_set, 512 .dma_setup = ide_dma_setup, 513 .dma_start = ide_dma_start, 514 .dma_end = ide_dma_end, 515 .dma_test_irq = ide_dma_test_irq, 516 .dma_lost_irq = ide_dma_lost_irq, 517 .dma_check = ali_dma_check, 518 .dma_timer_expiry = ide_dma_sff_timer_expiry, 519 .dma_sff_read_status = ide_dma_sff_read_status, 520}; 521 522static const struct ide_port_info ali15x3_chipset __devinitdata = { 523 .name = DRV_NAME, 524 .init_chipset = init_chipset_ali15x3, 525 .init_hwif = init_hwif_ali15x3, 526 .init_dma = init_dma_ali15x3, 527 .port_ops = &ali_port_ops, 528 .dma_ops = &sff_dma_ops, 529 .pio_mask = ATA_PIO5, 530 .swdma_mask = ATA_SWDMA2, 531 .mwdma_mask = ATA_MWDMA2, 532}; 533 534/** 535 * alim15x3_init_one - set up an ALi15x3 IDE controller 536 * @dev: PCI device to set up 537 * 538 * Perform the actual set up for an ALi15x3 that has been found by the 539 * hot plug layer. 540 */ 541 542static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id) 543{ 544 struct ide_port_info d = ali15x3_chipset; 545 u8 rev = dev->revision, idx = id->driver_data; 546 547 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */ 548 if (rev <= 0xC4) 549 d.host_flags |= IDE_HFLAG_NO_LBA48_DMA; 550 551 if (rev >= 0x20) { 552 if (rev == 0x20) 553 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; 554 555 if (rev < 0xC2) 556 d.udma_mask = ATA_UDMA2; 557 else if (rev == 0xC2 || rev == 0xC3) 558 d.udma_mask = ATA_UDMA4; 559 else if (rev == 0xC4) 560 d.udma_mask = ATA_UDMA5; 561 else 562 d.udma_mask = ATA_UDMA6; 563 564 d.dma_ops = &ali_dma_ops; 565 } else { 566 d.host_flags |= IDE_HFLAG_NO_DMA; 567 568 d.mwdma_mask = d.swdma_mask = 0; 569 } 570 571 if (idx == 0) 572 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX; 573 574 return ide_pci_init_one(dev, &d, NULL); 575} 576 577 578static const struct pci_device_id alim15x3_pci_tbl[] = { 579 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 }, 580 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 }, 581 { 0, }, 582}; 583MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl); 584 585static struct pci_driver alim15x3_pci_driver = { 586 .name = "ALI15x3_IDE", 587 .id_table = alim15x3_pci_tbl, 588 .probe = alim15x3_init_one, 589 .remove = ide_pci_remove, 590 .suspend = ide_pci_suspend, 591 .resume = ide_pci_resume, 592}; 593 594static int __init ali15x3_ide_init(void) 595{ 596 return ide_pci_register_driver(&alim15x3_pci_driver); 597} 598 599static void __exit ali15x3_ide_exit(void) 600{ 601 pci_unregister_driver(&alim15x3_pci_driver); 602} 603 604module_init(ali15x3_ide_init); 605module_exit(ali15x3_ide_exit); 606 607MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox, Bartlomiej Zolnierkiewicz"); 608MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE"); 609MODULE_LICENSE("GPL"); 610