ide-timings.c revision 4dde4492d850a4c9bcaa92e5bd7f4eebe3e2f5ab
1/* 2 * Copyright (c) 1999-2001 Vojtech Pavlik 3 * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * 19 * Should you need to contact me, the author, you can do so either by 20 * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail: 21 * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic 22 */ 23 24#include <linux/kernel.h> 25#include <linux/hdreg.h> 26#include <linux/ide.h> 27#include <linux/module.h> 28 29/* 30 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds). 31 * These were taken from ATA/ATAPI-6 standard, rev 0a, except 32 * for PIO 5, which is a nonstandard extension and UDMA6, which 33 * is currently supported only by Maxtor drives. 34 */ 35 36static struct ide_timing ide_timing[] = { 37 38 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, 39 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, 40 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, 41 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, 42 43 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, 44 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, 45 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, 46 47 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, 48 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, 49 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, 50 51 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, 52 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, 53 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, 54 55 { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, 56 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, 57 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, 58 59 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, 60 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, 61 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, 62 63 { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, 64 65 { 0xff } 66}; 67 68struct ide_timing *ide_timing_find_mode(u8 speed) 69{ 70 struct ide_timing *t; 71 72 for (t = ide_timing; t->mode != speed; t++) 73 if (t->mode == 0xff) 74 return NULL; 75 return t; 76} 77EXPORT_SYMBOL_GPL(ide_timing_find_mode); 78 79u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio) 80{ 81 u16 *id = drive->id; 82 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 83 u16 cycle = 0; 84 85 if (id[ATA_ID_FIELD_VALID] & 2) { 86 if (drive->driveid->capability & 8) 87 cycle = id[ATA_ID_EIDE_PIO_IORDY]; 88 else 89 cycle = id[ATA_ID_EIDE_PIO]; 90 91 /* conservative "downgrade" for all pre-ATA2 drives */ 92 if (pio < 3 && cycle < t->cycle) 93 cycle = 0; /* use standard timing */ 94 } 95 96 return cycle ? cycle : t->cycle; 97} 98EXPORT_SYMBOL_GPL(ide_pio_cycle_time); 99 100#define ENOUGH(v, unit) (((v) - 1) / (unit) + 1) 101#define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0) 102 103static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, 104 int T, int UT) 105{ 106 q->setup = EZ(t->setup * 1000, T); 107 q->act8b = EZ(t->act8b * 1000, T); 108 q->rec8b = EZ(t->rec8b * 1000, T); 109 q->cyc8b = EZ(t->cyc8b * 1000, T); 110 q->active = EZ(t->active * 1000, T); 111 q->recover = EZ(t->recover * 1000, T); 112 q->cycle = EZ(t->cycle * 1000, T); 113 q->udma = EZ(t->udma * 1000, UT); 114} 115 116void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, 117 struct ide_timing *m, unsigned int what) 118{ 119 if (what & IDE_TIMING_SETUP) 120 m->setup = max(a->setup, b->setup); 121 if (what & IDE_TIMING_ACT8B) 122 m->act8b = max(a->act8b, b->act8b); 123 if (what & IDE_TIMING_REC8B) 124 m->rec8b = max(a->rec8b, b->rec8b); 125 if (what & IDE_TIMING_CYC8B) 126 m->cyc8b = max(a->cyc8b, b->cyc8b); 127 if (what & IDE_TIMING_ACTIVE) 128 m->active = max(a->active, b->active); 129 if (what & IDE_TIMING_RECOVER) 130 m->recover = max(a->recover, b->recover); 131 if (what & IDE_TIMING_CYCLE) 132 m->cycle = max(a->cycle, b->cycle); 133 if (what & IDE_TIMING_UDMA) 134 m->udma = max(a->udma, b->udma); 135} 136EXPORT_SYMBOL_GPL(ide_timing_merge); 137 138int ide_timing_compute(ide_drive_t *drive, u8 speed, 139 struct ide_timing *t, int T, int UT) 140{ 141 u16 *id = drive->id; 142 struct ide_timing *s, p; 143 144 /* 145 * Find the mode. 146 */ 147 s = ide_timing_find_mode(speed); 148 if (s == NULL) 149 return -EINVAL; 150 151 /* 152 * Copy the timing from the table. 153 */ 154 *t = *s; 155 156 /* 157 * If the drive is an EIDE drive, it can tell us it needs extended 158 * PIO/MWDMA cycle timing. 159 */ 160 if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */ 161 memset(&p, 0, sizeof(p)); 162 163 if (speed <= XFER_PIO_2) 164 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; 165 else if (speed <= XFER_PIO_5) 166 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; 167 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) 168 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; 169 170 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); 171 } 172 173 /* 174 * Convert the timing to bus clock counts. 175 */ 176 ide_timing_quantize(t, t, T, UT); 177 178 /* 179 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, 180 * S.M.A.R.T and some other commands. We have to ensure that the 181 * DMA cycle timing is slower/equal than the fastest PIO timing. 182 */ 183 if (speed >= XFER_SW_DMA_0) { 184 u8 pio = ide_get_best_pio_mode(drive, 255, 5); 185 ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT); 186 ide_timing_merge(&p, t, t, IDE_TIMING_ALL); 187 } 188 189 /* 190 * Lengthen active & recovery time so that cycle time is correct. 191 */ 192 if (t->act8b + t->rec8b < t->cyc8b) { 193 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2; 194 t->rec8b = t->cyc8b - t->act8b; 195 } 196 197 if (t->active + t->recover < t->cycle) { 198 t->active += (t->cycle - (t->active + t->recover)) / 2; 199 t->recover = t->cycle - t->active; 200 } 201 202 return 0; 203} 204EXPORT_SYMBOL_GPL(ide_timing_compute); 205