1/******************************************************************* 2 * This file is part of the Emulex RoCE Device Driver for * 3 * RoCE (RDMA over Converged Ethernet) adapters. * 4 * Copyright (C) 2008-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 * 20 * Contact Information: 21 * linux-drivers@emulex.com 22 * 23 * Emulex 24 * 3333 Susan Street 25 * Costa Mesa, CA 92626 26 *******************************************************************/ 27 28#ifndef __OCRDMA_SLI_H__ 29#define __OCRDMA_SLI_H__ 30 31enum { 32 OCRDMA_ASIC_GEN_SKH_R = 0x04, 33 OCRDMA_ASIC_GEN_LANCER = 0x0B 34}; 35 36enum { 37 OCRDMA_ASIC_REV_A0 = 0x00, 38 OCRDMA_ASIC_REV_B0 = 0x10, 39 OCRDMA_ASIC_REV_C0 = 0x20 40}; 41 42#define OCRDMA_SUBSYS_ROCE 10 43enum { 44 OCRDMA_CMD_QUERY_CONFIG = 1, 45 OCRDMA_CMD_ALLOC_PD = 2, 46 OCRDMA_CMD_DEALLOC_PD = 3, 47 48 OCRDMA_CMD_CREATE_AH_TBL = 4, 49 OCRDMA_CMD_DELETE_AH_TBL = 5, 50 51 OCRDMA_CMD_CREATE_QP = 6, 52 OCRDMA_CMD_QUERY_QP = 7, 53 OCRDMA_CMD_MODIFY_QP = 8 , 54 OCRDMA_CMD_DELETE_QP = 9, 55 56 OCRDMA_CMD_RSVD1 = 10, 57 OCRDMA_CMD_ALLOC_LKEY = 11, 58 OCRDMA_CMD_DEALLOC_LKEY = 12, 59 OCRDMA_CMD_REGISTER_NSMR = 13, 60 OCRDMA_CMD_REREGISTER_NSMR = 14, 61 OCRDMA_CMD_REGISTER_NSMR_CONT = 15, 62 OCRDMA_CMD_QUERY_NSMR = 16, 63 OCRDMA_CMD_ALLOC_MW = 17, 64 OCRDMA_CMD_QUERY_MW = 18, 65 66 OCRDMA_CMD_CREATE_SRQ = 19, 67 OCRDMA_CMD_QUERY_SRQ = 20, 68 OCRDMA_CMD_MODIFY_SRQ = 21, 69 OCRDMA_CMD_DELETE_SRQ = 22, 70 71 OCRDMA_CMD_ATTACH_MCAST = 23, 72 OCRDMA_CMD_DETACH_MCAST = 24, 73 74 OCRDMA_CMD_CREATE_RBQ = 25, 75 OCRDMA_CMD_DESTROY_RBQ = 26, 76 77 OCRDMA_CMD_GET_RDMA_STATS = 27, 78 79 OCRDMA_CMD_MAX 80}; 81 82#define OCRDMA_SUBSYS_COMMON 1 83enum { 84 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5, 85 OCRDMA_CMD_CREATE_CQ = 12, 86 OCRDMA_CMD_CREATE_EQ = 13, 87 OCRDMA_CMD_CREATE_MQ = 21, 88 OCRDMA_CMD_GET_CTRL_ATTRIBUTES = 32, 89 OCRDMA_CMD_GET_FW_VER = 35, 90 OCRDMA_CMD_DELETE_MQ = 53, 91 OCRDMA_CMD_DELETE_CQ = 54, 92 OCRDMA_CMD_DELETE_EQ = 55, 93 OCRDMA_CMD_GET_FW_CONFIG = 58, 94 OCRDMA_CMD_CREATE_MQ_EXT = 90, 95 OCRDMA_CMD_PHY_DETAILS = 102 96}; 97 98enum { 99 QTYPE_EQ = 1, 100 QTYPE_CQ = 2, 101 QTYPE_MCCQ = 3 102}; 103 104#define OCRDMA_MAX_SGID 8 105 106#define OCRDMA_MAX_QP 2048 107#define OCRDMA_MAX_CQ 2048 108#define OCRDMA_MAX_STAG 16384 109 110enum { 111 OCRDMA_DB_RQ_OFFSET = 0xE0, 112 OCRDMA_DB_GEN2_RQ_OFFSET = 0x100, 113 OCRDMA_DB_SQ_OFFSET = 0x60, 114 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0, 115 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET, 116 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ_OFFSET, 117 OCRDMA_DB_CQ_OFFSET = 0x120, 118 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET, 119 OCRDMA_DB_MQ_OFFSET = 0x140, 120 121 OCRDMA_DB_SQ_SHIFT = 16, 122 OCRDMA_DB_RQ_SHIFT = 24 123}; 124 125#define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 126#define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */ 127/* qid #2 msbits at 12-11 */ 128#define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1 129#define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */ 130/* Rearm bit */ 131#define OCRDMA_DB_CQ_REARM_SHIFT 29 /* bit 29 */ 132/* solicited bit */ 133#define OCRDMA_DB_CQ_SOLICIT_SHIFT 31 /* bit 31 */ 134 135#define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */ 136#define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 137#define OCRDMA_EQ_ID_EXT_MASK_SHIFT 2 /* qid bits 9-13 at 11-15 */ 138 139/* Clear the interrupt for this eq */ 140#define OCRDMA_EQ_CLR_SHIFT 9 /* bit 9 */ 141/* Must be 1 */ 142#define OCRDMA_EQ_TYPE_SHIFT 10 /* bit 10 */ 143/* Number of event entries processed */ 144#define OCRDMA_NUM_EQE_SHIFT 16 /* bits 16 - 28 */ 145/* Rearm bit */ 146#define OCRDMA_REARM_SHIFT 29 /* bit 29 */ 147 148#define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */ 149/* Number of entries posted */ 150#define OCRDMA_MQ_NUM_MQE_SHIFT 16 /* bits 16 - 29 */ 151 152#define OCRDMA_MIN_HPAGE_SIZE 4096 153 154#define OCRDMA_MIN_Q_PAGE_SIZE 4096 155#define OCRDMA_MAX_Q_PAGES 8 156 157#define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C 158#define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF 159#define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00 160#define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08 161/* 162# 0: 4K Bytes 163# 1: 8K Bytes 164# 2: 16K Bytes 165# 3: 32K Bytes 166# 4: 64K Bytes 167# 5: 128K Bytes 168# 6: 256K Bytes 169# 7: 512K Bytes 170*/ 171#define OCRDMA_MAX_Q_PAGE_SIZE_CNT 8 172#define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES) 173 174#define MAX_OCRDMA_QP_PAGES 8 175#define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE) 176 177#define OCRDMA_CREATE_CQ_MAX_PAGES 4 178#define OCRDMA_DPP_CQE_SIZE 4 179 180#define OCRDMA_GEN2_MAX_CQE 1024 181#define OCRDMA_GEN2_CQ_PAGE_SIZE 4096 182#define OCRDMA_GEN2_WQE_SIZE 256 183#define OCRDMA_MAX_CQE 4095 184#define OCRDMA_CQ_PAGE_SIZE 16384 185#define OCRDMA_WQE_SIZE 128 186#define OCRDMA_WQE_STRIDE 8 187#define OCRDMA_WQE_ALIGN_BYTES 16 188 189#define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES 190 191enum { 192 OCRDMA_MCH_OPCODE_SHIFT = 0, 193 OCRDMA_MCH_OPCODE_MASK = 0xFF, 194 OCRDMA_MCH_SUBSYS_SHIFT = 8, 195 OCRDMA_MCH_SUBSYS_MASK = 0xFF00 196}; 197 198/* mailbox cmd header */ 199struct ocrdma_mbx_hdr { 200 u32 subsys_op; 201 u32 timeout; /* in seconds */ 202 u32 cmd_len; 203 u32 rsvd_version; 204}; 205 206enum { 207 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0, 208 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF, 209 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8, 210 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT, 211 212 OCRDMA_MBX_RSP_STATUS_SHIFT = 0, 213 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF, 214 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8, 215 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT 216}; 217 218/* mailbox cmd response */ 219struct ocrdma_mbx_rsp { 220 u32 subsys_op; 221 u32 status; 222 u32 rsp_len; 223 u32 add_rsp_len; 224}; 225 226enum { 227 OCRDMA_MQE_EMBEDDED = 1, 228 OCRDMA_MQE_NONEMBEDDED = 0 229}; 230 231struct ocrdma_mqe_sge { 232 u32 pa_lo; 233 u32 pa_hi; 234 u32 len; 235}; 236 237enum { 238 OCRDMA_MQE_HDR_EMB_SHIFT = 0, 239 OCRDMA_MQE_HDR_EMB_MASK = BIT(0), 240 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3, 241 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT, 242 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24, 243 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT 244}; 245 246struct ocrdma_mqe_hdr { 247 u32 spcl_sge_cnt_emb; 248 u32 pyld_len; 249 u32 tag_lo; 250 u32 tag_hi; 251 u32 rsvd3; 252}; 253 254struct ocrdma_mqe_emb_cmd { 255 struct ocrdma_mbx_hdr mch; 256 u8 pyld[220]; 257}; 258 259struct ocrdma_mqe { 260 struct ocrdma_mqe_hdr hdr; 261 union { 262 struct ocrdma_mqe_emb_cmd emb_req; 263 struct { 264 struct ocrdma_mqe_sge sge[19]; 265 } nonemb_req; 266 u8 cmd[236]; 267 struct ocrdma_mbx_rsp rsp; 268 } u; 269}; 270 271#define OCRDMA_EQ_LEN 4096 272#define OCRDMA_MQ_CQ_LEN 256 273#define OCRDMA_MQ_LEN 128 274 275#define PAGE_SHIFT_4K 12 276#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 277 278/* Returns number of pages spanned by the data starting at the given addr */ 279#define PAGES_4K_SPANNED(_address, size) \ 280 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 281 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 282 283struct ocrdma_delete_q_req { 284 struct ocrdma_mbx_hdr req; 285 u32 id; 286}; 287 288struct ocrdma_pa { 289 u32 lo; 290 u32 hi; 291}; 292 293#define MAX_OCRDMA_EQ_PAGES 8 294struct ocrdma_create_eq_req { 295 struct ocrdma_mbx_hdr req; 296 u32 num_pages; 297 u32 valid; 298 u32 cnt; 299 u32 delay; 300 u32 rsvd; 301 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES]; 302}; 303 304enum { 305 OCRDMA_CREATE_EQ_VALID = BIT(29), 306 OCRDMA_CREATE_EQ_CNT_SHIFT = 26, 307 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13, 308}; 309 310struct ocrdma_create_eq_rsp { 311 struct ocrdma_mbx_rsp rsp; 312 u32 vector_eqid; 313}; 314 315#define OCRDMA_EQ_MINOR_OTHER 0x1 316 317enum { 318 OCRDMA_MCQE_STATUS_SHIFT = 0, 319 OCRDMA_MCQE_STATUS_MASK = 0xFFFF, 320 OCRDMA_MCQE_ESTATUS_SHIFT = 16, 321 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT, 322 OCRDMA_MCQE_CONS_SHIFT = 27, 323 OCRDMA_MCQE_CONS_MASK = BIT(27), 324 OCRDMA_MCQE_CMPL_SHIFT = 28, 325 OCRDMA_MCQE_CMPL_MASK = BIT(28), 326 OCRDMA_MCQE_AE_SHIFT = 30, 327 OCRDMA_MCQE_AE_MASK = BIT(30), 328 OCRDMA_MCQE_VALID_SHIFT = 31, 329 OCRDMA_MCQE_VALID_MASK = BIT(31) 330}; 331 332struct ocrdma_mcqe { 333 u32 status; 334 u32 tag_lo; 335 u32 tag_hi; 336 u32 valid_ae_cmpl_cons; 337}; 338 339enum { 340 OCRDMA_AE_MCQE_QPVALID = BIT(31), 341 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF, 342 343 OCRDMA_AE_MCQE_CQVALID = BIT(31), 344 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF, 345 OCRDMA_AE_MCQE_VALID = BIT(31), 346 OCRDMA_AE_MCQE_AE = BIT(30), 347 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16, 348 OCRDMA_AE_MCQE_EVENT_TYPE_MASK = 349 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT, 350 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8, 351 OCRDMA_AE_MCQE_EVENT_CODE_MASK = 352 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT 353}; 354struct ocrdma_ae_mcqe { 355 u32 qpvalid_qpid; 356 u32 cqvalid_cqid; 357 u32 evt_tag; 358 u32 valid_ae_event; 359}; 360 361enum { 362 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0, 363 OCRDMA_AE_PVID_MCQE_ENABLED_MASK = 0xFF, 364 OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16, 365 OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT 366}; 367 368struct ocrdma_ae_pvid_mcqe { 369 u32 tag_enabled; 370 u32 event_tag; 371 u32 rsvd1; 372 u32 rsvd2; 373}; 374 375enum { 376 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16, 377 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF << 378 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT, 379 380 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8, 381 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF << 382 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT, 383 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16, 384 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF << 385 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT, 386 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30, 387 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = BIT(30), 388 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31, 389 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = BIT(31) 390}; 391 392struct ocrdma_ae_mpa_mcqe { 393 u32 req_id; 394 u32 w1; 395 u32 w2; 396 u32 valid_ae_event; 397}; 398 399enum { 400 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0, 401 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF, 402 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16, 403 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF << 404 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT, 405 406 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8, 407 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF << 408 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT, 409 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16, 410 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF << 411 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT, 412 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30, 413 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = BIT(30), 414 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31, 415 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = BIT(31) 416}; 417 418struct ocrdma_ae_qp_mcqe { 419 u32 qp_id_state; 420 u32 w1; 421 u32 w2; 422 u32 valid_ae_event; 423}; 424 425#define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14 426#define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5 427 428enum ocrdma_async_grp5_events { 429 OCRDMA_ASYNC_EVENT_QOS_VALUE = 0x01, 430 OCRDMA_ASYNC_EVENT_COS_VALUE = 0x02, 431 OCRDMA_ASYNC_EVENT_PVID_STATE = 0x03 432}; 433 434enum OCRDMA_ASYNC_EVENT_TYPE { 435 OCRDMA_CQ_ERROR = 0x00, 436 OCRDMA_CQ_OVERRUN_ERROR = 0x01, 437 OCRDMA_CQ_QPCAT_ERROR = 0x02, 438 OCRDMA_QP_ACCESS_ERROR = 0x03, 439 OCRDMA_QP_COMM_EST_EVENT = 0x04, 440 OCRDMA_SQ_DRAINED_EVENT = 0x05, 441 OCRDMA_DEVICE_FATAL_EVENT = 0x08, 442 OCRDMA_SRQCAT_ERROR = 0x0E, 443 OCRDMA_SRQ_LIMIT_EVENT = 0x0F, 444 OCRDMA_QP_LAST_WQE_EVENT = 0x10 445}; 446 447/* mailbox command request and responses */ 448enum { 449 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2, 450 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = BIT(2), 451 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3, 452 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = BIT(3), 453 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8, 454 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF << 455 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT, 456 457 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16, 458 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF << 459 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT, 460 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8, 461 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF << 462 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT, 463 464 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0, 465 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF, 466 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16, 467 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK = 0xFFFF << 468 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT, 469 470 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0, 471 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF, 472 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16, 473 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF << 474 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT, 475 476 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24, 477 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF << 478 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET, 479 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16, 480 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF << 481 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET, 482 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0, 483 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF << 484 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET, 485 486 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16, 487 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF << 488 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET, 489 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0, 490 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF << 491 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET, 492 493 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16, 494 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF << 495 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET, 496 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0, 497 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF << 498 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET, 499 500 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0, 501 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF << 502 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET, 503 504 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16, 505 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF << 506 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET, 507 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0, 508 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF << 509 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET, 510 511 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16, 512 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF << 513 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET, 514 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0, 515 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF << 516 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET, 517 518 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16, 519 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF << 520 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET, 521 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0, 522 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF << 523 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET, 524}; 525 526struct ocrdma_mbx_query_config { 527 struct ocrdma_mqe_hdr hdr; 528 struct ocrdma_mbx_rsp rsp; 529 u32 qp_srq_cq_ird_ord; 530 u32 max_pd_ca_ack_delay; 531 u32 max_write_send_sge; 532 u32 max_ird_ord_per_qp; 533 u32 max_shared_ird_ord; 534 u32 max_mr; 535 u32 max_mr_size_hi; 536 u32 max_mr_size_lo; 537 u32 max_num_mr_pbl; 538 u32 max_mw; 539 u32 max_fmr; 540 u32 max_pages_per_frmr; 541 u32 max_mcast_group; 542 u32 max_mcast_qp_attach; 543 u32 max_total_mcast_qp_attach; 544 u32 wqe_rqe_stride_max_dpp_cqs; 545 u32 max_srq_rpir_qps; 546 u32 max_dpp_pds_credits; 547 u32 max_dpp_credits_pds_per_pd; 548 u32 max_wqes_rqes_per_q; 549 u32 max_cq_cqes_per_cq; 550 u32 max_srq_rqe_sge; 551}; 552 553struct ocrdma_fw_ver_rsp { 554 struct ocrdma_mqe_hdr hdr; 555 struct ocrdma_mbx_rsp rsp; 556 557 u8 running_ver[32]; 558}; 559 560struct ocrdma_fw_conf_rsp { 561 struct ocrdma_mqe_hdr hdr; 562 struct ocrdma_mbx_rsp rsp; 563 564 u32 config_num; 565 u32 asic_revision; 566 u32 phy_port; 567 u32 fn_mode; 568 struct { 569 u32 mode; 570 u32 nic_wqid_base; 571 u32 nic_wq_tot; 572 u32 prot_wqid_base; 573 u32 prot_wq_tot; 574 u32 prot_rqid_base; 575 u32 prot_rqid_tot; 576 u32 rsvd[6]; 577 } ulp[2]; 578 u32 fn_capabilities; 579 u32 rsvd1; 580 u32 rsvd2; 581 u32 base_eqid; 582 u32 max_eq; 583 584}; 585 586enum { 587 OCRDMA_FN_MODE_RDMA = 0x4 588}; 589 590enum { 591 OCRDMA_IF_TYPE_MASK = 0xFFFF0000, 592 OCRDMA_IF_TYPE_SHIFT = 0x10, 593 OCRDMA_PHY_TYPE_MASK = 0x0000FFFF, 594 OCRDMA_FUTURE_DETAILS_MASK = 0xFFFF0000, 595 OCRDMA_FUTURE_DETAILS_SHIFT = 0x10, 596 OCRDMA_EX_PHY_DETAILS_MASK = 0x0000FFFF, 597 OCRDMA_FSPEED_SUPP_MASK = 0xFFFF0000, 598 OCRDMA_FSPEED_SUPP_SHIFT = 0x10, 599 OCRDMA_ASPEED_SUPP_MASK = 0x0000FFFF 600}; 601 602struct ocrdma_get_phy_info_rsp { 603 struct ocrdma_mqe_hdr hdr; 604 struct ocrdma_mbx_rsp rsp; 605 606 u32 ityp_ptyp; 607 u32 misc_params; 608 u32 ftrdtl_exphydtl; 609 u32 fspeed_aspeed; 610 u32 future_use[2]; 611}; 612 613enum { 614 OCRDMA_PHY_SPEED_ZERO = 0x0, 615 OCRDMA_PHY_SPEED_10MBPS = 0x1, 616 OCRDMA_PHY_SPEED_100MBPS = 0x2, 617 OCRDMA_PHY_SPEED_1GBPS = 0x4, 618 OCRDMA_PHY_SPEED_10GBPS = 0x8, 619 OCRDMA_PHY_SPEED_40GBPS = 0x20 620}; 621 622enum { 623 OCRDMA_PORT_NUM_MASK = 0x3F, 624 OCRDMA_PT_MASK = 0xC0, 625 OCRDMA_PT_SHIFT = 0x6, 626 OCRDMA_LINK_DUP_MASK = 0x0000FF00, 627 OCRDMA_LINK_DUP_SHIFT = 0x8, 628 OCRDMA_PHY_PS_MASK = 0x00FF0000, 629 OCRDMA_PHY_PS_SHIFT = 0x10, 630 OCRDMA_PHY_PFLT_MASK = 0xFF000000, 631 OCRDMA_PHY_PFLT_SHIFT = 0x18, 632 OCRDMA_QOS_LNKSP_MASK = 0xFFFF0000, 633 OCRDMA_QOS_LNKSP_SHIFT = 0x10, 634 OCRDMA_LLST_MASK = 0xFF, 635 OCRDMA_PLFC_MASK = 0x00000400, 636 OCRDMA_PLFC_SHIFT = 0x8, 637 OCRDMA_PLRFC_MASK = 0x00000200, 638 OCRDMA_PLRFC_SHIFT = 0x8, 639 OCRDMA_PLTFC_MASK = 0x00000100, 640 OCRDMA_PLTFC_SHIFT = 0x8 641}; 642 643struct ocrdma_get_link_speed_rsp { 644 struct ocrdma_mqe_hdr hdr; 645 struct ocrdma_mbx_rsp rsp; 646 647 u32 pflt_pps_ld_pnum; 648 u32 qos_lsp; 649 u32 res_lls; 650}; 651 652enum { 653 OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0, 654 OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1, 655 OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2, 656 OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3, 657 OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4, 658 OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5, 659 OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6, 660 OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7, 661 OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8 662}; 663 664enum { 665 OCRDMA_CREATE_CQ_VER2 = 2, 666 OCRDMA_CREATE_CQ_VER3 = 3, 667 668 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF, 669 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16, 670 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF, 671 672 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12, 673 OCRDMA_CREATE_CQ_COALESCWM_MASK = BIT(13) | BIT(12), 674 OCRDMA_CREATE_CQ_FLAGS_NODELAY = BIT(14), 675 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = BIT(15), 676 677 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF, 678 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF 679}; 680 681enum { 682 OCRDMA_CREATE_CQ_VER0 = 0, 683 OCRDMA_CREATE_CQ_DPP = 1, 684 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24, 685 OCRDMA_CREATE_CQ_EQID_SHIFT = 22, 686 687 OCRDMA_CREATE_CQ_CNT_SHIFT = 27, 688 OCRDMA_CREATE_CQ_FLAGS_VALID = BIT(29), 689 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = BIT(31), 690 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID | 691 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE | 692 OCRDMA_CREATE_CQ_FLAGS_NODELAY 693}; 694 695struct ocrdma_create_cq_cmd { 696 struct ocrdma_mbx_hdr req; 697 u32 pgsz_pgcnt; 698 u32 ev_cnt_flags; 699 u32 eqn; 700 u32 pdid_cqecnt; 701 u32 rsvd6; 702 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES]; 703}; 704 705struct ocrdma_create_cq { 706 struct ocrdma_mqe_hdr hdr; 707 struct ocrdma_create_cq_cmd cmd; 708}; 709 710enum { 711 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT = 0x10 712}; 713 714enum { 715 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF 716}; 717 718struct ocrdma_create_cq_cmd_rsp { 719 struct ocrdma_mbx_rsp rsp; 720 u32 cq_id; 721}; 722 723struct ocrdma_create_cq_rsp { 724 struct ocrdma_mqe_hdr hdr; 725 struct ocrdma_create_cq_cmd_rsp rsp; 726}; 727 728enum { 729 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22, 730 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16, 731 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16, 732 OCRDMA_CREATE_MQ_VALID = BIT(31), 733 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = BIT(0) 734}; 735 736struct ocrdma_create_mq_req { 737 struct ocrdma_mbx_hdr req; 738 u32 cqid_pages; 739 u32 async_event_bitmap; 740 u32 async_cqid_ringsize; 741 u32 valid; 742 u32 async_cqid_valid; 743 u32 rsvd; 744 struct ocrdma_pa pa[8]; 745}; 746 747struct ocrdma_create_mq_rsp { 748 struct ocrdma_mbx_rsp rsp; 749 u32 id; 750}; 751 752enum { 753 OCRDMA_DESTROY_CQ_QID_SHIFT = 0, 754 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF, 755 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16, 756 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF << 757 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT 758}; 759 760struct ocrdma_destroy_cq { 761 struct ocrdma_mqe_hdr hdr; 762 struct ocrdma_mbx_hdr req; 763 764 u32 bypass_flush_qid; 765}; 766 767struct ocrdma_destroy_cq_rsp { 768 struct ocrdma_mqe_hdr hdr; 769 struct ocrdma_mbx_rsp rsp; 770}; 771 772enum { 773 OCRDMA_QPT_GSI = 1, 774 OCRDMA_QPT_RC = 2, 775 OCRDMA_QPT_UD = 4, 776}; 777 778enum { 779 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0, 780 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF, 781 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16, 782 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19, 783 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29, 784 OCRDMA_CREATE_QP_REQ_QPT_MASK = BIT(31) | BIT(30) | BIT(29), 785 786 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0, 787 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF, 788 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16, 789 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF << 790 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT, 791 792 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0, 793 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF, 794 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16, 795 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF << 796 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT, 797 798 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0, 799 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = BIT(0), 800 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1, 801 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = BIT(1), 802 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2, 803 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = BIT(2), 804 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3, 805 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = BIT(3), 806 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4, 807 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = BIT(4), 808 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5, 809 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = BIT(5), 810 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6, 811 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = BIT(6), 812 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7, 813 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = BIT(7), 814 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8, 815 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = BIT(8), 816 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16, 817 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF << 818 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT, 819 820 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0, 821 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF, 822 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16, 823 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF << 824 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT, 825 826 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0, 827 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF, 828 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16, 829 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF << 830 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT, 831 832 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0, 833 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF, 834 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16, 835 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF << 836 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT, 837 838 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0, 839 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF, 840 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16, 841 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF << 842 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT, 843 844 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0, 845 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF, 846 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16, 847 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF << 848 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT 849}; 850 851enum { 852 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16, 853 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1 854}; 855 856#define MAX_OCRDMA_IRD_PAGES 4 857 858enum ocrdma_qp_flags { 859 OCRDMA_QP_MW_BIND = 1, 860 OCRDMA_QP_LKEY0 = (1 << 1), 861 OCRDMA_QP_FAST_REG = (1 << 2), 862 OCRDMA_QP_INB_RD = (1 << 6), 863 OCRDMA_QP_INB_WR = (1 << 7), 864}; 865 866enum ocrdma_qp_state { 867 OCRDMA_QPS_RST = 0, 868 OCRDMA_QPS_INIT = 1, 869 OCRDMA_QPS_RTR = 2, 870 OCRDMA_QPS_RTS = 3, 871 OCRDMA_QPS_SQE = 4, 872 OCRDMA_QPS_SQ_DRAINING = 5, 873 OCRDMA_QPS_ERR = 6, 874 OCRDMA_QPS_SQD = 7 875}; 876 877struct ocrdma_create_qp_req { 878 struct ocrdma_mqe_hdr hdr; 879 struct ocrdma_mbx_hdr req; 880 881 u32 type_pgsz_pdn; 882 u32 max_wqe_rqe; 883 u32 max_sge_send_write; 884 u32 max_sge_recv_flags; 885 u32 max_ord_ird; 886 u32 num_wq_rq_pages; 887 u32 wqe_rqe_size; 888 u32 wq_rq_cqid; 889 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES]; 890 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES]; 891 u32 dpp_credits_cqid; 892 u32 rpir_lkey; 893 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES]; 894}; 895 896enum { 897 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0, 898 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF, 899 900 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0, 901 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF, 902 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16, 903 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF << 904 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT, 905 906 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0, 907 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF, 908 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16, 909 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF << 910 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT, 911 912 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16, 913 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF << 914 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT, 915 916 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0, 917 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF, 918 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16, 919 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF << 920 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT, 921 922 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0, 923 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF, 924 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16, 925 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF << 926 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT, 927 928 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = BIT(0), 929 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1, 930 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF << 931 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT, 932 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16, 933 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF << 934 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT, 935}; 936 937struct ocrdma_create_qp_rsp { 938 struct ocrdma_mqe_hdr hdr; 939 struct ocrdma_mbx_rsp rsp; 940 941 u32 qp_id; 942 u32 max_wqe_rqe; 943 u32 max_sge_send_write; 944 u32 max_sge_recv; 945 u32 max_ord_ird; 946 u32 sq_rq_id; 947 u32 dpp_response; 948}; 949 950struct ocrdma_destroy_qp { 951 struct ocrdma_mqe_hdr hdr; 952 struct ocrdma_mbx_hdr req; 953 u32 qp_id; 954}; 955 956struct ocrdma_destroy_qp_rsp { 957 struct ocrdma_mqe_hdr hdr; 958 struct ocrdma_mbx_rsp rsp; 959}; 960 961enum { 962 OCRDMA_MODIFY_QP_ID_SHIFT = 0, 963 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF, 964 965 OCRDMA_QP_PARA_QPS_VALID = BIT(0), 966 OCRDMA_QP_PARA_SQD_ASYNC_VALID = BIT(1), 967 OCRDMA_QP_PARA_PKEY_VALID = BIT(2), 968 OCRDMA_QP_PARA_QKEY_VALID = BIT(3), 969 OCRDMA_QP_PARA_PMTU_VALID = BIT(4), 970 OCRDMA_QP_PARA_ACK_TO_VALID = BIT(5), 971 OCRDMA_QP_PARA_RETRY_CNT_VALID = BIT(6), 972 OCRDMA_QP_PARA_RRC_VALID = BIT(7), 973 OCRDMA_QP_PARA_RQPSN_VALID = BIT(8), 974 OCRDMA_QP_PARA_MAX_IRD_VALID = BIT(9), 975 OCRDMA_QP_PARA_MAX_ORD_VALID = BIT(10), 976 OCRDMA_QP_PARA_RNT_VALID = BIT(11), 977 OCRDMA_QP_PARA_SQPSN_VALID = BIT(12), 978 OCRDMA_QP_PARA_DST_QPN_VALID = BIT(13), 979 OCRDMA_QP_PARA_MAX_WQE_VALID = BIT(14), 980 OCRDMA_QP_PARA_MAX_RQE_VALID = BIT(15), 981 OCRDMA_QP_PARA_SGE_SEND_VALID = BIT(16), 982 OCRDMA_QP_PARA_SGE_RECV_VALID = BIT(17), 983 OCRDMA_QP_PARA_SGE_WR_VALID = BIT(18), 984 OCRDMA_QP_PARA_INB_RDEN_VALID = BIT(19), 985 OCRDMA_QP_PARA_INB_WREN_VALID = BIT(20), 986 OCRDMA_QP_PARA_FLOW_LBL_VALID = BIT(21), 987 OCRDMA_QP_PARA_BIND_EN_VALID = BIT(22), 988 OCRDMA_QP_PARA_ZLKEY_EN_VALID = BIT(23), 989 OCRDMA_QP_PARA_FMR_EN_VALID = BIT(24), 990 OCRDMA_QP_PARA_INBAT_EN_VALID = BIT(25), 991 OCRDMA_QP_PARA_VLAN_EN_VALID = BIT(26), 992 993 OCRDMA_MODIFY_QP_FLAGS_RD = BIT(0), 994 OCRDMA_MODIFY_QP_FLAGS_WR = BIT(1), 995 OCRDMA_MODIFY_QP_FLAGS_SEND = BIT(2), 996 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = BIT(3) 997}; 998 999enum { 1000 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0, 1001 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF, 1002 1003 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0, 1004 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF, 1005 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16, 1006 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF << 1007 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT, 1008 1009 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0, 1010 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF, 1011 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16, 1012 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF << 1013 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT, 1014 1015 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = BIT(0), 1016 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = BIT(1), 1017 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = BIT(2), 1018 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = BIT(3), 1019 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = BIT(4), 1020 OCRDMA_QP_PARAMS_STATE_SHIFT = 5, 1021 OCRDMA_QP_PARAMS_STATE_MASK = BIT(5) | BIT(6) | BIT(7), 1022 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = BIT(8), 1023 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = BIT(9), 1024 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16, 1025 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF << 1026 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT, 1027 1028 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0, 1029 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF, 1030 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16, 1031 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF << 1032 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT, 1033 1034 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0, 1035 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF, 1036 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16, 1037 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF << 1038 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT, 1039 1040 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0, 1041 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF, 1042 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24, 1043 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF << 1044 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT, 1045 1046 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0, 1047 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF, 1048 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24, 1049 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF << 1050 OCRDMA_QP_PARAMS_TCLASS_SHIFT, 1051 1052 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0, 1053 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF, 1054 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24, 1055 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 << 1056 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT, 1057 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27, 1058 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F << 1059 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT, 1060 1061 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0, 1062 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF, 1063 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18, 1064 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF << 1065 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT, 1066 1067 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0, 1068 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF, 1069 OCRDMA_QP_PARAMS_SL_SHIFT = 20, 1070 OCRDMA_QP_PARAMS_SL_MASK = 0xF << 1071 OCRDMA_QP_PARAMS_SL_SHIFT, 1072 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24, 1073 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 << 1074 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT, 1075 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27, 1076 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F << 1077 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT, 1078 1079 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0, 1080 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF, 1081 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16, 1082 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF << 1083 OCRDMA_QP_PARAMS_VLAN_SHIFT 1084}; 1085 1086struct ocrdma_qp_params { 1087 u32 id; 1088 u32 max_wqe_rqe; 1089 u32 max_sge_send_write; 1090 u32 max_sge_recv_flags; 1091 u32 max_ord_ird; 1092 u32 wq_rq_cqid; 1093 u32 hop_lmt_rq_psn; 1094 u32 tclass_sq_psn; 1095 u32 ack_to_rnr_rtc_dest_qpn; 1096 u32 path_mtu_pkey_indx; 1097 u32 rnt_rc_sl_fl; 1098 u8 sgid[16]; 1099 u8 dgid[16]; 1100 u32 dmac_b0_to_b3; 1101 u32 vlan_dmac_b4_to_b5; 1102 u32 qkey; 1103}; 1104 1105 1106struct ocrdma_modify_qp { 1107 struct ocrdma_mqe_hdr hdr; 1108 struct ocrdma_mbx_hdr req; 1109 1110 struct ocrdma_qp_params params; 1111 u32 flags; 1112 u32 rdma_flags; 1113 u32 num_outstanding_atomic_rd; 1114}; 1115 1116enum { 1117 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0, 1118 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF, 1119 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16, 1120 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF << 1121 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT, 1122 1123 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0, 1124 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF, 1125 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16, 1126 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF << 1127 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT 1128}; 1129 1130struct ocrdma_modify_qp_rsp { 1131 struct ocrdma_mqe_hdr hdr; 1132 struct ocrdma_mbx_rsp rsp; 1133 1134 u32 max_wqe_rqe; 1135 u32 max_ord_ird; 1136}; 1137 1138struct ocrdma_query_qp { 1139 struct ocrdma_mqe_hdr hdr; 1140 struct ocrdma_mbx_hdr req; 1141 1142#define OCRDMA_QUERY_UP_QP_ID_SHIFT 0 1143#define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF 1144 u32 qp_id; 1145}; 1146 1147struct ocrdma_query_qp_rsp { 1148 struct ocrdma_mqe_hdr hdr; 1149 struct ocrdma_mbx_rsp rsp; 1150 struct ocrdma_qp_params params; 1151}; 1152 1153enum { 1154 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0, 1155 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF, 1156 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16, 1157 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 << 1158 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT, 1159 1160 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0, 1161 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16, 1162 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF << 1163 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT, 1164 1165 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0, 1166 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF, 1167 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16, 1168 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF << 1169 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT 1170}; 1171 1172struct ocrdma_create_srq { 1173 struct ocrdma_mqe_hdr hdr; 1174 struct ocrdma_mbx_hdr req; 1175 1176 u32 pgsz_pdid; 1177 u32 max_sge_rqe; 1178 u32 pages_rqe_sz; 1179 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES]; 1180}; 1181 1182enum { 1183 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0, 1184 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF, 1185 1186 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0, 1187 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF, 1188 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16, 1189 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF << 1190 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT 1191}; 1192 1193struct ocrdma_create_srq_rsp { 1194 struct ocrdma_mqe_hdr hdr; 1195 struct ocrdma_mbx_rsp rsp; 1196 1197 u32 id; 1198 u32 max_sge_rqe_allocated; 1199}; 1200 1201enum { 1202 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0, 1203 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF, 1204 1205 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0, 1206 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF, 1207 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16, 1208 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF << 1209 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT 1210}; 1211 1212struct ocrdma_modify_srq { 1213 struct ocrdma_mqe_hdr hdr; 1214 struct ocrdma_mbx_rsp rep; 1215 1216 u32 id; 1217 u32 limit_max_rqe; 1218}; 1219 1220enum { 1221 OCRDMA_QUERY_SRQ_ID_SHIFT = 0, 1222 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF 1223}; 1224 1225struct ocrdma_query_srq { 1226 struct ocrdma_mqe_hdr hdr; 1227 struct ocrdma_mbx_rsp req; 1228 1229 u32 id; 1230}; 1231 1232enum { 1233 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0, 1234 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF, 1235 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16, 1236 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF << 1237 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT, 1238 1239 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0, 1240 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF, 1241 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16, 1242 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF << 1243 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT 1244}; 1245 1246struct ocrdma_query_srq_rsp { 1247 struct ocrdma_mqe_hdr hdr; 1248 struct ocrdma_mbx_rsp req; 1249 1250 u32 max_rqe_pdid; 1251 u32 srq_lmt_max_sge; 1252}; 1253 1254enum { 1255 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0, 1256 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF 1257}; 1258 1259struct ocrdma_destroy_srq { 1260 struct ocrdma_mqe_hdr hdr; 1261 struct ocrdma_mbx_rsp req; 1262 1263 u32 id; 1264}; 1265 1266enum { 1267 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16), 1268 OCRDMA_DPP_PAGE_SIZE = 4096 1269}; 1270 1271struct ocrdma_alloc_pd { 1272 struct ocrdma_mqe_hdr hdr; 1273 struct ocrdma_mbx_hdr req; 1274 u32 enable_dpp_rsvd; 1275}; 1276 1277enum { 1278 OCRDMA_ALLOC_PD_RSP_DPP = BIT(16), 1279 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20, 1280 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF, 1281}; 1282 1283struct ocrdma_alloc_pd_rsp { 1284 struct ocrdma_mqe_hdr hdr; 1285 struct ocrdma_mbx_rsp rsp; 1286 u32 dpp_page_pdid; 1287}; 1288 1289struct ocrdma_dealloc_pd { 1290 struct ocrdma_mqe_hdr hdr; 1291 struct ocrdma_mbx_hdr req; 1292 u32 id; 1293}; 1294 1295struct ocrdma_dealloc_pd_rsp { 1296 struct ocrdma_mqe_hdr hdr; 1297 struct ocrdma_mbx_rsp rsp; 1298}; 1299 1300enum { 1301 OCRDMA_ADDR_CHECK_ENABLE = 1, 1302 OCRDMA_ADDR_CHECK_DISABLE = 0 1303}; 1304 1305enum { 1306 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0, 1307 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF, 1308 1309 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0, 1310 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = BIT(0), 1311 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1, 1312 OCRDMA_ALLOC_LKEY_FMR_MASK = BIT(1), 1313 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2, 1314 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = BIT(2), 1315 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3, 1316 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = BIT(3), 1317 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4, 1318 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = BIT(4), 1319 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5, 1320 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = BIT(5), 1321 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = BIT(6), 1322 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6, 1323 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16, 1324 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF << 1325 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT 1326}; 1327 1328struct ocrdma_alloc_lkey { 1329 struct ocrdma_mqe_hdr hdr; 1330 struct ocrdma_mbx_hdr req; 1331 1332 u32 pdid; 1333 u32 pbl_sz_flags; 1334}; 1335 1336struct ocrdma_alloc_lkey_rsp { 1337 struct ocrdma_mqe_hdr hdr; 1338 struct ocrdma_mbx_rsp rsp; 1339 1340 u32 lrkey; 1341 u32 num_pbl_rsvd; 1342}; 1343 1344struct ocrdma_dealloc_lkey { 1345 struct ocrdma_mqe_hdr hdr; 1346 struct ocrdma_mbx_hdr req; 1347 1348 u32 lkey; 1349 u32 rsvd_frmr; 1350}; 1351 1352struct ocrdma_dealloc_lkey_rsp { 1353 struct ocrdma_mqe_hdr hdr; 1354 struct ocrdma_mbx_rsp rsp; 1355}; 1356 1357#define MAX_OCRDMA_NSMR_PBL (u32)22 1358#define MAX_OCRDMA_PBL_SIZE 65536 1359#define MAX_OCRDMA_PBL_PER_LKEY 32767 1360 1361enum { 1362 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0, 1363 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF, 1364 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24, 1365 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF << 1366 OCRDMA_REG_NSMR_LRKEY_SHIFT, 1367 1368 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0, 1369 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF, 1370 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16, 1371 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF << 1372 OCRDMA_REG_NSMR_NUM_PBL_SHIFT, 1373 1374 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0, 1375 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF, 1376 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16, 1377 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF << 1378 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT, 1379 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24, 1380 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = BIT(24), 1381 OCRDMA_REG_NSMR_ZB_SHIFT = 25, 1382 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = BIT(25), 1383 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26, 1384 OCRDMA_REG_NSMR_REMOTE_INV_MASK = BIT(26), 1385 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27, 1386 OCRDMA_REG_NSMR_REMOTE_WR_MASK = BIT(27), 1387 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28, 1388 OCRDMA_REG_NSMR_REMOTE_RD_MASK = BIT(28), 1389 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29, 1390 OCRDMA_REG_NSMR_LOCAL_WR_MASK = BIT(29), 1391 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30, 1392 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = BIT(30), 1393 OCRDMA_REG_NSMR_LAST_SHIFT = 31, 1394 OCRDMA_REG_NSMR_LAST_MASK = BIT(31) 1395}; 1396 1397struct ocrdma_reg_nsmr { 1398 struct ocrdma_mqe_hdr hdr; 1399 struct ocrdma_mbx_hdr cmd; 1400 1401 u32 fr_mr; 1402 u32 num_pbl_pdid; 1403 u32 flags_hpage_pbe_sz; 1404 u32 totlen_low; 1405 u32 totlen_high; 1406 u32 fbo_low; 1407 u32 fbo_high; 1408 u32 va_loaddr; 1409 u32 va_hiaddr; 1410 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1411}; 1412 1413enum { 1414 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0, 1415 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF, 1416 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16, 1417 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF << 1418 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT, 1419 1420 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31, 1421 OCRDMA_REG_NSMR_CONT_LAST_MASK = BIT(31) 1422}; 1423 1424struct ocrdma_reg_nsmr_cont { 1425 struct ocrdma_mqe_hdr hdr; 1426 struct ocrdma_mbx_hdr cmd; 1427 1428 u32 lrkey; 1429 u32 num_pbl_offset; 1430 u32 last; 1431 1432 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1433}; 1434 1435struct ocrdma_pbe { 1436 u32 pa_hi; 1437 u32 pa_lo; 1438}; 1439 1440enum { 1441 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16, 1442 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000 1443}; 1444struct ocrdma_reg_nsmr_rsp { 1445 struct ocrdma_mqe_hdr hdr; 1446 struct ocrdma_mbx_rsp rsp; 1447 1448 u32 lrkey; 1449 u32 num_pbl; 1450}; 1451 1452enum { 1453 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0, 1454 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF, 1455 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24, 1456 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF << 1457 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT, 1458 1459 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16, 1460 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF << 1461 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT 1462}; 1463 1464struct ocrdma_reg_nsmr_cont_rsp { 1465 struct ocrdma_mqe_hdr hdr; 1466 struct ocrdma_mbx_rsp rsp; 1467 1468 u32 lrkey_key_index; 1469 u32 num_pbl; 1470}; 1471 1472enum { 1473 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0, 1474 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF 1475}; 1476 1477struct ocrdma_alloc_mw { 1478 struct ocrdma_mqe_hdr hdr; 1479 struct ocrdma_mbx_hdr req; 1480 1481 u32 pdid; 1482}; 1483 1484enum { 1485 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0, 1486 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF 1487}; 1488 1489struct ocrdma_alloc_mw_rsp { 1490 struct ocrdma_mqe_hdr hdr; 1491 struct ocrdma_mbx_rsp rsp; 1492 1493 u32 lrkey_index; 1494}; 1495 1496struct ocrdma_attach_mcast { 1497 struct ocrdma_mqe_hdr hdr; 1498 struct ocrdma_mbx_hdr req; 1499 u32 qp_id; 1500 u8 mgid[16]; 1501 u32 mac_b0_to_b3; 1502 u32 vlan_mac_b4_to_b5; 1503}; 1504 1505struct ocrdma_attach_mcast_rsp { 1506 struct ocrdma_mqe_hdr hdr; 1507 struct ocrdma_mbx_rsp rsp; 1508}; 1509 1510struct ocrdma_detach_mcast { 1511 struct ocrdma_mqe_hdr hdr; 1512 struct ocrdma_mbx_hdr req; 1513 u32 qp_id; 1514 u8 mgid[16]; 1515 u32 mac_b0_to_b3; 1516 u32 vlan_mac_b4_to_b5; 1517}; 1518 1519struct ocrdma_detach_mcast_rsp { 1520 struct ocrdma_mqe_hdr hdr; 1521 struct ocrdma_mbx_rsp rsp; 1522}; 1523 1524enum { 1525 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19, 1526 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF << 1527 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT, 1528 1529 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16, 1530 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 << 1531 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT, 1532 1533 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23, 1534 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF << 1535 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT, 1536}; 1537 1538#define OCRDMA_AH_TBL_PAGES 8 1539 1540struct ocrdma_create_ah_tbl { 1541 struct ocrdma_mqe_hdr hdr; 1542 struct ocrdma_mbx_hdr req; 1543 1544 u32 ah_conf; 1545 struct ocrdma_pa tbl_addr[8]; 1546}; 1547 1548struct ocrdma_create_ah_tbl_rsp { 1549 struct ocrdma_mqe_hdr hdr; 1550 struct ocrdma_mbx_rsp rsp; 1551 u32 ahid; 1552}; 1553 1554struct ocrdma_delete_ah_tbl { 1555 struct ocrdma_mqe_hdr hdr; 1556 struct ocrdma_mbx_hdr req; 1557 u32 ahid; 1558}; 1559 1560struct ocrdma_delete_ah_tbl_rsp { 1561 struct ocrdma_mqe_hdr hdr; 1562 struct ocrdma_mbx_rsp rsp; 1563}; 1564 1565enum { 1566 OCRDMA_EQE_VALID_SHIFT = 0, 1567 OCRDMA_EQE_VALID_MASK = BIT(0), 1568 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE, 1569 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16, 1570 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF << 1571 OCRDMA_EQE_RESOURCE_ID_SHIFT, 1572}; 1573 1574struct ocrdma_eqe { 1575 u32 id_valid; 1576}; 1577 1578enum OCRDMA_CQE_STATUS { 1579 OCRDMA_CQE_SUCCESS = 0, 1580 OCRDMA_CQE_LOC_LEN_ERR, 1581 OCRDMA_CQE_LOC_QP_OP_ERR, 1582 OCRDMA_CQE_LOC_EEC_OP_ERR, 1583 OCRDMA_CQE_LOC_PROT_ERR, 1584 OCRDMA_CQE_WR_FLUSH_ERR, 1585 OCRDMA_CQE_MW_BIND_ERR, 1586 OCRDMA_CQE_BAD_RESP_ERR, 1587 OCRDMA_CQE_LOC_ACCESS_ERR, 1588 OCRDMA_CQE_REM_INV_REQ_ERR, 1589 OCRDMA_CQE_REM_ACCESS_ERR, 1590 OCRDMA_CQE_REM_OP_ERR, 1591 OCRDMA_CQE_RETRY_EXC_ERR, 1592 OCRDMA_CQE_RNR_RETRY_EXC_ERR, 1593 OCRDMA_CQE_LOC_RDD_VIOL_ERR, 1594 OCRDMA_CQE_REM_INV_RD_REQ_ERR, 1595 OCRDMA_CQE_REM_ABORT_ERR, 1596 OCRDMA_CQE_INV_EECN_ERR, 1597 OCRDMA_CQE_INV_EEC_STATE_ERR, 1598 OCRDMA_CQE_FATAL_ERR, 1599 OCRDMA_CQE_RESP_TIMEOUT_ERR, 1600 OCRDMA_CQE_GENERAL_ERR 1601}; 1602 1603enum { 1604 /* w0 */ 1605 OCRDMA_CQE_WQEIDX_SHIFT = 0, 1606 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF, 1607 1608 /* w1 */ 1609 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16, 1610 OCRDMA_CQE_PKEY_SHIFT = 0, 1611 OCRDMA_CQE_PKEY_MASK = 0xFFFF, 1612 1613 /* w2 */ 1614 OCRDMA_CQE_QPN_SHIFT = 0, 1615 OCRDMA_CQE_QPN_MASK = 0x0000FFFF, 1616 1617 OCRDMA_CQE_BUFTAG_SHIFT = 16, 1618 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT, 1619 1620 /* w3 */ 1621 OCRDMA_CQE_UD_STATUS_SHIFT = 24, 1622 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT, 1623 OCRDMA_CQE_STATUS_SHIFT = 16, 1624 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT, 1625 OCRDMA_CQE_VALID = BIT(31), 1626 OCRDMA_CQE_INVALIDATE = BIT(30), 1627 OCRDMA_CQE_QTYPE = BIT(29), 1628 OCRDMA_CQE_IMM = BIT(28), 1629 OCRDMA_CQE_WRITE_IMM = BIT(27), 1630 OCRDMA_CQE_QTYPE_SQ = 0, 1631 OCRDMA_CQE_QTYPE_RQ = 1, 1632 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF 1633}; 1634 1635struct ocrdma_cqe { 1636 union { 1637 /* w0 to w2 */ 1638 struct { 1639 u32 wqeidx; 1640 u32 bytes_xfered; 1641 u32 qpn; 1642 } wq; 1643 struct { 1644 u32 lkey_immdt; 1645 u32 rxlen; 1646 u32 buftag_qpn; 1647 } rq; 1648 struct { 1649 u32 lkey_immdt; 1650 u32 rxlen_pkey; 1651 u32 buftag_qpn; 1652 } ud; 1653 struct { 1654 u32 word_0; 1655 u32 word_1; 1656 u32 qpn; 1657 } cmn; 1658 }; 1659 u32 flags_status_srcqpn; /* w3 */ 1660}; 1661 1662struct ocrdma_sge { 1663 u32 addr_hi; 1664 u32 addr_lo; 1665 u32 lrkey; 1666 u32 len; 1667}; 1668 1669enum { 1670 OCRDMA_FLAG_SIG = 0x1, 1671 OCRDMA_FLAG_INV = 0x2, 1672 OCRDMA_FLAG_FENCE_L = 0x4, 1673 OCRDMA_FLAG_FENCE_R = 0x8, 1674 OCRDMA_FLAG_SOLICIT = 0x10, 1675 OCRDMA_FLAG_IMM = 0x20, 1676 1677 /* Stag flags */ 1678 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1, 1679 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2, 1680 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4, 1681 OCRDMA_LKEY_FLAG_VATO = 0x8, 1682}; 1683 1684enum OCRDMA_WQE_OPCODE { 1685 OCRDMA_WRITE = 0x06, 1686 OCRDMA_READ = 0x0C, 1687 OCRDMA_RESV0 = 0x02, 1688 OCRDMA_SEND = 0x00, 1689 OCRDMA_CMP_SWP = 0x14, 1690 OCRDMA_BIND_MW = 0x10, 1691 OCRDMA_FR_MR = 0x11, 1692 OCRDMA_RESV1 = 0x0A, 1693 OCRDMA_LKEY_INV = 0x15, 1694 OCRDMA_FETCH_ADD = 0x13, 1695 OCRDMA_POST_RQ = 0x12 1696}; 1697 1698enum { 1699 OCRDMA_TYPE_INLINE = 0x0, 1700 OCRDMA_TYPE_LKEY = 0x1, 1701}; 1702 1703enum { 1704 OCRDMA_WQE_OPCODE_SHIFT = 0, 1705 OCRDMA_WQE_OPCODE_MASK = 0x0000001F, 1706 OCRDMA_WQE_FLAGS_SHIFT = 5, 1707 OCRDMA_WQE_TYPE_SHIFT = 16, 1708 OCRDMA_WQE_TYPE_MASK = 0x00030000, 1709 OCRDMA_WQE_SIZE_SHIFT = 18, 1710 OCRDMA_WQE_SIZE_MASK = 0xFF, 1711 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25, 1712 1713 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0, 1714 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF 1715}; 1716 1717/* header WQE for all the SQ and RQ operations */ 1718struct ocrdma_hdr_wqe { 1719 u32 cw; 1720 union { 1721 u32 rsvd_tag; 1722 u32 rsvd_lkey_flags; 1723 }; 1724 union { 1725 u32 immdt; 1726 u32 lkey; 1727 }; 1728 u32 total_len; 1729}; 1730 1731struct ocrdma_ewqe_ud_hdr { 1732 u32 rsvd_dest_qpn; 1733 u32 qkey; 1734 u32 rsvd_ahid; 1735 u32 rsvd; 1736}; 1737 1738/* extended wqe followed by hdr_wqe for Fast Memory register */ 1739struct ocrdma_ewqe_fr { 1740 u32 va_hi; 1741 u32 va_lo; 1742 u32 fbo_hi; 1743 u32 fbo_lo; 1744 u32 size_sge; 1745 u32 num_sges; 1746 u32 rsvd; 1747 u32 rsvd2; 1748}; 1749 1750struct ocrdma_eth_basic { 1751 u8 dmac[6]; 1752 u8 smac[6]; 1753 __be16 eth_type; 1754} __packed; 1755 1756struct ocrdma_eth_vlan { 1757 u8 dmac[6]; 1758 u8 smac[6]; 1759 __be16 eth_type; 1760 __be16 vlan_tag; 1761#define OCRDMA_ROCE_ETH_TYPE 0x8915 1762 __be16 roce_eth_type; 1763} __packed; 1764 1765struct ocrdma_grh { 1766 __be32 tclass_flow; 1767 __be32 pdid_hoplimit; 1768 u8 sgid[16]; 1769 u8 dgid[16]; 1770 u16 rsvd; 1771} __packed; 1772 1773#define OCRDMA_AV_VALID BIT(7) 1774#define OCRDMA_AV_VLAN_VALID BIT(1) 1775 1776struct ocrdma_av { 1777 struct ocrdma_eth_vlan eth_hdr; 1778 struct ocrdma_grh grh; 1779 u32 valid; 1780} __packed; 1781 1782struct ocrdma_rsrc_stats { 1783 u32 dpp_pds; 1784 u32 non_dpp_pds; 1785 u32 rc_dpp_qps; 1786 u32 uc_dpp_qps; 1787 u32 ud_dpp_qps; 1788 u32 rc_non_dpp_qps; 1789 u32 rsvd; 1790 u32 uc_non_dpp_qps; 1791 u32 ud_non_dpp_qps; 1792 u32 rsvd1; 1793 u32 srqs; 1794 u32 rbqs; 1795 u32 r64K_nsmr; 1796 u32 r64K_to_2M_nsmr; 1797 u32 r2M_to_44M_nsmr; 1798 u32 r44M_to_1G_nsmr; 1799 u32 r1G_to_4G_nsmr; 1800 u32 nsmr_count_4G_to_32G; 1801 u32 r32G_to_64G_nsmr; 1802 u32 r64G_to_128G_nsmr; 1803 u32 r128G_to_higher_nsmr; 1804 u32 embedded_nsmr; 1805 u32 frmr; 1806 u32 prefetch_qps; 1807 u32 ondemand_qps; 1808 u32 phy_mr; 1809 u32 mw; 1810 u32 rsvd2[7]; 1811}; 1812 1813struct ocrdma_db_err_stats { 1814 u32 sq_doorbell_errors; 1815 u32 cq_doorbell_errors; 1816 u32 rq_srq_doorbell_errors; 1817 u32 cq_overflow_errors; 1818 u32 rsvd[4]; 1819}; 1820 1821struct ocrdma_wqe_stats { 1822 u32 large_send_rc_wqes_lo; 1823 u32 large_send_rc_wqes_hi; 1824 u32 large_write_rc_wqes_lo; 1825 u32 large_write_rc_wqes_hi; 1826 u32 rsvd[4]; 1827 u32 read_wqes_lo; 1828 u32 read_wqes_hi; 1829 u32 frmr_wqes_lo; 1830 u32 frmr_wqes_hi; 1831 u32 mw_bind_wqes_lo; 1832 u32 mw_bind_wqes_hi; 1833 u32 invalidate_wqes_lo; 1834 u32 invalidate_wqes_hi; 1835 u32 rsvd1[2]; 1836 u32 dpp_wqe_drops; 1837 u32 rsvd2[5]; 1838}; 1839 1840struct ocrdma_tx_stats { 1841 u32 send_pkts_lo; 1842 u32 send_pkts_hi; 1843 u32 write_pkts_lo; 1844 u32 write_pkts_hi; 1845 u32 read_pkts_lo; 1846 u32 read_pkts_hi; 1847 u32 read_rsp_pkts_lo; 1848 u32 read_rsp_pkts_hi; 1849 u32 ack_pkts_lo; 1850 u32 ack_pkts_hi; 1851 u32 send_bytes_lo; 1852 u32 send_bytes_hi; 1853 u32 write_bytes_lo; 1854 u32 write_bytes_hi; 1855 u32 read_req_bytes_lo; 1856 u32 read_req_bytes_hi; 1857 u32 read_rsp_bytes_lo; 1858 u32 read_rsp_bytes_hi; 1859 u32 ack_timeouts; 1860 u32 rsvd[5]; 1861}; 1862 1863 1864struct ocrdma_tx_qp_err_stats { 1865 u32 local_length_errors; 1866 u32 local_protection_errors; 1867 u32 local_qp_operation_errors; 1868 u32 retry_count_exceeded_errors; 1869 u32 rnr_retry_count_exceeded_errors; 1870 u32 rsvd[3]; 1871}; 1872 1873struct ocrdma_rx_stats { 1874 u32 roce_frame_bytes_lo; 1875 u32 roce_frame_bytes_hi; 1876 u32 roce_frame_icrc_drops; 1877 u32 roce_frame_payload_len_drops; 1878 u32 ud_drops; 1879 u32 qp1_drops; 1880 u32 psn_error_request_packets; 1881 u32 psn_error_resp_packets; 1882 u32 rnr_nak_timeouts; 1883 u32 rnr_nak_receives; 1884 u32 roce_frame_rxmt_drops; 1885 u32 nak_count_psn_sequence_errors; 1886 u32 rc_drop_count_lookup_errors; 1887 u32 rq_rnr_naks; 1888 u32 srq_rnr_naks; 1889 u32 roce_frames_lo; 1890 u32 roce_frames_hi; 1891 u32 rsvd; 1892}; 1893 1894struct ocrdma_rx_qp_err_stats { 1895 u32 nak_invalid_requst_errors; 1896 u32 nak_remote_operation_errors; 1897 u32 nak_count_remote_access_errors; 1898 u32 local_length_errors; 1899 u32 local_protection_errors; 1900 u32 local_qp_operation_errors; 1901 u32 rsvd[2]; 1902}; 1903 1904struct ocrdma_tx_dbg_stats { 1905 u32 data[100]; 1906}; 1907 1908struct ocrdma_rx_dbg_stats { 1909 u32 data[200]; 1910}; 1911 1912struct ocrdma_rdma_stats_req { 1913 struct ocrdma_mbx_hdr hdr; 1914 u8 reset_stats; 1915 u8 rsvd[3]; 1916} __packed; 1917 1918struct ocrdma_rdma_stats_resp { 1919 struct ocrdma_mbx_hdr hdr; 1920 struct ocrdma_rsrc_stats act_rsrc_stats; 1921 struct ocrdma_rsrc_stats th_rsrc_stats; 1922 struct ocrdma_db_err_stats db_err_stats; 1923 struct ocrdma_wqe_stats wqe_stats; 1924 struct ocrdma_tx_stats tx_stats; 1925 struct ocrdma_tx_qp_err_stats tx_qp_err_stats; 1926 struct ocrdma_rx_stats rx_stats; 1927 struct ocrdma_rx_qp_err_stats rx_qp_err_stats; 1928 struct ocrdma_tx_dbg_stats tx_dbg_stats; 1929 struct ocrdma_rx_dbg_stats rx_dbg_stats; 1930} __packed; 1931 1932enum { 1933 OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK = 0xFF, 1934 OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK = 0xFF00, 1935 OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT = 0x08, 1936 OCRDMA_HBA_ATTRB_CDBLEN_MASK = 0xFFFF, 1937 OCRDMA_HBA_ATTRB_ASIC_REV_MASK = 0xFF0000, 1938 OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT = 0x10, 1939 OCRDMA_HBA_ATTRB_GUID0_MASK = 0xFF000000, 1940 OCRDMA_HBA_ATTRB_GUID0_SHIFT = 0x18, 1941 OCRDMA_HBA_ATTRB_GUID13_MASK = 0xFF, 1942 OCRDMA_HBA_ATTRB_GUID14_MASK = 0xFF00, 1943 OCRDMA_HBA_ATTRB_GUID14_SHIFT = 0x08, 1944 OCRDMA_HBA_ATTRB_GUID15_MASK = 0xFF0000, 1945 OCRDMA_HBA_ATTRB_GUID15_SHIFT = 0x10, 1946 OCRDMA_HBA_ATTRB_PCNT_MASK = 0xFF000000, 1947 OCRDMA_HBA_ATTRB_PCNT_SHIFT = 0x18, 1948 OCRDMA_HBA_ATTRB_LDTOUT_MASK = 0xFFFF, 1949 OCRDMA_HBA_ATTRB_ISCSI_VER_MASK = 0xFF0000, 1950 OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT = 0x10, 1951 OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK = 0xFF000000, 1952 OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT = 0x18, 1953 OCRDMA_HBA_ATTRB_CV_MASK = 0xFF, 1954 OCRDMA_HBA_ATTRB_HBA_ST_MASK = 0xFF00, 1955 OCRDMA_HBA_ATTRB_HBA_ST_SHIFT = 0x08, 1956 OCRDMA_HBA_ATTRB_MAX_DOMS_MASK = 0xFF0000, 1957 OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT = 0x10, 1958 OCRDMA_HBA_ATTRB_PTNUM_MASK = 0x3F000000, 1959 OCRDMA_HBA_ATTRB_PTNUM_SHIFT = 0x18, 1960 OCRDMA_HBA_ATTRB_PT_MASK = 0xC0000000, 1961 OCRDMA_HBA_ATTRB_PT_SHIFT = 0x1E, 1962 OCRDMA_HBA_ATTRB_ISCSI_FET_MASK = 0xFF, 1963 OCRDMA_HBA_ATTRB_ASIC_GEN_MASK = 0xFF00, 1964 OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT = 0x08, 1965 OCRDMA_HBA_ATTRB_PCI_VID_MASK = 0xFFFF, 1966 OCRDMA_HBA_ATTRB_PCI_DID_MASK = 0xFFFF0000, 1967 OCRDMA_HBA_ATTRB_PCI_DID_SHIFT = 0x10, 1968 OCRDMA_HBA_ATTRB_PCI_SVID_MASK = 0xFFFF, 1969 OCRDMA_HBA_ATTRB_PCI_SSID_MASK = 0xFFFF0000, 1970 OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT = 0x10, 1971 OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK = 0xFF, 1972 OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK = 0xFF00, 1973 OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT = 0x08, 1974 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK = 0xFF0000, 1975 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT = 0x10, 1976 OCRDMA_HBA_ATTRB_IF_TYPE_MASK = 0xFF000000, 1977 OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT = 0x18, 1978 OCRDMA_HBA_ATTRB_NETFIL_MASK =0xFF 1979}; 1980 1981struct mgmt_hba_attribs { 1982 u8 flashrom_version_string[32]; 1983 u8 manufacturer_name[32]; 1984 u32 supported_modes; 1985 u32 rsvd_eprom_verhi_verlo; 1986 u32 mbx_ds_ver; 1987 u32 epfw_ds_ver; 1988 u8 ncsi_ver_string[12]; 1989 u32 default_extended_timeout; 1990 u8 controller_model_number[32]; 1991 u8 controller_description[64]; 1992 u8 controller_serial_number[32]; 1993 u8 ip_version_string[32]; 1994 u8 firmware_version_string[32]; 1995 u8 bios_version_string[32]; 1996 u8 redboot_version_string[32]; 1997 u8 driver_version_string[32]; 1998 u8 fw_on_flash_version_string[32]; 1999 u32 functionalities_supported; 2000 u32 guid0_asicrev_cdblen; 2001 u8 generational_guid[12]; 2002 u32 portcnt_guid15; 2003 u32 mfuncdev_iscsi_ldtout; 2004 u32 ptpnum_maxdoms_hbast_cv; 2005 u32 firmware_post_status; 2006 u32 hba_mtu[8]; 2007 u32 res_asicgen_iscsi_feaures; 2008 u32 rsvd1[3]; 2009}; 2010 2011struct mgmt_controller_attrib { 2012 struct mgmt_hba_attribs hba_attribs; 2013 u32 pci_did_vid; 2014 u32 pci_ssid_svid; 2015 u32 ityp_fnum_devnum_bnum; 2016 u32 uid_hi; 2017 u32 uid_lo; 2018 u32 res_nnetfil; 2019 u32 rsvd0[4]; 2020}; 2021 2022struct ocrdma_get_ctrl_attribs_rsp { 2023 struct ocrdma_mbx_hdr hdr; 2024 struct mgmt_controller_attrib ctrl_attribs; 2025}; 2026 2027#define OCRDMA_SUBSYS_DCBX 0x10 2028 2029enum OCRDMA_DCBX_OPCODE { 2030 OCRDMA_CMD_GET_DCBX_CONFIG = 0x01 2031}; 2032 2033enum OCRDMA_DCBX_PARAM_TYPE { 2034 OCRDMA_PARAMETER_TYPE_ADMIN = 0x00, 2035 OCRDMA_PARAMETER_TYPE_OPER = 0x01, 2036 OCRDMA_PARAMETER_TYPE_PEER = 0x02 2037}; 2038 2039enum OCRDMA_DCBX_APP_PROTO { 2040 OCRDMA_APP_PROTO_ROCE = 0x8915 2041}; 2042 2043enum OCRDMA_DCBX_PROTO { 2044 OCRDMA_PROTO_SELECT_L2 = 0x00, 2045 OCRDMA_PROTO_SELECT_L4 = 0x01 2046}; 2047 2048enum OCRDMA_DCBX_APP_PARAM { 2049 OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF, 2050 OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF, 2051 OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10, 2052 OCRDMA_APP_PARAM_VALID_MASK = 0xFF, 2053 OCRDMA_APP_PARAM_VALID_SHIFT = 0x18 2054}; 2055 2056enum OCRDMA_DCBX_STATE_FLAGS { 2057 OCRDMA_STATE_FLAG_ENABLED = 0x01, 2058 OCRDMA_STATE_FLAG_ADDVERTISED = 0x02, 2059 OCRDMA_STATE_FLAG_WILLING = 0x04, 2060 OCRDMA_STATE_FLAG_SYNC = 0x08, 2061 OCRDMA_STATE_FLAG_UNSUPPORTED = 0x40000000, 2062 OCRDMA_STATE_FLAG_NEG_FAILD = 0x80000000 2063}; 2064 2065enum OCRDMA_TCV_AEV_OPV_ST { 2066 OCRDMA_DCBX_TC_SUPPORT_MASK = 0xFF, 2067 OCRDMA_DCBX_TC_SUPPORT_SHIFT = 0x18, 2068 OCRDMA_DCBX_APP_ENTRY_SHIFT = 0x10, 2069 OCRDMA_DCBX_OP_PARAM_SHIFT = 0x08, 2070 OCRDMA_DCBX_STATE_MASK = 0xFF 2071}; 2072 2073struct ocrdma_app_parameter { 2074 u32 valid_proto_app; 2075 u32 oui; 2076 u32 app_prio[2]; 2077}; 2078 2079struct ocrdma_dcbx_cfg { 2080 u32 tcv_aev_opv_st; 2081 u32 tc_state; 2082 u32 pfc_state; 2083 u32 qcn_state; 2084 u32 appl_state; 2085 u32 ll_state; 2086 u32 tc_bw[2]; 2087 u32 tc_prio[8]; 2088 u32 pfc_prio[2]; 2089 struct ocrdma_app_parameter app_param[15]; 2090}; 2091 2092struct ocrdma_get_dcbx_cfg_req { 2093 struct ocrdma_mbx_hdr hdr; 2094 u32 param_type; 2095} __packed; 2096 2097struct ocrdma_get_dcbx_cfg_rsp { 2098 struct ocrdma_mbx_rsp hdr; 2099 struct ocrdma_dcbx_cfg cfg; 2100} __packed; 2101 2102#endif /* __OCRDMA_SLI_H__ */ 2103