1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright (C) 2013 Freescale Semiconductor, Inc. 16 * 17 */ 18 19#ifndef __FSL_PAMU_H 20#define __FSL_PAMU_H 21 22#include <asm/fsl_pamu_stash.h> 23 24/* Bit Field macros 25 * v = bit field variable; m = mask, m##_SHIFT = shift, x = value to load 26 */ 27#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << (m##_SHIFT)) & (m))) 28#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT)) 29 30/* PAMU CCSR space */ 31#define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */ 32#define PAMU_PE 0x40000000 /* enable PAMU */ 33 34/* PAMU_OFFSET to the next pamu space in ccsr */ 35#define PAMU_OFFSET 0x1000 36 37#define PAMU_MMAP_REGS_BASE 0 38 39struct pamu_mmap_regs { 40 u32 ppbah; 41 u32 ppbal; 42 u32 pplah; 43 u32 pplal; 44 u32 spbah; 45 u32 spbal; 46 u32 splah; 47 u32 splal; 48 u32 obah; 49 u32 obal; 50 u32 olah; 51 u32 olal; 52}; 53 54/* PAMU Error Registers */ 55#define PAMU_POES1 0x0040 56#define PAMU_POES2 0x0044 57#define PAMU_POEAH 0x0048 58#define PAMU_POEAL 0x004C 59#define PAMU_AVS1 0x0050 60#define PAMU_AVS1_AV 0x1 61#define PAMU_AVS1_OTV 0x6 62#define PAMU_AVS1_APV 0x78 63#define PAMU_AVS1_WAV 0x380 64#define PAMU_AVS1_LAV 0x1c00 65#define PAMU_AVS1_GCV 0x2000 66#define PAMU_AVS1_PDV 0x4000 67#define PAMU_AV_MASK (PAMU_AVS1_AV | PAMU_AVS1_OTV | PAMU_AVS1_APV | PAMU_AVS1_WAV \ 68 | PAMU_AVS1_LAV | PAMU_AVS1_GCV | PAMU_AVS1_PDV) 69#define PAMU_AVS1_LIODN_SHIFT 16 70#define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400 71 72#define PAMU_AVS2 0x0054 73#define PAMU_AVAH 0x0058 74#define PAMU_AVAL 0x005C 75#define PAMU_EECTL 0x0060 76#define PAMU_EEDIS 0x0064 77#define PAMU_EEINTEN 0x0068 78#define PAMU_EEDET 0x006C 79#define PAMU_EEATTR 0x0070 80#define PAMU_EEAHI 0x0074 81#define PAMU_EEALO 0x0078 82#define PAMU_EEDHI 0X007C 83#define PAMU_EEDLO 0x0080 84#define PAMU_EECC 0x0084 85#define PAMU_UDAD 0x0090 86 87/* PAMU Revision Registers */ 88#define PAMU_PR1 0x0BF8 89#define PAMU_PR2 0x0BFC 90 91/* PAMU version mask */ 92#define PAMU_PR1_MASK 0xffff 93 94/* PAMU Capabilities Registers */ 95#define PAMU_PC1 0x0C00 96#define PAMU_PC2 0x0C04 97#define PAMU_PC3 0x0C08 98#define PAMU_PC4 0x0C0C 99 100/* PAMU Control Register */ 101#define PAMU_PC 0x0C10 102 103/* PAMU control defs */ 104#define PAMU_CONTROL 0x0C10 105#define PAMU_PC_PGC 0x80000000 /* PAMU gate closed bit */ 106#define PAMU_PC_PE 0x40000000 /* PAMU enable bit */ 107#define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */ 108#define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */ 109#define PAMU_PC_OCE 0x00001000 /* OMT cache enable */ 110 111#define PAMU_PFA1 0x0C14 112#define PAMU_PFA2 0x0C18 113 114#define PAMU_PC2_MLIODN(X) ((X) >> 16) 115#define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf) 116 117/* PAMU Interrupt control and Status Register */ 118#define PAMU_PICS 0x0C1C 119#define PAMU_ACCESS_VIOLATION_STAT 0x8 120#define PAMU_ACCESS_VIOLATION_ENABLE 0x4 121 122/* PAMU Debug Registers */ 123#define PAMU_PD1 0x0F00 124#define PAMU_PD2 0x0F04 125#define PAMU_PD3 0x0F08 126#define PAMU_PD4 0x0F0C 127 128#define PAACE_AP_PERMS_DENIED 0x0 129#define PAACE_AP_PERMS_QUERY 0x1 130#define PAACE_AP_PERMS_UPDATE 0x2 131#define PAACE_AP_PERMS_ALL 0x3 132 133#define PAACE_DD_TO_HOST 0x0 134#define PAACE_DD_TO_IO 0x1 135#define PAACE_PT_PRIMARY 0x0 136#define PAACE_PT_SECONDARY 0x1 137#define PAACE_V_INVALID 0x0 138#define PAACE_V_VALID 0x1 139#define PAACE_MW_SUBWINDOWS 0x1 140 141#define PAACE_WSE_4K 0xB 142#define PAACE_WSE_8K 0xC 143#define PAACE_WSE_16K 0xD 144#define PAACE_WSE_32K 0xE 145#define PAACE_WSE_64K 0xF 146#define PAACE_WSE_128K 0x10 147#define PAACE_WSE_256K 0x11 148#define PAACE_WSE_512K 0x12 149#define PAACE_WSE_1M 0x13 150#define PAACE_WSE_2M 0x14 151#define PAACE_WSE_4M 0x15 152#define PAACE_WSE_8M 0x16 153#define PAACE_WSE_16M 0x17 154#define PAACE_WSE_32M 0x18 155#define PAACE_WSE_64M 0x19 156#define PAACE_WSE_128M 0x1A 157#define PAACE_WSE_256M 0x1B 158#define PAACE_WSE_512M 0x1C 159#define PAACE_WSE_1G 0x1D 160#define PAACE_WSE_2G 0x1E 161#define PAACE_WSE_4G 0x1F 162 163#define PAACE_DID_PCI_EXPRESS_1 0x00 164#define PAACE_DID_PCI_EXPRESS_2 0x01 165#define PAACE_DID_PCI_EXPRESS_3 0x02 166#define PAACE_DID_PCI_EXPRESS_4 0x03 167#define PAACE_DID_LOCAL_BUS 0x04 168#define PAACE_DID_SRIO 0x0C 169#define PAACE_DID_MEM_1 0x10 170#define PAACE_DID_MEM_2 0x11 171#define PAACE_DID_MEM_3 0x12 172#define PAACE_DID_MEM_4 0x13 173#define PAACE_DID_MEM_1_2 0x14 174#define PAACE_DID_MEM_3_4 0x15 175#define PAACE_DID_MEM_1_4 0x16 176#define PAACE_DID_BM_SW_PORTAL 0x18 177#define PAACE_DID_PAMU 0x1C 178#define PAACE_DID_CAAM 0x21 179#define PAACE_DID_QM_SW_PORTAL 0x3C 180#define PAACE_DID_CORE0_INST 0x80 181#define PAACE_DID_CORE0_DATA 0x81 182#define PAACE_DID_CORE1_INST 0x82 183#define PAACE_DID_CORE1_DATA 0x83 184#define PAACE_DID_CORE2_INST 0x84 185#define PAACE_DID_CORE2_DATA 0x85 186#define PAACE_DID_CORE3_INST 0x86 187#define PAACE_DID_CORE3_DATA 0x87 188#define PAACE_DID_CORE4_INST 0x88 189#define PAACE_DID_CORE4_DATA 0x89 190#define PAACE_DID_CORE5_INST 0x8A 191#define PAACE_DID_CORE5_DATA 0x8B 192#define PAACE_DID_CORE6_INST 0x8C 193#define PAACE_DID_CORE6_DATA 0x8D 194#define PAACE_DID_CORE7_INST 0x8E 195#define PAACE_DID_CORE7_DATA 0x8F 196#define PAACE_DID_BROADCAST 0xFF 197 198#define PAACE_ATM_NO_XLATE 0x00 199#define PAACE_ATM_WINDOW_XLATE 0x01 200#define PAACE_ATM_PAGE_XLATE 0x02 201#define PAACE_ATM_WIN_PG_XLATE \ 202 (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE) 203#define PAACE_OTM_NO_XLATE 0x00 204#define PAACE_OTM_IMMEDIATE 0x01 205#define PAACE_OTM_INDEXED 0x02 206#define PAACE_OTM_RESERVED 0x03 207 208#define PAACE_M_COHERENCE_REQ 0x01 209 210#define PAACE_PID_0 0x0 211#define PAACE_PID_1 0x1 212#define PAACE_PID_2 0x2 213#define PAACE_PID_3 0x3 214#define PAACE_PID_4 0x4 215#define PAACE_PID_5 0x5 216#define PAACE_PID_6 0x6 217#define PAACE_PID_7 0x7 218 219#define PAACE_TCEF_FORMAT0_8B 0x00 220#define PAACE_TCEF_FORMAT1_RSVD 0x01 221/* 222 * Hard coded value for the PAACT size to accomodate 223 * maximum LIODN value generated by u-boot. 224 */ 225#define PAACE_NUMBER_ENTRIES 0x500 226/* Hard coded value for the SPAACT size */ 227#define SPAACE_NUMBER_ENTRIES 0x800 228 229#define OME_NUMBER_ENTRIES 16 230 231/* PAACE Bit Field Defines */ 232#define PPAACE_AF_WBAL 0xfffff000 233#define PPAACE_AF_WBAL_SHIFT 12 234#define PPAACE_AF_WSE 0x00000fc0 235#define PPAACE_AF_WSE_SHIFT 6 236#define PPAACE_AF_MW 0x00000020 237#define PPAACE_AF_MW_SHIFT 5 238 239#define SPAACE_AF_LIODN 0xffff0000 240#define SPAACE_AF_LIODN_SHIFT 16 241 242#define PAACE_AF_AP 0x00000018 243#define PAACE_AF_AP_SHIFT 3 244#define PAACE_AF_DD 0x00000004 245#define PAACE_AF_DD_SHIFT 2 246#define PAACE_AF_PT 0x00000002 247#define PAACE_AF_PT_SHIFT 1 248#define PAACE_AF_V 0x00000001 249#define PAACE_AF_V_SHIFT 0 250 251#define PAACE_DA_HOST_CR 0x80 252#define PAACE_DA_HOST_CR_SHIFT 7 253 254#define PAACE_IA_CID 0x00FF0000 255#define PAACE_IA_CID_SHIFT 16 256#define PAACE_IA_WCE 0x000000F0 257#define PAACE_IA_WCE_SHIFT 4 258#define PAACE_IA_ATM 0x0000000C 259#define PAACE_IA_ATM_SHIFT 2 260#define PAACE_IA_OTM 0x00000003 261#define PAACE_IA_OTM_SHIFT 0 262 263#define PAACE_WIN_TWBAL 0xfffff000 264#define PAACE_WIN_TWBAL_SHIFT 12 265#define PAACE_WIN_SWSE 0x00000fc0 266#define PAACE_WIN_SWSE_SHIFT 6 267 268/* PAMU Data Structures */ 269/* primary / secondary paact structure */ 270struct paace { 271 /* PAACE Offset 0x00 */ 272 u32 wbah; /* only valid for Primary PAACE */ 273 u32 addr_bitfields; /* See P/S PAACE_AF_* */ 274 275 /* PAACE Offset 0x08 */ 276 /* Interpretation of first 32 bits dependent on DD above */ 277 union { 278 struct { 279 /* Destination ID, see PAACE_DID_* defines */ 280 u8 did; 281 /* Partition ID */ 282 u8 pid; 283 /* Snoop ID */ 284 u8 snpid; 285 /* coherency_required : 1 reserved : 7 */ 286 u8 coherency_required; /* See PAACE_DA_* */ 287 } to_host; 288 struct { 289 /* Destination ID, see PAACE_DID_* defines */ 290 u8 did; 291 u8 reserved1; 292 u16 reserved2; 293 } to_io; 294 } domain_attr; 295 296 /* Implementation attributes + window count + address & operation translation modes */ 297 u32 impl_attr; /* See PAACE_IA_* */ 298 299 /* PAACE Offset 0x10 */ 300 /* Translated window base address */ 301 u32 twbah; 302 u32 win_bitfields; /* See PAACE_WIN_* */ 303 304 /* PAACE Offset 0x18 */ 305 /* first secondary paace entry */ 306 u32 fspi; /* only valid for Primary PAACE */ 307 union { 308 struct { 309 u8 ioea; 310 u8 moea; 311 u8 ioeb; 312 u8 moeb; 313 } immed_ot; 314 struct { 315 u16 reserved; 316 u16 omi; 317 } index_ot; 318 } op_encode; 319 320 /* PAACE Offsets 0x20-0x38 */ 321 u32 reserved[8]; /* not currently implemented */ 322}; 323 324/* OME : Operation mapping entry 325 * MOE : Mapped Operation Encodings 326 * The operation mapping table is table containing operation mapping entries (OME). 327 * The index of a particular OME is programmed in the PAACE entry for translation 328 * in bound I/O operations corresponding to an LIODN. The OMT is used for translation 329 * specifically in case of the indexed translation mode. Each OME contains a 128 330 * byte mapped operation encoding (MOE), where each byte represents an MOE. 331 */ 332#define NUM_MOE 128 333struct ome { 334 u8 moe[NUM_MOE]; 335} __attribute__((packed)); 336 337#define PAACT_SIZE (sizeof(struct paace) * PAACE_NUMBER_ENTRIES) 338#define SPAACT_SIZE (sizeof(struct paace) * SPAACE_NUMBER_ENTRIES) 339#define OMT_SIZE (sizeof(struct ome) * OME_NUMBER_ENTRIES) 340 341#define PAMU_PAGE_SHIFT 12 342#define PAMU_PAGE_SIZE 4096ULL 343 344#define IOE_READ 0x00 345#define IOE_READ_IDX 0x00 346#define IOE_WRITE 0x81 347#define IOE_WRITE_IDX 0x01 348#define IOE_EREAD0 0x82 /* Enhanced read type 0 */ 349#define IOE_EREAD0_IDX 0x02 /* Enhanced read type 0 */ 350#define IOE_EWRITE0 0x83 /* Enhanced write type 0 */ 351#define IOE_EWRITE0_IDX 0x03 /* Enhanced write type 0 */ 352#define IOE_DIRECT0 0x84 /* Directive type 0 */ 353#define IOE_DIRECT0_IDX 0x04 /* Directive type 0 */ 354#define IOE_EREAD1 0x85 /* Enhanced read type 1 */ 355#define IOE_EREAD1_IDX 0x05 /* Enhanced read type 1 */ 356#define IOE_EWRITE1 0x86 /* Enhanced write type 1 */ 357#define IOE_EWRITE1_IDX 0x06 /* Enhanced write type 1 */ 358#define IOE_DIRECT1 0x87 /* Directive type 1 */ 359#define IOE_DIRECT1_IDX 0x07 /* Directive type 1 */ 360#define IOE_RAC 0x8c /* Read with Atomic clear */ 361#define IOE_RAC_IDX 0x0c /* Read with Atomic clear */ 362#define IOE_RAS 0x8d /* Read with Atomic set */ 363#define IOE_RAS_IDX 0x0d /* Read with Atomic set */ 364#define IOE_RAD 0x8e /* Read with Atomic decrement */ 365#define IOE_RAD_IDX 0x0e /* Read with Atomic decrement */ 366#define IOE_RAI 0x8f /* Read with Atomic increment */ 367#define IOE_RAI_IDX 0x0f /* Read with Atomic increment */ 368 369#define EOE_READ 0x00 370#define EOE_WRITE 0x01 371#define EOE_RAC 0x0c /* Read with Atomic clear */ 372#define EOE_RAS 0x0d /* Read with Atomic set */ 373#define EOE_RAD 0x0e /* Read with Atomic decrement */ 374#define EOE_RAI 0x0f /* Read with Atomic increment */ 375#define EOE_LDEC 0x10 /* Load external cache */ 376#define EOE_LDECL 0x11 /* Load external cache with stash lock */ 377#define EOE_LDECPE 0x12 /* Load external cache with preferred exclusive */ 378#define EOE_LDECPEL 0x13 /* Load external cache with preferred exclusive and lock */ 379#define EOE_LDECFE 0x14 /* Load external cache with forced exclusive */ 380#define EOE_LDECFEL 0x15 /* Load external cache with forced exclusive and lock */ 381#define EOE_RSA 0x16 /* Read with stash allocate */ 382#define EOE_RSAU 0x17 /* Read with stash allocate and unlock */ 383#define EOE_READI 0x18 /* Read with invalidate */ 384#define EOE_RWNITC 0x19 /* Read with no intention to cache */ 385#define EOE_WCI 0x1a /* Write cache inhibited */ 386#define EOE_WWSA 0x1b /* Write with stash allocate */ 387#define EOE_WWSAL 0x1c /* Write with stash allocate and lock */ 388#define EOE_WWSAO 0x1d /* Write with stash allocate only */ 389#define EOE_WWSAOL 0x1e /* Write with stash allocate only and lock */ 390#define EOE_VALID 0x80 391 392/* Function prototypes */ 393int pamu_domain_init(void); 394int pamu_enable_liodn(int liodn); 395int pamu_disable_liodn(int liodn); 396void pamu_free_subwins(int liodn); 397int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size, 398 u32 omi, unsigned long rpn, u32 snoopid, uint32_t stashid, 399 u32 subwin_cnt, int prot); 400int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin_addr, 401 phys_addr_t subwin_size, u32 omi, unsigned long rpn, 402 uint32_t snoopid, u32 stashid, int enable, int prot); 403 404u32 get_stash_id(u32 stash_dest_hint, u32 vcpu); 405void get_ome_index(u32 *omi_index, struct device *dev); 406int pamu_update_paace_stash(int liodn, u32 subwin, u32 value); 407int pamu_disable_spaace(int liodn, u32 subwin); 408u32 pamu_get_max_subwin_cnt(void); 409 410#endif /* __FSL_PAMU_H */ 411