1/* 2 * omap iommu: omap2/3 architecture specific functions 3 * 4 * Copyright (C) 2008-2009 Nokia Corporation 5 * 6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, 7 * Paul Mundt and Toshihiro Kobayashi 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#include <linux/err.h> 15#include <linux/device.h> 16#include <linux/io.h> 17#include <linux/jiffies.h> 18#include <linux/module.h> 19#include <linux/omap-iommu.h> 20#include <linux/slab.h> 21#include <linux/stringify.h> 22#include <linux/platform_data/iommu-omap.h> 23 24#include "omap-iommu.h" 25 26/* 27 * omap2 architecture specific register bit definitions 28 */ 29#define IOMMU_ARCH_VERSION 0x00000011 30 31/* IRQSTATUS & IRQENABLE */ 32#define MMU_IRQ_MULTIHITFAULT (1 << 4) 33#define MMU_IRQ_TABLEWALKFAULT (1 << 3) 34#define MMU_IRQ_EMUMISS (1 << 2) 35#define MMU_IRQ_TRANSLATIONFAULT (1 << 1) 36#define MMU_IRQ_TLBMISS (1 << 0) 37 38#define __MMU_IRQ_FAULT \ 39 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) 40#define MMU_IRQ_MASK \ 41 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) 42#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) 43#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) 44 45/* MMU_CNTL */ 46#define MMU_CNTL_SHIFT 1 47#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) 48#define MMU_CNTL_EML_TLB (1 << 3) 49#define MMU_CNTL_TWL_EN (1 << 2) 50#define MMU_CNTL_MMU_EN (1 << 1) 51 52#define get_cam_va_mask(pgsz) \ 53 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ 54 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ 55 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ 56 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) 57 58/* IOMMU errors */ 59#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0) 60#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1) 61#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2) 62#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3) 63#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4) 64 65static void __iommu_set_twl(struct omap_iommu *obj, bool on) 66{ 67 u32 l = iommu_read_reg(obj, MMU_CNTL); 68 69 if (on) 70 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); 71 else 72 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); 73 74 l &= ~MMU_CNTL_MASK; 75 if (on) 76 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); 77 else 78 l |= (MMU_CNTL_MMU_EN); 79 80 iommu_write_reg(obj, l, MMU_CNTL); 81} 82 83 84static int omap2_iommu_enable(struct omap_iommu *obj) 85{ 86 u32 l, pa; 87 88 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) 89 return -EINVAL; 90 91 pa = virt_to_phys(obj->iopgd); 92 if (!IS_ALIGNED(pa, SZ_16K)) 93 return -EINVAL; 94 95 l = iommu_read_reg(obj, MMU_REVISION); 96 dev_info(obj->dev, "%s: version %d.%d\n", obj->name, 97 (l >> 4) & 0xf, l & 0xf); 98 99 iommu_write_reg(obj, pa, MMU_TTB); 100 101 if (obj->has_bus_err_back) 102 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); 103 104 __iommu_set_twl(obj, true); 105 106 return 0; 107} 108 109static void omap2_iommu_disable(struct omap_iommu *obj) 110{ 111 u32 l = iommu_read_reg(obj, MMU_CNTL); 112 113 l &= ~MMU_CNTL_MASK; 114 iommu_write_reg(obj, l, MMU_CNTL); 115 116 dev_dbg(obj->dev, "%s is shutting down\n", obj->name); 117} 118 119static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on) 120{ 121 __iommu_set_twl(obj, false); 122} 123 124static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra) 125{ 126 u32 stat, da; 127 u32 errs = 0; 128 129 stat = iommu_read_reg(obj, MMU_IRQSTATUS); 130 stat &= MMU_IRQ_MASK; 131 if (!stat) { 132 *ra = 0; 133 return 0; 134 } 135 136 da = iommu_read_reg(obj, MMU_FAULT_AD); 137 *ra = da; 138 139 if (stat & MMU_IRQ_TLBMISS) 140 errs |= OMAP_IOMMU_ERR_TLB_MISS; 141 if (stat & MMU_IRQ_TRANSLATIONFAULT) 142 errs |= OMAP_IOMMU_ERR_TRANS_FAULT; 143 if (stat & MMU_IRQ_EMUMISS) 144 errs |= OMAP_IOMMU_ERR_EMU_MISS; 145 if (stat & MMU_IRQ_TABLEWALKFAULT) 146 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT; 147 if (stat & MMU_IRQ_MULTIHITFAULT) 148 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT; 149 iommu_write_reg(obj, stat, MMU_IRQSTATUS); 150 151 return errs; 152} 153 154static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) 155{ 156 cr->cam = iommu_read_reg(obj, MMU_READ_CAM); 157 cr->ram = iommu_read_reg(obj, MMU_READ_RAM); 158} 159 160static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) 161{ 162 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); 163 iommu_write_reg(obj, cr->ram, MMU_RAM); 164} 165 166static u32 omap2_cr_to_virt(struct cr_regs *cr) 167{ 168 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; 169 u32 mask = get_cam_va_mask(cr->cam & page_size); 170 171 return cr->cam & mask; 172} 173 174static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj, 175 struct iotlb_entry *e) 176{ 177 struct cr_regs *cr; 178 179 if (e->da & ~(get_cam_va_mask(e->pgsz))) { 180 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, 181 e->da); 182 return ERR_PTR(-EINVAL); 183 } 184 185 cr = kmalloc(sizeof(*cr), GFP_KERNEL); 186 if (!cr) 187 return ERR_PTR(-ENOMEM); 188 189 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; 190 cr->ram = e->pa | e->endian | e->elsz | e->mixed; 191 192 return cr; 193} 194 195static inline int omap2_cr_valid(struct cr_regs *cr) 196{ 197 return cr->cam & MMU_CAM_V; 198} 199 200static u32 omap2_get_pte_attr(struct iotlb_entry *e) 201{ 202 u32 attr; 203 204 attr = e->mixed << 5; 205 attr |= e->endian; 206 attr |= e->elsz >> 3; 207 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) || 208 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6); 209 return attr; 210} 211 212static ssize_t 213omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf) 214{ 215 char *p = buf; 216 217 /* FIXME: Need more detail analysis of cam/ram */ 218 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram, 219 (cr->cam & MMU_CAM_P) ? 1 : 0); 220 221 return p - buf; 222} 223 224#define pr_reg(name) \ 225 do { \ 226 ssize_t bytes; \ 227 const char *str = "%20s: %08x\n"; \ 228 const int maxcol = 32; \ 229 bytes = snprintf(p, maxcol, str, __stringify(name), \ 230 iommu_read_reg(obj, MMU_##name)); \ 231 p += bytes; \ 232 len -= bytes; \ 233 if (len < maxcol) \ 234 goto out; \ 235 } while (0) 236 237static ssize_t 238omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len) 239{ 240 char *p = buf; 241 242 pr_reg(REVISION); 243 pr_reg(IRQSTATUS); 244 pr_reg(IRQENABLE); 245 pr_reg(WALKING_ST); 246 pr_reg(CNTL); 247 pr_reg(FAULT_AD); 248 pr_reg(TTB); 249 pr_reg(LOCK); 250 pr_reg(LD_TLB); 251 pr_reg(CAM); 252 pr_reg(RAM); 253 pr_reg(GFLUSH); 254 pr_reg(FLUSH_ENTRY); 255 pr_reg(READ_CAM); 256 pr_reg(READ_RAM); 257 pr_reg(EMU_FAULT_AD); 258out: 259 return p - buf; 260} 261 262static void omap2_iommu_save_ctx(struct omap_iommu *obj) 263{ 264 int i; 265 u32 *p = obj->ctx; 266 267 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { 268 p[i] = iommu_read_reg(obj, i * sizeof(u32)); 269 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); 270 } 271 272 BUG_ON(p[0] != IOMMU_ARCH_VERSION); 273} 274 275static void omap2_iommu_restore_ctx(struct omap_iommu *obj) 276{ 277 int i; 278 u32 *p = obj->ctx; 279 280 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { 281 iommu_write_reg(obj, p[i], i * sizeof(u32)); 282 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); 283 } 284 285 BUG_ON(p[0] != IOMMU_ARCH_VERSION); 286} 287 288static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) 289{ 290 e->da = cr->cam & MMU_CAM_VATAG_MASK; 291 e->pa = cr->ram & MMU_RAM_PADDR_MASK; 292 e->valid = cr->cam & MMU_CAM_V; 293 e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK; 294 e->endian = cr->ram & MMU_RAM_ENDIAN_MASK; 295 e->elsz = cr->ram & MMU_RAM_ELSZ_MASK; 296 e->mixed = cr->ram & MMU_RAM_MIXED; 297} 298 299static const struct iommu_functions omap2_iommu_ops = { 300 .version = IOMMU_ARCH_VERSION, 301 302 .enable = omap2_iommu_enable, 303 .disable = omap2_iommu_disable, 304 .set_twl = omap2_iommu_set_twl, 305 .fault_isr = omap2_iommu_fault_isr, 306 307 .tlb_read_cr = omap2_tlb_read_cr, 308 .tlb_load_cr = omap2_tlb_load_cr, 309 310 .cr_to_e = omap2_cr_to_e, 311 .cr_to_virt = omap2_cr_to_virt, 312 .alloc_cr = omap2_alloc_cr, 313 .cr_valid = omap2_cr_valid, 314 .dump_cr = omap2_dump_cr, 315 316 .get_pte_attr = omap2_get_pte_attr, 317 318 .save_ctx = omap2_iommu_save_ctx, 319 .restore_ctx = omap2_iommu_restore_ctx, 320 .dump_ctx = omap2_iommu_dump_ctx, 321}; 322 323static int __init omap2_iommu_init(void) 324{ 325 return omap_install_iommu_arch(&omap2_iommu_ops); 326} 327module_init(omap2_iommu_init); 328 329static void __exit omap2_iommu_exit(void) 330{ 331 omap_uninstall_iommu_arch(&omap2_iommu_ops); 332} 333module_exit(omap2_iommu_exit); 334 335MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); 336MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions"); 337MODULE_LICENSE("GPL v2"); 338