mt312.c revision 9a0bf528b4d66b605f02634236da085595c22101
1/* 2 Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder 3 4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org> 5 Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22 References: 23 http://products.zarlink.com/product_profiles/MT312.htm 24 http://products.zarlink.com/product_profiles/SL1935.htm 25*/ 26 27#include <linux/delay.h> 28#include <linux/errno.h> 29#include <linux/init.h> 30#include <linux/kernel.h> 31#include <linux/module.h> 32#include <linux/string.h> 33#include <linux/slab.h> 34 35#include "dvb_frontend.h" 36#include "mt312_priv.h" 37#include "mt312.h" 38 39 40struct mt312_state { 41 struct i2c_adapter *i2c; 42 /* configuration settings */ 43 const struct mt312_config *config; 44 struct dvb_frontend frontend; 45 46 u8 id; 47 unsigned long xtal; 48 u8 freq_mult; 49}; 50 51static int debug; 52#define dprintk(args...) \ 53 do { \ 54 if (debug) \ 55 printk(KERN_DEBUG "mt312: " args); \ 56 } while (0) 57 58#define MT312_PLL_CLK 10000000UL /* 10 MHz */ 59#define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */ 60 61static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg, 62 u8 *buf, const size_t count) 63{ 64 int ret; 65 struct i2c_msg msg[2]; 66 u8 regbuf[1] = { reg }; 67 68 msg[0].addr = state->config->demod_address; 69 msg[0].flags = 0; 70 msg[0].buf = regbuf; 71 msg[0].len = 1; 72 msg[1].addr = state->config->demod_address; 73 msg[1].flags = I2C_M_RD; 74 msg[1].buf = buf; 75 msg[1].len = count; 76 77 ret = i2c_transfer(state->i2c, msg, 2); 78 79 if (ret != 2) { 80 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret); 81 return -EREMOTEIO; 82 } 83 84 if (debug) { 85 int i; 86 dprintk("R(%d):", reg & 0x7f); 87 for (i = 0; i < count; i++) 88 printk(KERN_CONT " %02x", buf[i]); 89 printk("\n"); 90 } 91 92 return 0; 93} 94 95static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg, 96 const u8 *src, const size_t count) 97{ 98 int ret; 99 u8 buf[count + 1]; 100 struct i2c_msg msg; 101 102 if (debug) { 103 int i; 104 dprintk("W(%d):", reg & 0x7f); 105 for (i = 0; i < count; i++) 106 printk(KERN_CONT " %02x", src[i]); 107 printk("\n"); 108 } 109 110 buf[0] = reg; 111 memcpy(&buf[1], src, count); 112 113 msg.addr = state->config->demod_address; 114 msg.flags = 0; 115 msg.buf = buf; 116 msg.len = count + 1; 117 118 ret = i2c_transfer(state->i2c, &msg, 1); 119 120 if (ret != 1) { 121 dprintk("%s: ret == %d\n", __func__, ret); 122 return -EREMOTEIO; 123 } 124 125 return 0; 126} 127 128static inline int mt312_readreg(struct mt312_state *state, 129 const enum mt312_reg_addr reg, u8 *val) 130{ 131 return mt312_read(state, reg, val, 1); 132} 133 134static inline int mt312_writereg(struct mt312_state *state, 135 const enum mt312_reg_addr reg, const u8 val) 136{ 137 return mt312_write(state, reg, &val, 1); 138} 139 140static inline u32 mt312_div(u32 a, u32 b) 141{ 142 return (a + (b / 2)) / b; 143} 144 145static int mt312_reset(struct mt312_state *state, const u8 full) 146{ 147 return mt312_writereg(state, RESET, full ? 0x80 : 0x40); 148} 149 150static int mt312_get_inversion(struct mt312_state *state, 151 fe_spectral_inversion_t *i) 152{ 153 int ret; 154 u8 vit_mode; 155 156 ret = mt312_readreg(state, VIT_MODE, &vit_mode); 157 if (ret < 0) 158 return ret; 159 160 if (vit_mode & 0x80) /* auto inversion was used */ 161 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF; 162 163 return 0; 164} 165 166static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr) 167{ 168 int ret; 169 u8 sym_rate_h; 170 u8 dec_ratio; 171 u16 sym_rat_op; 172 u16 monitor; 173 u8 buf[2]; 174 175 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); 176 if (ret < 0) 177 return ret; 178 179 if (sym_rate_h & 0x80) { 180 /* symbol rate search was used */ 181 ret = mt312_writereg(state, MON_CTRL, 0x03); 182 if (ret < 0) 183 return ret; 184 185 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); 186 if (ret < 0) 187 return ret; 188 189 monitor = (buf[0] << 8) | buf[1]; 190 191 dprintk("sr(auto) = %u\n", 192 mt312_div(monitor * 15625, 4)); 193 } else { 194 ret = mt312_writereg(state, MON_CTRL, 0x05); 195 if (ret < 0) 196 return ret; 197 198 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); 199 if (ret < 0) 200 return ret; 201 202 dec_ratio = ((buf[0] >> 5) & 0x07) * 32; 203 204 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); 205 if (ret < 0) 206 return ret; 207 208 sym_rat_op = (buf[0] << 8) | buf[1]; 209 210 dprintk("sym_rat_op=%d dec_ratio=%d\n", 211 sym_rat_op, dec_ratio); 212 dprintk("*sr(manual) = %lu\n", 213 (((state->xtal * 8192) / (sym_rat_op + 8192)) * 214 2) - dec_ratio); 215 } 216 217 return 0; 218} 219 220static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr) 221{ 222 const fe_code_rate_t fec_tab[8] = 223 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8, 224 FEC_AUTO, FEC_AUTO }; 225 226 int ret; 227 u8 fec_status; 228 229 ret = mt312_readreg(state, FEC_STATUS, &fec_status); 230 if (ret < 0) 231 return ret; 232 233 *cr = fec_tab[(fec_status >> 4) & 0x07]; 234 235 return 0; 236} 237 238static int mt312_initfe(struct dvb_frontend *fe) 239{ 240 struct mt312_state *state = fe->demodulator_priv; 241 int ret; 242 u8 buf[2]; 243 244 /* wake up */ 245 ret = mt312_writereg(state, CONFIG, 246 (state->freq_mult == 6 ? 0x88 : 0x8c)); 247 if (ret < 0) 248 return ret; 249 250 /* wait at least 150 usec */ 251 udelay(150); 252 253 /* full reset */ 254 ret = mt312_reset(state, 1); 255 if (ret < 0) 256 return ret; 257 258/* Per datasheet, write correct values. 09/28/03 ACCJr. 259 * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */ 260 { 261 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02, 262 0x01, 0x00, 0x00, 0x00 }; 263 264 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); 265 if (ret < 0) 266 return ret; 267 } 268 269 switch (state->id) { 270 case ID_ZL10313: 271 /* enable ADC */ 272 ret = mt312_writereg(state, GPP_CTRL, 0x80); 273 if (ret < 0) 274 return ret; 275 276 /* configure ZL10313 for optimal ADC performance */ 277 buf[0] = 0x80; 278 buf[1] = 0xB0; 279 ret = mt312_write(state, HW_CTRL, buf, 2); 280 if (ret < 0) 281 return ret; 282 283 /* enable MPEG output and ADCs */ 284 ret = mt312_writereg(state, HW_CTRL, 0x00); 285 if (ret < 0) 286 return ret; 287 288 ret = mt312_writereg(state, MPEG_CTRL, 0x00); 289 if (ret < 0) 290 return ret; 291 292 break; 293 } 294 295 /* SYS_CLK */ 296 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000); 297 298 /* DISEQC_RATIO */ 299 buf[1] = mt312_div(state->xtal, 22000 * 4); 300 301 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); 302 if (ret < 0) 303 return ret; 304 305 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); 306 if (ret < 0) 307 return ret; 308 309 /* different MOCLK polarity */ 310 switch (state->id) { 311 case ID_ZL10313: 312 buf[0] = 0x33; 313 break; 314 default: 315 buf[0] = 0x53; 316 break; 317 } 318 319 ret = mt312_writereg(state, OP_CTRL, buf[0]); 320 if (ret < 0) 321 return ret; 322 323 /* TS_SW_LIM */ 324 buf[0] = 0x8c; 325 buf[1] = 0x98; 326 327 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); 328 if (ret < 0) 329 return ret; 330 331 ret = mt312_writereg(state, CS_SW_LIM, 0x69); 332 if (ret < 0) 333 return ret; 334 335 return 0; 336} 337 338static int mt312_send_master_cmd(struct dvb_frontend *fe, 339 struct dvb_diseqc_master_cmd *c) 340{ 341 struct mt312_state *state = fe->demodulator_priv; 342 int ret; 343 u8 diseqc_mode; 344 345 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg))) 346 return -EINVAL; 347 348 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 349 if (ret < 0) 350 return ret; 351 352 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); 353 if (ret < 0) 354 return ret; 355 356 ret = mt312_writereg(state, DISEQC_MODE, 357 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3) 358 | 0x04); 359 if (ret < 0) 360 return ret; 361 362 /* is there a better way to wait for message to be transmitted */ 363 msleep(100); 364 365 /* set DISEQC_MODE[2:0] to zero if a return message is expected */ 366 if (c->msg[0] & 0x02) { 367 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); 368 if (ret < 0) 369 return ret; 370 } 371 372 return 0; 373} 374 375static int mt312_send_burst(struct dvb_frontend *fe, const fe_sec_mini_cmd_t c) 376{ 377 struct mt312_state *state = fe->demodulator_priv; 378 const u8 mini_tab[2] = { 0x02, 0x03 }; 379 380 int ret; 381 u8 diseqc_mode; 382 383 if (c > SEC_MINI_B) 384 return -EINVAL; 385 386 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 387 if (ret < 0) 388 return ret; 389 390 ret = mt312_writereg(state, DISEQC_MODE, 391 (diseqc_mode & 0x40) | mini_tab[c]); 392 if (ret < 0) 393 return ret; 394 395 return 0; 396} 397 398static int mt312_set_tone(struct dvb_frontend *fe, const fe_sec_tone_mode_t t) 399{ 400 struct mt312_state *state = fe->demodulator_priv; 401 const u8 tone_tab[2] = { 0x01, 0x00 }; 402 403 int ret; 404 u8 diseqc_mode; 405 406 if (t > SEC_TONE_OFF) 407 return -EINVAL; 408 409 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 410 if (ret < 0) 411 return ret; 412 413 ret = mt312_writereg(state, DISEQC_MODE, 414 (diseqc_mode & 0x40) | tone_tab[t]); 415 if (ret < 0) 416 return ret; 417 418 return 0; 419} 420 421static int mt312_set_voltage(struct dvb_frontend *fe, const fe_sec_voltage_t v) 422{ 423 struct mt312_state *state = fe->demodulator_priv; 424 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 }; 425 u8 val; 426 427 if (v > SEC_VOLTAGE_OFF) 428 return -EINVAL; 429 430 val = volt_tab[v]; 431 if (state->config->voltage_inverted) 432 val ^= 0x40; 433 434 return mt312_writereg(state, DISEQC_MODE, val); 435} 436 437static int mt312_read_status(struct dvb_frontend *fe, fe_status_t *s) 438{ 439 struct mt312_state *state = fe->demodulator_priv; 440 int ret; 441 u8 status[3]; 442 443 *s = 0; 444 445 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); 446 if (ret < 0) 447 return ret; 448 449 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x," 450 " FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]); 451 452 if (status[0] & 0xc0) 453 *s |= FE_HAS_SIGNAL; /* signal noise ratio */ 454 if (status[0] & 0x04) 455 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */ 456 if (status[2] & 0x02) 457 *s |= FE_HAS_VITERBI; /* viterbi lock */ 458 if (status[2] & 0x04) 459 *s |= FE_HAS_SYNC; /* byte align lock */ 460 if (status[0] & 0x01) 461 *s |= FE_HAS_LOCK; /* qpsk lock */ 462 463 return 0; 464} 465 466static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber) 467{ 468 struct mt312_state *state = fe->demodulator_priv; 469 int ret; 470 u8 buf[3]; 471 472 ret = mt312_read(state, RS_BERCNT_H, buf, 3); 473 if (ret < 0) 474 return ret; 475 476 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64; 477 478 return 0; 479} 480 481static int mt312_read_signal_strength(struct dvb_frontend *fe, 482 u16 *signal_strength) 483{ 484 struct mt312_state *state = fe->demodulator_priv; 485 int ret; 486 u8 buf[3]; 487 u16 agc; 488 s16 err_db; 489 490 ret = mt312_read(state, AGC_H, buf, sizeof(buf)); 491 if (ret < 0) 492 return ret; 493 494 agc = (buf[0] << 6) | (buf[1] >> 2); 495 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6; 496 497 *signal_strength = agc; 498 499 dprintk("agc=%08x err_db=%hd\n", agc, err_db); 500 501 return 0; 502} 503 504static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr) 505{ 506 struct mt312_state *state = fe->demodulator_priv; 507 int ret; 508 u8 buf[2]; 509 510 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); 511 if (ret < 0) 512 return ret; 513 514 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1); 515 516 return 0; 517} 518 519static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc) 520{ 521 struct mt312_state *state = fe->demodulator_priv; 522 int ret; 523 u8 buf[2]; 524 525 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); 526 if (ret < 0) 527 return ret; 528 529 *ubc = (buf[0] << 8) | buf[1]; 530 531 return 0; 532} 533 534static int mt312_set_frontend(struct dvb_frontend *fe) 535{ 536 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 537 struct mt312_state *state = fe->demodulator_priv; 538 int ret; 539 u8 buf[5], config_val; 540 u16 sr; 541 542 const u8 fec_tab[10] = 543 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f }; 544 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 }; 545 546 dprintk("%s: Freq %d\n", __func__, p->frequency); 547 548 if ((p->frequency < fe->ops.info.frequency_min) 549 || (p->frequency > fe->ops.info.frequency_max)) 550 return -EINVAL; 551 552 if ((p->inversion < INVERSION_OFF) 553 || (p->inversion > INVERSION_ON)) 554 return -EINVAL; 555 556 if ((p->symbol_rate < fe->ops.info.symbol_rate_min) 557 || (p->symbol_rate > fe->ops.info.symbol_rate_max)) 558 return -EINVAL; 559 560 if ((p->fec_inner < FEC_NONE) 561 || (p->fec_inner > FEC_AUTO)) 562 return -EINVAL; 563 564 if ((p->fec_inner == FEC_4_5) 565 || (p->fec_inner == FEC_8_9)) 566 return -EINVAL; 567 568 switch (state->id) { 569 case ID_VP310: 570 /* For now we will do this only for the VP310. 571 * It should be better for the mt312 as well, 572 * but tuning will be slower. ACCJr 09/29/03 573 */ 574 ret = mt312_readreg(state, CONFIG, &config_val); 575 if (ret < 0) 576 return ret; 577 if (p->symbol_rate >= 30000000) { 578 /* Note that 30MS/s should use 90MHz */ 579 if (state->freq_mult == 6) { 580 /* We are running 60MHz */ 581 state->freq_mult = 9; 582 ret = mt312_initfe(fe); 583 if (ret < 0) 584 return ret; 585 } 586 } else { 587 if (state->freq_mult == 9) { 588 /* We are running 90MHz */ 589 state->freq_mult = 6; 590 ret = mt312_initfe(fe); 591 if (ret < 0) 592 return ret; 593 } 594 } 595 break; 596 597 case ID_MT312: 598 case ID_ZL10313: 599 break; 600 601 default: 602 return -EINVAL; 603 } 604 605 if (fe->ops.tuner_ops.set_params) { 606 fe->ops.tuner_ops.set_params(fe); 607 if (fe->ops.i2c_gate_ctrl) 608 fe->ops.i2c_gate_ctrl(fe, 0); 609 } 610 611 /* sr = (u16)(sr * 256.0 / 1000000.0) */ 612 sr = mt312_div(p->symbol_rate * 4, 15625); 613 614 /* SYM_RATE */ 615 buf[0] = (sr >> 8) & 0x3f; 616 buf[1] = (sr >> 0) & 0xff; 617 618 /* VIT_MODE */ 619 buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner]; 620 621 /* QPSK_CTRL */ 622 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */ 623 624 if (p->symbol_rate < 10000000) 625 buf[3] |= 0x04; /* use afc mode */ 626 627 /* GO */ 628 buf[4] = 0x01; 629 630 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); 631 if (ret < 0) 632 return ret; 633 634 mt312_reset(state, 0); 635 636 return 0; 637} 638 639static int mt312_get_frontend(struct dvb_frontend *fe) 640{ 641 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 642 struct mt312_state *state = fe->demodulator_priv; 643 int ret; 644 645 ret = mt312_get_inversion(state, &p->inversion); 646 if (ret < 0) 647 return ret; 648 649 ret = mt312_get_symbol_rate(state, &p->symbol_rate); 650 if (ret < 0) 651 return ret; 652 653 ret = mt312_get_code_rate(state, &p->fec_inner); 654 if (ret < 0) 655 return ret; 656 657 return 0; 658} 659 660static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 661{ 662 struct mt312_state *state = fe->demodulator_priv; 663 664 u8 val = 0x00; 665 int ret; 666 667 switch (state->id) { 668 case ID_ZL10313: 669 ret = mt312_readreg(state, GPP_CTRL, &val); 670 if (ret < 0) 671 goto error; 672 673 /* preserve this bit to not accidentally shutdown ADC */ 674 val &= 0x80; 675 break; 676 } 677 678 if (enable) 679 val |= 0x40; 680 else 681 val &= ~0x40; 682 683 ret = mt312_writereg(state, GPP_CTRL, val); 684 685error: 686 return ret; 687} 688 689static int mt312_sleep(struct dvb_frontend *fe) 690{ 691 struct mt312_state *state = fe->demodulator_priv; 692 int ret; 693 u8 config; 694 695 /* reset all registers to defaults */ 696 ret = mt312_reset(state, 1); 697 if (ret < 0) 698 return ret; 699 700 if (state->id == ID_ZL10313) { 701 /* reset ADC */ 702 ret = mt312_writereg(state, GPP_CTRL, 0x00); 703 if (ret < 0) 704 return ret; 705 706 /* full shutdown of ADCs, mpeg bus tristated */ 707 ret = mt312_writereg(state, HW_CTRL, 0x0d); 708 if (ret < 0) 709 return ret; 710 } 711 712 ret = mt312_readreg(state, CONFIG, &config); 713 if (ret < 0) 714 return ret; 715 716 /* enter standby */ 717 ret = mt312_writereg(state, CONFIG, config & 0x7f); 718 if (ret < 0) 719 return ret; 720 721 return 0; 722} 723 724static int mt312_get_tune_settings(struct dvb_frontend *fe, 725 struct dvb_frontend_tune_settings *fesettings) 726{ 727 fesettings->min_delay_ms = 50; 728 fesettings->step_size = 0; 729 fesettings->max_drift = 0; 730 return 0; 731} 732 733static void mt312_release(struct dvb_frontend *fe) 734{ 735 struct mt312_state *state = fe->demodulator_priv; 736 kfree(state); 737} 738 739#define MT312_SYS_CLK 90000000UL /* 90 MHz */ 740static struct dvb_frontend_ops mt312_ops = { 741 .delsys = { SYS_DVBS }, 742 .info = { 743 .name = "Zarlink ???? DVB-S", 744 .frequency_min = 950000, 745 .frequency_max = 2150000, 746 /* FIXME: adjust freq to real used xtal */ 747 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128, 748 .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */ 749 .symbol_rate_max = MT312_SYS_CLK / 2, 750 .caps = 751 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 752 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 753 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS | 754 FE_CAN_RECOVER 755 }, 756 757 .release = mt312_release, 758 759 .init = mt312_initfe, 760 .sleep = mt312_sleep, 761 .i2c_gate_ctrl = mt312_i2c_gate_ctrl, 762 763 .set_frontend = mt312_set_frontend, 764 .get_frontend = mt312_get_frontend, 765 .get_tune_settings = mt312_get_tune_settings, 766 767 .read_status = mt312_read_status, 768 .read_ber = mt312_read_ber, 769 .read_signal_strength = mt312_read_signal_strength, 770 .read_snr = mt312_read_snr, 771 .read_ucblocks = mt312_read_ucblocks, 772 773 .diseqc_send_master_cmd = mt312_send_master_cmd, 774 .diseqc_send_burst = mt312_send_burst, 775 .set_tone = mt312_set_tone, 776 .set_voltage = mt312_set_voltage, 777}; 778 779struct dvb_frontend *mt312_attach(const struct mt312_config *config, 780 struct i2c_adapter *i2c) 781{ 782 struct mt312_state *state = NULL; 783 784 /* allocate memory for the internal state */ 785 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL); 786 if (state == NULL) 787 goto error; 788 789 /* setup the state */ 790 state->config = config; 791 state->i2c = i2c; 792 793 /* check if the demod is there */ 794 if (mt312_readreg(state, ID, &state->id) < 0) 795 goto error; 796 797 /* create dvb_frontend */ 798 memcpy(&state->frontend.ops, &mt312_ops, 799 sizeof(struct dvb_frontend_ops)); 800 state->frontend.demodulator_priv = state; 801 802 switch (state->id) { 803 case ID_VP310: 804 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S"); 805 state->xtal = MT312_PLL_CLK; 806 state->freq_mult = 9; 807 break; 808 case ID_MT312: 809 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S"); 810 state->xtal = MT312_PLL_CLK; 811 state->freq_mult = 6; 812 break; 813 case ID_ZL10313: 814 strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S"); 815 state->xtal = MT312_PLL_CLK_10_111; 816 state->freq_mult = 9; 817 break; 818 default: 819 printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313" 820 " are supported chips.\n"); 821 goto error; 822 } 823 824 return &state->frontend; 825 826error: 827 kfree(state); 828 return NULL; 829} 830EXPORT_SYMBOL(mt312_attach); 831 832module_param(debug, int, 0644); 833MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 834 835MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver"); 836MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>"); 837MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>"); 838MODULE_LICENSE("GPL"); 839 840