1/* 2 NXP TDA10048HN DVB OFDM demodulator driver 3 4 Copyright (C) 2009 Steven Toth <stoth@kernellabs.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20*/ 21 22#include <linux/kernel.h> 23#include <linux/init.h> 24#include <linux/module.h> 25#include <linux/string.h> 26#include <linux/slab.h> 27#include <linux/delay.h> 28#include <linux/math64.h> 29#include <asm/div64.h> 30#include "dvb_frontend.h" 31#include "dvb_math.h" 32#include "tda10048.h" 33 34#define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw" 35#define TDA10048_DEFAULT_FIRMWARE_SIZE 24878 36 37/* Register name definitions */ 38#define TDA10048_IDENTITY 0x00 39#define TDA10048_VERSION 0x01 40#define TDA10048_DSP_CODE_CPT 0x0C 41#define TDA10048_DSP_CODE_IN 0x0E 42#define TDA10048_IN_CONF1 0x10 43#define TDA10048_IN_CONF2 0x11 44#define TDA10048_IN_CONF3 0x12 45#define TDA10048_OUT_CONF1 0x14 46#define TDA10048_OUT_CONF2 0x15 47#define TDA10048_OUT_CONF3 0x16 48#define TDA10048_AUTO 0x18 49#define TDA10048_SYNC_STATUS 0x1A 50#define TDA10048_CONF_C4_1 0x1E 51#define TDA10048_CONF_C4_2 0x1F 52#define TDA10048_CODE_IN_RAM 0x20 53#define TDA10048_CHANNEL_INFO1_R 0x22 54#define TDA10048_CHANNEL_INFO2_R 0x23 55#define TDA10048_CHANNEL_INFO1 0x24 56#define TDA10048_CHANNEL_INFO2 0x25 57#define TDA10048_TIME_ERROR_R 0x26 58#define TDA10048_TIME_ERROR 0x27 59#define TDA10048_FREQ_ERROR_LSB_R 0x28 60#define TDA10048_FREQ_ERROR_MSB_R 0x29 61#define TDA10048_FREQ_ERROR_LSB 0x2A 62#define TDA10048_FREQ_ERROR_MSB 0x2B 63#define TDA10048_IT_SEL 0x30 64#define TDA10048_IT_STAT 0x32 65#define TDA10048_DSP_AD_LSB 0x3C 66#define TDA10048_DSP_AD_MSB 0x3D 67#define TDA10048_DSP_REG_LSB 0x3E 68#define TDA10048_DSP_REG_MSB 0x3F 69#define TDA10048_CONF_TRISTATE1 0x44 70#define TDA10048_CONF_TRISTATE2 0x45 71#define TDA10048_CONF_POLARITY 0x46 72#define TDA10048_GPIO_SP_DS0 0x48 73#define TDA10048_GPIO_SP_DS1 0x49 74#define TDA10048_GPIO_SP_DS2 0x4A 75#define TDA10048_GPIO_SP_DS3 0x4B 76#define TDA10048_GPIO_OUT_SEL 0x4C 77#define TDA10048_GPIO_SELECT 0x4D 78#define TDA10048_IC_MODE 0x4E 79#define TDA10048_CONF_XO 0x50 80#define TDA10048_CONF_PLL1 0x51 81#define TDA10048_CONF_PLL2 0x52 82#define TDA10048_CONF_PLL3 0x53 83#define TDA10048_CONF_ADC 0x54 84#define TDA10048_CONF_ADC_2 0x55 85#define TDA10048_CONF_C1_1 0x60 86#define TDA10048_CONF_C1_3 0x62 87#define TDA10048_AGC_CONF 0x70 88#define TDA10048_AGC_THRESHOLD_LSB 0x72 89#define TDA10048_AGC_THRESHOLD_MSB 0x73 90#define TDA10048_AGC_RENORM 0x74 91#define TDA10048_AGC_GAINS 0x76 92#define TDA10048_AGC_TUN_MIN 0x78 93#define TDA10048_AGC_TUN_MAX 0x79 94#define TDA10048_AGC_IF_MIN 0x7A 95#define TDA10048_AGC_IF_MAX 0x7B 96#define TDA10048_AGC_TUN_LEVEL 0x7E 97#define TDA10048_AGC_IF_LEVEL 0x7F 98#define TDA10048_DIG_AGC_LEVEL 0x81 99#define TDA10048_FREQ_PHY2_LSB 0x86 100#define TDA10048_FREQ_PHY2_MSB 0x87 101#define TDA10048_TIME_INVWREF_LSB 0x88 102#define TDA10048_TIME_INVWREF_MSB 0x89 103#define TDA10048_TIME_WREF_LSB 0x8A 104#define TDA10048_TIME_WREF_MID1 0x8B 105#define TDA10048_TIME_WREF_MID2 0x8C 106#define TDA10048_TIME_WREF_MSB 0x8D 107#define TDA10048_NP_OUT 0xA2 108#define TDA10048_CELL_ID_LSB 0xA4 109#define TDA10048_CELL_ID_MSB 0xA5 110#define TDA10048_EXTTPS_ODD 0xAA 111#define TDA10048_EXTTPS_EVEN 0xAB 112#define TDA10048_TPS_LENGTH 0xAC 113#define TDA10048_FREE_REG_1 0xB2 114#define TDA10048_FREE_REG_2 0xB3 115#define TDA10048_CONF_C3_1 0xC0 116#define TDA10048_CVBER_CTRL 0xC2 117#define TDA10048_CBER_NMAX_LSB 0xC4 118#define TDA10048_CBER_NMAX_MSB 0xC5 119#define TDA10048_CBER_LSB 0xC6 120#define TDA10048_CBER_MSB 0xC7 121#define TDA10048_VBER_LSB 0xC8 122#define TDA10048_VBER_MID 0xC9 123#define TDA10048_VBER_MSB 0xCA 124#define TDA10048_CVBER_LUT 0xCC 125#define TDA10048_UNCOR_CTRL 0xCD 126#define TDA10048_UNCOR_CPT_LSB 0xCE 127#define TDA10048_UNCOR_CPT_MSB 0xCF 128#define TDA10048_SOFT_IT_C3 0xD6 129#define TDA10048_CONF_TS2 0xE0 130#define TDA10048_CONF_TS1 0xE1 131 132static unsigned int debug; 133 134#define dprintk(level, fmt, arg...)\ 135 do { if (debug >= level)\ 136 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\ 137 } while (0) 138 139struct tda10048_state { 140 141 struct i2c_adapter *i2c; 142 143 /* We'll cache and update the attach config settings */ 144 struct tda10048_config config; 145 struct dvb_frontend frontend; 146 147 int fwloaded; 148 149 u32 freq_if_hz; 150 u32 xtal_hz; 151 u32 pll_mfactor; 152 u32 pll_nfactor; 153 u32 pll_pfactor; 154 u32 sample_freq; 155 156 u32 bandwidth; 157}; 158 159static struct init_tab { 160 u8 reg; 161 u16 data; 162} init_tab[] = { 163 { TDA10048_CONF_PLL1, 0x08 }, 164 { TDA10048_CONF_ADC_2, 0x00 }, 165 { TDA10048_CONF_C4_1, 0x00 }, 166 { TDA10048_CONF_PLL1, 0x0f }, 167 { TDA10048_CONF_PLL2, 0x0a }, 168 { TDA10048_CONF_PLL3, 0x43 }, 169 { TDA10048_FREQ_PHY2_LSB, 0x02 }, 170 { TDA10048_FREQ_PHY2_MSB, 0x0a }, 171 { TDA10048_TIME_WREF_LSB, 0xbd }, 172 { TDA10048_TIME_WREF_MID1, 0xe4 }, 173 { TDA10048_TIME_WREF_MID2, 0xa8 }, 174 { TDA10048_TIME_WREF_MSB, 0x02 }, 175 { TDA10048_TIME_INVWREF_LSB, 0x04 }, 176 { TDA10048_TIME_INVWREF_MSB, 0x06 }, 177 { TDA10048_CONF_C4_1, 0x00 }, 178 { TDA10048_CONF_C1_1, 0xa8 }, 179 { TDA10048_AGC_CONF, 0x16 }, 180 { TDA10048_CONF_C1_3, 0x0b }, 181 { TDA10048_AGC_TUN_MIN, 0x00 }, 182 { TDA10048_AGC_TUN_MAX, 0xff }, 183 { TDA10048_AGC_IF_MIN, 0x00 }, 184 { TDA10048_AGC_IF_MAX, 0xff }, 185 { TDA10048_AGC_THRESHOLD_MSB, 0x00 }, 186 { TDA10048_AGC_THRESHOLD_LSB, 0x70 }, 187 { TDA10048_CVBER_CTRL, 0x38 }, 188 { TDA10048_AGC_GAINS, 0x12 }, 189 { TDA10048_CONF_XO, 0x00 }, 190 { TDA10048_CONF_TS1, 0x07 }, 191 { TDA10048_IC_MODE, 0x00 }, 192 { TDA10048_CONF_TS2, 0xc0 }, 193 { TDA10048_CONF_TRISTATE1, 0x21 }, 194 { TDA10048_CONF_TRISTATE2, 0x00 }, 195 { TDA10048_CONF_POLARITY, 0x00 }, 196 { TDA10048_CONF_C4_2, 0x04 }, 197 { TDA10048_CONF_ADC, 0x60 }, 198 { TDA10048_CONF_ADC_2, 0x10 }, 199 { TDA10048_CONF_ADC, 0x60 }, 200 { TDA10048_CONF_ADC_2, 0x00 }, 201 { TDA10048_CONF_C1_1, 0xa8 }, 202 { TDA10048_UNCOR_CTRL, 0x00 }, 203 { TDA10048_CONF_C4_2, 0x04 }, 204}; 205 206static struct pll_tab { 207 u32 clk_freq_khz; 208 u32 if_freq_khz; 209} pll_tab[] = { 210 { TDA10048_CLK_4000, TDA10048_IF_36130 }, 211 { TDA10048_CLK_16000, TDA10048_IF_3300 }, 212 { TDA10048_CLK_16000, TDA10048_IF_3500 }, 213 { TDA10048_CLK_16000, TDA10048_IF_3800 }, 214 { TDA10048_CLK_16000, TDA10048_IF_4000 }, 215 { TDA10048_CLK_16000, TDA10048_IF_4300 }, 216 { TDA10048_CLK_16000, TDA10048_IF_4500 }, 217 { TDA10048_CLK_16000, TDA10048_IF_5000 }, 218 { TDA10048_CLK_16000, TDA10048_IF_36130 }, 219}; 220 221static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data) 222{ 223 struct tda10048_config *config = &state->config; 224 int ret; 225 u8 buf[] = { reg, data }; 226 struct i2c_msg msg = { 227 .addr = config->demod_address, 228 .flags = 0, .buf = buf, .len = 2 }; 229 230 dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data); 231 232 ret = i2c_transfer(state->i2c, &msg, 1); 233 234 if (ret != 1) 235 printk("%s: writereg error (ret == %i)\n", __func__, ret); 236 237 return (ret != 1) ? -1 : 0; 238} 239 240static u8 tda10048_readreg(struct tda10048_state *state, u8 reg) 241{ 242 struct tda10048_config *config = &state->config; 243 int ret; 244 u8 b0[] = { reg }; 245 u8 b1[] = { 0 }; 246 struct i2c_msg msg[] = { 247 { .addr = config->demod_address, 248 .flags = 0, .buf = b0, .len = 1 }, 249 { .addr = config->demod_address, 250 .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 251 252 dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg); 253 254 ret = i2c_transfer(state->i2c, msg, 2); 255 256 if (ret != 2) 257 printk(KERN_ERR "%s: readreg error (ret == %i)\n", 258 __func__, ret); 259 260 return b1[0]; 261} 262 263static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg, 264 const u8 *data, u16 len) 265{ 266 struct tda10048_config *config = &state->config; 267 int ret = -EREMOTEIO; 268 struct i2c_msg msg; 269 u8 *buf; 270 271 dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len); 272 273 buf = kmalloc(len + 1, GFP_KERNEL); 274 if (buf == NULL) { 275 ret = -ENOMEM; 276 goto error; 277 } 278 279 *buf = reg; 280 memcpy(buf + 1, data, len); 281 282 msg.addr = config->demod_address; 283 msg.flags = 0; 284 msg.buf = buf; 285 msg.len = len + 1; 286 287 dprintk(2, "%s(): write len = %d\n", 288 __func__, msg.len); 289 290 ret = i2c_transfer(state->i2c, &msg, 1); 291 if (ret != 1) { 292 printk(KERN_ERR "%s(): writereg error err %i\n", 293 __func__, ret); 294 ret = -EREMOTEIO; 295 } 296 297error: 298 kfree(buf); 299 300 return ret; 301} 302 303static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz, 304 u32 if_hz) 305{ 306 struct tda10048_state *state = fe->demodulator_priv; 307 u64 t; 308 309 dprintk(1, "%s()\n", __func__); 310 311 if (sample_freq_hz == 0) 312 return -EINVAL; 313 314 if (if_hz < (sample_freq_hz / 2)) { 315 /* PHY2 = (if2/fs) * 2^15 */ 316 t = if_hz; 317 t *= 10; 318 t *= 32768; 319 do_div(t, sample_freq_hz); 320 t += 5; 321 do_div(t, 10); 322 } else { 323 /* PHY2 = ((IF1-fs)/fs) * 2^15 */ 324 t = sample_freq_hz - if_hz; 325 t *= 10; 326 t *= 32768; 327 do_div(t, sample_freq_hz); 328 t += 5; 329 do_div(t, 10); 330 t = ~t + 1; 331 } 332 333 tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t); 334 tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8)); 335 336 return 0; 337} 338 339static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz, 340 u32 bw) 341{ 342 struct tda10048_state *state = fe->demodulator_priv; 343 u64 t, z; 344 345 dprintk(1, "%s()\n", __func__); 346 347 if (sample_freq_hz == 0) 348 return -EINVAL; 349 350 /* WREF = (B / (7 * fs)) * 2^31 */ 351 t = bw * 10; 352 /* avoid warning: this decimal constant is unsigned only in ISO C90 */ 353 /* t *= 2147483648 on 32bit platforms */ 354 t *= (2048 * 1024); 355 t *= 1024; 356 z = 7 * sample_freq_hz; 357 do_div(t, z); 358 t += 5; 359 do_div(t, 10); 360 361 tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t); 362 tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8)); 363 tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16)); 364 tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24)); 365 366 return 0; 367} 368 369static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz, 370 u32 bw) 371{ 372 struct tda10048_state *state = fe->demodulator_priv; 373 u64 t; 374 375 dprintk(1, "%s()\n", __func__); 376 377 if (sample_freq_hz == 0) 378 return -EINVAL; 379 380 /* INVWREF = ((7 * fs) / B) * 2^5 */ 381 t = sample_freq_hz; 382 t *= 7; 383 t *= 32; 384 t *= 10; 385 do_div(t, bw); 386 t += 5; 387 do_div(t, 10); 388 389 tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t); 390 tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8)); 391 392 return 0; 393} 394 395static int tda10048_set_bandwidth(struct dvb_frontend *fe, 396 u32 bw) 397{ 398 struct tda10048_state *state = fe->demodulator_priv; 399 dprintk(1, "%s(bw=%d)\n", __func__, bw); 400 401 /* Bandwidth setting may need to be adjusted */ 402 switch (bw) { 403 case 6000000: 404 case 7000000: 405 case 8000000: 406 tda10048_set_wref(fe, state->sample_freq, bw); 407 tda10048_set_invwref(fe, state->sample_freq, bw); 408 break; 409 default: 410 printk(KERN_ERR "%s() invalid bandwidth\n", __func__); 411 return -EINVAL; 412 } 413 414 state->bandwidth = bw; 415 416 return 0; 417} 418 419static int tda10048_set_if(struct dvb_frontend *fe, u32 bw) 420{ 421 struct tda10048_state *state = fe->demodulator_priv; 422 struct tda10048_config *config = &state->config; 423 int i; 424 u32 if_freq_khz; 425 426 dprintk(1, "%s(bw = %d)\n", __func__, bw); 427 428 /* based on target bandwidth and clk we calculate pll factors */ 429 switch (bw) { 430 case 6000000: 431 if_freq_khz = config->dtv6_if_freq_khz; 432 break; 433 case 7000000: 434 if_freq_khz = config->dtv7_if_freq_khz; 435 break; 436 case 8000000: 437 if_freq_khz = config->dtv8_if_freq_khz; 438 break; 439 default: 440 printk(KERN_ERR "%s() no default\n", __func__); 441 return -EINVAL; 442 } 443 444 for (i = 0; i < ARRAY_SIZE(pll_tab); i++) { 445 if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) && 446 (pll_tab[i].if_freq_khz == if_freq_khz)) { 447 448 state->freq_if_hz = pll_tab[i].if_freq_khz * 1000; 449 state->xtal_hz = pll_tab[i].clk_freq_khz * 1000; 450 break; 451 } 452 } 453 if (i == ARRAY_SIZE(pll_tab)) { 454 printk(KERN_ERR "%s() Incorrect attach settings\n", 455 __func__); 456 return -EINVAL; 457 } 458 459 dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz); 460 dprintk(1, "- xtal_hz = %d\n", state->xtal_hz); 461 dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor); 462 dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor); 463 dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor); 464 465 /* Calculate the sample frequency */ 466 state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45); 467 state->sample_freq /= (state->pll_nfactor + 1); 468 state->sample_freq /= (state->pll_pfactor + 4); 469 dprintk(1, "- sample_freq = %d\n", state->sample_freq); 470 471 /* Update the I/F */ 472 tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz); 473 474 return 0; 475} 476 477static int tda10048_firmware_upload(struct dvb_frontend *fe) 478{ 479 struct tda10048_state *state = fe->demodulator_priv; 480 struct tda10048_config *config = &state->config; 481 const struct firmware *fw; 482 int ret; 483 int pos = 0; 484 int cnt; 485 u8 wlen = config->fwbulkwritelen; 486 487 if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50)) 488 wlen = TDA10048_BULKWRITE_200; 489 490 /* request the firmware, this will block and timeout */ 491 printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n", 492 __func__, 493 TDA10048_DEFAULT_FIRMWARE); 494 495 ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE, 496 state->i2c->dev.parent); 497 if (ret) { 498 printk(KERN_ERR "%s: Upload failed. (file not found?)\n", 499 __func__); 500 return -EIO; 501 } else { 502 printk(KERN_INFO "%s: firmware read %Zu bytes.\n", 503 __func__, 504 fw->size); 505 ret = 0; 506 } 507 508 if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) { 509 printk(KERN_ERR "%s: firmware incorrect size\n", __func__); 510 ret = -EIO; 511 } else { 512 printk(KERN_INFO "%s: firmware uploading\n", __func__); 513 514 /* Soft reset */ 515 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 516 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 517 & 0xfe); 518 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 519 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 520 | 0x01); 521 522 /* Put the demod into host download mode */ 523 tda10048_writereg(state, TDA10048_CONF_C4_1, 524 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9); 525 526 /* Boot the DSP */ 527 tda10048_writereg(state, TDA10048_CONF_C4_1, 528 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08); 529 530 /* Prepare for download */ 531 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0); 532 533 /* Download the firmware payload */ 534 while (pos < fw->size) { 535 536 if ((fw->size - pos) > wlen) 537 cnt = wlen; 538 else 539 cnt = fw->size - pos; 540 541 tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN, 542 &fw->data[pos], cnt); 543 544 pos += cnt; 545 } 546 547 ret = -EIO; 548 /* Wait up to 250ms for the DSP to boot */ 549 for (cnt = 0; cnt < 250 ; cnt += 10) { 550 551 msleep(10); 552 553 if (tda10048_readreg(state, TDA10048_SYNC_STATUS) 554 & 0x40) { 555 ret = 0; 556 break; 557 } 558 } 559 } 560 561 release_firmware(fw); 562 563 if (ret == 0) { 564 printk(KERN_INFO "%s: firmware uploaded\n", __func__); 565 state->fwloaded = 1; 566 } else 567 printk(KERN_ERR "%s: firmware upload failed\n", __func__); 568 569 return ret; 570} 571 572static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion) 573{ 574 struct tda10048_state *state = fe->demodulator_priv; 575 576 dprintk(1, "%s(%d)\n", __func__, inversion); 577 578 if (inversion == TDA10048_INVERSION_ON) 579 tda10048_writereg(state, TDA10048_CONF_C1_1, 580 tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20); 581 else 582 tda10048_writereg(state, TDA10048_CONF_C1_1, 583 tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf); 584 585 return 0; 586} 587 588/* Retrieve the demod settings */ 589static int tda10048_get_tps(struct tda10048_state *state, 590 struct dtv_frontend_properties *p) 591{ 592 u8 val; 593 594 /* Make sure the TPS regs are valid */ 595 if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01)) 596 return -EAGAIN; 597 598 val = tda10048_readreg(state, TDA10048_OUT_CONF2); 599 switch ((val & 0x60) >> 5) { 600 case 0: 601 p->modulation = QPSK; 602 break; 603 case 1: 604 p->modulation = QAM_16; 605 break; 606 case 2: 607 p->modulation = QAM_64; 608 break; 609 } 610 switch ((val & 0x18) >> 3) { 611 case 0: 612 p->hierarchy = HIERARCHY_NONE; 613 break; 614 case 1: 615 p->hierarchy = HIERARCHY_1; 616 break; 617 case 2: 618 p->hierarchy = HIERARCHY_2; 619 break; 620 case 3: 621 p->hierarchy = HIERARCHY_4; 622 break; 623 } 624 switch (val & 0x07) { 625 case 0: 626 p->code_rate_HP = FEC_1_2; 627 break; 628 case 1: 629 p->code_rate_HP = FEC_2_3; 630 break; 631 case 2: 632 p->code_rate_HP = FEC_3_4; 633 break; 634 case 3: 635 p->code_rate_HP = FEC_5_6; 636 break; 637 case 4: 638 p->code_rate_HP = FEC_7_8; 639 break; 640 } 641 642 val = tda10048_readreg(state, TDA10048_OUT_CONF3); 643 switch (val & 0x07) { 644 case 0: 645 p->code_rate_LP = FEC_1_2; 646 break; 647 case 1: 648 p->code_rate_LP = FEC_2_3; 649 break; 650 case 2: 651 p->code_rate_LP = FEC_3_4; 652 break; 653 case 3: 654 p->code_rate_LP = FEC_5_6; 655 break; 656 case 4: 657 p->code_rate_LP = FEC_7_8; 658 break; 659 } 660 661 val = tda10048_readreg(state, TDA10048_OUT_CONF1); 662 switch ((val & 0x0c) >> 2) { 663 case 0: 664 p->guard_interval = GUARD_INTERVAL_1_32; 665 break; 666 case 1: 667 p->guard_interval = GUARD_INTERVAL_1_16; 668 break; 669 case 2: 670 p->guard_interval = GUARD_INTERVAL_1_8; 671 break; 672 case 3: 673 p->guard_interval = GUARD_INTERVAL_1_4; 674 break; 675 } 676 switch (val & 0x03) { 677 case 0: 678 p->transmission_mode = TRANSMISSION_MODE_2K; 679 break; 680 case 1: 681 p->transmission_mode = TRANSMISSION_MODE_8K; 682 break; 683 } 684 685 return 0; 686} 687 688static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 689{ 690 struct tda10048_state *state = fe->demodulator_priv; 691 struct tda10048_config *config = &state->config; 692 dprintk(1, "%s(%d)\n", __func__, enable); 693 694 if (config->disable_gate_access) 695 return 0; 696 697 if (enable) 698 return tda10048_writereg(state, TDA10048_CONF_C4_1, 699 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02); 700 else 701 return tda10048_writereg(state, TDA10048_CONF_C4_1, 702 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd); 703} 704 705static int tda10048_output_mode(struct dvb_frontend *fe, int serial) 706{ 707 struct tda10048_state *state = fe->demodulator_priv; 708 dprintk(1, "%s(%d)\n", __func__, serial); 709 710 /* Ensure pins are out of tri-state */ 711 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21); 712 tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00); 713 714 if (serial) { 715 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20); 716 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0); 717 } else { 718 tda10048_writereg(state, TDA10048_IC_MODE, 0x00); 719 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01); 720 } 721 722 return 0; 723} 724 725/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 726/* TODO: Support manual tuning with specific params */ 727static int tda10048_set_frontend(struct dvb_frontend *fe) 728{ 729 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 730 struct tda10048_state *state = fe->demodulator_priv; 731 732 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency); 733 734 /* Update the I/F pll's if the bandwidth changes */ 735 if (p->bandwidth_hz != state->bandwidth) { 736 tda10048_set_if(fe, p->bandwidth_hz); 737 tda10048_set_bandwidth(fe, p->bandwidth_hz); 738 } 739 740 if (fe->ops.tuner_ops.set_params) { 741 742 if (fe->ops.i2c_gate_ctrl) 743 fe->ops.i2c_gate_ctrl(fe, 1); 744 745 fe->ops.tuner_ops.set_params(fe); 746 747 if (fe->ops.i2c_gate_ctrl) 748 fe->ops.i2c_gate_ctrl(fe, 0); 749 } 750 751 /* Enable demod TPS auto detection and begin acquisition */ 752 tda10048_writereg(state, TDA10048_AUTO, 0x57); 753 /* trigger cber and vber acquisition */ 754 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B); 755 756 return 0; 757} 758 759/* Establish sane defaults and load firmware. */ 760static int tda10048_init(struct dvb_frontend *fe) 761{ 762 struct tda10048_state *state = fe->demodulator_priv; 763 struct tda10048_config *config = &state->config; 764 int ret = 0, i; 765 766 dprintk(1, "%s()\n", __func__); 767 768 /* PLL */ 769 init_tab[4].data = (u8)(state->pll_mfactor); 770 init_tab[5].data = (u8)(state->pll_nfactor) | 0x40; 771 772 /* Apply register defaults */ 773 for (i = 0; i < ARRAY_SIZE(init_tab); i++) 774 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data); 775 776 if (state->fwloaded == 0) 777 ret = tda10048_firmware_upload(fe); 778 779 /* Set either serial or parallel */ 780 tda10048_output_mode(fe, config->output_mode); 781 782 /* Set inversion */ 783 tda10048_set_inversion(fe, config->inversion); 784 785 /* Establish default RF values */ 786 tda10048_set_if(fe, 8000000); 787 tda10048_set_bandwidth(fe, 8000000); 788 789 /* Ensure we leave the gate closed */ 790 tda10048_i2c_gate_ctrl(fe, 0); 791 792 return ret; 793} 794 795static int tda10048_read_status(struct dvb_frontend *fe, fe_status_t *status) 796{ 797 struct tda10048_state *state = fe->demodulator_priv; 798 u8 reg; 799 800 *status = 0; 801 802 reg = tda10048_readreg(state, TDA10048_SYNC_STATUS); 803 804 dprintk(1, "%s() status =0x%02x\n", __func__, reg); 805 806 if (reg & 0x02) 807 *status |= FE_HAS_CARRIER; 808 809 if (reg & 0x04) 810 *status |= FE_HAS_SIGNAL; 811 812 if (reg & 0x08) { 813 *status |= FE_HAS_LOCK; 814 *status |= FE_HAS_VITERBI; 815 *status |= FE_HAS_SYNC; 816 } 817 818 return 0; 819} 820 821static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber) 822{ 823 struct tda10048_state *state = fe->demodulator_priv; 824 static u32 cber_current; 825 u32 cber_nmax; 826 u64 cber_tmp; 827 828 dprintk(1, "%s()\n", __func__); 829 830 /* update cber on interrupt */ 831 if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) { 832 cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 | 833 tda10048_readreg(state, TDA10048_CBER_LSB); 834 cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 | 835 tda10048_readreg(state, TDA10048_CBER_NMAX_LSB); 836 cber_tmp *= 100000000; 837 cber_tmp *= 2; 838 cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1); 839 cber_current = (u32)cber_tmp; 840 /* retrigger cber acquisition */ 841 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39); 842 } 843 /* actual cber is (*ber)/1e8 */ 844 *ber = cber_current; 845 846 return 0; 847} 848 849static int tda10048_read_signal_strength(struct dvb_frontend *fe, 850 u16 *signal_strength) 851{ 852 struct tda10048_state *state = fe->demodulator_priv; 853 u8 v; 854 855 dprintk(1, "%s()\n", __func__); 856 857 *signal_strength = 65535; 858 859 v = tda10048_readreg(state, TDA10048_NP_OUT); 860 if (v > 0) 861 *signal_strength -= (v << 8) | v; 862 863 return 0; 864} 865 866/* SNR lookup table */ 867static struct snr_tab { 868 u8 val; 869 u8 data; 870} snr_tab[] = { 871 { 0, 0 }, 872 { 1, 246 }, 873 { 2, 215 }, 874 { 3, 198 }, 875 { 4, 185 }, 876 { 5, 176 }, 877 { 6, 168 }, 878 { 7, 161 }, 879 { 8, 155 }, 880 { 9, 150 }, 881 { 10, 146 }, 882 { 11, 141 }, 883 { 12, 138 }, 884 { 13, 134 }, 885 { 14, 131 }, 886 { 15, 128 }, 887 { 16, 125 }, 888 { 17, 122 }, 889 { 18, 120 }, 890 { 19, 118 }, 891 { 20, 115 }, 892 { 21, 113 }, 893 { 22, 111 }, 894 { 23, 109 }, 895 { 24, 107 }, 896 { 25, 106 }, 897 { 26, 104 }, 898 { 27, 102 }, 899 { 28, 101 }, 900 { 29, 99 }, 901 { 30, 98 }, 902 { 31, 96 }, 903 { 32, 95 }, 904 { 33, 94 }, 905 { 34, 92 }, 906 { 35, 91 }, 907 { 36, 90 }, 908 { 37, 89 }, 909 { 38, 88 }, 910 { 39, 86 }, 911 { 40, 85 }, 912 { 41, 84 }, 913 { 42, 83 }, 914 { 43, 82 }, 915 { 44, 81 }, 916 { 45, 80 }, 917 { 46, 79 }, 918 { 47, 78 }, 919 { 48, 77 }, 920 { 49, 76 }, 921 { 50, 76 }, 922 { 51, 75 }, 923 { 52, 74 }, 924 { 53, 73 }, 925 { 54, 72 }, 926 { 56, 71 }, 927 { 57, 70 }, 928 { 58, 69 }, 929 { 60, 68 }, 930 { 61, 67 }, 931 { 63, 66 }, 932 { 64, 65 }, 933 { 66, 64 }, 934 { 67, 63 }, 935 { 68, 62 }, 936 { 69, 62 }, 937 { 70, 61 }, 938 { 72, 60 }, 939 { 74, 59 }, 940 { 75, 58 }, 941 { 77, 57 }, 942 { 79, 56 }, 943 { 81, 55 }, 944 { 83, 54 }, 945 { 85, 53 }, 946 { 87, 52 }, 947 { 89, 51 }, 948 { 91, 50 }, 949 { 93, 49 }, 950 { 95, 48 }, 951 { 97, 47 }, 952 { 100, 46 }, 953 { 102, 45 }, 954 { 104, 44 }, 955 { 107, 43 }, 956 { 109, 42 }, 957 { 112, 41 }, 958 { 114, 40 }, 959 { 117, 39 }, 960 { 120, 38 }, 961 { 123, 37 }, 962 { 125, 36 }, 963 { 128, 35 }, 964 { 131, 34 }, 965 { 134, 33 }, 966 { 138, 32 }, 967 { 141, 31 }, 968 { 144, 30 }, 969 { 147, 29 }, 970 { 151, 28 }, 971 { 154, 27 }, 972 { 158, 26 }, 973 { 162, 25 }, 974 { 165, 24 }, 975 { 169, 23 }, 976 { 173, 22 }, 977 { 177, 21 }, 978 { 181, 20 }, 979 { 186, 19 }, 980 { 190, 18 }, 981 { 194, 17 }, 982 { 199, 16 }, 983 { 204, 15 }, 984 { 208, 14 }, 985 { 213, 13 }, 986 { 218, 12 }, 987 { 223, 11 }, 988 { 229, 10 }, 989 { 234, 9 }, 990 { 239, 8 }, 991 { 245, 7 }, 992 { 251, 6 }, 993 { 255, 5 }, 994}; 995 996static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr) 997{ 998 struct tda10048_state *state = fe->demodulator_priv; 999 u8 v; 1000 int i, ret = -EINVAL; 1001 1002 dprintk(1, "%s()\n", __func__); 1003 1004 v = tda10048_readreg(state, TDA10048_NP_OUT); 1005 for (i = 0; i < ARRAY_SIZE(snr_tab); i++) { 1006 if (v <= snr_tab[i].val) { 1007 *snr = snr_tab[i].data; 1008 ret = 0; 1009 break; 1010 } 1011 } 1012 1013 return ret; 1014} 1015 1016static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1017{ 1018 struct tda10048_state *state = fe->demodulator_priv; 1019 1020 dprintk(1, "%s()\n", __func__); 1021 1022 *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 | 1023 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB); 1024 /* clear the uncorrected TS packets counter when saturated */ 1025 if (*ucblocks == 0xFFFF) 1026 tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80); 1027 1028 return 0; 1029} 1030 1031static int tda10048_get_frontend(struct dvb_frontend *fe) 1032{ 1033 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1034 struct tda10048_state *state = fe->demodulator_priv; 1035 1036 dprintk(1, "%s()\n", __func__); 1037 1038 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1) 1039 & 0x20 ? INVERSION_ON : INVERSION_OFF; 1040 1041 return tda10048_get_tps(state, p); 1042} 1043 1044static int tda10048_get_tune_settings(struct dvb_frontend *fe, 1045 struct dvb_frontend_tune_settings *tune) 1046{ 1047 tune->min_delay_ms = 1000; 1048 return 0; 1049} 1050 1051static void tda10048_release(struct dvb_frontend *fe) 1052{ 1053 struct tda10048_state *state = fe->demodulator_priv; 1054 dprintk(1, "%s()\n", __func__); 1055 kfree(state); 1056} 1057 1058static void tda10048_establish_defaults(struct dvb_frontend *fe) 1059{ 1060 struct tda10048_state *state = fe->demodulator_priv; 1061 struct tda10048_config *config = &state->config; 1062 1063 /* Validate/default the config */ 1064 if (config->dtv6_if_freq_khz == 0) { 1065 config->dtv6_if_freq_khz = TDA10048_IF_4300; 1066 printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz " 1067 "is not set (defaulting to %d)\n", 1068 __func__, 1069 config->dtv6_if_freq_khz); 1070 } 1071 1072 if (config->dtv7_if_freq_khz == 0) { 1073 config->dtv7_if_freq_khz = TDA10048_IF_4300; 1074 printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz " 1075 "is not set (defaulting to %d)\n", 1076 __func__, 1077 config->dtv7_if_freq_khz); 1078 } 1079 1080 if (config->dtv8_if_freq_khz == 0) { 1081 config->dtv8_if_freq_khz = TDA10048_IF_4300; 1082 printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz " 1083 "is not set (defaulting to %d)\n", 1084 __func__, 1085 config->dtv8_if_freq_khz); 1086 } 1087 1088 if (config->clk_freq_khz == 0) { 1089 config->clk_freq_khz = TDA10048_CLK_16000; 1090 printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz " 1091 "is not set (defaulting to %d)\n", 1092 __func__, 1093 config->clk_freq_khz); 1094 } 1095} 1096 1097static struct dvb_frontend_ops tda10048_ops; 1098 1099struct dvb_frontend *tda10048_attach(const struct tda10048_config *config, 1100 struct i2c_adapter *i2c) 1101{ 1102 struct tda10048_state *state = NULL; 1103 1104 dprintk(1, "%s()\n", __func__); 1105 1106 /* allocate memory for the internal state */ 1107 state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL); 1108 if (state == NULL) 1109 goto error; 1110 1111 /* setup the state and clone the config */ 1112 memcpy(&state->config, config, sizeof(*config)); 1113 state->i2c = i2c; 1114 state->fwloaded = config->no_firmware; 1115 state->bandwidth = 8000000; 1116 1117 /* check if the demod is present */ 1118 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048) 1119 goto error; 1120 1121 /* create dvb_frontend */ 1122 memcpy(&state->frontend.ops, &tda10048_ops, 1123 sizeof(struct dvb_frontend_ops)); 1124 state->frontend.demodulator_priv = state; 1125 1126 /* set pll */ 1127 if (config->set_pll) { 1128 state->pll_mfactor = config->pll_m; 1129 state->pll_nfactor = config->pll_n; 1130 state->pll_pfactor = config->pll_p; 1131 } else { 1132 state->pll_mfactor = 10; 1133 state->pll_nfactor = 3; 1134 state->pll_pfactor = 0; 1135 } 1136 1137 /* Establish any defaults the the user didn't pass */ 1138 tda10048_establish_defaults(&state->frontend); 1139 1140 /* Set the xtal and freq defaults */ 1141 if (tda10048_set_if(&state->frontend, 8000000) != 0) 1142 goto error; 1143 1144 /* Default bandwidth */ 1145 if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0) 1146 goto error; 1147 1148 /* Leave the gate closed */ 1149 tda10048_i2c_gate_ctrl(&state->frontend, 0); 1150 1151 return &state->frontend; 1152 1153error: 1154 kfree(state); 1155 return NULL; 1156} 1157EXPORT_SYMBOL(tda10048_attach); 1158 1159static struct dvb_frontend_ops tda10048_ops = { 1160 .delsys = { SYS_DVBT }, 1161 .info = { 1162 .name = "NXP TDA10048HN DVB-T", 1163 .frequency_min = 177000000, 1164 .frequency_max = 858000000, 1165 .frequency_stepsize = 166666, 1166 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1167 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1168 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1169 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | 1170 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER 1171 }, 1172 1173 .release = tda10048_release, 1174 .init = tda10048_init, 1175 .i2c_gate_ctrl = tda10048_i2c_gate_ctrl, 1176 .set_frontend = tda10048_set_frontend, 1177 .get_frontend = tda10048_get_frontend, 1178 .get_tune_settings = tda10048_get_tune_settings, 1179 .read_status = tda10048_read_status, 1180 .read_ber = tda10048_read_ber, 1181 .read_signal_strength = tda10048_read_signal_strength, 1182 .read_snr = tda10048_read_snr, 1183 .read_ucblocks = tda10048_read_ucblocks, 1184}; 1185 1186module_param(debug, int, 0644); 1187MODULE_PARM_DESC(debug, "Enable verbose debug messages"); 1188 1189MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver"); 1190MODULE_AUTHOR("Steven Toth"); 1191MODULE_LICENSE("GPL"); 1192