1/* 2 * Samsung S5P Multi Format Codec v 5.0 3 * 4 * This file contains definitions of enums and structs used by the codec 5 * driver. 6 * 7 * Copyright (C) 2011 Samsung Electronics Co., Ltd. 8 * Kamil Debski, <k.debski@samsung.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version 14 */ 15 16#ifndef S5P_MFC_COMMON_H_ 17#define S5P_MFC_COMMON_H_ 18 19#include <linux/platform_device.h> 20#include <linux/videodev2.h> 21#include <media/v4l2-ctrls.h> 22#include <media/v4l2-device.h> 23#include <media/v4l2-ioctl.h> 24#include <media/videobuf2-core.h> 25#include "regs-mfc.h" 26#include "regs-mfc-v8.h" 27 28/* Definitions related to MFC memory */ 29 30/* Offset base used to differentiate between CAPTURE and OUTPUT 31* while mmaping */ 32#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2) 33 34#define MFC_BANK1_ALLOC_CTX 0 35#define MFC_BANK2_ALLOC_CTX 1 36 37#define MFC_BANK1_ALIGN_ORDER 13 38#define MFC_BANK2_ALIGN_ORDER 13 39#define MFC_BASE_ALIGN_ORDER 17 40 41#define MFC_FW_MAX_VERSIONS 2 42 43#include <media/videobuf2-dma-contig.h> 44 45static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b) 46{ 47 /* Same functionality as the vb2_dma_contig_plane_paddr */ 48 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b); 49 50 return *paddr; 51} 52 53/* MFC definitions */ 54#define MFC_MAX_EXTRA_DPB 5 55#define MFC_MAX_BUFFERS 32 56#define MFC_NUM_CONTEXTS 4 57/* Interrupt timeout */ 58#define MFC_INT_TIMEOUT 2000 59/* Busy wait timeout */ 60#define MFC_BW_TIMEOUT 500 61/* Watchdog interval */ 62#define MFC_WATCHDOG_INTERVAL 1000 63/* After how many executions watchdog should assume lock up */ 64#define MFC_WATCHDOG_CNT 10 65#define MFC_NO_INSTANCE_SET -1 66#define MFC_ENC_CAP_PLANE_COUNT 1 67#define MFC_ENC_OUT_PLANE_COUNT 2 68#define STUFF_BYTE 4 69#define MFC_MAX_CTRLS 77 70 71#define S5P_MFC_CODEC_NONE -1 72#define S5P_MFC_CODEC_H264_DEC 0 73#define S5P_MFC_CODEC_H264_MVC_DEC 1 74#define S5P_MFC_CODEC_VC1_DEC 2 75#define S5P_MFC_CODEC_MPEG4_DEC 3 76#define S5P_MFC_CODEC_MPEG2_DEC 4 77#define S5P_MFC_CODEC_H263_DEC 5 78#define S5P_MFC_CODEC_VC1RCV_DEC 6 79#define S5P_MFC_CODEC_VP8_DEC 7 80 81#define S5P_MFC_CODEC_H264_ENC 20 82#define S5P_MFC_CODEC_H264_MVC_ENC 21 83#define S5P_MFC_CODEC_MPEG4_ENC 22 84#define S5P_MFC_CODEC_H263_ENC 23 85#define S5P_MFC_CODEC_VP8_ENC 24 86 87#define S5P_MFC_R2H_CMD_EMPTY 0 88#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1 89#define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2 90#define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3 91#define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4 92#define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6 93#define S5P_MFC_R2H_CMD_SLEEP_RET 7 94#define S5P_MFC_R2H_CMD_WAKEUP_RET 8 95#define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9 96#define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10 97#define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11 98#define S5P_MFC_R2H_CMD_FW_STATUS_RET 12 99#define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13 100#define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14 101#define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15 102#define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16 103#define S5P_MFC_R2H_CMD_ERR_RET 32 104 105#define mfc_read(dev, offset) readl(dev->regs_base + (offset)) 106#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \ 107 (offset)) 108 109/** 110 * enum s5p_mfc_fmt_type - type of the pixelformat 111 */ 112enum s5p_mfc_fmt_type { 113 MFC_FMT_DEC, 114 MFC_FMT_ENC, 115 MFC_FMT_RAW, 116}; 117 118/** 119 * enum s5p_mfc_inst_type - The type of an MFC instance. 120 */ 121enum s5p_mfc_inst_type { 122 MFCINST_INVALID, 123 MFCINST_DECODER, 124 MFCINST_ENCODER, 125}; 126 127/** 128 * enum s5p_mfc_inst_state - The state of an MFC instance. 129 */ 130enum s5p_mfc_inst_state { 131 MFCINST_FREE = 0, 132 MFCINST_INIT = 100, 133 MFCINST_GOT_INST, 134 MFCINST_HEAD_PARSED, 135 MFCINST_HEAD_PRODUCED, 136 MFCINST_BUFS_SET, 137 MFCINST_RUNNING, 138 MFCINST_FINISHING, 139 MFCINST_FINISHED, 140 MFCINST_RETURN_INST, 141 MFCINST_ERROR, 142 MFCINST_ABORT, 143 MFCINST_FLUSH, 144 MFCINST_RES_CHANGE_INIT, 145 MFCINST_RES_CHANGE_FLUSH, 146 MFCINST_RES_CHANGE_END, 147}; 148 149/** 150 * enum s5p_mfc_queue_state - The state of buffer queue. 151 */ 152enum s5p_mfc_queue_state { 153 QUEUE_FREE, 154 QUEUE_BUFS_REQUESTED, 155 QUEUE_BUFS_QUERIED, 156 QUEUE_BUFS_MMAPED, 157}; 158 159/** 160 * enum s5p_mfc_decode_arg - type of frame decoding 161 */ 162enum s5p_mfc_decode_arg { 163 MFC_DEC_FRAME, 164 MFC_DEC_LAST_FRAME, 165 MFC_DEC_RES_CHANGE, 166}; 167 168enum s5p_mfc_fw_ver { 169 MFC_FW_V1, 170 MFC_FW_V2, 171}; 172 173#define MFC_BUF_FLAG_USED (1 << 0) 174#define MFC_BUF_FLAG_EOS (1 << 1) 175 176struct s5p_mfc_ctx; 177 178/** 179 * struct s5p_mfc_buf - MFC buffer 180 */ 181struct s5p_mfc_buf { 182 struct list_head list; 183 struct vb2_buffer *b; 184 union { 185 struct { 186 size_t luma; 187 size_t chroma; 188 } raw; 189 size_t stream; 190 } cookie; 191 int flags; 192}; 193 194/** 195 * struct s5p_mfc_pm - power management data structure 196 */ 197struct s5p_mfc_pm { 198 struct clk *clock; 199 struct clk *clock_gate; 200 atomic_t power; 201 struct device *device; 202}; 203 204struct s5p_mfc_buf_size_v5 { 205 unsigned int h264_ctx; 206 unsigned int non_h264_ctx; 207 unsigned int dsc; 208 unsigned int shm; 209}; 210 211struct s5p_mfc_buf_size_v6 { 212 unsigned int dev_ctx; 213 unsigned int h264_dec_ctx; 214 unsigned int other_dec_ctx; 215 unsigned int h264_enc_ctx; 216 unsigned int other_enc_ctx; 217}; 218 219struct s5p_mfc_buf_size { 220 unsigned int fw; 221 unsigned int cpb; 222 void *priv; 223}; 224 225struct s5p_mfc_buf_align { 226 unsigned int base; 227}; 228 229struct s5p_mfc_variant { 230 unsigned int version; 231 unsigned int port_num; 232 u32 version_bit; 233 struct s5p_mfc_buf_size *buf_size; 234 struct s5p_mfc_buf_align *buf_align; 235 char *fw_name[MFC_FW_MAX_VERSIONS]; 236}; 237 238/** 239 * struct s5p_mfc_priv_buf - represents internal used buffer 240 * @alloc: allocation-specific context for each buffer 241 * (videobuf2 allocator) 242 * @ofs: offset of each buffer, will be used for MFC 243 * @virt: kernel virtual address, only valid when the 244 * buffer accessed by driver 245 * @dma: DMA address, only valid when kernel DMA API used 246 * @size: size of the buffer 247 */ 248struct s5p_mfc_priv_buf { 249 void *alloc; 250 unsigned long ofs; 251 void *virt; 252 dma_addr_t dma; 253 size_t size; 254}; 255 256/** 257 * struct s5p_mfc_dev - The struct containing driver internal parameters. 258 * 259 * @v4l2_dev: v4l2_device 260 * @vfd_dec: video device for decoding 261 * @vfd_enc: video device for encoding 262 * @plat_dev: platform device 263 * @mem_dev_l: child device of the left memory bank (0) 264 * @mem_dev_r: child device of the right memory bank (1) 265 * @regs_base: base address of the MFC hw registers 266 * @irq: irq resource 267 * @dec_ctrl_handler: control framework handler for decoding 268 * @enc_ctrl_handler: control framework handler for encoding 269 * @pm: power management control 270 * @variant: MFC hardware variant information 271 * @num_inst: couter of active MFC instances 272 * @irqlock: lock for operations on videobuf2 queues 273 * @condlock: lock for changing/checking if a context is ready to be 274 * processed 275 * @mfc_mutex: lock for video_device 276 * @int_cond: variable used by the waitqueue 277 * @int_type: type of last interrupt 278 * @int_err: error number for last interrupt 279 * @queue: waitqueue for waiting for completion of device commands 280 * @fw_size: size of firmware 281 * @fw_virt_addr: virtual firmware address 282 * @bank1: address of the beginning of bank 1 memory 283 * @bank2: address of the beginning of bank 2 memory 284 * @hw_lock: used for hardware locking 285 * @ctx: array of driver contexts 286 * @curr_ctx: number of the currently running context 287 * @ctx_work_bits: used to mark which contexts are waiting for hardware 288 * @watchdog_cnt: counter for the watchdog 289 * @watchdog_workqueue: workqueue for the watchdog 290 * @watchdog_work: worker for the watchdog 291 * @alloc_ctx: videobuf2 allocator contexts for two memory banks 292 * @enter_suspend: flag set when entering suspend 293 * @ctx_buf: common context memory (MFCv6) 294 * @warn_start: hardware error code from which warnings start 295 * @mfc_ops: ops structure holding HW operation function pointers 296 * @mfc_cmds: cmd structure holding HW commands function pointers 297 * @fw_ver: loaded firmware sub-version 298 * 299 */ 300struct s5p_mfc_dev { 301 struct v4l2_device v4l2_dev; 302 struct video_device *vfd_dec; 303 struct video_device *vfd_enc; 304 struct platform_device *plat_dev; 305 struct device *mem_dev_l; 306 struct device *mem_dev_r; 307 void __iomem *regs_base; 308 int irq; 309 struct v4l2_ctrl_handler dec_ctrl_handler; 310 struct v4l2_ctrl_handler enc_ctrl_handler; 311 struct s5p_mfc_pm pm; 312 struct s5p_mfc_variant *variant; 313 int num_inst; 314 spinlock_t irqlock; /* lock when operating on videobuf2 queues */ 315 spinlock_t condlock; /* lock when changing/checking if a context is 316 ready to be processed */ 317 struct mutex mfc_mutex; /* video_device lock */ 318 int int_cond; 319 int int_type; 320 unsigned int int_err; 321 wait_queue_head_t queue; 322 size_t fw_size; 323 void *fw_virt_addr; 324 dma_addr_t bank1; 325 dma_addr_t bank2; 326 unsigned long hw_lock; 327 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS]; 328 int curr_ctx; 329 unsigned long ctx_work_bits; 330 atomic_t watchdog_cnt; 331 struct timer_list watchdog_timer; 332 struct workqueue_struct *watchdog_workqueue; 333 struct work_struct watchdog_work; 334 void *alloc_ctx[2]; 335 unsigned long enter_suspend; 336 337 struct s5p_mfc_priv_buf ctx_buf; 338 int warn_start; 339 struct s5p_mfc_hw_ops *mfc_ops; 340 struct s5p_mfc_hw_cmds *mfc_cmds; 341 const struct s5p_mfc_regs *mfc_regs; 342 enum s5p_mfc_fw_ver fw_ver; 343}; 344 345/** 346 * struct s5p_mfc_h264_enc_params - encoding parameters for h264 347 */ 348struct s5p_mfc_h264_enc_params { 349 enum v4l2_mpeg_video_h264_profile profile; 350 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode; 351 s8 loop_filter_alpha; 352 s8 loop_filter_beta; 353 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode; 354 u8 max_ref_pic; 355 u8 num_ref_pic_4p; 356 int _8x8_transform; 357 int rc_mb_dark; 358 int rc_mb_smooth; 359 int rc_mb_static; 360 int rc_mb_activity; 361 int vui_sar; 362 u8 vui_sar_idc; 363 u16 vui_ext_sar_width; 364 u16 vui_ext_sar_height; 365 int open_gop; 366 u16 open_gop_size; 367 u8 rc_frame_qp; 368 u8 rc_min_qp; 369 u8 rc_max_qp; 370 u8 rc_p_frame_qp; 371 u8 rc_b_frame_qp; 372 enum v4l2_mpeg_video_h264_level level_v4l2; 373 int level; 374 u16 cpb_size; 375 int interlace; 376 u8 hier_qp; 377 u8 hier_qp_type; 378 u8 hier_qp_layer; 379 u8 hier_qp_layer_qp[7]; 380 u8 sei_frame_packing; 381 u8 sei_fp_curr_frame_0; 382 u8 sei_fp_arrangement_type; 383 384 u8 fmo; 385 u8 fmo_map_type; 386 u8 fmo_slice_grp; 387 u8 fmo_chg_dir; 388 u32 fmo_chg_rate; 389 u32 fmo_run_len[4]; 390 u8 aso; 391 u32 aso_slice_order[8]; 392}; 393 394/** 395 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4 396 */ 397struct s5p_mfc_mpeg4_enc_params { 398 /* MPEG4 Only */ 399 enum v4l2_mpeg_video_mpeg4_profile profile; 400 int quarter_pixel; 401 /* Common for MPEG4, H263 */ 402 u16 vop_time_res; 403 u16 vop_frm_delta; 404 u8 rc_frame_qp; 405 u8 rc_min_qp; 406 u8 rc_max_qp; 407 u8 rc_p_frame_qp; 408 u8 rc_b_frame_qp; 409 enum v4l2_mpeg_video_mpeg4_level level_v4l2; 410 int level; 411}; 412 413/** 414 * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8 415 */ 416struct s5p_mfc_vp8_enc_params { 417 u8 imd_4x4; 418 enum v4l2_vp8_num_partitions num_partitions; 419 enum v4l2_vp8_num_ref_frames num_ref; 420 u8 filter_level; 421 u8 filter_sharpness; 422 u32 golden_frame_ref_period; 423 enum v4l2_vp8_golden_frame_sel golden_frame_sel; 424 u8 hier_layer; 425 u8 hier_layer_qp[3]; 426 u8 rc_min_qp; 427 u8 rc_max_qp; 428 u8 rc_frame_qp; 429 u8 rc_p_frame_qp; 430 u8 profile; 431}; 432 433/** 434 * struct s5p_mfc_enc_params - general encoding parameters 435 */ 436struct s5p_mfc_enc_params { 437 u16 width; 438 u16 height; 439 u32 mv_h_range; 440 u32 mv_v_range; 441 442 u16 gop_size; 443 enum v4l2_mpeg_video_multi_slice_mode slice_mode; 444 u16 slice_mb; 445 u32 slice_bit; 446 u16 intra_refresh_mb; 447 int pad; 448 u8 pad_luma; 449 u8 pad_cb; 450 u8 pad_cr; 451 int rc_frame; 452 int rc_mb; 453 u32 rc_bitrate; 454 u16 rc_reaction_coeff; 455 u16 vbv_size; 456 u32 vbv_delay; 457 458 enum v4l2_mpeg_video_header_mode seq_hdr_mode; 459 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode; 460 int fixed_target_bit; 461 462 u8 num_b_frame; 463 u32 rc_framerate_num; 464 u32 rc_framerate_denom; 465 466 struct { 467 struct s5p_mfc_h264_enc_params h264; 468 struct s5p_mfc_mpeg4_enc_params mpeg4; 469 struct s5p_mfc_vp8_enc_params vp8; 470 } codec; 471 472}; 473 474/** 475 * struct s5p_mfc_codec_ops - codec ops, used by encoding 476 */ 477struct s5p_mfc_codec_ops { 478 /* initialization routines */ 479 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx); 480 int (*post_seq_start) (struct s5p_mfc_ctx *ctx); 481 /* execution routines */ 482 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx); 483 int (*post_frame_start) (struct s5p_mfc_ctx *ctx); 484}; 485 486#define call_cop(c, op, args...) \ 487 (((c)->c_ops->op) ? \ 488 ((c)->c_ops->op(args)) : 0) 489 490/** 491 * struct s5p_mfc_ctx - This struct contains the instance context 492 * 493 * @dev: pointer to the s5p_mfc_dev of the device 494 * @fh: struct v4l2_fh 495 * @num: number of the context that this structure describes 496 * @int_cond: variable used by the waitqueue 497 * @int_type: type of the last interrupt 498 * @int_err: error number received from MFC hw in the interrupt 499 * @queue: waitqueue that can be used to wait for this context to 500 * finish 501 * @src_fmt: source pixelformat information 502 * @dst_fmt: destination pixelformat information 503 * @vq_src: vb2 queue for source buffers 504 * @vq_dst: vb2 queue for destination buffers 505 * @src_queue: driver internal queue for source buffers 506 * @dst_queue: driver internal queue for destination buffers 507 * @src_queue_cnt: number of buffers queued on the source internal queue 508 * @dst_queue_cnt: number of buffers queued on the dest internal queue 509 * @type: type of the instance - decoder or encoder 510 * @state: state of the context 511 * @inst_no: number of hw instance associated with the context 512 * @img_width: width of the image that is decoded or encoded 513 * @img_height: height of the image that is decoded or encoded 514 * @buf_width: width of the buffer for processed image 515 * @buf_height: height of the buffer for processed image 516 * @luma_size: size of a luma plane 517 * @chroma_size: size of a chroma plane 518 * @mv_size: size of a motion vectors buffer 519 * @consumed_stream: number of bytes that have been used so far from the 520 * decoding buffer 521 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being 522 * flushed 523 * @head_processed: flag mentioning whether the header data is processed 524 * completely or not 525 * @bank1: handle to memory allocated for temporary buffers from 526 * memory bank 1 527 * @bank2: handle to memory allocated for temporary buffers from 528 * memory bank 2 529 * @capture_state: state of the capture buffers queue 530 * @output_state: state of the output buffers queue 531 * @src_bufs: information on allocated source buffers 532 * @dst_bufs: information on allocated destination buffers 533 * @sequence: counter for the sequence number for v4l2 534 * @dec_dst_flag: flags for buffers queued in the hardware 535 * @dec_src_buf_size: size of the buffer for source buffers in decoding 536 * @codec_mode: number of codec mode used by MFC hw 537 * @slice_interface: slice interface flag 538 * @loop_filter_mpeg4: loop filter for MPEG4 flag 539 * @display_delay: value of the display delay for H264 540 * @display_delay_enable: display delay for H264 enable flag 541 * @after_packed_pb: flag used to track buffer when stream is in 542 * Packed PB format 543 * @sei_fp_parse: enable/disable parsing of frame packing SEI information 544 * @dpb_count: count of the DPB buffers required by MFC hw 545 * @total_dpb_count: count of DPB buffers with additional buffers 546 * requested by the application 547 * @ctx: context buffer information 548 * @dsc: descriptor buffer information 549 * @shm: shared memory buffer information 550 * @mv_count: number of MV buffers allocated for decoding 551 * @enc_params: encoding parameters for MFC 552 * @enc_dst_buf_size: size of the buffers for encoder output 553 * @luma_dpb_size: dpb buffer size for luma 554 * @chroma_dpb_size: dpb buffer size for chroma 555 * @me_buffer_size: size of the motion estimation buffer 556 * @tmv_buffer_size: size of temporal predictor motion vector buffer 557 * @frame_type: used to force the type of the next encoded frame 558 * @ref_queue: list of the reference buffers for encoding 559 * @ref_queue_cnt: number of the buffers in the reference list 560 * @c_ops: ops for encoding 561 * @ctrls: array of controls, used when adding controls to the 562 * v4l2 control framework 563 * @ctrl_handler: handler for v4l2 framework 564 */ 565struct s5p_mfc_ctx { 566 struct s5p_mfc_dev *dev; 567 struct v4l2_fh fh; 568 569 int num; 570 571 int int_cond; 572 int int_type; 573 unsigned int int_err; 574 wait_queue_head_t queue; 575 576 struct s5p_mfc_fmt *src_fmt; 577 struct s5p_mfc_fmt *dst_fmt; 578 579 struct vb2_queue vq_src; 580 struct vb2_queue vq_dst; 581 582 struct list_head src_queue; 583 struct list_head dst_queue; 584 585 unsigned int src_queue_cnt; 586 unsigned int dst_queue_cnt; 587 588 enum s5p_mfc_inst_type type; 589 enum s5p_mfc_inst_state state; 590 int inst_no; 591 592 /* Image parameters */ 593 int img_width; 594 int img_height; 595 int buf_width; 596 int buf_height; 597 598 int luma_size; 599 int chroma_size; 600 int mv_size; 601 602 unsigned long consumed_stream; 603 604 unsigned int dpb_flush_flag; 605 unsigned int head_processed; 606 607 struct s5p_mfc_priv_buf bank1; 608 struct s5p_mfc_priv_buf bank2; 609 610 enum s5p_mfc_queue_state capture_state; 611 enum s5p_mfc_queue_state output_state; 612 613 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS]; 614 int src_bufs_cnt; 615 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS]; 616 int dst_bufs_cnt; 617 618 unsigned int sequence; 619 unsigned long dec_dst_flag; 620 size_t dec_src_buf_size; 621 622 /* Control values */ 623 int codec_mode; 624 int slice_interface; 625 int loop_filter_mpeg4; 626 int display_delay; 627 int display_delay_enable; 628 int after_packed_pb; 629 int sei_fp_parse; 630 631 int pb_count; 632 int total_dpb_count; 633 int mv_count; 634 /* Buffers */ 635 struct s5p_mfc_priv_buf ctx; 636 struct s5p_mfc_priv_buf dsc; 637 struct s5p_mfc_priv_buf shm; 638 639 struct s5p_mfc_enc_params enc_params; 640 641 size_t enc_dst_buf_size; 642 size_t luma_dpb_size; 643 size_t chroma_dpb_size; 644 size_t me_buffer_size; 645 size_t tmv_buffer_size; 646 647 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type; 648 649 struct list_head ref_queue; 650 unsigned int ref_queue_cnt; 651 652 enum v4l2_mpeg_video_multi_slice_mode slice_mode; 653 union { 654 unsigned int mb; 655 unsigned int bits; 656 } slice_size; 657 658 struct s5p_mfc_codec_ops *c_ops; 659 660 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS]; 661 struct v4l2_ctrl_handler ctrl_handler; 662 unsigned int frame_tag; 663 size_t scratch_buf_size; 664}; 665 666/* 667 * struct s5p_mfc_fmt - structure used to store information about pixelformats 668 * used by the MFC 669 */ 670struct s5p_mfc_fmt { 671 char *name; 672 u32 fourcc; 673 u32 codec_mode; 674 enum s5p_mfc_fmt_type type; 675 u32 num_planes; 676 u32 versions; 677}; 678 679/** 680 * struct mfc_control - structure used to store information about MFC controls 681 * it is used to initialize the control framework. 682 */ 683struct mfc_control { 684 __u32 id; 685 enum v4l2_ctrl_type type; 686 __u8 name[32]; /* Whatever */ 687 __s32 minimum; /* Note signedness */ 688 __s32 maximum; 689 __s32 step; 690 __u32 menu_skip_mask; 691 __s32 default_value; 692 __u32 flags; 693 __u32 reserved[2]; 694 __u8 is_volatile; 695}; 696 697/* Macro for making hardware specific calls */ 698#define s5p_mfc_hw_call(f, op, args...) \ 699 ((f && f->op) ? f->op(args) : -ENODEV) 700 701#define s5p_mfc_hw_call_void(f, op, args...) \ 702do { \ 703 if (f && f->op) \ 704 f->op(args); \ 705} while (0) 706 707#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh) 708#define ctrl_to_ctx(__ctrl) \ 709 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler) 710 711void clear_work_bit(struct s5p_mfc_ctx *ctx); 712void set_work_bit(struct s5p_mfc_ctx *ctx); 713void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx); 714void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx); 715 716#define HAS_PORTNUM(dev) (dev ? (dev->variant ? \ 717 (dev->variant->port_num ? 1 : 0) : 0) : 0) 718#define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0) 719#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0) 720#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0) 721#define IS_MFCV8(dev) (dev->variant->version >= 0x80 ? 1 : 0) 722 723#define MFC_V5_BIT BIT(0) 724#define MFC_V6_BIT BIT(1) 725#define MFC_V7_BIT BIT(2) 726#define MFC_V8_BIT BIT(3) 727 728 729#endif /* S5P_MFC_COMMON_H_ */ 730