s5p_mfc_common.h revision 8f532a7fec5ee872a65d2096f846f76afd9ede6f
1/* 2 * Samsung S5P Multi Format Codec v 5.0 3 * 4 * This file contains definitions of enums and structs used by the codec 5 * driver. 6 * 7 * Copyright (C) 2011 Samsung Electronics Co., Ltd. 8 * Kamil Debski, <k.debski@samsung.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version 14 */ 15 16#ifndef S5P_MFC_COMMON_H_ 17#define S5P_MFC_COMMON_H_ 18 19#include "regs-mfc.h" 20#include <linux/platform_device.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-ctrls.h> 23#include <media/v4l2-device.h> 24#include <media/v4l2-ioctl.h> 25#include <media/videobuf2-core.h> 26 27/* Definitions related to MFC memory */ 28 29/* Offset base used to differentiate between CAPTURE and OUTPUT 30* while mmaping */ 31#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2) 32 33#define MFC_BANK1_ALLOC_CTX 0 34#define MFC_BANK2_ALLOC_CTX 1 35 36#define MFC_BANK1_ALIGN_ORDER 13 37#define MFC_BANK2_ALIGN_ORDER 13 38#define MFC_BASE_ALIGN_ORDER 17 39 40#include <media/videobuf2-dma-contig.h> 41 42static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b) 43{ 44 /* Same functionality as the vb2_dma_contig_plane_paddr */ 45 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b); 46 47 return *paddr; 48} 49 50/* MFC definitions */ 51#define MFC_MAX_EXTRA_DPB 5 52#define MFC_MAX_BUFFERS 32 53#define MFC_NUM_CONTEXTS 4 54/* Interrupt timeout */ 55#define MFC_INT_TIMEOUT 2000 56/* Busy wait timeout */ 57#define MFC_BW_TIMEOUT 500 58/* Watchdog interval */ 59#define MFC_WATCHDOG_INTERVAL 1000 60/* After how many executions watchdog should assume lock up */ 61#define MFC_WATCHDOG_CNT 10 62#define MFC_NO_INSTANCE_SET -1 63#define MFC_ENC_CAP_PLANE_COUNT 1 64#define MFC_ENC_OUT_PLANE_COUNT 2 65#define STUFF_BYTE 4 66#define MFC_MAX_CTRLS 70 67 68#define S5P_MFC_CODEC_NONE -1 69#define S5P_MFC_CODEC_H264_DEC 0 70#define S5P_MFC_CODEC_H264_MVC_DEC 1 71#define S5P_MFC_CODEC_VC1_DEC 2 72#define S5P_MFC_CODEC_MPEG4_DEC 3 73#define S5P_MFC_CODEC_MPEG2_DEC 4 74#define S5P_MFC_CODEC_H263_DEC 5 75#define S5P_MFC_CODEC_VC1RCV_DEC 6 76#define S5P_MFC_CODEC_VP8_DEC 7 77 78#define S5P_MFC_CODEC_H264_ENC 20 79#define S5P_MFC_CODEC_H264_MVC_ENC 21 80#define S5P_MFC_CODEC_MPEG4_ENC 22 81#define S5P_MFC_CODEC_H263_ENC 23 82 83#define S5P_MFC_R2H_CMD_EMPTY 0 84#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1 85#define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2 86#define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3 87#define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4 88#define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6 89#define S5P_MFC_R2H_CMD_SLEEP_RET 7 90#define S5P_MFC_R2H_CMD_WAKEUP_RET 8 91#define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9 92#define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10 93#define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11 94#define S5P_MFC_R2H_CMD_FW_STATUS_RET 12 95#define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13 96#define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14 97#define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15 98#define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16 99#define S5P_MFC_R2H_CMD_ERR_RET 32 100 101#define mfc_read(dev, offset) readl(dev->regs_base + (offset)) 102#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \ 103 (offset)) 104 105/** 106 * enum s5p_mfc_fmt_type - type of the pixelformat 107 */ 108enum s5p_mfc_fmt_type { 109 MFC_FMT_DEC, 110 MFC_FMT_ENC, 111 MFC_FMT_RAW, 112}; 113 114/** 115 * enum s5p_mfc_node_type - The type of an MFC device node. 116 */ 117enum s5p_mfc_node_type { 118 MFCNODE_INVALID = -1, 119 MFCNODE_DECODER = 0, 120 MFCNODE_ENCODER = 1, 121}; 122 123/** 124 * enum s5p_mfc_inst_type - The type of an MFC instance. 125 */ 126enum s5p_mfc_inst_type { 127 MFCINST_INVALID, 128 MFCINST_DECODER, 129 MFCINST_ENCODER, 130}; 131 132/** 133 * enum s5p_mfc_inst_state - The state of an MFC instance. 134 */ 135enum s5p_mfc_inst_state { 136 MFCINST_FREE = 0, 137 MFCINST_INIT = 100, 138 MFCINST_GOT_INST, 139 MFCINST_HEAD_PARSED, 140 MFCINST_BUFS_SET, 141 MFCINST_RUNNING, 142 MFCINST_FINISHING, 143 MFCINST_FINISHED, 144 MFCINST_RETURN_INST, 145 MFCINST_ERROR, 146 MFCINST_ABORT, 147 MFCINST_RES_CHANGE_INIT, 148 MFCINST_RES_CHANGE_FLUSH, 149 MFCINST_RES_CHANGE_END, 150}; 151 152/** 153 * enum s5p_mfc_queue_state - The state of buffer queue. 154 */ 155enum s5p_mfc_queue_state { 156 QUEUE_FREE, 157 QUEUE_BUFS_REQUESTED, 158 QUEUE_BUFS_QUERIED, 159 QUEUE_BUFS_MMAPED, 160}; 161 162/** 163 * enum s5p_mfc_decode_arg - type of frame decoding 164 */ 165enum s5p_mfc_decode_arg { 166 MFC_DEC_FRAME, 167 MFC_DEC_LAST_FRAME, 168 MFC_DEC_RES_CHANGE, 169}; 170 171#define MFC_BUF_FLAG_USED (1 << 0) 172#define MFC_BUF_FLAG_EOS (1 << 1) 173 174struct s5p_mfc_ctx; 175 176/** 177 * struct s5p_mfc_buf - MFC buffer 178 */ 179struct s5p_mfc_buf { 180 struct list_head list; 181 struct vb2_buffer *b; 182 union { 183 struct { 184 size_t luma; 185 size_t chroma; 186 } raw; 187 size_t stream; 188 } cookie; 189 int flags; 190}; 191 192/** 193 * struct s5p_mfc_pm - power management data structure 194 */ 195struct s5p_mfc_pm { 196 struct clk *clock; 197 struct clk *clock_gate; 198 atomic_t power; 199 struct device *device; 200}; 201 202struct s5p_mfc_buf_size_v5 { 203 unsigned int h264_ctx; 204 unsigned int non_h264_ctx; 205 unsigned int dsc; 206 unsigned int shm; 207}; 208 209struct s5p_mfc_buf_size { 210 unsigned int fw; 211 unsigned int cpb; 212 void *priv; 213}; 214 215struct s5p_mfc_buf_align { 216 unsigned int base; 217}; 218 219struct s5p_mfc_variant { 220 unsigned int version; 221 unsigned int port_num; 222 struct s5p_mfc_buf_size *buf_size; 223 struct s5p_mfc_buf_align *buf_align; 224}; 225 226/** 227 * struct s5p_mfc_priv_buf - represents internal used buffer 228 * @alloc: allocation-specific context for each buffer 229 * (videobuf2 allocator) 230 * @ofs: offset of each buffer, will be used for MFC 231 * @virt: kernel virtual address, only valid when the 232 * buffer accessed by driver 233 * @dma: DMA address, only valid when kernel DMA API used 234 * @size: size of the buffer 235 */ 236struct s5p_mfc_priv_buf { 237 void *alloc; 238 unsigned long ofs; 239 void *virt; 240 dma_addr_t dma; 241 size_t size; 242}; 243 244/** 245 * struct s5p_mfc_dev - The struct containing driver internal parameters. 246 * 247 * @v4l2_dev: v4l2_device 248 * @vfd_dec: video device for decoding 249 * @vfd_enc: video device for encoding 250 * @plat_dev: platform device 251 * @mem_dev_l: child device of the left memory bank (0) 252 * @mem_dev_r: child device of the right memory bank (1) 253 * @regs_base: base address of the MFC hw registers 254 * @irq: irq resource 255 * @dec_ctrl_handler: control framework handler for decoding 256 * @enc_ctrl_handler: control framework handler for encoding 257 * @pm: power management control 258 * @variant: MFC hardware variant information 259 * @num_inst: couter of active MFC instances 260 * @irqlock: lock for operations on videobuf2 queues 261 * @condlock: lock for changing/checking if a context is ready to be 262 * processed 263 * @mfc_mutex: lock for video_device 264 * @int_cond: variable used by the waitqueue 265 * @int_type: type of last interrupt 266 * @int_err: error number for last interrupt 267 * @queue: waitqueue for waiting for completion of device commands 268 * @fw_size: size of firmware 269 * @bank1: address of the beggining of bank 1 memory 270 * @bank2: address of the beggining of bank 2 memory 271 * @hw_lock: used for hardware locking 272 * @ctx: array of driver contexts 273 * @curr_ctx: number of the currently running context 274 * @ctx_work_bits: used to mark which contexts are waiting for hardware 275 * @watchdog_cnt: counter for the watchdog 276 * @watchdog_workqueue: workqueue for the watchdog 277 * @watchdog_work: worker for the watchdog 278 * @alloc_ctx: videobuf2 allocator contexts for two memory banks 279 * @enter_suspend: flag set when entering suspend 280 * @warn_start: hardware error code from which warnings start 281 * @mfc_ops: ops structure holding HW operation function pointers 282 * @mfc_cmds: cmd structure holding HW commands function pointers 283 * 284 */ 285struct s5p_mfc_dev { 286 struct v4l2_device v4l2_dev; 287 struct video_device *vfd_dec; 288 struct video_device *vfd_enc; 289 struct platform_device *plat_dev; 290 struct device *mem_dev_l; 291 struct device *mem_dev_r; 292 void __iomem *regs_base; 293 int irq; 294 struct v4l2_ctrl_handler dec_ctrl_handler; 295 struct v4l2_ctrl_handler enc_ctrl_handler; 296 struct s5p_mfc_pm pm; 297 struct s5p_mfc_variant *variant; 298 int num_inst; 299 spinlock_t irqlock; /* lock when operating on videobuf2 queues */ 300 spinlock_t condlock; /* lock when changing/checking if a context is 301 ready to be processed */ 302 struct mutex mfc_mutex; /* video_device lock */ 303 int int_cond; 304 int int_type; 305 unsigned int int_err; 306 wait_queue_head_t queue; 307 size_t fw_size; 308 size_t bank1; 309 size_t bank2; 310 unsigned long hw_lock; 311 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS]; 312 int curr_ctx; 313 unsigned long ctx_work_bits; 314 atomic_t watchdog_cnt; 315 struct timer_list watchdog_timer; 316 struct workqueue_struct *watchdog_workqueue; 317 struct work_struct watchdog_work; 318 void *alloc_ctx[2]; 319 unsigned long enter_suspend; 320 321 int warn_start; 322 struct s5p_mfc_hw_ops *mfc_ops; 323 struct s5p_mfc_hw_cmds *mfc_cmds; 324}; 325 326/** 327 * struct s5p_mfc_h264_enc_params - encoding parameters for h264 328 */ 329struct s5p_mfc_h264_enc_params { 330 enum v4l2_mpeg_video_h264_profile profile; 331 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode; 332 s8 loop_filter_alpha; 333 s8 loop_filter_beta; 334 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode; 335 u8 max_ref_pic; 336 u8 num_ref_pic_4p; 337 int _8x8_transform; 338 int rc_mb_dark; 339 int rc_mb_smooth; 340 int rc_mb_static; 341 int rc_mb_activity; 342 int vui_sar; 343 u8 vui_sar_idc; 344 u16 vui_ext_sar_width; 345 u16 vui_ext_sar_height; 346 int open_gop; 347 u16 open_gop_size; 348 u8 rc_frame_qp; 349 u8 rc_min_qp; 350 u8 rc_max_qp; 351 u8 rc_p_frame_qp; 352 u8 rc_b_frame_qp; 353 enum v4l2_mpeg_video_h264_level level_v4l2; 354 int level; 355 u16 cpb_size; 356 int interlace; 357}; 358 359/** 360 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4 361 */ 362struct s5p_mfc_mpeg4_enc_params { 363 /* MPEG4 Only */ 364 enum v4l2_mpeg_video_mpeg4_profile profile; 365 int quarter_pixel; 366 /* Common for MPEG4, H263 */ 367 u16 vop_time_res; 368 u16 vop_frm_delta; 369 u8 rc_frame_qp; 370 u8 rc_min_qp; 371 u8 rc_max_qp; 372 u8 rc_p_frame_qp; 373 u8 rc_b_frame_qp; 374 enum v4l2_mpeg_video_mpeg4_level level_v4l2; 375 int level; 376}; 377 378/** 379 * struct s5p_mfc_enc_params - general encoding parameters 380 */ 381struct s5p_mfc_enc_params { 382 u16 width; 383 u16 height; 384 385 u16 gop_size; 386 enum v4l2_mpeg_video_multi_slice_mode slice_mode; 387 u16 slice_mb; 388 u32 slice_bit; 389 u16 intra_refresh_mb; 390 int pad; 391 u8 pad_luma; 392 u8 pad_cb; 393 u8 pad_cr; 394 int rc_frame; 395 int rc_mb; 396 u32 rc_bitrate; 397 u16 rc_reaction_coeff; 398 u16 vbv_size; 399 400 enum v4l2_mpeg_video_header_mode seq_hdr_mode; 401 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode; 402 int fixed_target_bit; 403 404 u8 num_b_frame; 405 u32 rc_framerate_num; 406 u32 rc_framerate_denom; 407 408 union { 409 struct s5p_mfc_h264_enc_params h264; 410 struct s5p_mfc_mpeg4_enc_params mpeg4; 411 } codec; 412 413}; 414 415/** 416 * struct s5p_mfc_codec_ops - codec ops, used by encoding 417 */ 418struct s5p_mfc_codec_ops { 419 /* initialization routines */ 420 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx); 421 int (*post_seq_start) (struct s5p_mfc_ctx *ctx); 422 /* execution routines */ 423 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx); 424 int (*post_frame_start) (struct s5p_mfc_ctx *ctx); 425}; 426 427#define call_cop(c, op, args...) \ 428 (((c)->c_ops->op) ? \ 429 ((c)->c_ops->op(args)) : 0) 430 431/** 432 * struct s5p_mfc_ctx - This struct contains the instance context 433 * 434 * @dev: pointer to the s5p_mfc_dev of the device 435 * @fh: struct v4l2_fh 436 * @num: number of the context that this structure describes 437 * @int_cond: variable used by the waitqueue 438 * @int_type: type of the last interrupt 439 * @int_err: error number received from MFC hw in the interrupt 440 * @queue: waitqueue that can be used to wait for this context to 441 * finish 442 * @src_fmt: source pixelformat information 443 * @dst_fmt: destination pixelformat information 444 * @vq_src: vb2 queue for source buffers 445 * @vq_dst: vb2 queue for destination buffers 446 * @src_queue: driver internal queue for source buffers 447 * @dst_queue: driver internal queue for destination buffers 448 * @src_queue_cnt: number of buffers queued on the source internal queue 449 * @dst_queue_cnt: number of buffers queued on the dest internal queue 450 * @type: type of the instance - decoder or encoder 451 * @state: state of the context 452 * @inst_no: number of hw instance associated with the context 453 * @img_width: width of the image that is decoded or encoded 454 * @img_height: height of the image that is decoded or encoded 455 * @buf_width: width of the buffer for processed image 456 * @buf_height: height of the buffer for processed image 457 * @luma_size: size of a luma plane 458 * @chroma_size: size of a chroma plane 459 * @mv_size: size of a motion vectors buffer 460 * @consumed_stream: number of bytes that have been used so far from the 461 * decoding buffer 462 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being 463 * flushed 464 * @bank1_buf: handle to memory allocated for temporary buffers from 465 * memory bank 1 466 * @bank1_phys: address of the temporary buffers from memory bank 1 467 * @bank1_size: size of the memory allocated for temporary buffers from 468 * memory bank 1 469 * @bank2_buf: handle to memory allocated for temporary buffers from 470 * memory bank 2 471 * @bank2_phys: address of the temporary buffers from memory bank 2 472 * @bank2_size: size of the memory allocated for temporary buffers from 473 * memory bank 2 474 * @capture_state: state of the capture buffers queue 475 * @output_state: state of the output buffers queue 476 * @src_bufs: information on allocated source buffers 477 * @dst_bufs: information on allocated destination buffers 478 * @sequence: counter for the sequence number for v4l2 479 * @dec_dst_flag: flags for buffers queued in the hardware 480 * @dec_src_buf_size: size of the buffer for source buffers in decoding 481 * @codec_mode: number of codec mode used by MFC hw 482 * @slice_interface: slice interface flag 483 * @loop_filter_mpeg4: loop filter for MPEG4 flag 484 * @display_delay: value of the display delay for H264 485 * @display_delay_enable: display delay for H264 enable flag 486 * @after_packed_pb: flag used to track buffer when stream is in 487 * Packed PB format 488 * @dpb_count: count of the DPB buffers required by MFC hw 489 * @total_dpb_count: count of DPB buffers with additional buffers 490 * requested by the application 491 * @ctx: context buffer information 492 * @dsc: descriptor buffer information 493 * @shm: shared memory buffer information 494 * @enc_params: encoding parameters for MFC 495 * @enc_dst_buf_size: size of the buffers for encoder output 496 * @frame_type: used to force the type of the next encoded frame 497 * @ref_queue: list of the reference buffers for encoding 498 * @ref_queue_cnt: number of the buffers in the reference list 499 * @c_ops: ops for encoding 500 * @ctrls: array of controls, used when adding controls to the 501 * v4l2 control framework 502 * @ctrl_handler: handler for v4l2 framework 503 */ 504struct s5p_mfc_ctx { 505 struct s5p_mfc_dev *dev; 506 struct v4l2_fh fh; 507 508 int num; 509 510 int int_cond; 511 int int_type; 512 unsigned int int_err; 513 wait_queue_head_t queue; 514 515 struct s5p_mfc_fmt *src_fmt; 516 struct s5p_mfc_fmt *dst_fmt; 517 518 struct vb2_queue vq_src; 519 struct vb2_queue vq_dst; 520 521 struct list_head src_queue; 522 struct list_head dst_queue; 523 524 unsigned int src_queue_cnt; 525 unsigned int dst_queue_cnt; 526 527 enum s5p_mfc_inst_type type; 528 enum s5p_mfc_inst_state state; 529 int inst_no; 530 531 /* Image parameters */ 532 int img_width; 533 int img_height; 534 int buf_width; 535 int buf_height; 536 537 int luma_size; 538 int chroma_size; 539 int mv_size; 540 541 unsigned long consumed_stream; 542 543 unsigned int dpb_flush_flag; 544 545 /* Buffers */ 546 void *bank1_buf; 547 size_t bank1_phys; 548 size_t bank1_size; 549 550 void *bank2_buf; 551 size_t bank2_phys; 552 size_t bank2_size; 553 554 enum s5p_mfc_queue_state capture_state; 555 enum s5p_mfc_queue_state output_state; 556 557 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS]; 558 int src_bufs_cnt; 559 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS]; 560 int dst_bufs_cnt; 561 562 unsigned int sequence; 563 unsigned long dec_dst_flag; 564 size_t dec_src_buf_size; 565 566 /* Control values */ 567 int codec_mode; 568 int slice_interface; 569 int loop_filter_mpeg4; 570 int display_delay; 571 int display_delay_enable; 572 int after_packed_pb; 573 574 int dpb_count; 575 int total_dpb_count; 576 577 /* Buffers */ 578 struct s5p_mfc_priv_buf ctx; 579 struct s5p_mfc_priv_buf dsc; 580 struct s5p_mfc_priv_buf shm; 581 582 struct s5p_mfc_enc_params enc_params; 583 584 size_t enc_dst_buf_size; 585 586 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type; 587 588 struct list_head ref_queue; 589 unsigned int ref_queue_cnt; 590 591 struct s5p_mfc_codec_ops *c_ops; 592 593 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS]; 594 struct v4l2_ctrl_handler ctrl_handler; 595}; 596 597/* 598 * struct s5p_mfc_fmt - structure used to store information about pixelformats 599 * used by the MFC 600 */ 601struct s5p_mfc_fmt { 602 char *name; 603 u32 fourcc; 604 u32 codec_mode; 605 enum s5p_mfc_fmt_type type; 606 u32 num_planes; 607}; 608 609/** 610 * struct mfc_control - structure used to store information about MFC controls 611 * it is used to initialize the control framework. 612 */ 613struct mfc_control { 614 __u32 id; 615 enum v4l2_ctrl_type type; 616 __u8 name[32]; /* Whatever */ 617 __s32 minimum; /* Note signedness */ 618 __s32 maximum; 619 __s32 step; 620 __u32 menu_skip_mask; 621 __s32 default_value; 622 __u32 flags; 623 __u32 reserved[2]; 624 __u8 is_volatile; 625}; 626 627/* Macro for making hardware specific calls */ 628#define s5p_mfc_hw_call(f, op, args...) \ 629 ((f && f->op) ? f->op(args) : -ENODEV) 630 631#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh) 632#define ctrl_to_ctx(__ctrl) \ 633 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler) 634 635void clear_work_bit(struct s5p_mfc_ctx *ctx); 636void set_work_bit(struct s5p_mfc_ctx *ctx); 637void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx); 638void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx); 639 640#endif /* S5P_MFC_COMMON_H_ */ 641