s5p_mfc_common.h revision bbd8f3fef9d289fcfddaefccc2e5a2355da5d2f4
1/* 2 * Samsung S5P Multi Format Codec v 5.0 3 * 4 * This file contains definitions of enums and structs used by the codec 5 * driver. 6 * 7 * Copyright (C) 2011 Samsung Electronics Co., Ltd. 8 * Kamil Debski, <k.debski@samsung.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version 14 */ 15 16#ifndef S5P_MFC_COMMON_H_ 17#define S5P_MFC_COMMON_H_ 18 19#include <linux/platform_device.h> 20#include <linux/videodev2.h> 21#include <media/v4l2-ctrls.h> 22#include <media/v4l2-device.h> 23#include <media/v4l2-ioctl.h> 24#include <media/videobuf2-core.h> 25#include "regs-mfc.h" 26#include "regs-mfc-v6.h" 27#include "regs-mfc-v7.h" 28 29/* Definitions related to MFC memory */ 30 31/* Offset base used to differentiate between CAPTURE and OUTPUT 32* while mmaping */ 33#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2) 34 35#define MFC_BANK1_ALLOC_CTX 0 36#define MFC_BANK2_ALLOC_CTX 1 37 38#define MFC_BANK1_ALIGN_ORDER 13 39#define MFC_BANK2_ALIGN_ORDER 13 40#define MFC_BASE_ALIGN_ORDER 17 41 42#include <media/videobuf2-dma-contig.h> 43 44static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b) 45{ 46 /* Same functionality as the vb2_dma_contig_plane_paddr */ 47 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b); 48 49 return *paddr; 50} 51 52/* MFC definitions */ 53#define MFC_MAX_EXTRA_DPB 5 54#define MFC_MAX_BUFFERS 32 55#define MFC_NUM_CONTEXTS 4 56/* Interrupt timeout */ 57#define MFC_INT_TIMEOUT 2000 58/* Busy wait timeout */ 59#define MFC_BW_TIMEOUT 500 60/* Watchdog interval */ 61#define MFC_WATCHDOG_INTERVAL 1000 62/* After how many executions watchdog should assume lock up */ 63#define MFC_WATCHDOG_CNT 10 64#define MFC_NO_INSTANCE_SET -1 65#define MFC_ENC_CAP_PLANE_COUNT 1 66#define MFC_ENC_OUT_PLANE_COUNT 2 67#define STUFF_BYTE 4 68#define MFC_MAX_CTRLS 77 69 70#define S5P_MFC_CODEC_NONE -1 71#define S5P_MFC_CODEC_H264_DEC 0 72#define S5P_MFC_CODEC_H264_MVC_DEC 1 73#define S5P_MFC_CODEC_VC1_DEC 2 74#define S5P_MFC_CODEC_MPEG4_DEC 3 75#define S5P_MFC_CODEC_MPEG2_DEC 4 76#define S5P_MFC_CODEC_H263_DEC 5 77#define S5P_MFC_CODEC_VC1RCV_DEC 6 78#define S5P_MFC_CODEC_VP8_DEC 7 79 80#define S5P_MFC_CODEC_H264_ENC 20 81#define S5P_MFC_CODEC_H264_MVC_ENC 21 82#define S5P_MFC_CODEC_MPEG4_ENC 22 83#define S5P_MFC_CODEC_H263_ENC 23 84#define S5P_MFC_CODEC_VP8_ENC 24 85 86#define S5P_MFC_R2H_CMD_EMPTY 0 87#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1 88#define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2 89#define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3 90#define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4 91#define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6 92#define S5P_MFC_R2H_CMD_SLEEP_RET 7 93#define S5P_MFC_R2H_CMD_WAKEUP_RET 8 94#define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9 95#define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10 96#define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11 97#define S5P_MFC_R2H_CMD_FW_STATUS_RET 12 98#define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13 99#define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14 100#define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15 101#define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16 102#define S5P_MFC_R2H_CMD_ERR_RET 32 103 104#define mfc_read(dev, offset) readl(dev->regs_base + (offset)) 105#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \ 106 (offset)) 107 108/** 109 * enum s5p_mfc_fmt_type - type of the pixelformat 110 */ 111enum s5p_mfc_fmt_type { 112 MFC_FMT_DEC, 113 MFC_FMT_ENC, 114 MFC_FMT_RAW, 115}; 116 117/** 118 * enum s5p_mfc_inst_type - The type of an MFC instance. 119 */ 120enum s5p_mfc_inst_type { 121 MFCINST_INVALID, 122 MFCINST_DECODER, 123 MFCINST_ENCODER, 124}; 125 126/** 127 * enum s5p_mfc_inst_state - The state of an MFC instance. 128 */ 129enum s5p_mfc_inst_state { 130 MFCINST_FREE = 0, 131 MFCINST_INIT = 100, 132 MFCINST_GOT_INST, 133 MFCINST_HEAD_PARSED, 134 MFCINST_HEAD_PRODUCED, 135 MFCINST_BUFS_SET, 136 MFCINST_RUNNING, 137 MFCINST_FINISHING, 138 MFCINST_FINISHED, 139 MFCINST_RETURN_INST, 140 MFCINST_ERROR, 141 MFCINST_ABORT, 142 MFCINST_FLUSH, 143 MFCINST_RES_CHANGE_INIT, 144 MFCINST_RES_CHANGE_FLUSH, 145 MFCINST_RES_CHANGE_END, 146}; 147 148/** 149 * enum s5p_mfc_queue_state - The state of buffer queue. 150 */ 151enum s5p_mfc_queue_state { 152 QUEUE_FREE, 153 QUEUE_BUFS_REQUESTED, 154 QUEUE_BUFS_QUERIED, 155 QUEUE_BUFS_MMAPED, 156}; 157 158/** 159 * enum s5p_mfc_decode_arg - type of frame decoding 160 */ 161enum s5p_mfc_decode_arg { 162 MFC_DEC_FRAME, 163 MFC_DEC_LAST_FRAME, 164 MFC_DEC_RES_CHANGE, 165}; 166 167#define MFC_BUF_FLAG_USED (1 << 0) 168#define MFC_BUF_FLAG_EOS (1 << 1) 169 170struct s5p_mfc_ctx; 171 172/** 173 * struct s5p_mfc_buf - MFC buffer 174 */ 175struct s5p_mfc_buf { 176 struct list_head list; 177 struct vb2_buffer *b; 178 union { 179 struct { 180 size_t luma; 181 size_t chroma; 182 } raw; 183 size_t stream; 184 } cookie; 185 int flags; 186}; 187 188/** 189 * struct s5p_mfc_pm - power management data structure 190 */ 191struct s5p_mfc_pm { 192 struct clk *clock; 193 struct clk *clock_gate; 194 atomic_t power; 195 struct device *device; 196}; 197 198struct s5p_mfc_buf_size_v5 { 199 unsigned int h264_ctx; 200 unsigned int non_h264_ctx; 201 unsigned int dsc; 202 unsigned int shm; 203}; 204 205struct s5p_mfc_buf_size_v6 { 206 unsigned int dev_ctx; 207 unsigned int h264_dec_ctx; 208 unsigned int other_dec_ctx; 209 unsigned int h264_enc_ctx; 210 unsigned int other_enc_ctx; 211}; 212 213struct s5p_mfc_buf_size { 214 unsigned int fw; 215 unsigned int cpb; 216 void *priv; 217}; 218 219struct s5p_mfc_buf_align { 220 unsigned int base; 221}; 222 223struct s5p_mfc_variant { 224 unsigned int version; 225 unsigned int port_num; 226 struct s5p_mfc_buf_size *buf_size; 227 struct s5p_mfc_buf_align *buf_align; 228 char *fw_name; 229}; 230 231/** 232 * struct s5p_mfc_priv_buf - represents internal used buffer 233 * @alloc: allocation-specific context for each buffer 234 * (videobuf2 allocator) 235 * @ofs: offset of each buffer, will be used for MFC 236 * @virt: kernel virtual address, only valid when the 237 * buffer accessed by driver 238 * @dma: DMA address, only valid when kernel DMA API used 239 * @size: size of the buffer 240 */ 241struct s5p_mfc_priv_buf { 242 void *alloc; 243 unsigned long ofs; 244 void *virt; 245 dma_addr_t dma; 246 size_t size; 247}; 248 249/** 250 * struct s5p_mfc_dev - The struct containing driver internal parameters. 251 * 252 * @v4l2_dev: v4l2_device 253 * @vfd_dec: video device for decoding 254 * @vfd_enc: video device for encoding 255 * @plat_dev: platform device 256 * @mem_dev_l: child device of the left memory bank (0) 257 * @mem_dev_r: child device of the right memory bank (1) 258 * @regs_base: base address of the MFC hw registers 259 * @irq: irq resource 260 * @dec_ctrl_handler: control framework handler for decoding 261 * @enc_ctrl_handler: control framework handler for encoding 262 * @pm: power management control 263 * @variant: MFC hardware variant information 264 * @num_inst: couter of active MFC instances 265 * @irqlock: lock for operations on videobuf2 queues 266 * @condlock: lock for changing/checking if a context is ready to be 267 * processed 268 * @mfc_mutex: lock for video_device 269 * @int_cond: variable used by the waitqueue 270 * @int_type: type of last interrupt 271 * @int_err: error number for last interrupt 272 * @queue: waitqueue for waiting for completion of device commands 273 * @fw_size: size of firmware 274 * @fw_virt_addr: virtual firmware address 275 * @bank1: address of the beginning of bank 1 memory 276 * @bank2: address of the beginning of bank 2 memory 277 * @hw_lock: used for hardware locking 278 * @ctx: array of driver contexts 279 * @curr_ctx: number of the currently running context 280 * @ctx_work_bits: used to mark which contexts are waiting for hardware 281 * @watchdog_cnt: counter for the watchdog 282 * @watchdog_workqueue: workqueue for the watchdog 283 * @watchdog_work: worker for the watchdog 284 * @alloc_ctx: videobuf2 allocator contexts for two memory banks 285 * @enter_suspend: flag set when entering suspend 286 * @ctx_buf: common context memory (MFCv6) 287 * @warn_start: hardware error code from which warnings start 288 * @mfc_ops: ops structure holding HW operation function pointers 289 * @mfc_cmds: cmd structure holding HW commands function pointers 290 * 291 */ 292struct s5p_mfc_dev { 293 struct v4l2_device v4l2_dev; 294 struct video_device *vfd_dec; 295 struct video_device *vfd_enc; 296 struct platform_device *plat_dev; 297 struct device *mem_dev_l; 298 struct device *mem_dev_r; 299 void __iomem *regs_base; 300 int irq; 301 struct v4l2_ctrl_handler dec_ctrl_handler; 302 struct v4l2_ctrl_handler enc_ctrl_handler; 303 struct s5p_mfc_pm pm; 304 struct s5p_mfc_variant *variant; 305 int num_inst; 306 spinlock_t irqlock; /* lock when operating on videobuf2 queues */ 307 spinlock_t condlock; /* lock when changing/checking if a context is 308 ready to be processed */ 309 struct mutex mfc_mutex; /* video_device lock */ 310 int int_cond; 311 int int_type; 312 unsigned int int_err; 313 wait_queue_head_t queue; 314 size_t fw_size; 315 void *fw_virt_addr; 316 dma_addr_t bank1; 317 dma_addr_t bank2; 318 unsigned long hw_lock; 319 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS]; 320 int curr_ctx; 321 unsigned long ctx_work_bits; 322 atomic_t watchdog_cnt; 323 struct timer_list watchdog_timer; 324 struct workqueue_struct *watchdog_workqueue; 325 struct work_struct watchdog_work; 326 void *alloc_ctx[2]; 327 unsigned long enter_suspend; 328 329 struct s5p_mfc_priv_buf ctx_buf; 330 int warn_start; 331 struct s5p_mfc_hw_ops *mfc_ops; 332 struct s5p_mfc_hw_cmds *mfc_cmds; 333}; 334 335/** 336 * struct s5p_mfc_h264_enc_params - encoding parameters for h264 337 */ 338struct s5p_mfc_h264_enc_params { 339 enum v4l2_mpeg_video_h264_profile profile; 340 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode; 341 s8 loop_filter_alpha; 342 s8 loop_filter_beta; 343 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode; 344 u8 max_ref_pic; 345 u8 num_ref_pic_4p; 346 int _8x8_transform; 347 int rc_mb_dark; 348 int rc_mb_smooth; 349 int rc_mb_static; 350 int rc_mb_activity; 351 int vui_sar; 352 u8 vui_sar_idc; 353 u16 vui_ext_sar_width; 354 u16 vui_ext_sar_height; 355 int open_gop; 356 u16 open_gop_size; 357 u8 rc_frame_qp; 358 u8 rc_min_qp; 359 u8 rc_max_qp; 360 u8 rc_p_frame_qp; 361 u8 rc_b_frame_qp; 362 enum v4l2_mpeg_video_h264_level level_v4l2; 363 int level; 364 u16 cpb_size; 365 int interlace; 366 u8 hier_qp; 367 u8 hier_qp_type; 368 u8 hier_qp_layer; 369 u8 hier_qp_layer_qp[7]; 370 u8 sei_frame_packing; 371 u8 sei_fp_curr_frame_0; 372 u8 sei_fp_arrangement_type; 373 374 u8 fmo; 375 u8 fmo_map_type; 376 u8 fmo_slice_grp; 377 u8 fmo_chg_dir; 378 u32 fmo_chg_rate; 379 u32 fmo_run_len[4]; 380 u8 aso; 381 u32 aso_slice_order[8]; 382}; 383 384/** 385 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4 386 */ 387struct s5p_mfc_mpeg4_enc_params { 388 /* MPEG4 Only */ 389 enum v4l2_mpeg_video_mpeg4_profile profile; 390 int quarter_pixel; 391 /* Common for MPEG4, H263 */ 392 u16 vop_time_res; 393 u16 vop_frm_delta; 394 u8 rc_frame_qp; 395 u8 rc_min_qp; 396 u8 rc_max_qp; 397 u8 rc_p_frame_qp; 398 u8 rc_b_frame_qp; 399 enum v4l2_mpeg_video_mpeg4_level level_v4l2; 400 int level; 401}; 402 403/** 404 * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8 405 */ 406struct s5p_mfc_vp8_enc_params { 407 u8 imd_4x4; 408 enum v4l2_vp8_num_partitions num_partitions; 409 enum v4l2_vp8_num_ref_frames num_ref; 410 u8 filter_level; 411 u8 filter_sharpness; 412 u32 golden_frame_ref_period; 413 enum v4l2_vp8_golden_frame_sel golden_frame_sel; 414 u8 hier_layer; 415 u8 hier_layer_qp[3]; 416 u8 rc_min_qp; 417 u8 rc_max_qp; 418 u8 rc_frame_qp; 419 u8 rc_p_frame_qp; 420 u8 profile; 421}; 422 423/** 424 * struct s5p_mfc_enc_params - general encoding parameters 425 */ 426struct s5p_mfc_enc_params { 427 u16 width; 428 u16 height; 429 430 u16 gop_size; 431 enum v4l2_mpeg_video_multi_slice_mode slice_mode; 432 u16 slice_mb; 433 u32 slice_bit; 434 u16 intra_refresh_mb; 435 int pad; 436 u8 pad_luma; 437 u8 pad_cb; 438 u8 pad_cr; 439 int rc_frame; 440 int rc_mb; 441 u32 rc_bitrate; 442 u16 rc_reaction_coeff; 443 u16 vbv_size; 444 u32 vbv_delay; 445 446 enum v4l2_mpeg_video_header_mode seq_hdr_mode; 447 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode; 448 int fixed_target_bit; 449 450 u8 num_b_frame; 451 u32 rc_framerate_num; 452 u32 rc_framerate_denom; 453 454 struct { 455 struct s5p_mfc_h264_enc_params h264; 456 struct s5p_mfc_mpeg4_enc_params mpeg4; 457 struct s5p_mfc_vp8_enc_params vp8; 458 } codec; 459 460}; 461 462/** 463 * struct s5p_mfc_codec_ops - codec ops, used by encoding 464 */ 465struct s5p_mfc_codec_ops { 466 /* initialization routines */ 467 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx); 468 int (*post_seq_start) (struct s5p_mfc_ctx *ctx); 469 /* execution routines */ 470 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx); 471 int (*post_frame_start) (struct s5p_mfc_ctx *ctx); 472}; 473 474#define call_cop(c, op, args...) \ 475 (((c)->c_ops->op) ? \ 476 ((c)->c_ops->op(args)) : 0) 477 478/** 479 * struct s5p_mfc_ctx - This struct contains the instance context 480 * 481 * @dev: pointer to the s5p_mfc_dev of the device 482 * @fh: struct v4l2_fh 483 * @num: number of the context that this structure describes 484 * @int_cond: variable used by the waitqueue 485 * @int_type: type of the last interrupt 486 * @int_err: error number received from MFC hw in the interrupt 487 * @queue: waitqueue that can be used to wait for this context to 488 * finish 489 * @src_fmt: source pixelformat information 490 * @dst_fmt: destination pixelformat information 491 * @vq_src: vb2 queue for source buffers 492 * @vq_dst: vb2 queue for destination buffers 493 * @src_queue: driver internal queue for source buffers 494 * @dst_queue: driver internal queue for destination buffers 495 * @src_queue_cnt: number of buffers queued on the source internal queue 496 * @dst_queue_cnt: number of buffers queued on the dest internal queue 497 * @type: type of the instance - decoder or encoder 498 * @state: state of the context 499 * @inst_no: number of hw instance associated with the context 500 * @img_width: width of the image that is decoded or encoded 501 * @img_height: height of the image that is decoded or encoded 502 * @buf_width: width of the buffer for processed image 503 * @buf_height: height of the buffer for processed image 504 * @luma_size: size of a luma plane 505 * @chroma_size: size of a chroma plane 506 * @mv_size: size of a motion vectors buffer 507 * @consumed_stream: number of bytes that have been used so far from the 508 * decoding buffer 509 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being 510 * flushed 511 * @head_processed: flag mentioning whether the header data is processed 512 * completely or not 513 * @bank1: handle to memory allocated for temporary buffers from 514 * memory bank 1 515 * @bank2: handle to memory allocated for temporary buffers from 516 * memory bank 2 517 * @capture_state: state of the capture buffers queue 518 * @output_state: state of the output buffers queue 519 * @src_bufs: information on allocated source buffers 520 * @dst_bufs: information on allocated destination buffers 521 * @sequence: counter for the sequence number for v4l2 522 * @dec_dst_flag: flags for buffers queued in the hardware 523 * @dec_src_buf_size: size of the buffer for source buffers in decoding 524 * @codec_mode: number of codec mode used by MFC hw 525 * @slice_interface: slice interface flag 526 * @loop_filter_mpeg4: loop filter for MPEG4 flag 527 * @display_delay: value of the display delay for H264 528 * @display_delay_enable: display delay for H264 enable flag 529 * @after_packed_pb: flag used to track buffer when stream is in 530 * Packed PB format 531 * @sei_fp_parse: enable/disable parsing of frame packing SEI information 532 * @dpb_count: count of the DPB buffers required by MFC hw 533 * @total_dpb_count: count of DPB buffers with additional buffers 534 * requested by the application 535 * @ctx: context buffer information 536 * @dsc: descriptor buffer information 537 * @shm: shared memory buffer information 538 * @mv_count: number of MV buffers allocated for decoding 539 * @enc_params: encoding parameters for MFC 540 * @enc_dst_buf_size: size of the buffers for encoder output 541 * @luma_dpb_size: dpb buffer size for luma 542 * @chroma_dpb_size: dpb buffer size for chroma 543 * @me_buffer_size: size of the motion estimation buffer 544 * @tmv_buffer_size: size of temporal predictor motion vector buffer 545 * @frame_type: used to force the type of the next encoded frame 546 * @ref_queue: list of the reference buffers for encoding 547 * @ref_queue_cnt: number of the buffers in the reference list 548 * @c_ops: ops for encoding 549 * @ctrls: array of controls, used when adding controls to the 550 * v4l2 control framework 551 * @ctrl_handler: handler for v4l2 framework 552 */ 553struct s5p_mfc_ctx { 554 struct s5p_mfc_dev *dev; 555 struct v4l2_fh fh; 556 557 int num; 558 559 int int_cond; 560 int int_type; 561 unsigned int int_err; 562 wait_queue_head_t queue; 563 564 struct s5p_mfc_fmt *src_fmt; 565 struct s5p_mfc_fmt *dst_fmt; 566 567 struct vb2_queue vq_src; 568 struct vb2_queue vq_dst; 569 570 struct list_head src_queue; 571 struct list_head dst_queue; 572 573 unsigned int src_queue_cnt; 574 unsigned int dst_queue_cnt; 575 576 enum s5p_mfc_inst_type type; 577 enum s5p_mfc_inst_state state; 578 int inst_no; 579 580 /* Image parameters */ 581 int img_width; 582 int img_height; 583 int buf_width; 584 int buf_height; 585 586 int luma_size; 587 int chroma_size; 588 int mv_size; 589 590 unsigned long consumed_stream; 591 592 unsigned int dpb_flush_flag; 593 unsigned int head_processed; 594 595 struct s5p_mfc_priv_buf bank1; 596 struct s5p_mfc_priv_buf bank2; 597 598 enum s5p_mfc_queue_state capture_state; 599 enum s5p_mfc_queue_state output_state; 600 601 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS]; 602 int src_bufs_cnt; 603 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS]; 604 int dst_bufs_cnt; 605 606 unsigned int sequence; 607 unsigned long dec_dst_flag; 608 size_t dec_src_buf_size; 609 610 /* Control values */ 611 int codec_mode; 612 int slice_interface; 613 int loop_filter_mpeg4; 614 int display_delay; 615 int display_delay_enable; 616 int after_packed_pb; 617 int sei_fp_parse; 618 619 int pb_count; 620 int total_dpb_count; 621 int mv_count; 622 /* Buffers */ 623 struct s5p_mfc_priv_buf ctx; 624 struct s5p_mfc_priv_buf dsc; 625 struct s5p_mfc_priv_buf shm; 626 627 struct s5p_mfc_enc_params enc_params; 628 629 size_t enc_dst_buf_size; 630 size_t luma_dpb_size; 631 size_t chroma_dpb_size; 632 size_t me_buffer_size; 633 size_t tmv_buffer_size; 634 635 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type; 636 637 struct list_head ref_queue; 638 unsigned int ref_queue_cnt; 639 640 enum v4l2_mpeg_video_multi_slice_mode slice_mode; 641 union { 642 unsigned int mb; 643 unsigned int bits; 644 } slice_size; 645 646 struct s5p_mfc_codec_ops *c_ops; 647 648 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS]; 649 struct v4l2_ctrl_handler ctrl_handler; 650 unsigned int frame_tag; 651 size_t scratch_buf_size; 652}; 653 654/* 655 * struct s5p_mfc_fmt - structure used to store information about pixelformats 656 * used by the MFC 657 */ 658struct s5p_mfc_fmt { 659 char *name; 660 u32 fourcc; 661 u32 codec_mode; 662 enum s5p_mfc_fmt_type type; 663 u32 num_planes; 664}; 665 666/** 667 * struct mfc_control - structure used to store information about MFC controls 668 * it is used to initialize the control framework. 669 */ 670struct mfc_control { 671 __u32 id; 672 enum v4l2_ctrl_type type; 673 __u8 name[32]; /* Whatever */ 674 __s32 minimum; /* Note signedness */ 675 __s32 maximum; 676 __s32 step; 677 __u32 menu_skip_mask; 678 __s32 default_value; 679 __u32 flags; 680 __u32 reserved[2]; 681 __u8 is_volatile; 682}; 683 684/* Macro for making hardware specific calls */ 685#define s5p_mfc_hw_call(f, op, args...) \ 686 ((f && f->op) ? f->op(args) : -ENODEV) 687 688#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh) 689#define ctrl_to_ctx(__ctrl) \ 690 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler) 691 692void clear_work_bit(struct s5p_mfc_ctx *ctx); 693void set_work_bit(struct s5p_mfc_ctx *ctx); 694void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx); 695void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx); 696 697#define HAS_PORTNUM(dev) (dev ? (dev->variant ? \ 698 (dev->variant->port_num ? 1 : 0) : 0) : 0) 699#define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0) 700#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0) 701#define IS_MFCV7(dev) (dev->variant->version >= 0x70 ? 1 : 0) 702 703#endif /* S5P_MFC_COMMON_H_ */ 704