1/* 2 * Copyright (c) 2000-2008 LSI Corporation. 3 * 4 * 5 * Name: mpi_ioc.h 6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 7 * Creation Date: August 11, 2000 8 * 9 * mpi_ioc.h Version: 01.05.16 10 * 11 * Version History 12 * --------------- 13 * 14 * Date Version Description 15 * -------- -------- ------------------------------------------------------ 16 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 17 * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure. 18 * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY. 19 * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure. 20 * Added _MSG_EVENT_ACK_REPLY structure. 21 * Added _MSG_FW_DOWNLOAD_REPLY structure. 22 * Added _MSG_TOOLBOX_REPLY structure. 23 * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure. 24 * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI, 25 * _LINK_STATUS, _LOOP_STATE and _LOGOUT. 26 * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in 27 * _MSG_EVENT_ACK_REPLY structure to match specification. 28 * 11-02-00 01.01.01 Original release for post 1.0 work. 29 * Added a value for Manufacturer to WhoInit. 30 * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and 31 * removed toolbox message. 32 * 01-09-01 01.01.03 Added event enabled and disabled defines. 33 * Added structures for FwHeader and DataHeader. 34 * Added ImageType to FwUpload reply. 35 * 02-20-01 01.01.04 Started using MPI_POINTER. 36 * 02-27-01 01.01.05 Added event for RAID status change and its event data. 37 * Added IocNumber field to MSG_IOC_FACTS_REPLY. 38 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER. 39 * Added structure offset comments. 40 * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE. 41 * 08-08-01 01.02.01 Original release for v1.2 work. 42 * New format for FWVersion and ProductId in 43 * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER. 44 * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and 45 * related structure and defines. 46 * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED. 47 * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE. 48 * Replaced a reserved field in MSG_IOC_FACTS_REPLY with 49 * IOCExceptions and changed DataImageSize to reserved. 50 * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and 51 * MPI_FW_UPLOAD_ITYPE_NVDATA. 52 * 09-28-01 01.02.03 Modified Event Data for Integrated RAID. 53 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field. 54 * 03-14-02 01.02.05 Added HeaderVersion field to MSG_IOC_FACTS_REPLY. 55 * 05-31-02 01.02.06 Added define for 56 * MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID. 57 * Added AliasIndex to EVENT_DATA_LOGOUT structure. 58 * 04-01-03 01.02.07 Added defines for MPI_FW_HEADER_SIGNATURE_. 59 * 06-26-03 01.02.08 Added new values to the product family defines. 60 * 04-29-04 01.02.09 Added IOCCapabilities field to MSG_IOC_FACTS_REPLY and 61 * added related defines. 62 * 05-11-04 01.03.01 Original release for MPI v1.3. 63 * 08-19-04 01.05.01 Added four new fields to MSG_IOC_INIT. 64 * Added three new fields to MSG_IOC_FACTS_REPLY. 65 * Defined four new bits for the IOCCapabilities field of 66 * the IOCFacts reply. 67 * Added two new PortTypes for the PortFacts reply. 68 * Added six new events along with their EventData 69 * structures. 70 * Added a new MsgFlag to the FwDownload request to 71 * indicate last segment. 72 * Defined a new image type of boot loader. 73 * Added FW family codes for SAS product families. 74 * 10-05-04 01.05.02 Added ReplyFifoHostSignalingAddr field to 75 * MSG_IOC_FACTS_REPLY. 76 * 12-07-04 01.05.03 Added more defines for SAS Discovery Error event. 77 * 12-09-04 01.05.04 Added Unsupported device to SAS Device event. 78 * 01-15-05 01.05.05 Added event data for SAS SES Event. 79 * 02-09-05 01.05.06 Added MPI_FW_UPLOAD_ITYPE_FW_BACKUP define. 80 * 02-22-05 01.05.07 Added Host Page Buffer Persistent flag to IOC Facts 81 * Reply and IOC Init Request. 82 * 03-11-05 01.05.08 Added family code for 1068E family. 83 * Removed IOCFacts Reply EEDP Capability bit. 84 * 06-24-05 01.05.09 Added 5 new IOCFacts Reply IOCCapabilities bits. 85 * Added Max SATA Targets to SAS Discovery Error event. 86 * 08-30-05 01.05.10 Added 4 new events and their event data structures. 87 * Added new ReasonCode value for SAS Device Status Change 88 * event. 89 * Added new family code for FC949E. 90 * 03-27-06 01.05.11 Added MPI_IOCFACTS_CAPABILITY_TLR. 91 * Added additional Reason Codes and more event data fields 92 * to EVENT_DATA_SAS_DEVICE_STATUS_CHANGE. 93 * Added EVENT_DATA_SAS_BROADCAST_PRIMITIVE structure and 94 * new event. 95 * Added MPI_EVENT_SAS_SMP_ERROR and event data structure. 96 * Added MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE and event 97 * data structure. 98 * Added MPI_EVENT_SAS_INIT_TABLE_OVERFLOW and event 99 * data structure. 100 * Added MPI_EXT_IMAGE_TYPE_INITIALIZATION. 101 * 10-11-06 01.05.12 Added MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED. 102 * Added MaxInitiators field to PortFacts reply. 103 * Added SAS Device Status Change ReasonCode for 104 * asynchronous notificaiton. 105 * Added MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE and event 106 * data structure. 107 * Added new ImageType values for FWDownload and FWUpload 108 * requests. 109 * 02-28-07 01.05.13 Added MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT for SAS 110 * Broadcast Event Data (replacing _RESERVED2). 111 * For Discovery Error Event Data DiscoveryStatus field, 112 * replaced _MULTPL_PATHS with _UNSUPPORTED_DEVICE and 113 * added _MULTI_PORT_DOMAIN. 114 * 05-24-07 01.05.14 Added Common Boot Block type to FWDownload Request. 115 * Added Common Boot Block type to FWUpload Request. 116 * 08-07-07 01.05.15 Added MPI_EVENT_SAS_INIT_RC_REMOVED define. 117 * Added MPI_EVENT_IR2_RC_DUAL_PORT_ADDED and 118 * MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED for IR2 event data. 119 * Added SASAddress field to SAS Initiator Device Table 120 * Overflow event data structure. 121 * 03-28-08 01.05.16 Added two new ReasonCode values to SAS Device Status 122 * Change Event data to indicate completion of internally 123 * generated task management. 124 * Added MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE define. 125 * Added MPI_EVENT_SAS_INIT_RC_INACCESSIBLE define. 126 * -------------------------------------------------------------------------- 127 */ 128 129#ifndef MPI_IOC_H 130#define MPI_IOC_H 131 132 133/***************************************************************************** 134* 135* I O C M e s s a g e s 136* 137*****************************************************************************/ 138 139/****************************************************************************/ 140/* IOCInit message */ 141/****************************************************************************/ 142 143typedef struct _MSG_IOC_INIT 144{ 145 U8 WhoInit; /* 00h */ 146 U8 Reserved; /* 01h */ 147 U8 ChainOffset; /* 02h */ 148 U8 Function; /* 03h */ 149 U8 Flags; /* 04h */ 150 U8 MaxDevices; /* 05h */ 151 U8 MaxBuses; /* 06h */ 152 U8 MsgFlags; /* 07h */ 153 U32 MsgContext; /* 08h */ 154 U16 ReplyFrameSize; /* 0Ch */ 155 U8 Reserved1[2]; /* 0Eh */ 156 U32 HostMfaHighAddr; /* 10h */ 157 U32 SenseBufferHighAddr; /* 14h */ 158 U32 ReplyFifoHostSignalingAddr; /* 18h */ 159 SGE_SIMPLE_UNION HostPageBufferSGE; /* 1Ch */ 160 U16 MsgVersion; /* 28h */ 161 U16 HeaderVersion; /* 2Ah */ 162} MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT, 163 IOCInit_t, MPI_POINTER pIOCInit_t; 164 165/* WhoInit values */ 166#define MPI_WHOINIT_NO_ONE (0x00) 167#define MPI_WHOINIT_SYSTEM_BIOS (0x01) 168#define MPI_WHOINIT_ROM_BIOS (0x02) 169#define MPI_WHOINIT_PCI_PEER (0x03) 170#define MPI_WHOINIT_HOST_DRIVER (0x04) 171#define MPI_WHOINIT_MANUFACTURER (0x05) 172 173/* Flags values */ 174#define MPI_IOCINIT_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04) 175#define MPI_IOCINIT_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02) 176#define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01) 177 178/* MsgVersion */ 179#define MPI_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 180#define MPI_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 181#define MPI_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 182#define MPI_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 183 184/* HeaderVersion */ 185#define MPI_IOCINIT_HEADERVERSION_UNIT_MASK (0xFF00) 186#define MPI_IOCINIT_HEADERVERSION_UNIT_SHIFT (8) 187#define MPI_IOCINIT_HEADERVERSION_DEV_MASK (0x00FF) 188#define MPI_IOCINIT_HEADERVERSION_DEV_SHIFT (0) 189 190 191typedef struct _MSG_IOC_INIT_REPLY 192{ 193 U8 WhoInit; /* 00h */ 194 U8 Reserved; /* 01h */ 195 U8 MsgLength; /* 02h */ 196 U8 Function; /* 03h */ 197 U8 Flags; /* 04h */ 198 U8 MaxDevices; /* 05h */ 199 U8 MaxBuses; /* 06h */ 200 U8 MsgFlags; /* 07h */ 201 U32 MsgContext; /* 08h */ 202 U16 Reserved2; /* 0Ch */ 203 U16 IOCStatus; /* 0Eh */ 204 U32 IOCLogInfo; /* 10h */ 205} MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY, 206 IOCInitReply_t, MPI_POINTER pIOCInitReply_t; 207 208 209 210/****************************************************************************/ 211/* IOC Facts message */ 212/****************************************************************************/ 213 214typedef struct _MSG_IOC_FACTS 215{ 216 U8 Reserved[2]; /* 00h */ 217 U8 ChainOffset; /* 01h */ 218 U8 Function; /* 02h */ 219 U8 Reserved1[3]; /* 03h */ 220 U8 MsgFlags; /* 04h */ 221 U32 MsgContext; /* 08h */ 222} MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS, 223 IOCFacts_t, MPI_POINTER pIOCFacts_t; 224 225typedef struct _MPI_FW_VERSION_STRUCT 226{ 227 U8 Dev; /* 00h */ 228 U8 Unit; /* 01h */ 229 U8 Minor; /* 02h */ 230 U8 Major; /* 03h */ 231} MPI_FW_VERSION_STRUCT; 232 233typedef union _MPI_FW_VERSION 234{ 235 MPI_FW_VERSION_STRUCT Struct; 236 U32 Word; 237} MPI_FW_VERSION; 238 239/* IOC Facts Reply */ 240typedef struct _MSG_IOC_FACTS_REPLY 241{ 242 U16 MsgVersion; /* 00h */ 243 U8 MsgLength; /* 02h */ 244 U8 Function; /* 03h */ 245 U16 HeaderVersion; /* 04h */ 246 U8 IOCNumber; /* 06h */ 247 U8 MsgFlags; /* 07h */ 248 U32 MsgContext; /* 08h */ 249 U16 IOCExceptions; /* 0Ch */ 250 U16 IOCStatus; /* 0Eh */ 251 U32 IOCLogInfo; /* 10h */ 252 U8 MaxChainDepth; /* 14h */ 253 U8 WhoInit; /* 15h */ 254 U8 BlockSize; /* 16h */ 255 U8 Flags; /* 17h */ 256 U16 ReplyQueueDepth; /* 18h */ 257 U16 RequestFrameSize; /* 1Ah */ 258 U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */ 259 U16 ProductID; /* 1Eh */ 260 U32 CurrentHostMfaHighAddr; /* 20h */ 261 U16 GlobalCredits; /* 24h */ 262 U8 NumberOfPorts; /* 26h */ 263 U8 EventState; /* 27h */ 264 U32 CurrentSenseBufferHighAddr; /* 28h */ 265 U16 CurReplyFrameSize; /* 2Ch */ 266 U8 MaxDevices; /* 2Eh */ 267 U8 MaxBuses; /* 2Fh */ 268 U32 FWImageSize; /* 30h */ 269 U32 IOCCapabilities; /* 34h */ 270 MPI_FW_VERSION FWVersion; /* 38h */ 271 U16 HighPriorityQueueDepth; /* 3Ch */ 272 U16 Reserved2; /* 3Eh */ 273 SGE_SIMPLE_UNION HostPageBufferSGE; /* 40h */ 274 U32 ReplyFifoHostSignalingAddr; /* 4Ch */ 275} MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY, 276 IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t; 277 278#define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 279#define MPI_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 280#define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 281#define MPI_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 282 283#define MPI_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 284#define MPI_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 285#define MPI_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 286#define MPI_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 287 288#define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 289#define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 290#define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 291#define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL (0x0008) 292#define MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 293 294#define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01) 295#define MPI_IOCFACTS_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02) 296#define MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04) 297 298#define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00) 299#define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01) 300 301#define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q (0x00000001) 302#define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL (0x00000002) 303#define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING (0x00000004) 304#define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 305#define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 306#define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 307#define MPI_IOCFACTS_CAPABILITY_EEDP (0x00000040) 308#define MPI_IOCFACTS_CAPABILITY_BIDIRECTIONAL (0x00000080) 309#define MPI_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 310#define MPI_IOCFACTS_CAPABILITY_SCSIIO32 (0x00000200) 311#define MPI_IOCFACTS_CAPABILITY_NO_SCSIIO16 (0x00000400) 312#define MPI_IOCFACTS_CAPABILITY_TLR (0x00000800) 313 314 315/***************************************************************************** 316* 317* P o r t M e s s a g e s 318* 319*****************************************************************************/ 320 321/****************************************************************************/ 322/* Port Facts message and Reply */ 323/****************************************************************************/ 324 325typedef struct _MSG_PORT_FACTS 326{ 327 U8 Reserved[2]; /* 00h */ 328 U8 ChainOffset; /* 02h */ 329 U8 Function; /* 03h */ 330 U8 Reserved1[2]; /* 04h */ 331 U8 PortNumber; /* 06h */ 332 U8 MsgFlags; /* 07h */ 333 U32 MsgContext; /* 08h */ 334} MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS, 335 PortFacts_t, MPI_POINTER pPortFacts_t; 336 337typedef struct _MSG_PORT_FACTS_REPLY 338{ 339 U16 Reserved; /* 00h */ 340 U8 MsgLength; /* 02h */ 341 U8 Function; /* 03h */ 342 U16 Reserved1; /* 04h */ 343 U8 PortNumber; /* 06h */ 344 U8 MsgFlags; /* 07h */ 345 U32 MsgContext; /* 08h */ 346 U16 Reserved2; /* 0Ch */ 347 U16 IOCStatus; /* 0Eh */ 348 U32 IOCLogInfo; /* 10h */ 349 U8 Reserved3; /* 14h */ 350 U8 PortType; /* 15h */ 351 U16 MaxDevices; /* 16h */ 352 U16 PortSCSIID; /* 18h */ 353 U16 ProtocolFlags; /* 1Ah */ 354 U16 MaxPostedCmdBuffers; /* 1Ch */ 355 U16 MaxPersistentIDs; /* 1Eh */ 356 U16 MaxLanBuckets; /* 20h */ 357 U8 MaxInitiators; /* 22h */ 358 U8 Reserved4; /* 23h */ 359 U32 Reserved5; /* 24h */ 360} MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY, 361 PortFactsReply_t, MPI_POINTER pPortFactsReply_t; 362 363 364/* PortTypes values */ 365 366#define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00) 367#define MPI_PORTFACTS_PORTTYPE_SCSI (0x01) 368#define MPI_PORTFACTS_PORTTYPE_FC (0x10) 369#define MPI_PORTFACTS_PORTTYPE_ISCSI (0x20) 370#define MPI_PORTFACTS_PORTTYPE_SAS (0x30) 371 372/* ProtocolFlags values */ 373 374#define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01) 375#define MPI_PORTFACTS_PROTOCOL_LAN (0x02) 376#define MPI_PORTFACTS_PROTOCOL_TARGET (0x04) 377#define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08) 378 379 380/****************************************************************************/ 381/* Port Enable Message */ 382/****************************************************************************/ 383 384typedef struct _MSG_PORT_ENABLE 385{ 386 U8 Reserved[2]; /* 00h */ 387 U8 ChainOffset; /* 02h */ 388 U8 Function; /* 03h */ 389 U8 Reserved1[2]; /* 04h */ 390 U8 PortNumber; /* 06h */ 391 U8 MsgFlags; /* 07h */ 392 U32 MsgContext; /* 08h */ 393} MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE, 394 PortEnable_t, MPI_POINTER pPortEnable_t; 395 396typedef struct _MSG_PORT_ENABLE_REPLY 397{ 398 U8 Reserved[2]; /* 00h */ 399 U8 MsgLength; /* 02h */ 400 U8 Function; /* 03h */ 401 U8 Reserved1[2]; /* 04h */ 402 U8 PortNumber; /* 05h */ 403 U8 MsgFlags; /* 07h */ 404 U32 MsgContext; /* 08h */ 405 U16 Reserved2; /* 0Ch */ 406 U16 IOCStatus; /* 0Eh */ 407 U32 IOCLogInfo; /* 10h */ 408} MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY, 409 PortEnableReply_t, MPI_POINTER pPortEnableReply_t; 410 411 412/***************************************************************************** 413* 414* E v e n t M e s s a g e s 415* 416*****************************************************************************/ 417 418/****************************************************************************/ 419/* Event Notification messages */ 420/****************************************************************************/ 421 422typedef struct _MSG_EVENT_NOTIFY 423{ 424 U8 Switch; /* 00h */ 425 U8 Reserved; /* 01h */ 426 U8 ChainOffset; /* 02h */ 427 U8 Function; /* 03h */ 428 U8 Reserved1[3]; /* 04h */ 429 U8 MsgFlags; /* 07h */ 430 U32 MsgContext; /* 08h */ 431} MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY, 432 EventNotification_t, MPI_POINTER pEventNotification_t; 433 434/* Event Notification Reply */ 435 436typedef struct _MSG_EVENT_NOTIFY_REPLY 437{ 438 U16 EventDataLength; /* 00h */ 439 U8 MsgLength; /* 02h */ 440 U8 Function; /* 03h */ 441 U8 Reserved1[2]; /* 04h */ 442 U8 AckRequired; /* 06h */ 443 U8 MsgFlags; /* 07h */ 444 U32 MsgContext; /* 08h */ 445 U8 Reserved2[2]; /* 0Ch */ 446 U16 IOCStatus; /* 0Eh */ 447 U32 IOCLogInfo; /* 10h */ 448 U32 Event; /* 14h */ 449 U32 EventContext; /* 18h */ 450 U32 Data[1]; /* 1Ch */ 451} MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY, 452 EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t; 453 454/* Event Acknowledge */ 455 456typedef struct _MSG_EVENT_ACK 457{ 458 U8 Reserved[2]; /* 00h */ 459 U8 ChainOffset; /* 02h */ 460 U8 Function; /* 03h */ 461 U8 Reserved1[3]; /* 04h */ 462 U8 MsgFlags; /* 07h */ 463 U32 MsgContext; /* 08h */ 464 U32 Event; /* 0Ch */ 465 U32 EventContext; /* 10h */ 466} MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK, 467 EventAck_t, MPI_POINTER pEventAck_t; 468 469typedef struct _MSG_EVENT_ACK_REPLY 470{ 471 U8 Reserved[2]; /* 00h */ 472 U8 MsgLength; /* 02h */ 473 U8 Function; /* 03h */ 474 U8 Reserved1[3]; /* 04h */ 475 U8 MsgFlags; /* 07h */ 476 U32 MsgContext; /* 08h */ 477 U16 Reserved2; /* 0Ch */ 478 U16 IOCStatus; /* 0Eh */ 479 U32 IOCLogInfo; /* 10h */ 480} MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY, 481 EventAckReply_t, MPI_POINTER pEventAckReply_t; 482 483/* Switch */ 484 485#define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00) 486#define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01) 487 488/* Event */ 489 490#define MPI_EVENT_NONE (0x00000000) 491#define MPI_EVENT_LOG_DATA (0x00000001) 492#define MPI_EVENT_STATE_CHANGE (0x00000002) 493#define MPI_EVENT_UNIT_ATTENTION (0x00000003) 494#define MPI_EVENT_IOC_BUS_RESET (0x00000004) 495#define MPI_EVENT_EXT_BUS_RESET (0x00000005) 496#define MPI_EVENT_RESCAN (0x00000006) 497#define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007) 498#define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008) 499#define MPI_EVENT_LOGOUT (0x00000009) 500#define MPI_EVENT_EVENT_CHANGE (0x0000000A) 501#define MPI_EVENT_INTEGRATED_RAID (0x0000000B) 502#define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C) 503#define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D) 504#define MPI_EVENT_QUEUE_FULL (0x0000000E) 505#define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0000000F) 506#define MPI_EVENT_SAS_SES (0x00000010) 507#define MPI_EVENT_PERSISTENT_TABLE_FULL (0x00000011) 508#define MPI_EVENT_SAS_PHY_LINK_STATUS (0x00000012) 509#define MPI_EVENT_SAS_DISCOVERY_ERROR (0x00000013) 510#define MPI_EVENT_IR_RESYNC_UPDATE (0x00000014) 511#define MPI_EVENT_IR2 (0x00000015) 512#define MPI_EVENT_SAS_DISCOVERY (0x00000016) 513#define MPI_EVENT_SAS_BROADCAST_PRIMITIVE (0x00000017) 514#define MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x00000018) 515#define MPI_EVENT_SAS_INIT_TABLE_OVERFLOW (0x00000019) 516#define MPI_EVENT_SAS_SMP_ERROR (0x0000001A) 517#define MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE (0x0000001B) 518#define MPI_EVENT_LOG_ENTRY_ADDED (0x00000021) 519 520/* AckRequired field values */ 521 522#define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 523#define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 524 525/* EventChange Event data */ 526 527typedef struct _EVENT_DATA_EVENT_CHANGE 528{ 529 U8 EventState; /* 00h */ 530 U8 Reserved; /* 01h */ 531 U16 Reserved1; /* 02h */ 532} EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE, 533 EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t; 534 535/* LogEntryAdded Event data */ 536 537/* this structure matches MPI_LOG_0_ENTRY in mpi_cnfg.h */ 538#define MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH (0x1C) 539typedef struct _EVENT_DATA_LOG_ENTRY 540{ 541 U32 TimeStamp; /* 00h */ 542 U32 Reserved1; /* 04h */ 543 U16 LogSequence; /* 08h */ 544 U16 LogEntryQualifier; /* 0Ah */ 545 U8 LogData[MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH]; /* 0Ch */ 546} EVENT_DATA_LOG_ENTRY, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY, 547 MpiEventDataLogEntry_t, MPI_POINTER pMpiEventDataLogEntry_t; 548 549typedef struct _EVENT_DATA_LOG_ENTRY_ADDED 550{ 551 U16 LogSequence; /* 00h */ 552 U16 Reserved1; /* 02h */ 553 U32 Reserved2; /* 04h */ 554 EVENT_DATA_LOG_ENTRY LogEntry; /* 08h */ 555} EVENT_DATA_LOG_ENTRY_ADDED, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY_ADDED, 556 MpiEventDataLogEntryAdded_t, MPI_POINTER pMpiEventDataLogEntryAdded_t; 557 558/* SCSI Event data for Port, Bus and Device forms */ 559 560typedef struct _EVENT_DATA_SCSI 561{ 562 U8 TargetID; /* 00h */ 563 U8 BusPort; /* 01h */ 564 U16 Reserved; /* 02h */ 565} EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI, 566 EventDataScsi_t, MPI_POINTER pEventDataScsi_t; 567 568/* SCSI Device Status Change Event data */ 569 570typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE 571{ 572 U8 TargetID; /* 00h */ 573 U8 Bus; /* 01h */ 574 U8 ReasonCode; /* 02h */ 575 U8 LUN; /* 03h */ 576 U8 ASC; /* 04h */ 577 U8 ASCQ; /* 05h */ 578 U16 Reserved; /* 06h */ 579} EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 580 MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 581 MpiEventDataScsiDeviceStatusChange_t, 582 MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t; 583 584/* MPI SCSI Device Status Change Event data ReasonCode values */ 585#define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03) 586#define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04) 587#define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05) 588 589/* SAS Device Status Change Event data */ 590 591typedef struct _EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 592{ 593 U8 TargetID; /* 00h */ 594 U8 Bus; /* 01h */ 595 U8 ReasonCode; /* 02h */ 596 U8 Reserved; /* 03h */ 597 U8 ASC; /* 04h */ 598 U8 ASCQ; /* 05h */ 599 U16 DevHandle; /* 06h */ 600 U32 DeviceInfo; /* 08h */ 601 U16 ParentDevHandle; /* 0Ch */ 602 U8 PhyNum; /* 0Eh */ 603 U8 Reserved1; /* 0Fh */ 604 U64 SASAddress; /* 10h */ 605 U8 LUN[8]; /* 18h */ 606 U16 TaskTag; /* 20h */ 607 U16 Reserved2; /* 22h */ 608} EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 609 MPI_POINTER PTR_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 610 MpiEventDataSasDeviceStatusChange_t, 611 MPI_POINTER pMpiEventDataSasDeviceStatusChange_t; 612 613/* MPI SAS Device Status Change Event data ReasonCode values */ 614#define MPI_EVENT_SAS_DEV_STAT_RC_ADDED (0x03) 615#define MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING (0x04) 616#define MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 617#define MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED (0x06) 618#define MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 619#define MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 620#define MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 621#define MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 622#define MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 623#define MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 624#define MPI_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 625#define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_INTERNAL_DEV_RESET (0x0E) 626#define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_TASK_ABORT_INTERNAL (0x0F) 627 628 629/* SCSI Event data for Queue Full event */ 630 631typedef struct _EVENT_DATA_QUEUE_FULL 632{ 633 U8 TargetID; /* 00h */ 634 U8 Bus; /* 01h */ 635 U16 CurrentDepth; /* 02h */ 636} EVENT_DATA_QUEUE_FULL, MPI_POINTER PTR_EVENT_DATA_QUEUE_FULL, 637 EventDataQueueFull_t, MPI_POINTER pEventDataQueueFull_t; 638 639/* MPI Integrated RAID Event data */ 640 641typedef struct _EVENT_DATA_RAID 642{ 643 U8 VolumeID; /* 00h */ 644 U8 VolumeBus; /* 01h */ 645 U8 ReasonCode; /* 02h */ 646 U8 PhysDiskNum; /* 03h */ 647 U8 ASC; /* 04h */ 648 U8 ASCQ; /* 05h */ 649 U16 Reserved; /* 06h */ 650 U32 SettingsStatus; /* 08h */ 651} EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID, 652 MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t; 653 654/* MPI Integrated RAID Event data ReasonCode values */ 655#define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00) 656#define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01) 657#define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02) 658#define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03) 659#define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04) 660#define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05) 661#define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06) 662#define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07) 663#define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08) 664#define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09) 665#define MPI_EVENT_RAID_RC_SMART_DATA (0x0A) 666#define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B) 667 668 669/* MPI Integrated RAID Resync Update Event data */ 670 671typedef struct _MPI_EVENT_DATA_IR_RESYNC_UPDATE 672{ 673 U8 VolumeID; /* 00h */ 674 U8 VolumeBus; /* 01h */ 675 U8 ResyncComplete; /* 02h */ 676 U8 Reserved1; /* 03h */ 677 U32 Reserved2; /* 04h */ 678} MPI_EVENT_DATA_IR_RESYNC_UPDATE, 679 MPI_POINTER PTR_MPI_EVENT_DATA_IR_RESYNC_UPDATE, 680 MpiEventDataIrResyncUpdate_t, MPI_POINTER pMpiEventDataIrResyncUpdate_t; 681 682/* MPI IR2 Event data */ 683 684/* MPI_LD_STATE or MPI_PD_STATE */ 685typedef struct _IR2_STATE_CHANGED 686{ 687 U16 PreviousState; /* 00h */ 688 U16 NewState; /* 02h */ 689} IR2_STATE_CHANGED, MPI_POINTER PTR_IR2_STATE_CHANGED; 690 691typedef struct _IR2_PD_INFO 692{ 693 U16 DeviceHandle; /* 00h */ 694 U8 TruncEnclosureHandle; /* 02h */ 695 U8 TruncatedSlot; /* 03h */ 696} IR2_PD_INFO, MPI_POINTER PTR_IR2_PD_INFO; 697 698typedef union _MPI_IR2_RC_EVENT_DATA 699{ 700 IR2_STATE_CHANGED StateChanged; 701 U32 Lba; 702 IR2_PD_INFO PdInfo; 703} MPI_IR2_RC_EVENT_DATA, MPI_POINTER PTR_MPI_IR2_RC_EVENT_DATA; 704 705typedef struct _MPI_EVENT_DATA_IR2 706{ 707 U8 TargetID; /* 00h */ 708 U8 Bus; /* 01h */ 709 U8 ReasonCode; /* 02h */ 710 U8 PhysDiskNum; /* 03h */ 711 MPI_IR2_RC_EVENT_DATA IR2EventData; /* 04h */ 712} MPI_EVENT_DATA_IR2, MPI_POINTER PTR_MPI_EVENT_DATA_IR2, 713 MpiEventDataIR2_t, MPI_POINTER pMpiEventDataIR2_t; 714 715/* MPI IR2 Event data ReasonCode values */ 716#define MPI_EVENT_IR2_RC_LD_STATE_CHANGED (0x01) 717#define MPI_EVENT_IR2_RC_PD_STATE_CHANGED (0x02) 718#define MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL (0x03) 719#define MPI_EVENT_IR2_RC_PD_INSERTED (0x04) 720#define MPI_EVENT_IR2_RC_PD_REMOVED (0x05) 721#define MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED (0x06) 722#define MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR (0x07) 723#define MPI_EVENT_IR2_RC_DUAL_PORT_ADDED (0x08) 724#define MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED (0x09) 725 726/* defines for logical disk states */ 727#define MPI_LD_STATE_OPTIMAL (0x00) 728#define MPI_LD_STATE_DEGRADED (0x01) 729#define MPI_LD_STATE_FAILED (0x02) 730#define MPI_LD_STATE_MISSING (0x03) 731#define MPI_LD_STATE_OFFLINE (0x04) 732 733/* defines for physical disk states */ 734#define MPI_PD_STATE_ONLINE (0x00) 735#define MPI_PD_STATE_MISSING (0x01) 736#define MPI_PD_STATE_NOT_COMPATIBLE (0x02) 737#define MPI_PD_STATE_FAILED (0x03) 738#define MPI_PD_STATE_INITIALIZING (0x04) 739#define MPI_PD_STATE_OFFLINE_AT_HOST_REQUEST (0x05) 740#define MPI_PD_STATE_FAILED_AT_HOST_REQUEST (0x06) 741#define MPI_PD_STATE_OFFLINE_FOR_ANOTHER_REASON (0xFF) 742 743/* MPI Link Status Change Event data */ 744 745typedef struct _EVENT_DATA_LINK_STATUS 746{ 747 U8 State; /* 00h */ 748 U8 Reserved; /* 01h */ 749 U16 Reserved1; /* 02h */ 750 U8 Reserved2; /* 04h */ 751 U8 Port; /* 05h */ 752 U16 Reserved3; /* 06h */ 753} EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS, 754 EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t; 755 756#define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000) 757#define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001) 758 759/* MPI Loop State Change Event data */ 760 761typedef struct _EVENT_DATA_LOOP_STATE 762{ 763 U8 Character4; /* 00h */ 764 U8 Character3; /* 01h */ 765 U8 Type; /* 02h */ 766 U8 Reserved; /* 03h */ 767 U8 Reserved1; /* 04h */ 768 U8 Port; /* 05h */ 769 U16 Reserved2; /* 06h */ 770} EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE, 771 EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t; 772 773#define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001) 774#define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002) 775#define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003) 776 777/* MPI LOGOUT Event data */ 778 779typedef struct _EVENT_DATA_LOGOUT 780{ 781 U32 NPortID; /* 00h */ 782 U8 AliasIndex; /* 04h */ 783 U8 Port; /* 05h */ 784 U16 Reserved1; /* 06h */ 785} EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT, 786 EventDataLogout_t, MPI_POINTER pEventDataLogout_t; 787 788#define MPI_EVENT_LOGOUT_ALL_ALIASES (0xFF) 789 790/* SAS SES Event data */ 791 792typedef struct _EVENT_DATA_SAS_SES 793{ 794 U8 PhyNum; /* 00h */ 795 U8 Port; /* 01h */ 796 U8 PortWidth; /* 02h */ 797 U8 Reserved1; /* 04h */ 798} EVENT_DATA_SAS_SES, MPI_POINTER PTR_EVENT_DATA_SAS_SES, 799 MpiEventDataSasSes_t, MPI_POINTER pMpiEventDataSasSes_t; 800 801/* SAS Broadcast Primitive Event data */ 802 803typedef struct _EVENT_DATA_SAS_BROADCAST_PRIMITIVE 804{ 805 U8 PhyNum; /* 00h */ 806 U8 Port; /* 01h */ 807 U8 PortWidth; /* 02h */ 808 U8 Primitive; /* 04h */ 809} EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 810 MPI_POINTER PTR_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 811 MpiEventDataSasBroadcastPrimitive_t, 812 MPI_POINTER pMpiEventDataSasBroadcastPrimitive_t; 813 814#define MPI_EVENT_PRIMITIVE_CHANGE (0x01) 815#define MPI_EVENT_PRIMITIVE_EXPANDER (0x03) 816#define MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 817#define MPI_EVENT_PRIMITIVE_RESERVED3 (0x05) 818#define MPI_EVENT_PRIMITIVE_RESERVED4 (0x06) 819#define MPI_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 820#define MPI_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 821 822/* SAS Phy Link Status Event data */ 823 824typedef struct _EVENT_DATA_SAS_PHY_LINK_STATUS 825{ 826 U8 PhyNum; /* 00h */ 827 U8 LinkRates; /* 01h */ 828 U16 DevHandle; /* 02h */ 829 U64 SASAddress; /* 04h */ 830} EVENT_DATA_SAS_PHY_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_SAS_PHY_LINK_STATUS, 831 MpiEventDataSasPhyLinkStatus_t, MPI_POINTER pMpiEventDataSasPhyLinkStatus_t; 832 833/* defines for the LinkRates field of the SAS PHY Link Status event */ 834#define MPI_EVENT_SAS_PLS_LR_CURRENT_MASK (0xF0) 835#define MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT (4) 836#define MPI_EVENT_SAS_PLS_LR_PREVIOUS_MASK (0x0F) 837#define MPI_EVENT_SAS_PLS_LR_PREVIOUS_SHIFT (0) 838#define MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN (0x00) 839#define MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED (0x01) 840#define MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION (0x02) 841#define MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE (0x03) 842#define MPI_EVENT_SAS_PLS_LR_RATE_1_5 (0x08) 843#define MPI_EVENT_SAS_PLS_LR_RATE_3_0 (0x09) 844#define MPI_EVENT_SAS_PLS_LR_RATE_6_0 (0x0A) 845 846/* SAS Discovery Event data */ 847 848typedef struct _EVENT_DATA_SAS_DISCOVERY 849{ 850 U32 DiscoveryStatus; /* 00h */ 851 U32 Reserved1; /* 04h */ 852} EVENT_DATA_SAS_DISCOVERY, MPI_POINTER PTR_EVENT_DATA_SAS_DISCOVERY, 853 EventDataSasDiscovery_t, MPI_POINTER pEventDataSasDiscovery_t; 854 855#define MPI_EVENT_SAS_DSCVRY_COMPLETE (0x00000000) 856#define MPI_EVENT_SAS_DSCVRY_IN_PROGRESS (0x00000001) 857#define MPI_EVENT_SAS_DSCVRY_PHY_BITS_MASK (0xFFFF0000) 858#define MPI_EVENT_SAS_DSCVRY_PHY_BITS_SHIFT (16) 859 860/* SAS Discovery Error Event data */ 861 862typedef struct _EVENT_DATA_DISCOVERY_ERROR 863{ 864 U32 DiscoveryStatus; /* 00h */ 865 U8 Port; /* 04h */ 866 U8 Reserved1; /* 05h */ 867 U16 Reserved2; /* 06h */ 868} EVENT_DATA_DISCOVERY_ERROR, MPI_POINTER PTR_EVENT_DATA_DISCOVERY_ERROR, 869 EventDataDiscoveryError_t, MPI_POINTER pEventDataDiscoveryError_t; 870 871#define MPI_EVENT_DSCVRY_ERR_DS_LOOP_DETECTED (0x00000001) 872#define MPI_EVENT_DSCVRY_ERR_DS_UNADDRESSABLE_DEVICE (0x00000002) 873#define MPI_EVENT_DSCVRY_ERR_DS_MULTIPLE_PORTS (0x00000004) 874#define MPI_EVENT_DSCVRY_ERR_DS_EXPANDER_ERR (0x00000008) 875#define MPI_EVENT_DSCVRY_ERR_DS_SMP_TIMEOUT (0x00000010) 876#define MPI_EVENT_DSCVRY_ERR_DS_OUT_ROUTE_ENTRIES (0x00000020) 877#define MPI_EVENT_DSCVRY_ERR_DS_INDEX_NOT_EXIST (0x00000040) 878#define MPI_EVENT_DSCVRY_ERR_DS_SMP_FUNCTION_FAILED (0x00000080) 879#define MPI_EVENT_DSCVRY_ERR_DS_SMP_CRC_ERROR (0x00000100) 880#define MPI_EVENT_DSCVRY_ERR_DS_MULTPL_SUBTRACTIVE (0x00000200) 881#define MPI_EVENT_DSCVRY_ERR_DS_TABLE_TO_TABLE (0x00000400) 882#define MPI_EVENT_DSCVRY_ERR_DS_UNSUPPORTED_DEVICE (0x00000800) 883#define MPI_EVENT_DSCVRY_ERR_DS_MAX_SATA_TARGETS (0x00001000) 884#define MPI_EVENT_DSCVRY_ERR_DS_MULTI_PORT_DOMAIN (0x00002000) 885#define MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE (0x00004000) 886 887/* SAS SMP Error Event data */ 888 889typedef struct _EVENT_DATA_SAS_SMP_ERROR 890{ 891 U8 Status; /* 00h */ 892 U8 Port; /* 01h */ 893 U8 SMPFunctionResult; /* 02h */ 894 U8 Reserved1; /* 03h */ 895 U64 SASAddress; /* 04h */ 896} EVENT_DATA_SAS_SMP_ERROR, MPI_POINTER PTR_EVENT_DATA_SAS_SMP_ERROR, 897 MpiEventDataSasSmpError_t, MPI_POINTER pMpiEventDataSasSmpError_t; 898 899/* defines for the Status field of the SAS SMP Error event */ 900#define MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID (0x00) 901#define MPI_EVENT_SAS_SMP_CRC_ERROR (0x01) 902#define MPI_EVENT_SAS_SMP_TIMEOUT (0x02) 903#define MPI_EVENT_SAS_SMP_NO_DESTINATION (0x03) 904#define MPI_EVENT_SAS_SMP_BAD_DESTINATION (0x04) 905 906/* SAS Initiator Device Status Change Event data */ 907 908typedef struct _EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 909{ 910 U8 ReasonCode; /* 00h */ 911 U8 Port; /* 01h */ 912 U16 DevHandle; /* 02h */ 913 U64 SASAddress; /* 04h */ 914} EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 915 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 916 MpiEventDataSasInitDevStatusChange_t, 917 MPI_POINTER pMpiEventDataSasInitDevStatusChange_t; 918 919/* defines for the ReasonCode field of the SAS Initiator Device Status Change event */ 920#define MPI_EVENT_SAS_INIT_RC_ADDED (0x01) 921#define MPI_EVENT_SAS_INIT_RC_REMOVED (0x02) 922#define MPI_EVENT_SAS_INIT_RC_INACCESSIBLE (0x03) 923 924/* SAS Initiator Device Table Overflow Event data */ 925 926typedef struct _EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 927{ 928 U8 MaxInit; /* 00h */ 929 U8 CurrentInit; /* 01h */ 930 U16 Reserved1; /* 02h */ 931 U64 SASAddress; /* 04h */ 932} EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 933 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 934 MpiEventDataSasInitTableOverflow_t, 935 MPI_POINTER pMpiEventDataSasInitTableOverflow_t; 936 937/* SAS Expander Status Change Event data */ 938 939typedef struct _EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE 940{ 941 U8 ReasonCode; /* 00h */ 942 U8 Reserved1; /* 01h */ 943 U16 Reserved2; /* 02h */ 944 U8 PhysicalPort; /* 04h */ 945 U8 Reserved3; /* 05h */ 946 U16 EnclosureHandle; /* 06h */ 947 U64 SASAddress; /* 08h */ 948 U32 DiscoveryStatus; /* 10h */ 949 U16 DevHandle; /* 14h */ 950 U16 ParentDevHandle; /* 16h */ 951 U16 ExpanderChangeCount; /* 18h */ 952 U16 ExpanderRouteIndexes; /* 1Ah */ 953 U8 NumPhys; /* 1Ch */ 954 U8 SASLevel; /* 1Dh */ 955 U8 Flags; /* 1Eh */ 956 U8 Reserved4; /* 1Fh */ 957} EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE, 958 MPI_POINTER PTR_EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE, 959 MpiEventDataSasExpanderStatusChange_t, 960 MPI_POINTER pMpiEventDataSasExpanderStatusChange_t; 961 962/* values for ReasonCode field of SAS Expander Status Change Event data */ 963#define MPI_EVENT_SAS_EXP_RC_ADDED (0x00) 964#define MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING (0x01) 965 966/* values for DiscoveryStatus field of SAS Expander Status Change Event data */ 967#define MPI_EVENT_SAS_EXP_DS_LOOP_DETECTED (0x00000001) 968#define MPI_EVENT_SAS_EXP_DS_UNADDRESSABLE_DEVICE (0x00000002) 969#define MPI_EVENT_SAS_EXP_DS_MULTIPLE_PORTS (0x00000004) 970#define MPI_EVENT_SAS_EXP_DS_EXPANDER_ERR (0x00000008) 971#define MPI_EVENT_SAS_EXP_DS_SMP_TIMEOUT (0x00000010) 972#define MPI_EVENT_SAS_EXP_DS_OUT_ROUTE_ENTRIES (0x00000020) 973#define MPI_EVENT_SAS_EXP_DS_INDEX_NOT_EXIST (0x00000040) 974#define MPI_EVENT_SAS_EXP_DS_SMP_FUNCTION_FAILED (0x00000080) 975#define MPI_EVENT_SAS_EXP_DS_SMP_CRC_ERROR (0x00000100) 976#define MPI_EVENT_SAS_EXP_DS_SUBTRACTIVE_LINK (0x00000200) 977#define MPI_EVENT_SAS_EXP_DS_TABLE_LINK (0x00000400) 978#define MPI_EVENT_SAS_EXP_DS_UNSUPPORTED_DEVICE (0x00000800) 979 980/* values for Flags field of SAS Expander Status Change Event data */ 981#define MPI_EVENT_SAS_EXP_FLAGS_ROUTE_TABLE_CONFIG (0x02) 982#define MPI_EVENT_SAS_EXP_FLAGS_CONFIG_IN_PROGRESS (0x01) 983 984 985 986/***************************************************************************** 987* 988* F i r m w a r e L o a d M e s s a g e s 989* 990*****************************************************************************/ 991 992/****************************************************************************/ 993/* Firmware Download message and associated structures */ 994/****************************************************************************/ 995 996typedef struct _MSG_FW_DOWNLOAD 997{ 998 U8 ImageType; /* 00h */ 999 U8 Reserved; /* 01h */ 1000 U8 ChainOffset; /* 02h */ 1001 U8 Function; /* 03h */ 1002 U8 Reserved1[3]; /* 04h */ 1003 U8 MsgFlags; /* 07h */ 1004 U32 MsgContext; /* 08h */ 1005 SGE_MPI_UNION SGL; /* 0Ch */ 1006} MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD, 1007 FWDownload_t, MPI_POINTER pFWDownload_t; 1008 1009#define MPI_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1010 1011#define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00) 1012#define MPI_FW_DOWNLOAD_ITYPE_FW (0x01) 1013#define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1014#define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03) 1015#define MPI_FW_DOWNLOAD_ITYPE_BOOTLOADER (0x04) 1016#define MPI_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1017#define MPI_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1018#define MPI_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1019#define MPI_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1020#define MPI_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1021 1022 1023typedef struct _FWDownloadTCSGE 1024{ 1025 U8 Reserved; /* 00h */ 1026 U8 ContextSize; /* 01h */ 1027 U8 DetailsLength; /* 02h */ 1028 U8 Flags; /* 03h */ 1029 U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */ 1030 U32 ImageOffset; /* 08h */ 1031 U32 ImageSize; /* 0Ch */ 1032} FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE, 1033 FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t; 1034 1035/* Firmware Download reply */ 1036typedef struct _MSG_FW_DOWNLOAD_REPLY 1037{ 1038 U8 ImageType; /* 00h */ 1039 U8 Reserved; /* 01h */ 1040 U8 MsgLength; /* 02h */ 1041 U8 Function; /* 03h */ 1042 U8 Reserved1[3]; /* 04h */ 1043 U8 MsgFlags; /* 07h */ 1044 U32 MsgContext; /* 08h */ 1045 U16 Reserved2; /* 0Ch */ 1046 U16 IOCStatus; /* 0Eh */ 1047 U32 IOCLogInfo; /* 10h */ 1048} MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY, 1049 FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t; 1050 1051 1052/****************************************************************************/ 1053/* Firmware Upload message and associated structures */ 1054/****************************************************************************/ 1055 1056typedef struct _MSG_FW_UPLOAD 1057{ 1058 U8 ImageType; /* 00h */ 1059 U8 Reserved; /* 01h */ 1060 U8 ChainOffset; /* 02h */ 1061 U8 Function; /* 03h */ 1062 U8 Reserved1[3]; /* 04h */ 1063 U8 MsgFlags; /* 07h */ 1064 U32 MsgContext; /* 08h */ 1065 SGE_MPI_UNION SGL; /* 0Ch */ 1066} MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD, 1067 FWUpload_t, MPI_POINTER pFWUpload_t; 1068 1069#define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00) 1070#define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1071#define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1072#define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03) 1073#define MPI_FW_UPLOAD_ITYPE_BOOTLOADER (0x04) 1074#define MPI_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1075#define MPI_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1076#define MPI_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1077#define MPI_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1078#define MPI_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1079#define MPI_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1080#define MPI_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1081 1082typedef struct _FWUploadTCSGE 1083{ 1084 U8 Reserved; /* 00h */ 1085 U8 ContextSize; /* 01h */ 1086 U8 DetailsLength; /* 02h */ 1087 U8 Flags; /* 03h */ 1088 U32 Reserved1; /* 04h */ 1089 U32 ImageOffset; /* 08h */ 1090 U32 ImageSize; /* 0Ch */ 1091} FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE, 1092 FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t; 1093 1094/* Firmware Upload reply */ 1095typedef struct _MSG_FW_UPLOAD_REPLY 1096{ 1097 U8 ImageType; /* 00h */ 1098 U8 Reserved; /* 01h */ 1099 U8 MsgLength; /* 02h */ 1100 U8 Function; /* 03h */ 1101 U8 Reserved1[3]; /* 04h */ 1102 U8 MsgFlags; /* 07h */ 1103 U32 MsgContext; /* 08h */ 1104 U16 Reserved2; /* 0Ch */ 1105 U16 IOCStatus; /* 0Eh */ 1106 U32 IOCLogInfo; /* 10h */ 1107 U32 ActualImageSize; /* 14h */ 1108} MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY, 1109 FWUploadReply_t, MPI_POINTER pFWUploadReply_t; 1110 1111 1112typedef struct _MPI_FW_HEADER 1113{ 1114 U32 ArmBranchInstruction0; /* 00h */ 1115 U32 Signature0; /* 04h */ 1116 U32 Signature1; /* 08h */ 1117 U32 Signature2; /* 0Ch */ 1118 U32 ArmBranchInstruction1; /* 10h */ 1119 U32 ArmBranchInstruction2; /* 14h */ 1120 U32 Reserved; /* 18h */ 1121 U32 Checksum; /* 1Ch */ 1122 U16 VendorId; /* 20h */ 1123 U16 ProductId; /* 22h */ 1124 MPI_FW_VERSION FWVersion; /* 24h */ 1125 U32 SeqCodeVersion; /* 28h */ 1126 U32 ImageSize; /* 2Ch */ 1127 U32 NextImageHeaderOffset; /* 30h */ 1128 U32 LoadStartAddress; /* 34h */ 1129 U32 IopResetVectorValue; /* 38h */ 1130 U32 IopResetRegAddr; /* 3Ch */ 1131 U32 VersionNameWhat; /* 40h */ 1132 U8 VersionName[32]; /* 44h */ 1133 U32 VendorNameWhat; /* 64h */ 1134 U8 VendorName[32]; /* 68h */ 1135} MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER, 1136 MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t; 1137 1138#define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1139 1140/* defines for using the ProductId field */ 1141#define MPI_FW_HEADER_PID_TYPE_MASK (0xF000) 1142#define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000) 1143#define MPI_FW_HEADER_PID_TYPE_FC (0x1000) 1144#define MPI_FW_HEADER_PID_TYPE_SAS (0x2000) 1145 1146#define MPI_FW_HEADER_SIGNATURE_0 (0x5AEAA55A) 1147#define MPI_FW_HEADER_SIGNATURE_1 (0xA55AEAA5) 1148#define MPI_FW_HEADER_SIGNATURE_2 (0x5AA55AEA) 1149 1150#define MPI_FW_HEADER_PID_PROD_MASK (0x0F00) 1151#define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100) 1152#define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1153#define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300) 1154#define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400) 1155#define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500) 1156#define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600) 1157#define MPI_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1158 1159#define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1160/* SCSI */ 1161#define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001) 1162#define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002) 1163#define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003) 1164#define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004) 1165#define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005) 1166#define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006) 1167#define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007) 1168#define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008) 1169#define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009) 1170#define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A) 1171#define MPI_FW_HEADER_PID_FAMILY_1030TA0_SCSI (0x000B) 1172#define MPI_FW_HEADER_PID_FAMILY_1020TA0_SCSI (0x000C) 1173/* Fibre Channel */ 1174#define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000) 1175#define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) /* 919 and 929 */ 1176#define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) /* 919X and 929X */ 1177#define MPI_FW_HEADER_PID_FAMILY_919XL_FC (0x0003) /* 919XL and 929XL */ 1178#define MPI_FW_HEADER_PID_FAMILY_939X_FC (0x0004) /* 939X and 949X */ 1179#define MPI_FW_HEADER_PID_FAMILY_959_FC (0x0005) 1180#define MPI_FW_HEADER_PID_FAMILY_949E_FC (0x0006) 1181/* SAS */ 1182#define MPI_FW_HEADER_PID_FAMILY_1064_SAS (0x0001) 1183#define MPI_FW_HEADER_PID_FAMILY_1068_SAS (0x0002) 1184#define MPI_FW_HEADER_PID_FAMILY_1078_SAS (0x0003) 1185#define MPI_FW_HEADER_PID_FAMILY_106xE_SAS (0x0004) /* 1068E, 1066E, and 1064E */ 1186 1187typedef struct _MPI_EXT_IMAGE_HEADER 1188{ 1189 U8 ImageType; /* 00h */ 1190 U8 Reserved; /* 01h */ 1191 U16 Reserved1; /* 02h */ 1192 U32 Checksum; /* 04h */ 1193 U32 ImageSize; /* 08h */ 1194 U32 NextImageHeaderOffset; /* 0Ch */ 1195 U32 LoadStartAddress; /* 10h */ 1196 U32 Reserved2; /* 14h */ 1197} MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER, 1198 MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t; 1199 1200/* defines for the ImageType field */ 1201#define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1202#define MPI_EXT_IMAGE_TYPE_FW (0x01) 1203#define MPI_EXT_IMAGE_TYPE_NVDATA (0x03) 1204#define MPI_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1205#define MPI_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1206 1207#endif 1208