1/* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16#include <linux/delay.h> 17#include <linux/highmem.h> 18#include <linux/io.h> 19#include <linux/module.h> 20#include <linux/dma-mapping.h> 21#include <linux/slab.h> 22#include <linux/scatterlist.h> 23#include <linux/regulator/consumer.h> 24#include <linux/pm_runtime.h> 25 26#include <linux/leds.h> 27 28#include <linux/mmc/mmc.h> 29#include <linux/mmc/host.h> 30#include <linux/mmc/card.h> 31#include <linux/mmc/slot-gpio.h> 32 33#include "sdhci.h" 34 35#define DRIVER_NAME "sdhci" 36 37#define DBG(f, x...) \ 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 39 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41 defined(CONFIG_MMC_SDHCI_MODULE)) 42#define SDHCI_USE_LEDS_CLASS 43#endif 44 45#define MAX_TUNING_LOOP 40 46 47#define ADMA_SIZE ((128 * 2 + 1) * 4) 48 49static unsigned int debug_quirks = 0; 50static unsigned int debug_quirks2; 51 52static void sdhci_finish_data(struct sdhci_host *); 53 54static void sdhci_finish_command(struct sdhci_host *); 55static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 56static void sdhci_tuning_timer(unsigned long data); 57static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 58 59#ifdef CONFIG_PM_RUNTIME 60static int sdhci_runtime_pm_get(struct sdhci_host *host); 61static int sdhci_runtime_pm_put(struct sdhci_host *host); 62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 63static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 64#else 65static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 66{ 67 return 0; 68} 69static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 70{ 71 return 0; 72} 73static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 74{ 75} 76static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 77{ 78} 79#endif 80 81static void sdhci_dumpregs(struct sdhci_host *host) 82{ 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 84 mmc_hostname(host->mmc)); 85 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 87 sdhci_readl(host, SDHCI_DMA_ADDRESS), 88 sdhci_readw(host, SDHCI_HOST_VERSION)); 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 90 sdhci_readw(host, SDHCI_BLOCK_SIZE), 91 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 93 sdhci_readl(host, SDHCI_ARGUMENT), 94 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 96 sdhci_readl(host, SDHCI_PRESENT_STATE), 97 sdhci_readb(host, SDHCI_HOST_CONTROL)); 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 99 sdhci_readb(host, SDHCI_POWER_CONTROL), 100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 103 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 106 sdhci_readl(host, SDHCI_INT_STATUS)); 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 108 sdhci_readl(host, SDHCI_INT_ENABLE), 109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 111 sdhci_readw(host, SDHCI_ACMD12_ERR), 112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 114 sdhci_readl(host, SDHCI_CAPABILITIES), 115 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 117 sdhci_readw(host, SDHCI_COMMAND), 118 sdhci_readl(host, SDHCI_MAX_CURRENT)); 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 120 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 121 122 if (host->flags & SDHCI_USE_ADMA) 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 124 readl(host->ioaddr + SDHCI_ADMA_ERROR), 125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 126 127 pr_debug(DRIVER_NAME ": ===========================================\n"); 128} 129 130/*****************************************************************************\ 131 * * 132 * Low level functions * 133 * * 134\*****************************************************************************/ 135 136static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 137{ 138 u32 present; 139 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 142 return; 143 144 if (enable) { 145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 146 SDHCI_CARD_PRESENT; 147 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 149 SDHCI_INT_CARD_INSERT; 150 } else { 151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 152 } 153 154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 156} 157 158static void sdhci_enable_card_detection(struct sdhci_host *host) 159{ 160 sdhci_set_card_detection(host, true); 161} 162 163static void sdhci_disable_card_detection(struct sdhci_host *host) 164{ 165 sdhci_set_card_detection(host, false); 166} 167 168void sdhci_reset(struct sdhci_host *host, u8 mask) 169{ 170 unsigned long timeout; 171 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 173 174 if (mask & SDHCI_RESET_ALL) { 175 host->clock = 0; 176 /* Reset-all turns off SD Bus Power */ 177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 178 sdhci_runtime_pm_bus_off(host); 179 } 180 181 /* Wait max 100 ms */ 182 timeout = 100; 183 184 /* hw clears the bit when it's done */ 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 186 if (timeout == 0) { 187 pr_err("%s: Reset 0x%x never completed.\n", 188 mmc_hostname(host->mmc), (int)mask); 189 sdhci_dumpregs(host); 190 return; 191 } 192 timeout--; 193 mdelay(1); 194 } 195} 196EXPORT_SYMBOL_GPL(sdhci_reset); 197 198static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 199{ 200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 202 SDHCI_CARD_PRESENT)) 203 return; 204 } 205 206 host->ops->reset(host, mask); 207 208 if (mask & SDHCI_RESET_ALL) { 209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 210 if (host->ops->enable_dma) 211 host->ops->enable_dma(host); 212 } 213 214 /* Resetting the controller clears many */ 215 host->preset_enabled = false; 216 } 217} 218 219static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 220 221static void sdhci_init(struct sdhci_host *host, int soft) 222{ 223 if (soft) 224 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 225 else 226 sdhci_do_reset(host, SDHCI_RESET_ALL); 227 228 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 230 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 231 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 232 SDHCI_INT_RESPONSE; 233 234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 236 237 if (soft) { 238 /* force clock reconfiguration */ 239 host->clock = 0; 240 sdhci_set_ios(host->mmc, &host->mmc->ios); 241 } 242} 243 244static void sdhci_reinit(struct sdhci_host *host) 245{ 246 sdhci_init(host, 0); 247 /* 248 * Retuning stuffs are affected by different cards inserted and only 249 * applicable to UHS-I cards. So reset these fields to their initial 250 * value when card is removed. 251 */ 252 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 253 host->flags &= ~SDHCI_USING_RETUNING_TIMER; 254 255 del_timer_sync(&host->tuning_timer); 256 host->flags &= ~SDHCI_NEEDS_RETUNING; 257 host->mmc->max_blk_count = 258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 259 } 260 sdhci_enable_card_detection(host); 261} 262 263static void sdhci_activate_led(struct sdhci_host *host) 264{ 265 u8 ctrl; 266 267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 268 ctrl |= SDHCI_CTRL_LED; 269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 270} 271 272static void sdhci_deactivate_led(struct sdhci_host *host) 273{ 274 u8 ctrl; 275 276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 277 ctrl &= ~SDHCI_CTRL_LED; 278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 279} 280 281#ifdef SDHCI_USE_LEDS_CLASS 282static void sdhci_led_control(struct led_classdev *led, 283 enum led_brightness brightness) 284{ 285 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 286 unsigned long flags; 287 288 spin_lock_irqsave(&host->lock, flags); 289 290 if (host->runtime_suspended) 291 goto out; 292 293 if (brightness == LED_OFF) 294 sdhci_deactivate_led(host); 295 else 296 sdhci_activate_led(host); 297out: 298 spin_unlock_irqrestore(&host->lock, flags); 299} 300#endif 301 302/*****************************************************************************\ 303 * * 304 * Core functions * 305 * * 306\*****************************************************************************/ 307 308static void sdhci_read_block_pio(struct sdhci_host *host) 309{ 310 unsigned long flags; 311 size_t blksize, len, chunk; 312 u32 uninitialized_var(scratch); 313 u8 *buf; 314 315 DBG("PIO reading\n"); 316 317 blksize = host->data->blksz; 318 chunk = 0; 319 320 local_irq_save(flags); 321 322 while (blksize) { 323 if (!sg_miter_next(&host->sg_miter)) 324 BUG(); 325 326 len = min(host->sg_miter.length, blksize); 327 328 blksize -= len; 329 host->sg_miter.consumed = len; 330 331 buf = host->sg_miter.addr; 332 333 while (len) { 334 if (chunk == 0) { 335 scratch = sdhci_readl(host, SDHCI_BUFFER); 336 chunk = 4; 337 } 338 339 *buf = scratch & 0xFF; 340 341 buf++; 342 scratch >>= 8; 343 chunk--; 344 len--; 345 } 346 } 347 348 sg_miter_stop(&host->sg_miter); 349 350 local_irq_restore(flags); 351} 352 353static void sdhci_write_block_pio(struct sdhci_host *host) 354{ 355 unsigned long flags; 356 size_t blksize, len, chunk; 357 u32 scratch; 358 u8 *buf; 359 360 DBG("PIO writing\n"); 361 362 blksize = host->data->blksz; 363 chunk = 0; 364 scratch = 0; 365 366 local_irq_save(flags); 367 368 while (blksize) { 369 if (!sg_miter_next(&host->sg_miter)) 370 BUG(); 371 372 len = min(host->sg_miter.length, blksize); 373 374 blksize -= len; 375 host->sg_miter.consumed = len; 376 377 buf = host->sg_miter.addr; 378 379 while (len) { 380 scratch |= (u32)*buf << (chunk * 8); 381 382 buf++; 383 chunk++; 384 len--; 385 386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 387 sdhci_writel(host, scratch, SDHCI_BUFFER); 388 chunk = 0; 389 scratch = 0; 390 } 391 } 392 } 393 394 sg_miter_stop(&host->sg_miter); 395 396 local_irq_restore(flags); 397} 398 399static void sdhci_transfer_pio(struct sdhci_host *host) 400{ 401 u32 mask; 402 403 BUG_ON(!host->data); 404 405 if (host->blocks == 0) 406 return; 407 408 if (host->data->flags & MMC_DATA_READ) 409 mask = SDHCI_DATA_AVAILABLE; 410 else 411 mask = SDHCI_SPACE_AVAILABLE; 412 413 /* 414 * Some controllers (JMicron JMB38x) mess up the buffer bits 415 * for transfers < 4 bytes. As long as it is just one block, 416 * we can ignore the bits. 417 */ 418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 419 (host->data->blocks == 1)) 420 mask = ~0; 421 422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 424 udelay(100); 425 426 if (host->data->flags & MMC_DATA_READ) 427 sdhci_read_block_pio(host); 428 else 429 sdhci_write_block_pio(host); 430 431 host->blocks--; 432 if (host->blocks == 0) 433 break; 434 } 435 436 DBG("PIO transfer complete.\n"); 437} 438 439static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 440{ 441 local_irq_save(*flags); 442 return kmap_atomic(sg_page(sg)) + sg->offset; 443} 444 445static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 446{ 447 kunmap_atomic(buffer); 448 local_irq_restore(*flags); 449} 450 451static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 452{ 453 __le32 *dataddr = (__le32 __force *)(desc + 4); 454 __le16 *cmdlen = (__le16 __force *)desc; 455 456 /* SDHCI specification says ADMA descriptors should be 4 byte 457 * aligned, so using 16 or 32bit operations should be safe. */ 458 459 cmdlen[0] = cpu_to_le16(cmd); 460 cmdlen[1] = cpu_to_le16(len); 461 462 dataddr[0] = cpu_to_le32(addr); 463} 464 465static int sdhci_adma_table_pre(struct sdhci_host *host, 466 struct mmc_data *data) 467{ 468 int direction; 469 470 u8 *desc; 471 u8 *align; 472 dma_addr_t addr; 473 dma_addr_t align_addr; 474 int len, offset; 475 476 struct scatterlist *sg; 477 int i; 478 char *buffer; 479 unsigned long flags; 480 481 /* 482 * The spec does not specify endianness of descriptor table. 483 * We currently guess that it is LE. 484 */ 485 486 if (data->flags & MMC_DATA_READ) 487 direction = DMA_FROM_DEVICE; 488 else 489 direction = DMA_TO_DEVICE; 490 491 host->align_addr = dma_map_single(mmc_dev(host->mmc), 492 host->align_buffer, 128 * 4, direction); 493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 494 goto fail; 495 BUG_ON(host->align_addr & 0x3); 496 497 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 498 data->sg, data->sg_len, direction); 499 if (host->sg_count == 0) 500 goto unmap_align; 501 502 desc = host->adma_desc; 503 align = host->align_buffer; 504 505 align_addr = host->align_addr; 506 507 for_each_sg(data->sg, sg, host->sg_count, i) { 508 addr = sg_dma_address(sg); 509 len = sg_dma_len(sg); 510 511 /* 512 * The SDHCI specification states that ADMA 513 * addresses must be 32-bit aligned. If they 514 * aren't, then we use a bounce buffer for 515 * the (up to three) bytes that screw up the 516 * alignment. 517 */ 518 offset = (4 - (addr & 0x3)) & 0x3; 519 if (offset) { 520 if (data->flags & MMC_DATA_WRITE) { 521 buffer = sdhci_kmap_atomic(sg, &flags); 522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 523 memcpy(align, buffer, offset); 524 sdhci_kunmap_atomic(buffer, &flags); 525 } 526 527 /* tran, valid */ 528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 529 530 BUG_ON(offset > 65536); 531 532 align += 4; 533 align_addr += 4; 534 535 desc += 8; 536 537 addr += offset; 538 len -= offset; 539 } 540 541 BUG_ON(len > 65536); 542 543 /* tran, valid */ 544 sdhci_set_adma_desc(desc, addr, len, 0x21); 545 desc += 8; 546 547 /* 548 * If this triggers then we have a calculation bug 549 * somewhere. :/ 550 */ 551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE); 552 } 553 554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 555 /* 556 * Mark the last descriptor as the terminating descriptor 557 */ 558 if (desc != host->adma_desc) { 559 desc -= 8; 560 desc[0] |= 0x2; /* end */ 561 } 562 } else { 563 /* 564 * Add a terminating entry. 565 */ 566 567 /* nop, end, valid */ 568 sdhci_set_adma_desc(desc, 0, 0, 0x3); 569 } 570 571 /* 572 * Resync align buffer as we might have changed it. 573 */ 574 if (data->flags & MMC_DATA_WRITE) { 575 dma_sync_single_for_device(mmc_dev(host->mmc), 576 host->align_addr, 128 * 4, direction); 577 } 578 579 return 0; 580 581unmap_align: 582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 583 128 * 4, direction); 584fail: 585 return -EINVAL; 586} 587 588static void sdhci_adma_table_post(struct sdhci_host *host, 589 struct mmc_data *data) 590{ 591 int direction; 592 593 struct scatterlist *sg; 594 int i, size; 595 u8 *align; 596 char *buffer; 597 unsigned long flags; 598 bool has_unaligned; 599 600 if (data->flags & MMC_DATA_READ) 601 direction = DMA_FROM_DEVICE; 602 else 603 direction = DMA_TO_DEVICE; 604 605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 606 128 * 4, direction); 607 608 /* Do a quick scan of the SG list for any unaligned mappings */ 609 has_unaligned = false; 610 for_each_sg(data->sg, sg, host->sg_count, i) 611 if (sg_dma_address(sg) & 3) { 612 has_unaligned = true; 613 break; 614 } 615 616 if (has_unaligned && data->flags & MMC_DATA_READ) { 617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 618 data->sg_len, direction); 619 620 align = host->align_buffer; 621 622 for_each_sg(data->sg, sg, host->sg_count, i) { 623 if (sg_dma_address(sg) & 0x3) { 624 size = 4 - (sg_dma_address(sg) & 0x3); 625 626 buffer = sdhci_kmap_atomic(sg, &flags); 627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 628 memcpy(buffer, align, size); 629 sdhci_kunmap_atomic(buffer, &flags); 630 631 align += 4; 632 } 633 } 634 } 635 636 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 637 data->sg_len, direction); 638} 639 640static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 641{ 642 u8 count; 643 struct mmc_data *data = cmd->data; 644 unsigned target_timeout, current_timeout; 645 646 /* 647 * If the host controller provides us with an incorrect timeout 648 * value, just skip the check and use 0xE. The hardware may take 649 * longer to time out, but that's much better than having a too-short 650 * timeout value. 651 */ 652 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 653 return 0xE; 654 655 /* Unspecified timeout, assume max */ 656 if (!data && !cmd->busy_timeout) 657 return 0xE; 658 659 /* timeout in us */ 660 if (!data) 661 target_timeout = cmd->busy_timeout * 1000; 662 else { 663 target_timeout = data->timeout_ns / 1000; 664 if (host->clock) 665 target_timeout += data->timeout_clks / host->clock; 666 } 667 668 /* 669 * Figure out needed cycles. 670 * We do this in steps in order to fit inside a 32 bit int. 671 * The first step is the minimum timeout, which will have a 672 * minimum resolution of 6 bits: 673 * (1) 2^13*1000 > 2^22, 674 * (2) host->timeout_clk < 2^16 675 * => 676 * (1) / (2) > 2^6 677 */ 678 count = 0; 679 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 680 while (current_timeout < target_timeout) { 681 count++; 682 current_timeout <<= 1; 683 if (count >= 0xF) 684 break; 685 } 686 687 if (count >= 0xF) { 688 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 689 mmc_hostname(host->mmc), count, cmd->opcode); 690 count = 0xE; 691 } 692 693 return count; 694} 695 696static void sdhci_set_transfer_irqs(struct sdhci_host *host) 697{ 698 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 699 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 700 701 if (host->flags & SDHCI_REQ_USE_DMA) 702 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 703 else 704 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 705 706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 708} 709 710static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 711{ 712 u8 count; 713 714 if (host->ops->set_timeout) { 715 host->ops->set_timeout(host, cmd); 716 } else { 717 count = sdhci_calc_timeout(host, cmd); 718 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 719 } 720} 721 722static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 723{ 724 u8 ctrl; 725 struct mmc_data *data = cmd->data; 726 int ret; 727 728 WARN_ON(host->data); 729 730 if (data || (cmd->flags & MMC_RSP_BUSY)) 731 sdhci_set_timeout(host, cmd); 732 733 if (!data) 734 return; 735 736 /* Sanity checks */ 737 BUG_ON(data->blksz * data->blocks > 524288); 738 BUG_ON(data->blksz > host->mmc->max_blk_size); 739 BUG_ON(data->blocks > 65535); 740 741 host->data = data; 742 host->data_early = 0; 743 host->data->bytes_xfered = 0; 744 745 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 746 host->flags |= SDHCI_REQ_USE_DMA; 747 748 /* 749 * FIXME: This doesn't account for merging when mapping the 750 * scatterlist. 751 */ 752 if (host->flags & SDHCI_REQ_USE_DMA) { 753 int broken, i; 754 struct scatterlist *sg; 755 756 broken = 0; 757 if (host->flags & SDHCI_USE_ADMA) { 758 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 759 broken = 1; 760 } else { 761 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 762 broken = 1; 763 } 764 765 if (unlikely(broken)) { 766 for_each_sg(data->sg, sg, data->sg_len, i) { 767 if (sg->length & 0x3) { 768 DBG("Reverting to PIO because of " 769 "transfer size (%d)\n", 770 sg->length); 771 host->flags &= ~SDHCI_REQ_USE_DMA; 772 break; 773 } 774 } 775 } 776 } 777 778 /* 779 * The assumption here being that alignment is the same after 780 * translation to device address space. 781 */ 782 if (host->flags & SDHCI_REQ_USE_DMA) { 783 int broken, i; 784 struct scatterlist *sg; 785 786 broken = 0; 787 if (host->flags & SDHCI_USE_ADMA) { 788 /* 789 * As we use 3 byte chunks to work around 790 * alignment problems, we need to check this 791 * quirk. 792 */ 793 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 794 broken = 1; 795 } else { 796 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 797 broken = 1; 798 } 799 800 if (unlikely(broken)) { 801 for_each_sg(data->sg, sg, data->sg_len, i) { 802 if (sg->offset & 0x3) { 803 DBG("Reverting to PIO because of " 804 "bad alignment\n"); 805 host->flags &= ~SDHCI_REQ_USE_DMA; 806 break; 807 } 808 } 809 } 810 } 811 812 if (host->flags & SDHCI_REQ_USE_DMA) { 813 if (host->flags & SDHCI_USE_ADMA) { 814 ret = sdhci_adma_table_pre(host, data); 815 if (ret) { 816 /* 817 * This only happens when someone fed 818 * us an invalid request. 819 */ 820 WARN_ON(1); 821 host->flags &= ~SDHCI_REQ_USE_DMA; 822 } else { 823 sdhci_writel(host, host->adma_addr, 824 SDHCI_ADMA_ADDRESS); 825 } 826 } else { 827 int sg_cnt; 828 829 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 830 data->sg, data->sg_len, 831 (data->flags & MMC_DATA_READ) ? 832 DMA_FROM_DEVICE : 833 DMA_TO_DEVICE); 834 if (sg_cnt == 0) { 835 /* 836 * This only happens when someone fed 837 * us an invalid request. 838 */ 839 WARN_ON(1); 840 host->flags &= ~SDHCI_REQ_USE_DMA; 841 } else { 842 WARN_ON(sg_cnt != 1); 843 sdhci_writel(host, sg_dma_address(data->sg), 844 SDHCI_DMA_ADDRESS); 845 } 846 } 847 } 848 849 /* 850 * Always adjust the DMA selection as some controllers 851 * (e.g. JMicron) can't do PIO properly when the selection 852 * is ADMA. 853 */ 854 if (host->version >= SDHCI_SPEC_200) { 855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 856 ctrl &= ~SDHCI_CTRL_DMA_MASK; 857 if ((host->flags & SDHCI_REQ_USE_DMA) && 858 (host->flags & SDHCI_USE_ADMA)) 859 ctrl |= SDHCI_CTRL_ADMA32; 860 else 861 ctrl |= SDHCI_CTRL_SDMA; 862 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 863 } 864 865 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 866 int flags; 867 868 flags = SG_MITER_ATOMIC; 869 if (host->data->flags & MMC_DATA_READ) 870 flags |= SG_MITER_TO_SG; 871 else 872 flags |= SG_MITER_FROM_SG; 873 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 874 host->blocks = data->blocks; 875 } 876 877 sdhci_set_transfer_irqs(host); 878 879 /* Set the DMA boundary value and block size */ 880 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 881 data->blksz), SDHCI_BLOCK_SIZE); 882 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 883} 884 885static void sdhci_set_transfer_mode(struct sdhci_host *host, 886 struct mmc_command *cmd) 887{ 888 u16 mode; 889 struct mmc_data *data = cmd->data; 890 891 if (data == NULL) { 892 /* clear Auto CMD settings for no data CMDs */ 893 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 894 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 895 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 896 return; 897 } 898 899 WARN_ON(!host->data); 900 901 mode = SDHCI_TRNS_BLK_CNT_EN; 902 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 903 mode |= SDHCI_TRNS_MULTI; 904 /* 905 * If we are sending CMD23, CMD12 never gets sent 906 * on successful completion (so no Auto-CMD12). 907 */ 908 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 909 mode |= SDHCI_TRNS_AUTO_CMD12; 910 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 911 mode |= SDHCI_TRNS_AUTO_CMD23; 912 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 913 } 914 } 915 916 if (data->flags & MMC_DATA_READ) 917 mode |= SDHCI_TRNS_READ; 918 if (host->flags & SDHCI_REQ_USE_DMA) 919 mode |= SDHCI_TRNS_DMA; 920 921 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 922} 923 924static void sdhci_finish_data(struct sdhci_host *host) 925{ 926 struct mmc_data *data; 927 928 BUG_ON(!host->data); 929 930 data = host->data; 931 host->data = NULL; 932 933 if (host->flags & SDHCI_REQ_USE_DMA) { 934 if (host->flags & SDHCI_USE_ADMA) 935 sdhci_adma_table_post(host, data); 936 else { 937 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 938 data->sg_len, (data->flags & MMC_DATA_READ) ? 939 DMA_FROM_DEVICE : DMA_TO_DEVICE); 940 } 941 } 942 943 /* 944 * The specification states that the block count register must 945 * be updated, but it does not specify at what point in the 946 * data flow. That makes the register entirely useless to read 947 * back so we have to assume that nothing made it to the card 948 * in the event of an error. 949 */ 950 if (data->error) 951 data->bytes_xfered = 0; 952 else 953 data->bytes_xfered = data->blksz * data->blocks; 954 955 /* 956 * Need to send CMD12 if - 957 * a) open-ended multiblock transfer (no CMD23) 958 * b) error in multiblock transfer 959 */ 960 if (data->stop && 961 (data->error || 962 !host->mrq->sbc)) { 963 964 /* 965 * The controller needs a reset of internal state machines 966 * upon error conditions. 967 */ 968 if (data->error) { 969 sdhci_do_reset(host, SDHCI_RESET_CMD); 970 sdhci_do_reset(host, SDHCI_RESET_DATA); 971 } 972 973 sdhci_send_command(host, data->stop); 974 } else 975 tasklet_schedule(&host->finish_tasklet); 976} 977 978void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 979{ 980 int flags; 981 u32 mask; 982 unsigned long timeout; 983 984 WARN_ON(host->cmd); 985 986 /* Wait max 10 ms */ 987 timeout = 10; 988 989 mask = SDHCI_CMD_INHIBIT; 990 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 991 mask |= SDHCI_DATA_INHIBIT; 992 993 /* We shouldn't wait for data inihibit for stop commands, even 994 though they might use busy signaling */ 995 if (host->mrq->data && (cmd == host->mrq->data->stop)) 996 mask &= ~SDHCI_DATA_INHIBIT; 997 998 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 999 if (timeout == 0) { 1000 pr_err("%s: Controller never released " 1001 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 1002 sdhci_dumpregs(host); 1003 cmd->error = -EIO; 1004 tasklet_schedule(&host->finish_tasklet); 1005 return; 1006 } 1007 timeout--; 1008 mdelay(1); 1009 } 1010 1011 timeout = jiffies; 1012 if (!cmd->data && cmd->busy_timeout > 9000) 1013 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1014 else 1015 timeout += 10 * HZ; 1016 mod_timer(&host->timer, timeout); 1017 1018 host->cmd = cmd; 1019 host->busy_handle = 0; 1020 1021 sdhci_prepare_data(host, cmd); 1022 1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1024 1025 sdhci_set_transfer_mode(host, cmd); 1026 1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1028 pr_err("%s: Unsupported response type!\n", 1029 mmc_hostname(host->mmc)); 1030 cmd->error = -EINVAL; 1031 tasklet_schedule(&host->finish_tasklet); 1032 return; 1033 } 1034 1035 if (!(cmd->flags & MMC_RSP_PRESENT)) 1036 flags = SDHCI_CMD_RESP_NONE; 1037 else if (cmd->flags & MMC_RSP_136) 1038 flags = SDHCI_CMD_RESP_LONG; 1039 else if (cmd->flags & MMC_RSP_BUSY) 1040 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1041 else 1042 flags = SDHCI_CMD_RESP_SHORT; 1043 1044 if (cmd->flags & MMC_RSP_CRC) 1045 flags |= SDHCI_CMD_CRC; 1046 if (cmd->flags & MMC_RSP_OPCODE) 1047 flags |= SDHCI_CMD_INDEX; 1048 1049 /* CMD19 is special in that the Data Present Select should be set */ 1050 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1051 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1052 flags |= SDHCI_CMD_DATA; 1053 1054 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1055} 1056EXPORT_SYMBOL_GPL(sdhci_send_command); 1057 1058static void sdhci_finish_command(struct sdhci_host *host) 1059{ 1060 int i; 1061 1062 BUG_ON(host->cmd == NULL); 1063 1064 if (host->cmd->flags & MMC_RSP_PRESENT) { 1065 if (host->cmd->flags & MMC_RSP_136) { 1066 /* CRC is stripped so we need to do some shifting. */ 1067 for (i = 0;i < 4;i++) { 1068 host->cmd->resp[i] = sdhci_readl(host, 1069 SDHCI_RESPONSE + (3-i)*4) << 8; 1070 if (i != 3) 1071 host->cmd->resp[i] |= 1072 sdhci_readb(host, 1073 SDHCI_RESPONSE + (3-i)*4-1); 1074 } 1075 } else { 1076 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1077 } 1078 } 1079 1080 host->cmd->error = 0; 1081 1082 /* Finished CMD23, now send actual command. */ 1083 if (host->cmd == host->mrq->sbc) { 1084 host->cmd = NULL; 1085 sdhci_send_command(host, host->mrq->cmd); 1086 } else { 1087 1088 /* Processed actual command. */ 1089 if (host->data && host->data_early) 1090 sdhci_finish_data(host); 1091 1092 if (!host->cmd->data) 1093 tasklet_schedule(&host->finish_tasklet); 1094 1095 host->cmd = NULL; 1096 } 1097} 1098 1099static u16 sdhci_get_preset_value(struct sdhci_host *host) 1100{ 1101 u16 preset = 0; 1102 1103 switch (host->timing) { 1104 case MMC_TIMING_UHS_SDR12: 1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1106 break; 1107 case MMC_TIMING_UHS_SDR25: 1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1109 break; 1110 case MMC_TIMING_UHS_SDR50: 1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1112 break; 1113 case MMC_TIMING_UHS_SDR104: 1114 case MMC_TIMING_MMC_HS200: 1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1116 break; 1117 case MMC_TIMING_UHS_DDR50: 1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1119 break; 1120 default: 1121 pr_warn("%s: Invalid UHS-I mode selected\n", 1122 mmc_hostname(host->mmc)); 1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1124 break; 1125 } 1126 return preset; 1127} 1128 1129void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1130{ 1131 int div = 0; /* Initialized for compiler warning */ 1132 int real_div = div, clk_mul = 1; 1133 u16 clk = 0; 1134 unsigned long timeout; 1135 1136 host->mmc->actual_clock = 0; 1137 1138 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1139 1140 if (clock == 0) 1141 return; 1142 1143 if (host->version >= SDHCI_SPEC_300) { 1144 if (host->preset_enabled) { 1145 u16 pre_val; 1146 1147 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1148 pre_val = sdhci_get_preset_value(host); 1149 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1150 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1151 if (host->clk_mul && 1152 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1153 clk = SDHCI_PROG_CLOCK_MODE; 1154 real_div = div + 1; 1155 clk_mul = host->clk_mul; 1156 } else { 1157 real_div = max_t(int, 1, div << 1); 1158 } 1159 goto clock_set; 1160 } 1161 1162 /* 1163 * Check if the Host Controller supports Programmable Clock 1164 * Mode. 1165 */ 1166 if (host->clk_mul) { 1167 for (div = 1; div <= 1024; div++) { 1168 if ((host->max_clk * host->clk_mul / div) 1169 <= clock) 1170 break; 1171 } 1172 /* 1173 * Set Programmable Clock Mode in the Clock 1174 * Control register. 1175 */ 1176 clk = SDHCI_PROG_CLOCK_MODE; 1177 real_div = div; 1178 clk_mul = host->clk_mul; 1179 div--; 1180 } else { 1181 /* Version 3.00 divisors must be a multiple of 2. */ 1182 if (host->max_clk <= clock) 1183 div = 1; 1184 else { 1185 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1186 div += 2) { 1187 if ((host->max_clk / div) <= clock) 1188 break; 1189 } 1190 } 1191 real_div = div; 1192 div >>= 1; 1193 } 1194 } else { 1195 /* Version 2.00 divisors must be a power of 2. */ 1196 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1197 if ((host->max_clk / div) <= clock) 1198 break; 1199 } 1200 real_div = div; 1201 div >>= 1; 1202 } 1203 1204clock_set: 1205 if (real_div) 1206 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1207 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1208 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1209 << SDHCI_DIVIDER_HI_SHIFT; 1210 clk |= SDHCI_CLOCK_INT_EN; 1211 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1212 1213 /* Wait max 20 ms */ 1214 timeout = 20; 1215 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1216 & SDHCI_CLOCK_INT_STABLE)) { 1217 if (timeout == 0) { 1218 pr_err("%s: Internal clock never " 1219 "stabilised.\n", mmc_hostname(host->mmc)); 1220 sdhci_dumpregs(host); 1221 return; 1222 } 1223 timeout--; 1224 mdelay(1); 1225 } 1226 1227 clk |= SDHCI_CLOCK_CARD_EN; 1228 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1229} 1230EXPORT_SYMBOL_GPL(sdhci_set_clock); 1231 1232static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1233 unsigned short vdd) 1234{ 1235 struct mmc_host *mmc = host->mmc; 1236 u8 pwr = 0; 1237 1238 if (!IS_ERR(mmc->supply.vmmc)) { 1239 spin_unlock_irq(&host->lock); 1240 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1241 spin_lock_irq(&host->lock); 1242 return; 1243 } 1244 1245 if (mode != MMC_POWER_OFF) { 1246 switch (1 << vdd) { 1247 case MMC_VDD_165_195: 1248 pwr = SDHCI_POWER_180; 1249 break; 1250 case MMC_VDD_29_30: 1251 case MMC_VDD_30_31: 1252 pwr = SDHCI_POWER_300; 1253 break; 1254 case MMC_VDD_32_33: 1255 case MMC_VDD_33_34: 1256 pwr = SDHCI_POWER_330; 1257 break; 1258 default: 1259 BUG(); 1260 } 1261 } 1262 1263 if (host->pwr == pwr) 1264 return; 1265 1266 host->pwr = pwr; 1267 1268 if (pwr == 0) { 1269 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1270 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1271 sdhci_runtime_pm_bus_off(host); 1272 vdd = 0; 1273 } else { 1274 /* 1275 * Spec says that we should clear the power reg before setting 1276 * a new value. Some controllers don't seem to like this though. 1277 */ 1278 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1280 1281 /* 1282 * At least the Marvell CaFe chip gets confused if we set the 1283 * voltage and set turn on power at the same time, so set the 1284 * voltage first. 1285 */ 1286 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1287 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1288 1289 pwr |= SDHCI_POWER_ON; 1290 1291 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1292 1293 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1294 sdhci_runtime_pm_bus_on(host); 1295 1296 /* 1297 * Some controllers need an extra 10ms delay of 10ms before 1298 * they can apply clock after applying power 1299 */ 1300 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1301 mdelay(10); 1302 } 1303} 1304 1305/*****************************************************************************\ 1306 * * 1307 * MMC callbacks * 1308 * * 1309\*****************************************************************************/ 1310 1311static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1312{ 1313 struct sdhci_host *host; 1314 int present; 1315 unsigned long flags; 1316 u32 tuning_opcode; 1317 1318 host = mmc_priv(mmc); 1319 1320 sdhci_runtime_pm_get(host); 1321 1322 spin_lock_irqsave(&host->lock, flags); 1323 1324 WARN_ON(host->mrq != NULL); 1325 1326#ifndef SDHCI_USE_LEDS_CLASS 1327 sdhci_activate_led(host); 1328#endif 1329 1330 /* 1331 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1332 * requests if Auto-CMD12 is enabled. 1333 */ 1334 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1335 if (mrq->stop) { 1336 mrq->data->stop = NULL; 1337 mrq->stop = NULL; 1338 } 1339 } 1340 1341 host->mrq = mrq; 1342 1343 /* 1344 * Firstly check card presence from cd-gpio. The return could 1345 * be one of the following possibilities: 1346 * negative: cd-gpio is not available 1347 * zero: cd-gpio is used, and card is removed 1348 * one: cd-gpio is used, and card is present 1349 */ 1350 present = mmc_gpio_get_cd(host->mmc); 1351 if (present < 0) { 1352 /* If polling, assume that the card is always present. */ 1353 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1354 present = 1; 1355 else 1356 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1357 SDHCI_CARD_PRESENT; 1358 } 1359 1360 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1361 host->mrq->cmd->error = -ENOMEDIUM; 1362 tasklet_schedule(&host->finish_tasklet); 1363 } else { 1364 u32 present_state; 1365 1366 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1367 /* 1368 * Check if the re-tuning timer has already expired and there 1369 * is no on-going data transfer and DAT0 is not busy. If so, 1370 * we need to execute tuning procedure before sending command. 1371 */ 1372 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1373 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) && 1374 (present_state & SDHCI_DATA_0_LVL_MASK)) { 1375 if (mmc->card) { 1376 /* eMMC uses cmd21 but sd and sdio use cmd19 */ 1377 tuning_opcode = 1378 mmc->card->type == MMC_TYPE_MMC ? 1379 MMC_SEND_TUNING_BLOCK_HS200 : 1380 MMC_SEND_TUNING_BLOCK; 1381 1382 /* Here we need to set the host->mrq to NULL, 1383 * in case the pending finish_tasklet 1384 * finishes it incorrectly. 1385 */ 1386 host->mrq = NULL; 1387 1388 spin_unlock_irqrestore(&host->lock, flags); 1389 sdhci_execute_tuning(mmc, tuning_opcode); 1390 spin_lock_irqsave(&host->lock, flags); 1391 1392 /* Restore original mmc_request structure */ 1393 host->mrq = mrq; 1394 } 1395 } 1396 1397 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1398 sdhci_send_command(host, mrq->sbc); 1399 else 1400 sdhci_send_command(host, mrq->cmd); 1401 } 1402 1403 mmiowb(); 1404 spin_unlock_irqrestore(&host->lock, flags); 1405} 1406 1407void sdhci_set_bus_width(struct sdhci_host *host, int width) 1408{ 1409 u8 ctrl; 1410 1411 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1412 if (width == MMC_BUS_WIDTH_8) { 1413 ctrl &= ~SDHCI_CTRL_4BITBUS; 1414 if (host->version >= SDHCI_SPEC_300) 1415 ctrl |= SDHCI_CTRL_8BITBUS; 1416 } else { 1417 if (host->version >= SDHCI_SPEC_300) 1418 ctrl &= ~SDHCI_CTRL_8BITBUS; 1419 if (width == MMC_BUS_WIDTH_4) 1420 ctrl |= SDHCI_CTRL_4BITBUS; 1421 else 1422 ctrl &= ~SDHCI_CTRL_4BITBUS; 1423 } 1424 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1425} 1426EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1427 1428void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1429{ 1430 u16 ctrl_2; 1431 1432 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1433 /* Select Bus Speed Mode for host */ 1434 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1435 if ((timing == MMC_TIMING_MMC_HS200) || 1436 (timing == MMC_TIMING_UHS_SDR104)) 1437 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1438 else if (timing == MMC_TIMING_UHS_SDR12) 1439 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1440 else if (timing == MMC_TIMING_UHS_SDR25) 1441 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1442 else if (timing == MMC_TIMING_UHS_SDR50) 1443 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1444 else if ((timing == MMC_TIMING_UHS_DDR50) || 1445 (timing == MMC_TIMING_MMC_DDR52)) 1446 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1447 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1448} 1449EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1450 1451static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1452{ 1453 unsigned long flags; 1454 u8 ctrl; 1455 struct mmc_host *mmc = host->mmc; 1456 1457 spin_lock_irqsave(&host->lock, flags); 1458 1459 if (host->flags & SDHCI_DEVICE_DEAD) { 1460 spin_unlock_irqrestore(&host->lock, flags); 1461 if (!IS_ERR(mmc->supply.vmmc) && 1462 ios->power_mode == MMC_POWER_OFF) 1463 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1464 return; 1465 } 1466 1467 /* 1468 * Reset the chip on each power off. 1469 * Should clear out any weird states. 1470 */ 1471 if (ios->power_mode == MMC_POWER_OFF) { 1472 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1473 sdhci_reinit(host); 1474 } 1475 1476 if (host->version >= SDHCI_SPEC_300 && 1477 (ios->power_mode == MMC_POWER_UP) && 1478 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1479 sdhci_enable_preset_value(host, false); 1480 1481 if (!ios->clock || ios->clock != host->clock) { 1482 host->ops->set_clock(host, ios->clock); 1483 host->clock = ios->clock; 1484 1485 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 1486 host->clock) { 1487 host->timeout_clk = host->mmc->actual_clock ? 1488 host->mmc->actual_clock / 1000 : 1489 host->clock / 1000; 1490 host->mmc->max_busy_timeout = 1491 host->ops->get_max_timeout_count ? 1492 host->ops->get_max_timeout_count(host) : 1493 1 << 27; 1494 host->mmc->max_busy_timeout /= host->timeout_clk; 1495 } 1496 } 1497 1498 sdhci_set_power(host, ios->power_mode, ios->vdd); 1499 1500 if (host->ops->platform_send_init_74_clocks) 1501 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1502 1503 host->ops->set_bus_width(host, ios->bus_width); 1504 1505 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1506 1507 if ((ios->timing == MMC_TIMING_SD_HS || 1508 ios->timing == MMC_TIMING_MMC_HS) 1509 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1510 ctrl |= SDHCI_CTRL_HISPD; 1511 else 1512 ctrl &= ~SDHCI_CTRL_HISPD; 1513 1514 if (host->version >= SDHCI_SPEC_300) { 1515 u16 clk, ctrl_2; 1516 1517 /* In case of UHS-I modes, set High Speed Enable */ 1518 if ((ios->timing == MMC_TIMING_MMC_HS200) || 1519 (ios->timing == MMC_TIMING_MMC_DDR52) || 1520 (ios->timing == MMC_TIMING_UHS_SDR50) || 1521 (ios->timing == MMC_TIMING_UHS_SDR104) || 1522 (ios->timing == MMC_TIMING_UHS_DDR50) || 1523 (ios->timing == MMC_TIMING_UHS_SDR25)) 1524 ctrl |= SDHCI_CTRL_HISPD; 1525 1526 if (!host->preset_enabled) { 1527 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1528 /* 1529 * We only need to set Driver Strength if the 1530 * preset value enable is not set. 1531 */ 1532 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1533 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1534 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1535 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1536 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1537 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1538 1539 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1540 } else { 1541 /* 1542 * According to SDHC Spec v3.00, if the Preset Value 1543 * Enable in the Host Control 2 register is set, we 1544 * need to reset SD Clock Enable before changing High 1545 * Speed Enable to avoid generating clock gliches. 1546 */ 1547 1548 /* Reset SD Clock Enable */ 1549 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1550 clk &= ~SDHCI_CLOCK_CARD_EN; 1551 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1552 1553 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1554 1555 /* Re-enable SD Clock */ 1556 host->ops->set_clock(host, host->clock); 1557 } 1558 1559 /* Reset SD Clock Enable */ 1560 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1561 clk &= ~SDHCI_CLOCK_CARD_EN; 1562 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1563 1564 host->ops->set_uhs_signaling(host, ios->timing); 1565 host->timing = ios->timing; 1566 1567 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1568 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1569 (ios->timing == MMC_TIMING_UHS_SDR25) || 1570 (ios->timing == MMC_TIMING_UHS_SDR50) || 1571 (ios->timing == MMC_TIMING_UHS_SDR104) || 1572 (ios->timing == MMC_TIMING_UHS_DDR50))) { 1573 u16 preset; 1574 1575 sdhci_enable_preset_value(host, true); 1576 preset = sdhci_get_preset_value(host); 1577 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1578 >> SDHCI_PRESET_DRV_SHIFT; 1579 } 1580 1581 /* Re-enable SD Clock */ 1582 host->ops->set_clock(host, host->clock); 1583 } else 1584 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1585 1586 /* 1587 * Some (ENE) controllers go apeshit on some ios operation, 1588 * signalling timeout and CRC errors even on CMD0. Resetting 1589 * it on each ios seems to solve the problem. 1590 */ 1591 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1592 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1593 1594 mmiowb(); 1595 spin_unlock_irqrestore(&host->lock, flags); 1596} 1597 1598static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1599{ 1600 struct sdhci_host *host = mmc_priv(mmc); 1601 1602 sdhci_runtime_pm_get(host); 1603 sdhci_do_set_ios(host, ios); 1604 sdhci_runtime_pm_put(host); 1605} 1606 1607static int sdhci_do_get_cd(struct sdhci_host *host) 1608{ 1609 int gpio_cd = mmc_gpio_get_cd(host->mmc); 1610 1611 if (host->flags & SDHCI_DEVICE_DEAD) 1612 return 0; 1613 1614 /* If polling/nonremovable, assume that the card is always present. */ 1615 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 1616 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 1617 return 1; 1618 1619 /* Try slot gpio detect */ 1620 if (!IS_ERR_VALUE(gpio_cd)) 1621 return !!gpio_cd; 1622 1623 /* Host native card detect */ 1624 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1625} 1626 1627static int sdhci_get_cd(struct mmc_host *mmc) 1628{ 1629 struct sdhci_host *host = mmc_priv(mmc); 1630 int ret; 1631 1632 sdhci_runtime_pm_get(host); 1633 ret = sdhci_do_get_cd(host); 1634 sdhci_runtime_pm_put(host); 1635 return ret; 1636} 1637 1638static int sdhci_check_ro(struct sdhci_host *host) 1639{ 1640 unsigned long flags; 1641 int is_readonly; 1642 1643 spin_lock_irqsave(&host->lock, flags); 1644 1645 if (host->flags & SDHCI_DEVICE_DEAD) 1646 is_readonly = 0; 1647 else if (host->ops->get_ro) 1648 is_readonly = host->ops->get_ro(host); 1649 else 1650 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1651 & SDHCI_WRITE_PROTECT); 1652 1653 spin_unlock_irqrestore(&host->lock, flags); 1654 1655 /* This quirk needs to be replaced by a callback-function later */ 1656 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1657 !is_readonly : is_readonly; 1658} 1659 1660#define SAMPLE_COUNT 5 1661 1662static int sdhci_do_get_ro(struct sdhci_host *host) 1663{ 1664 int i, ro_count; 1665 1666 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1667 return sdhci_check_ro(host); 1668 1669 ro_count = 0; 1670 for (i = 0; i < SAMPLE_COUNT; i++) { 1671 if (sdhci_check_ro(host)) { 1672 if (++ro_count > SAMPLE_COUNT / 2) 1673 return 1; 1674 } 1675 msleep(30); 1676 } 1677 return 0; 1678} 1679 1680static void sdhci_hw_reset(struct mmc_host *mmc) 1681{ 1682 struct sdhci_host *host = mmc_priv(mmc); 1683 1684 if (host->ops && host->ops->hw_reset) 1685 host->ops->hw_reset(host); 1686} 1687 1688static int sdhci_get_ro(struct mmc_host *mmc) 1689{ 1690 struct sdhci_host *host = mmc_priv(mmc); 1691 int ret; 1692 1693 sdhci_runtime_pm_get(host); 1694 ret = sdhci_do_get_ro(host); 1695 sdhci_runtime_pm_put(host); 1696 return ret; 1697} 1698 1699static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1700{ 1701 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1702 if (enable) 1703 host->ier |= SDHCI_INT_CARD_INT; 1704 else 1705 host->ier &= ~SDHCI_INT_CARD_INT; 1706 1707 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1708 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1709 mmiowb(); 1710 } 1711} 1712 1713static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1714{ 1715 struct sdhci_host *host = mmc_priv(mmc); 1716 unsigned long flags; 1717 1718 sdhci_runtime_pm_get(host); 1719 1720 spin_lock_irqsave(&host->lock, flags); 1721 if (enable) 1722 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1723 else 1724 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1725 1726 sdhci_enable_sdio_irq_nolock(host, enable); 1727 spin_unlock_irqrestore(&host->lock, flags); 1728 1729 sdhci_runtime_pm_put(host); 1730} 1731 1732static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1733 struct mmc_ios *ios) 1734{ 1735 struct mmc_host *mmc = host->mmc; 1736 u16 ctrl; 1737 int ret; 1738 1739 /* 1740 * Signal Voltage Switching is only applicable for Host Controllers 1741 * v3.00 and above. 1742 */ 1743 if (host->version < SDHCI_SPEC_300) 1744 return 0; 1745 1746 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1747 1748 switch (ios->signal_voltage) { 1749 case MMC_SIGNAL_VOLTAGE_330: 1750 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1751 ctrl &= ~SDHCI_CTRL_VDD_180; 1752 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1753 1754 if (!IS_ERR(mmc->supply.vqmmc)) { 1755 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, 1756 3600000); 1757 if (ret) { 1758 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 1759 mmc_hostname(mmc)); 1760 return -EIO; 1761 } 1762 } 1763 /* Wait for 5ms */ 1764 usleep_range(5000, 5500); 1765 1766 /* 3.3V regulator output should be stable within 5 ms */ 1767 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1768 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1769 return 0; 1770 1771 pr_warn("%s: 3.3V regulator output did not became stable\n", 1772 mmc_hostname(mmc)); 1773 1774 return -EAGAIN; 1775 case MMC_SIGNAL_VOLTAGE_180: 1776 if (!IS_ERR(mmc->supply.vqmmc)) { 1777 ret = regulator_set_voltage(mmc->supply.vqmmc, 1778 1700000, 1950000); 1779 if (ret) { 1780 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 1781 mmc_hostname(mmc)); 1782 return -EIO; 1783 } 1784 } 1785 1786 /* 1787 * Enable 1.8V Signal Enable in the Host Control2 1788 * register 1789 */ 1790 ctrl |= SDHCI_CTRL_VDD_180; 1791 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1792 1793 /* 1.8V regulator output should be stable within 5 ms */ 1794 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1795 if (ctrl & SDHCI_CTRL_VDD_180) 1796 return 0; 1797 1798 pr_warn("%s: 1.8V regulator output did not became stable\n", 1799 mmc_hostname(mmc)); 1800 1801 return -EAGAIN; 1802 case MMC_SIGNAL_VOLTAGE_120: 1803 if (!IS_ERR(mmc->supply.vqmmc)) { 1804 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, 1805 1300000); 1806 if (ret) { 1807 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 1808 mmc_hostname(mmc)); 1809 return -EIO; 1810 } 1811 } 1812 return 0; 1813 default: 1814 /* No signal voltage switch required */ 1815 return 0; 1816 } 1817} 1818 1819static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1820 struct mmc_ios *ios) 1821{ 1822 struct sdhci_host *host = mmc_priv(mmc); 1823 int err; 1824 1825 if (host->version < SDHCI_SPEC_300) 1826 return 0; 1827 sdhci_runtime_pm_get(host); 1828 err = sdhci_do_start_signal_voltage_switch(host, ios); 1829 sdhci_runtime_pm_put(host); 1830 return err; 1831} 1832 1833static int sdhci_card_busy(struct mmc_host *mmc) 1834{ 1835 struct sdhci_host *host = mmc_priv(mmc); 1836 u32 present_state; 1837 1838 sdhci_runtime_pm_get(host); 1839 /* Check whether DAT[3:0] is 0000 */ 1840 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1841 sdhci_runtime_pm_put(host); 1842 1843 return !(present_state & SDHCI_DATA_LVL_MASK); 1844} 1845 1846static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1847{ 1848 struct sdhci_host *host = mmc_priv(mmc); 1849 u16 ctrl; 1850 int tuning_loop_counter = MAX_TUNING_LOOP; 1851 int err = 0; 1852 unsigned long flags; 1853 1854 sdhci_runtime_pm_get(host); 1855 spin_lock_irqsave(&host->lock, flags); 1856 1857 /* 1858 * The Host Controller needs tuning only in case of SDR104 mode 1859 * and for SDR50 mode when Use Tuning for SDR50 is set in the 1860 * Capabilities register. 1861 * If the Host Controller supports the HS200 mode then the 1862 * tuning function has to be executed. 1863 */ 1864 switch (host->timing) { 1865 case MMC_TIMING_MMC_HS200: 1866 case MMC_TIMING_UHS_SDR104: 1867 break; 1868 1869 case MMC_TIMING_UHS_SDR50: 1870 if (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1871 host->flags & SDHCI_SDR104_NEEDS_TUNING) 1872 break; 1873 /* FALLTHROUGH */ 1874 1875 default: 1876 spin_unlock_irqrestore(&host->lock, flags); 1877 sdhci_runtime_pm_put(host); 1878 return 0; 1879 } 1880 1881 if (host->ops->platform_execute_tuning) { 1882 spin_unlock_irqrestore(&host->lock, flags); 1883 err = host->ops->platform_execute_tuning(host, opcode); 1884 sdhci_runtime_pm_put(host); 1885 return err; 1886 } 1887 1888 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1889 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1890 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1891 1892 /* 1893 * As per the Host Controller spec v3.00, tuning command 1894 * generates Buffer Read Ready interrupt, so enable that. 1895 * 1896 * Note: The spec clearly says that when tuning sequence 1897 * is being performed, the controller does not generate 1898 * interrupts other than Buffer Read Ready interrupt. But 1899 * to make sure we don't hit a controller bug, we _only_ 1900 * enable Buffer Read Ready interrupt here. 1901 */ 1902 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1903 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1904 1905 /* 1906 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1907 * of loops reaches 40 times or a timeout of 150ms occurs. 1908 */ 1909 do { 1910 struct mmc_command cmd = {0}; 1911 struct mmc_request mrq = {NULL}; 1912 1913 cmd.opcode = opcode; 1914 cmd.arg = 0; 1915 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1916 cmd.retries = 0; 1917 cmd.data = NULL; 1918 cmd.error = 0; 1919 1920 if (tuning_loop_counter-- == 0) 1921 break; 1922 1923 mrq.cmd = &cmd; 1924 host->mrq = &mrq; 1925 1926 /* 1927 * In response to CMD19, the card sends 64 bytes of tuning 1928 * block to the Host Controller. So we set the block size 1929 * to 64 here. 1930 */ 1931 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1932 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1933 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1934 SDHCI_BLOCK_SIZE); 1935 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1936 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1937 SDHCI_BLOCK_SIZE); 1938 } else { 1939 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1940 SDHCI_BLOCK_SIZE); 1941 } 1942 1943 /* 1944 * The tuning block is sent by the card to the host controller. 1945 * So we set the TRNS_READ bit in the Transfer Mode register. 1946 * This also takes care of setting DMA Enable and Multi Block 1947 * Select in the same register to 0. 1948 */ 1949 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1950 1951 sdhci_send_command(host, &cmd); 1952 1953 host->cmd = NULL; 1954 host->mrq = NULL; 1955 1956 spin_unlock_irqrestore(&host->lock, flags); 1957 /* Wait for Buffer Read Ready interrupt */ 1958 wait_event_interruptible_timeout(host->buf_ready_int, 1959 (host->tuning_done == 1), 1960 msecs_to_jiffies(50)); 1961 spin_lock_irqsave(&host->lock, flags); 1962 1963 if (!host->tuning_done) { 1964 pr_info(DRIVER_NAME ": Timeout waiting for " 1965 "Buffer Read Ready interrupt during tuning " 1966 "procedure, falling back to fixed sampling " 1967 "clock\n"); 1968 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1969 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1970 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1971 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1972 1973 err = -EIO; 1974 goto out; 1975 } 1976 1977 host->tuning_done = 0; 1978 1979 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1980 1981 /* eMMC spec does not require a delay between tuning cycles */ 1982 if (opcode == MMC_SEND_TUNING_BLOCK) 1983 mdelay(1); 1984 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1985 1986 /* 1987 * The Host Driver has exhausted the maximum number of loops allowed, 1988 * so use fixed sampling frequency. 1989 */ 1990 if (tuning_loop_counter < 0) { 1991 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1992 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1993 } 1994 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1995 pr_info(DRIVER_NAME ": Tuning procedure" 1996 " failed, falling back to fixed sampling" 1997 " clock\n"); 1998 err = -EIO; 1999 } 2000 2001out: 2002 /* 2003 * If this is the very first time we are here, we start the retuning 2004 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 2005 * flag won't be set, we check this condition before actually starting 2006 * the timer. 2007 */ 2008 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 2009 (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 2010 host->flags |= SDHCI_USING_RETUNING_TIMER; 2011 mod_timer(&host->tuning_timer, jiffies + 2012 host->tuning_count * HZ); 2013 /* Tuning mode 1 limits the maximum data length to 4MB */ 2014 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 2015 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2016 host->flags &= ~SDHCI_NEEDS_RETUNING; 2017 /* Reload the new initial value for timer */ 2018 mod_timer(&host->tuning_timer, jiffies + 2019 host->tuning_count * HZ); 2020 } 2021 2022 /* 2023 * In case tuning fails, host controllers which support re-tuning can 2024 * try tuning again at a later time, when the re-tuning timer expires. 2025 * So for these controllers, we return 0. Since there might be other 2026 * controllers who do not have this capability, we return error for 2027 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 2028 * a retuning timer to do the retuning for the card. 2029 */ 2030 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 2031 err = 0; 2032 2033 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2034 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2035 spin_unlock_irqrestore(&host->lock, flags); 2036 sdhci_runtime_pm_put(host); 2037 2038 return err; 2039} 2040 2041 2042static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2043{ 2044 /* Host Controller v3.00 defines preset value registers */ 2045 if (host->version < SDHCI_SPEC_300) 2046 return; 2047 2048 /* 2049 * We only enable or disable Preset Value if they are not already 2050 * enabled or disabled respectively. Otherwise, we bail out. 2051 */ 2052 if (host->preset_enabled != enable) { 2053 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2054 2055 if (enable) 2056 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2057 else 2058 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2059 2060 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2061 2062 if (enable) 2063 host->flags |= SDHCI_PV_ENABLED; 2064 else 2065 host->flags &= ~SDHCI_PV_ENABLED; 2066 2067 host->preset_enabled = enable; 2068 } 2069} 2070 2071static void sdhci_card_event(struct mmc_host *mmc) 2072{ 2073 struct sdhci_host *host = mmc_priv(mmc); 2074 unsigned long flags; 2075 2076 /* First check if client has provided their own card event */ 2077 if (host->ops->card_event) 2078 host->ops->card_event(host); 2079 2080 spin_lock_irqsave(&host->lock, flags); 2081 2082 /* Check host->mrq first in case we are runtime suspended */ 2083 if (host->mrq && !sdhci_do_get_cd(host)) { 2084 pr_err("%s: Card removed during transfer!\n", 2085 mmc_hostname(host->mmc)); 2086 pr_err("%s: Resetting controller.\n", 2087 mmc_hostname(host->mmc)); 2088 2089 sdhci_do_reset(host, SDHCI_RESET_CMD); 2090 sdhci_do_reset(host, SDHCI_RESET_DATA); 2091 2092 host->mrq->cmd->error = -ENOMEDIUM; 2093 tasklet_schedule(&host->finish_tasklet); 2094 } 2095 2096 spin_unlock_irqrestore(&host->lock, flags); 2097} 2098 2099static const struct mmc_host_ops sdhci_ops = { 2100 .request = sdhci_request, 2101 .set_ios = sdhci_set_ios, 2102 .get_cd = sdhci_get_cd, 2103 .get_ro = sdhci_get_ro, 2104 .hw_reset = sdhci_hw_reset, 2105 .enable_sdio_irq = sdhci_enable_sdio_irq, 2106 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2107 .execute_tuning = sdhci_execute_tuning, 2108 .card_event = sdhci_card_event, 2109 .card_busy = sdhci_card_busy, 2110}; 2111 2112/*****************************************************************************\ 2113 * * 2114 * Tasklets * 2115 * * 2116\*****************************************************************************/ 2117 2118static void sdhci_tasklet_finish(unsigned long param) 2119{ 2120 struct sdhci_host *host; 2121 unsigned long flags; 2122 struct mmc_request *mrq; 2123 2124 host = (struct sdhci_host*)param; 2125 2126 spin_lock_irqsave(&host->lock, flags); 2127 2128 /* 2129 * If this tasklet gets rescheduled while running, it will 2130 * be run again afterwards but without any active request. 2131 */ 2132 if (!host->mrq) { 2133 spin_unlock_irqrestore(&host->lock, flags); 2134 return; 2135 } 2136 2137 del_timer(&host->timer); 2138 2139 mrq = host->mrq; 2140 2141 /* 2142 * The controller needs a reset of internal state machines 2143 * upon error conditions. 2144 */ 2145 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2146 ((mrq->cmd && mrq->cmd->error) || 2147 (mrq->data && (mrq->data->error || 2148 (mrq->data->stop && mrq->data->stop->error))) || 2149 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2150 2151 /* Some controllers need this kick or reset won't work here */ 2152 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2153 /* This is to force an update */ 2154 host->ops->set_clock(host, host->clock); 2155 2156 /* Spec says we should do both at the same time, but Ricoh 2157 controllers do not like that. */ 2158 sdhci_do_reset(host, SDHCI_RESET_CMD); 2159 sdhci_do_reset(host, SDHCI_RESET_DATA); 2160 } 2161 2162 host->mrq = NULL; 2163 host->cmd = NULL; 2164 host->data = NULL; 2165 2166#ifndef SDHCI_USE_LEDS_CLASS 2167 sdhci_deactivate_led(host); 2168#endif 2169 2170 mmiowb(); 2171 spin_unlock_irqrestore(&host->lock, flags); 2172 2173 mmc_request_done(host->mmc, mrq); 2174 sdhci_runtime_pm_put(host); 2175} 2176 2177static void sdhci_timeout_timer(unsigned long data) 2178{ 2179 struct sdhci_host *host; 2180 unsigned long flags; 2181 2182 host = (struct sdhci_host*)data; 2183 2184 spin_lock_irqsave(&host->lock, flags); 2185 2186 if (host->mrq) { 2187 pr_err("%s: Timeout waiting for hardware " 2188 "interrupt.\n", mmc_hostname(host->mmc)); 2189 sdhci_dumpregs(host); 2190 2191 if (host->data) { 2192 host->data->error = -ETIMEDOUT; 2193 sdhci_finish_data(host); 2194 } else { 2195 if (host->cmd) 2196 host->cmd->error = -ETIMEDOUT; 2197 else 2198 host->mrq->cmd->error = -ETIMEDOUT; 2199 2200 tasklet_schedule(&host->finish_tasklet); 2201 } 2202 } 2203 2204 mmiowb(); 2205 spin_unlock_irqrestore(&host->lock, flags); 2206} 2207 2208static void sdhci_tuning_timer(unsigned long data) 2209{ 2210 struct sdhci_host *host; 2211 unsigned long flags; 2212 2213 host = (struct sdhci_host *)data; 2214 2215 spin_lock_irqsave(&host->lock, flags); 2216 2217 host->flags |= SDHCI_NEEDS_RETUNING; 2218 2219 spin_unlock_irqrestore(&host->lock, flags); 2220} 2221 2222/*****************************************************************************\ 2223 * * 2224 * Interrupt handling * 2225 * * 2226\*****************************************************************************/ 2227 2228static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) 2229{ 2230 BUG_ON(intmask == 0); 2231 2232 if (!host->cmd) { 2233 pr_err("%s: Got command interrupt 0x%08x even " 2234 "though no command operation was in progress.\n", 2235 mmc_hostname(host->mmc), (unsigned)intmask); 2236 sdhci_dumpregs(host); 2237 return; 2238 } 2239 2240 if (intmask & SDHCI_INT_TIMEOUT) 2241 host->cmd->error = -ETIMEDOUT; 2242 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 2243 SDHCI_INT_INDEX)) 2244 host->cmd->error = -EILSEQ; 2245 2246 if (host->cmd->error) { 2247 tasklet_schedule(&host->finish_tasklet); 2248 return; 2249 } 2250 2251 /* 2252 * The host can send and interrupt when the busy state has 2253 * ended, allowing us to wait without wasting CPU cycles. 2254 * Unfortunately this is overloaded on the "data complete" 2255 * interrupt, so we need to take some care when handling 2256 * it. 2257 * 2258 * Note: The 1.0 specification is a bit ambiguous about this 2259 * feature so there might be some problems with older 2260 * controllers. 2261 */ 2262 if (host->cmd->flags & MMC_RSP_BUSY) { 2263 if (host->cmd->data) 2264 DBG("Cannot wait for busy signal when also " 2265 "doing a data transfer"); 2266 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) 2267 && !host->busy_handle) { 2268 /* Mark that command complete before busy is ended */ 2269 host->busy_handle = 1; 2270 return; 2271 } 2272 2273 /* The controller does not support the end-of-busy IRQ, 2274 * fall through and take the SDHCI_INT_RESPONSE */ 2275 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 2276 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) { 2277 *mask &= ~SDHCI_INT_DATA_END; 2278 } 2279 2280 if (intmask & SDHCI_INT_RESPONSE) 2281 sdhci_finish_command(host); 2282} 2283 2284#ifdef CONFIG_MMC_DEBUG 2285static void sdhci_show_adma_error(struct sdhci_host *host) 2286{ 2287 const char *name = mmc_hostname(host->mmc); 2288 u8 *desc = host->adma_desc; 2289 __le32 *dma; 2290 __le16 *len; 2291 u8 attr; 2292 2293 sdhci_dumpregs(host); 2294 2295 while (true) { 2296 dma = (__le32 *)(desc + 4); 2297 len = (__le16 *)(desc + 2); 2298 attr = *desc; 2299 2300 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2301 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 2302 2303 desc += 8; 2304 2305 if (attr & 2) 2306 break; 2307 } 2308} 2309#else 2310static void sdhci_show_adma_error(struct sdhci_host *host) { } 2311#endif 2312 2313static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2314{ 2315 u32 command; 2316 BUG_ON(intmask == 0); 2317 2318 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2319 if (intmask & SDHCI_INT_DATA_AVAIL) { 2320 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2321 if (command == MMC_SEND_TUNING_BLOCK || 2322 command == MMC_SEND_TUNING_BLOCK_HS200) { 2323 host->tuning_done = 1; 2324 wake_up(&host->buf_ready_int); 2325 return; 2326 } 2327 } 2328 2329 if (!host->data) { 2330 /* 2331 * The "data complete" interrupt is also used to 2332 * indicate that a busy state has ended. See comment 2333 * above in sdhci_cmd_irq(). 2334 */ 2335 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2336 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2337 host->cmd->error = -ETIMEDOUT; 2338 tasklet_schedule(&host->finish_tasklet); 2339 return; 2340 } 2341 if (intmask & SDHCI_INT_DATA_END) { 2342 /* 2343 * Some cards handle busy-end interrupt 2344 * before the command completed, so make 2345 * sure we do things in the proper order. 2346 */ 2347 if (host->busy_handle) 2348 sdhci_finish_command(host); 2349 else 2350 host->busy_handle = 1; 2351 return; 2352 } 2353 } 2354 2355 pr_err("%s: Got data interrupt 0x%08x even " 2356 "though no data operation was in progress.\n", 2357 mmc_hostname(host->mmc), (unsigned)intmask); 2358 sdhci_dumpregs(host); 2359 2360 return; 2361 } 2362 2363 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2364 host->data->error = -ETIMEDOUT; 2365 else if (intmask & SDHCI_INT_DATA_END_BIT) 2366 host->data->error = -EILSEQ; 2367 else if ((intmask & SDHCI_INT_DATA_CRC) && 2368 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2369 != MMC_BUS_TEST_R) 2370 host->data->error = -EILSEQ; 2371 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2372 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2373 sdhci_show_adma_error(host); 2374 host->data->error = -EIO; 2375 if (host->ops->adma_workaround) 2376 host->ops->adma_workaround(host, intmask); 2377 } 2378 2379 if (host->data->error) 2380 sdhci_finish_data(host); 2381 else { 2382 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2383 sdhci_transfer_pio(host); 2384 2385 /* 2386 * We currently don't do anything fancy with DMA 2387 * boundaries, but as we can't disable the feature 2388 * we need to at least restart the transfer. 2389 * 2390 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2391 * should return a valid address to continue from, but as 2392 * some controllers are faulty, don't trust them. 2393 */ 2394 if (intmask & SDHCI_INT_DMA_END) { 2395 u32 dmastart, dmanow; 2396 dmastart = sg_dma_address(host->data->sg); 2397 dmanow = dmastart + host->data->bytes_xfered; 2398 /* 2399 * Force update to the next DMA block boundary. 2400 */ 2401 dmanow = (dmanow & 2402 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2403 SDHCI_DEFAULT_BOUNDARY_SIZE; 2404 host->data->bytes_xfered = dmanow - dmastart; 2405 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2406 " next 0x%08x\n", 2407 mmc_hostname(host->mmc), dmastart, 2408 host->data->bytes_xfered, dmanow); 2409 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2410 } 2411 2412 if (intmask & SDHCI_INT_DATA_END) { 2413 if (host->cmd) { 2414 /* 2415 * Data managed to finish before the 2416 * command completed. Make sure we do 2417 * things in the proper order. 2418 */ 2419 host->data_early = 1; 2420 } else { 2421 sdhci_finish_data(host); 2422 } 2423 } 2424 } 2425} 2426 2427static irqreturn_t sdhci_irq(int irq, void *dev_id) 2428{ 2429 irqreturn_t result = IRQ_NONE; 2430 struct sdhci_host *host = dev_id; 2431 u32 intmask, mask, unexpected = 0; 2432 int max_loops = 16; 2433 2434 spin_lock(&host->lock); 2435 2436 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2437 spin_unlock(&host->lock); 2438 return IRQ_NONE; 2439 } 2440 2441 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2442 if (!intmask || intmask == 0xffffffff) { 2443 result = IRQ_NONE; 2444 goto out; 2445 } 2446 2447 do { 2448 /* Clear selected interrupts. */ 2449 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2450 SDHCI_INT_BUS_POWER); 2451 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2452 2453 DBG("*** %s got interrupt: 0x%08x\n", 2454 mmc_hostname(host->mmc), intmask); 2455 2456 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2457 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2458 SDHCI_CARD_PRESENT; 2459 2460 /* 2461 * There is a observation on i.mx esdhc. INSERT 2462 * bit will be immediately set again when it gets 2463 * cleared, if a card is inserted. We have to mask 2464 * the irq to prevent interrupt storm which will 2465 * freeze the system. And the REMOVE gets the 2466 * same situation. 2467 * 2468 * More testing are needed here to ensure it works 2469 * for other platforms though. 2470 */ 2471 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2472 SDHCI_INT_CARD_REMOVE); 2473 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2474 SDHCI_INT_CARD_INSERT; 2475 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2476 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2477 2478 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2479 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2480 2481 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2482 SDHCI_INT_CARD_REMOVE); 2483 result = IRQ_WAKE_THREAD; 2484 } 2485 2486 if (intmask & SDHCI_INT_CMD_MASK) 2487 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, 2488 &intmask); 2489 2490 if (intmask & SDHCI_INT_DATA_MASK) 2491 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2492 2493 if (intmask & SDHCI_INT_BUS_POWER) 2494 pr_err("%s: Card is consuming too much power!\n", 2495 mmc_hostname(host->mmc)); 2496 2497 if (intmask & SDHCI_INT_CARD_INT) { 2498 sdhci_enable_sdio_irq_nolock(host, false); 2499 host->thread_isr |= SDHCI_INT_CARD_INT; 2500 result = IRQ_WAKE_THREAD; 2501 } 2502 2503 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2504 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2505 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2506 SDHCI_INT_CARD_INT); 2507 2508 if (intmask) { 2509 unexpected |= intmask; 2510 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2511 } 2512 2513 if (result == IRQ_NONE) 2514 result = IRQ_HANDLED; 2515 2516 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2517 } while (intmask && --max_loops); 2518out: 2519 spin_unlock(&host->lock); 2520 2521 if (unexpected) { 2522 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2523 mmc_hostname(host->mmc), unexpected); 2524 sdhci_dumpregs(host); 2525 } 2526 2527 return result; 2528} 2529 2530static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2531{ 2532 struct sdhci_host *host = dev_id; 2533 unsigned long flags; 2534 u32 isr; 2535 2536 spin_lock_irqsave(&host->lock, flags); 2537 isr = host->thread_isr; 2538 host->thread_isr = 0; 2539 spin_unlock_irqrestore(&host->lock, flags); 2540 2541 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2542 sdhci_card_event(host->mmc); 2543 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2544 } 2545 2546 if (isr & SDHCI_INT_CARD_INT) { 2547 sdio_run_irqs(host->mmc); 2548 2549 spin_lock_irqsave(&host->lock, flags); 2550 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2551 sdhci_enable_sdio_irq_nolock(host, true); 2552 spin_unlock_irqrestore(&host->lock, flags); 2553 } 2554 2555 return isr ? IRQ_HANDLED : IRQ_NONE; 2556} 2557 2558/*****************************************************************************\ 2559 * * 2560 * Suspend/resume * 2561 * * 2562\*****************************************************************************/ 2563 2564#ifdef CONFIG_PM 2565void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2566{ 2567 u8 val; 2568 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2569 | SDHCI_WAKE_ON_INT; 2570 2571 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2572 val |= mask ; 2573 /* Avoid fake wake up */ 2574 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2575 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2576 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2577} 2578EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2579 2580static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2581{ 2582 u8 val; 2583 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2584 | SDHCI_WAKE_ON_INT; 2585 2586 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2587 val &= ~mask; 2588 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2589} 2590 2591int sdhci_suspend_host(struct sdhci_host *host) 2592{ 2593 sdhci_disable_card_detection(host); 2594 2595 /* Disable tuning since we are suspending */ 2596 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2597 del_timer_sync(&host->tuning_timer); 2598 host->flags &= ~SDHCI_NEEDS_RETUNING; 2599 } 2600 2601 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2602 host->ier = 0; 2603 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2604 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2605 free_irq(host->irq, host); 2606 } else { 2607 sdhci_enable_irq_wakeups(host); 2608 enable_irq_wake(host->irq); 2609 } 2610 return 0; 2611} 2612 2613EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2614 2615int sdhci_resume_host(struct sdhci_host *host) 2616{ 2617 int ret = 0; 2618 2619 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2620 if (host->ops->enable_dma) 2621 host->ops->enable_dma(host); 2622 } 2623 2624 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2625 ret = request_threaded_irq(host->irq, sdhci_irq, 2626 sdhci_thread_irq, IRQF_SHARED, 2627 mmc_hostname(host->mmc), host); 2628 if (ret) 2629 return ret; 2630 } else { 2631 sdhci_disable_irq_wakeups(host); 2632 disable_irq_wake(host->irq); 2633 } 2634 2635 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2636 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2637 /* Card keeps power but host controller does not */ 2638 sdhci_init(host, 0); 2639 host->pwr = 0; 2640 host->clock = 0; 2641 sdhci_do_set_ios(host, &host->mmc->ios); 2642 } else { 2643 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2644 mmiowb(); 2645 } 2646 2647 sdhci_enable_card_detection(host); 2648 2649 /* Set the re-tuning expiration flag */ 2650 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2651 host->flags |= SDHCI_NEEDS_RETUNING; 2652 2653 return ret; 2654} 2655 2656EXPORT_SYMBOL_GPL(sdhci_resume_host); 2657#endif /* CONFIG_PM */ 2658 2659#ifdef CONFIG_PM_RUNTIME 2660 2661static int sdhci_runtime_pm_get(struct sdhci_host *host) 2662{ 2663 return pm_runtime_get_sync(host->mmc->parent); 2664} 2665 2666static int sdhci_runtime_pm_put(struct sdhci_host *host) 2667{ 2668 pm_runtime_mark_last_busy(host->mmc->parent); 2669 return pm_runtime_put_autosuspend(host->mmc->parent); 2670} 2671 2672static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2673{ 2674 if (host->runtime_suspended || host->bus_on) 2675 return; 2676 host->bus_on = true; 2677 pm_runtime_get_noresume(host->mmc->parent); 2678} 2679 2680static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2681{ 2682 if (host->runtime_suspended || !host->bus_on) 2683 return; 2684 host->bus_on = false; 2685 pm_runtime_put_noidle(host->mmc->parent); 2686} 2687 2688int sdhci_runtime_suspend_host(struct sdhci_host *host) 2689{ 2690 unsigned long flags; 2691 2692 /* Disable tuning since we are suspending */ 2693 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2694 del_timer_sync(&host->tuning_timer); 2695 host->flags &= ~SDHCI_NEEDS_RETUNING; 2696 } 2697 2698 spin_lock_irqsave(&host->lock, flags); 2699 host->ier &= SDHCI_INT_CARD_INT; 2700 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2701 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2702 spin_unlock_irqrestore(&host->lock, flags); 2703 2704 synchronize_hardirq(host->irq); 2705 2706 spin_lock_irqsave(&host->lock, flags); 2707 host->runtime_suspended = true; 2708 spin_unlock_irqrestore(&host->lock, flags); 2709 2710 return 0; 2711} 2712EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2713 2714int sdhci_runtime_resume_host(struct sdhci_host *host) 2715{ 2716 unsigned long flags; 2717 int host_flags = host->flags; 2718 2719 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2720 if (host->ops->enable_dma) 2721 host->ops->enable_dma(host); 2722 } 2723 2724 sdhci_init(host, 0); 2725 2726 /* Force clock and power re-program */ 2727 host->pwr = 0; 2728 host->clock = 0; 2729 sdhci_do_set_ios(host, &host->mmc->ios); 2730 2731 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2732 if ((host_flags & SDHCI_PV_ENABLED) && 2733 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2734 spin_lock_irqsave(&host->lock, flags); 2735 sdhci_enable_preset_value(host, true); 2736 spin_unlock_irqrestore(&host->lock, flags); 2737 } 2738 2739 /* Set the re-tuning expiration flag */ 2740 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2741 host->flags |= SDHCI_NEEDS_RETUNING; 2742 2743 spin_lock_irqsave(&host->lock, flags); 2744 2745 host->runtime_suspended = false; 2746 2747 /* Enable SDIO IRQ */ 2748 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2749 sdhci_enable_sdio_irq_nolock(host, true); 2750 2751 /* Enable Card Detection */ 2752 sdhci_enable_card_detection(host); 2753 2754 spin_unlock_irqrestore(&host->lock, flags); 2755 2756 return 0; 2757} 2758EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2759 2760#endif 2761 2762/*****************************************************************************\ 2763 * * 2764 * Device allocation/registration * 2765 * * 2766\*****************************************************************************/ 2767 2768struct sdhci_host *sdhci_alloc_host(struct device *dev, 2769 size_t priv_size) 2770{ 2771 struct mmc_host *mmc; 2772 struct sdhci_host *host; 2773 2774 WARN_ON(dev == NULL); 2775 2776 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2777 if (!mmc) 2778 return ERR_PTR(-ENOMEM); 2779 2780 host = mmc_priv(mmc); 2781 host->mmc = mmc; 2782 2783 return host; 2784} 2785 2786EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2787 2788int sdhci_add_host(struct sdhci_host *host) 2789{ 2790 struct mmc_host *mmc; 2791 u32 caps[2] = {0, 0}; 2792 u32 max_current_caps; 2793 unsigned int ocr_avail; 2794 unsigned int override_timeout_clk; 2795 int ret; 2796 2797 WARN_ON(host == NULL); 2798 if (host == NULL) 2799 return -EINVAL; 2800 2801 mmc = host->mmc; 2802 2803 if (debug_quirks) 2804 host->quirks = debug_quirks; 2805 if (debug_quirks2) 2806 host->quirks2 = debug_quirks2; 2807 2808 override_timeout_clk = host->timeout_clk; 2809 2810 sdhci_do_reset(host, SDHCI_RESET_ALL); 2811 2812 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2813 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2814 >> SDHCI_SPEC_VER_SHIFT; 2815 if (host->version > SDHCI_SPEC_300) { 2816 pr_err("%s: Unknown controller version (%d). " 2817 "You may experience problems.\n", mmc_hostname(mmc), 2818 host->version); 2819 } 2820 2821 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2822 sdhci_readl(host, SDHCI_CAPABILITIES); 2823 2824 if (host->version >= SDHCI_SPEC_300) 2825 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2826 host->caps1 : 2827 sdhci_readl(host, SDHCI_CAPABILITIES_1); 2828 2829 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2830 host->flags |= SDHCI_USE_SDMA; 2831 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2832 DBG("Controller doesn't have SDMA capability\n"); 2833 else 2834 host->flags |= SDHCI_USE_SDMA; 2835 2836 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2837 (host->flags & SDHCI_USE_SDMA)) { 2838 DBG("Disabling DMA as it is marked broken\n"); 2839 host->flags &= ~SDHCI_USE_SDMA; 2840 } 2841 2842 if ((host->version >= SDHCI_SPEC_200) && 2843 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2844 host->flags |= SDHCI_USE_ADMA; 2845 2846 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2847 (host->flags & SDHCI_USE_ADMA)) { 2848 DBG("Disabling ADMA as it is marked broken\n"); 2849 host->flags &= ~SDHCI_USE_ADMA; 2850 } 2851 2852 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2853 if (host->ops->enable_dma) { 2854 if (host->ops->enable_dma(host)) { 2855 pr_warn("%s: No suitable DMA available - falling back to PIO\n", 2856 mmc_hostname(mmc)); 2857 host->flags &= 2858 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2859 } 2860 } 2861 } 2862 2863 if (host->flags & SDHCI_USE_ADMA) { 2864 /* 2865 * We need to allocate descriptors for all sg entries 2866 * (128) and potentially one alignment transfer for 2867 * each of those entries. 2868 */ 2869 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc), 2870 ADMA_SIZE, &host->adma_addr, 2871 GFP_KERNEL); 2872 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 2873 if (!host->adma_desc || !host->align_buffer) { 2874 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE, 2875 host->adma_desc, host->adma_addr); 2876 kfree(host->align_buffer); 2877 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 2878 mmc_hostname(mmc)); 2879 host->flags &= ~SDHCI_USE_ADMA; 2880 host->adma_desc = NULL; 2881 host->align_buffer = NULL; 2882 } else if (host->adma_addr & 3) { 2883 pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 2884 mmc_hostname(mmc)); 2885 host->flags &= ~SDHCI_USE_ADMA; 2886 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE, 2887 host->adma_desc, host->adma_addr); 2888 kfree(host->align_buffer); 2889 host->adma_desc = NULL; 2890 host->align_buffer = NULL; 2891 } 2892 } 2893 2894 /* 2895 * If we use DMA, then it's up to the caller to set the DMA 2896 * mask, but PIO does not need the hw shim so we set a new 2897 * mask here in that case. 2898 */ 2899 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2900 host->dma_mask = DMA_BIT_MASK(64); 2901 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2902 } 2903 2904 if (host->version >= SDHCI_SPEC_300) 2905 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2906 >> SDHCI_CLOCK_BASE_SHIFT; 2907 else 2908 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2909 >> SDHCI_CLOCK_BASE_SHIFT; 2910 2911 host->max_clk *= 1000000; 2912 if (host->max_clk == 0 || host->quirks & 2913 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2914 if (!host->ops->get_max_clock) { 2915 pr_err("%s: Hardware doesn't specify base clock " 2916 "frequency.\n", mmc_hostname(mmc)); 2917 return -ENODEV; 2918 } 2919 host->max_clk = host->ops->get_max_clock(host); 2920 } 2921 2922 /* 2923 * In case of Host Controller v3.00, find out whether clock 2924 * multiplier is supported. 2925 */ 2926 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2927 SDHCI_CLOCK_MUL_SHIFT; 2928 2929 /* 2930 * In case the value in Clock Multiplier is 0, then programmable 2931 * clock mode is not supported, otherwise the actual clock 2932 * multiplier is one more than the value of Clock Multiplier 2933 * in the Capabilities Register. 2934 */ 2935 if (host->clk_mul) 2936 host->clk_mul += 1; 2937 2938 /* 2939 * Set host parameters. 2940 */ 2941 mmc->ops = &sdhci_ops; 2942 mmc->f_max = host->max_clk; 2943 if (host->ops->get_min_clock) 2944 mmc->f_min = host->ops->get_min_clock(host); 2945 else if (host->version >= SDHCI_SPEC_300) { 2946 if (host->clk_mul) { 2947 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2948 mmc->f_max = host->max_clk * host->clk_mul; 2949 } else 2950 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2951 } else 2952 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 2953 2954 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2955 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> 2956 SDHCI_TIMEOUT_CLK_SHIFT; 2957 if (host->timeout_clk == 0) { 2958 if (host->ops->get_timeout_clock) { 2959 host->timeout_clk = 2960 host->ops->get_timeout_clock(host); 2961 } else { 2962 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 2963 mmc_hostname(mmc)); 2964 return -ENODEV; 2965 } 2966 } 2967 2968 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2969 host->timeout_clk *= 1000; 2970 2971 mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 2972 host->ops->get_max_timeout_count(host) : 1 << 27; 2973 mmc->max_busy_timeout /= host->timeout_clk; 2974 } 2975 2976 if (override_timeout_clk) 2977 host->timeout_clk = override_timeout_clk; 2978 2979 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2980 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2981 2982 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2983 host->flags |= SDHCI_AUTO_CMD12; 2984 2985 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 2986 if ((host->version >= SDHCI_SPEC_300) && 2987 ((host->flags & SDHCI_USE_ADMA) || 2988 !(host->flags & SDHCI_USE_SDMA))) { 2989 host->flags |= SDHCI_AUTO_CMD23; 2990 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 2991 } else { 2992 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 2993 } 2994 2995 /* 2996 * A controller may support 8-bit width, but the board itself 2997 * might not have the pins brought out. Boards that support 2998 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 2999 * their platform code before calling sdhci_add_host(), and we 3000 * won't assume 8-bit width for hosts without that CAP. 3001 */ 3002 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 3003 mmc->caps |= MMC_CAP_4_BIT_DATA; 3004 3005 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3006 mmc->caps &= ~MMC_CAP_CMD23; 3007 3008 if (caps[0] & SDHCI_CAN_DO_HISPD) 3009 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3010 3011 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3012 !(mmc->caps & MMC_CAP_NONREMOVABLE)) 3013 mmc->caps |= MMC_CAP_NEEDS_POLL; 3014 3015 /* If there are external regulators, get them */ 3016 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) 3017 return -EPROBE_DEFER; 3018 3019 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 3020 if (!IS_ERR(mmc->supply.vqmmc)) { 3021 ret = regulator_enable(mmc->supply.vqmmc); 3022 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3023 1950000)) 3024 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 3025 SDHCI_SUPPORT_SDR50 | 3026 SDHCI_SUPPORT_DDR50); 3027 if (ret) { 3028 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3029 mmc_hostname(mmc), ret); 3030 mmc->supply.vqmmc = NULL; 3031 } 3032 } 3033 3034 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 3035 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3036 SDHCI_SUPPORT_DDR50); 3037 3038 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3039 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3040 SDHCI_SUPPORT_DDR50)) 3041 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3042 3043 /* SDR104 supports also implies SDR50 support */ 3044 if (caps[1] & SDHCI_SUPPORT_SDR104) { 3045 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3046 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3047 * field can be promoted to support HS200. 3048 */ 3049 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) { 3050 mmc->caps2 |= MMC_CAP2_HS200; 3051 if (IS_ERR(mmc->supply.vqmmc) || 3052 !regulator_is_supported_voltage 3053 (mmc->supply.vqmmc, 1100000, 1300000)) 3054 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR; 3055 } 3056 } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3057 mmc->caps |= MMC_CAP_UHS_SDR50; 3058 3059 if ((caps[1] & SDHCI_SUPPORT_DDR50) && 3060 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3061 mmc->caps |= MMC_CAP_UHS_DDR50; 3062 3063 /* Does the host need tuning for SDR50? */ 3064 if (caps[1] & SDHCI_USE_SDR50_TUNING) 3065 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3066 3067 /* Does the host need tuning for SDR104 / HS200? */ 3068 if (mmc->caps2 & MMC_CAP2_HS200) 3069 host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3070 3071 /* Driver Type(s) (A, C, D) supported by the host */ 3072 if (caps[1] & SDHCI_DRIVER_TYPE_A) 3073 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3074 if (caps[1] & SDHCI_DRIVER_TYPE_C) 3075 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3076 if (caps[1] & SDHCI_DRIVER_TYPE_D) 3077 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3078 3079 /* Initial value for re-tuning timer count */ 3080 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3081 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3082 3083 /* 3084 * In case Re-tuning Timer is not disabled, the actual value of 3085 * re-tuning timer will be 2 ^ (n - 1). 3086 */ 3087 if (host->tuning_count) 3088 host->tuning_count = 1 << (host->tuning_count - 1); 3089 3090 /* Re-tuning mode supported by the Host Controller */ 3091 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3092 SDHCI_RETUNING_MODE_SHIFT; 3093 3094 ocr_avail = 0; 3095 3096 /* 3097 * According to SD Host Controller spec v3.00, if the Host System 3098 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3099 * the value is meaningful only if Voltage Support in the Capabilities 3100 * register is set. The actual current value is 4 times the register 3101 * value. 3102 */ 3103 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3104 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3105 int curr = regulator_get_current_limit(mmc->supply.vmmc); 3106 if (curr > 0) { 3107 3108 /* convert to SDHCI_MAX_CURRENT format */ 3109 curr = curr/1000; /* convert to mA */ 3110 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3111 3112 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3113 max_current_caps = 3114 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3115 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3116 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3117 } 3118 } 3119 3120 if (caps[0] & SDHCI_CAN_VDD_330) { 3121 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3122 3123 mmc->max_current_330 = ((max_current_caps & 3124 SDHCI_MAX_CURRENT_330_MASK) >> 3125 SDHCI_MAX_CURRENT_330_SHIFT) * 3126 SDHCI_MAX_CURRENT_MULTIPLIER; 3127 } 3128 if (caps[0] & SDHCI_CAN_VDD_300) { 3129 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3130 3131 mmc->max_current_300 = ((max_current_caps & 3132 SDHCI_MAX_CURRENT_300_MASK) >> 3133 SDHCI_MAX_CURRENT_300_SHIFT) * 3134 SDHCI_MAX_CURRENT_MULTIPLIER; 3135 } 3136 if (caps[0] & SDHCI_CAN_VDD_180) { 3137 ocr_avail |= MMC_VDD_165_195; 3138 3139 mmc->max_current_180 = ((max_current_caps & 3140 SDHCI_MAX_CURRENT_180_MASK) >> 3141 SDHCI_MAX_CURRENT_180_SHIFT) * 3142 SDHCI_MAX_CURRENT_MULTIPLIER; 3143 } 3144 3145 /* If OCR set by external regulators, use it instead */ 3146 if (mmc->ocr_avail) 3147 ocr_avail = mmc->ocr_avail; 3148 3149 if (host->ocr_mask) 3150 ocr_avail &= host->ocr_mask; 3151 3152 mmc->ocr_avail = ocr_avail; 3153 mmc->ocr_avail_sdio = ocr_avail; 3154 if (host->ocr_avail_sdio) 3155 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3156 mmc->ocr_avail_sd = ocr_avail; 3157 if (host->ocr_avail_sd) 3158 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3159 else /* normal SD controllers don't support 1.8V */ 3160 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3161 mmc->ocr_avail_mmc = ocr_avail; 3162 if (host->ocr_avail_mmc) 3163 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3164 3165 if (mmc->ocr_avail == 0) { 3166 pr_err("%s: Hardware doesn't report any " 3167 "support voltages.\n", mmc_hostname(mmc)); 3168 return -ENODEV; 3169 } 3170 3171 spin_lock_init(&host->lock); 3172 3173 /* 3174 * Maximum number of segments. Depends on if the hardware 3175 * can do scatter/gather or not. 3176 */ 3177 if (host->flags & SDHCI_USE_ADMA) 3178 mmc->max_segs = 128; 3179 else if (host->flags & SDHCI_USE_SDMA) 3180 mmc->max_segs = 1; 3181 else /* PIO */ 3182 mmc->max_segs = 128; 3183 3184 /* 3185 * Maximum number of sectors in one transfer. Limited by DMA boundary 3186 * size (512KiB). 3187 */ 3188 mmc->max_req_size = 524288; 3189 3190 /* 3191 * Maximum segment size. Could be one segment with the maximum number 3192 * of bytes. When doing hardware scatter/gather, each entry cannot 3193 * be larger than 64 KiB though. 3194 */ 3195 if (host->flags & SDHCI_USE_ADMA) { 3196 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3197 mmc->max_seg_size = 65535; 3198 else 3199 mmc->max_seg_size = 65536; 3200 } else { 3201 mmc->max_seg_size = mmc->max_req_size; 3202 } 3203 3204 /* 3205 * Maximum block size. This varies from controller to controller and 3206 * is specified in the capabilities register. 3207 */ 3208 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3209 mmc->max_blk_size = 2; 3210 } else { 3211 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3212 SDHCI_MAX_BLOCK_SHIFT; 3213 if (mmc->max_blk_size >= 3) { 3214 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 3215 mmc_hostname(mmc)); 3216 mmc->max_blk_size = 0; 3217 } 3218 } 3219 3220 mmc->max_blk_size = 512 << mmc->max_blk_size; 3221 3222 /* 3223 * Maximum block count. 3224 */ 3225 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3226 3227 /* 3228 * Init tasklets. 3229 */ 3230 tasklet_init(&host->finish_tasklet, 3231 sdhci_tasklet_finish, (unsigned long)host); 3232 3233 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3234 3235 if (host->version >= SDHCI_SPEC_300) { 3236 init_waitqueue_head(&host->buf_ready_int); 3237 3238 /* Initialize re-tuning timer */ 3239 init_timer(&host->tuning_timer); 3240 host->tuning_timer.data = (unsigned long)host; 3241 host->tuning_timer.function = sdhci_tuning_timer; 3242 } 3243 3244 sdhci_init(host, 0); 3245 3246 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3247 IRQF_SHARED, mmc_hostname(mmc), host); 3248 if (ret) { 3249 pr_err("%s: Failed to request IRQ %d: %d\n", 3250 mmc_hostname(mmc), host->irq, ret); 3251 goto untasklet; 3252 } 3253 3254#ifdef CONFIG_MMC_DEBUG 3255 sdhci_dumpregs(host); 3256#endif 3257 3258#ifdef SDHCI_USE_LEDS_CLASS 3259 snprintf(host->led_name, sizeof(host->led_name), 3260 "%s::", mmc_hostname(mmc)); 3261 host->led.name = host->led_name; 3262 host->led.brightness = LED_OFF; 3263 host->led.default_trigger = mmc_hostname(mmc); 3264 host->led.brightness_set = sdhci_led_control; 3265 3266 ret = led_classdev_register(mmc_dev(mmc), &host->led); 3267 if (ret) { 3268 pr_err("%s: Failed to register LED device: %d\n", 3269 mmc_hostname(mmc), ret); 3270 goto reset; 3271 } 3272#endif 3273 3274 mmiowb(); 3275 3276 mmc_add_host(mmc); 3277 3278 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3279 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3280 (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3281 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3282 3283 sdhci_enable_card_detection(host); 3284 3285 return 0; 3286 3287#ifdef SDHCI_USE_LEDS_CLASS 3288reset: 3289 sdhci_do_reset(host, SDHCI_RESET_ALL); 3290 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3291 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3292 free_irq(host->irq, host); 3293#endif 3294untasklet: 3295 tasklet_kill(&host->finish_tasklet); 3296 3297 return ret; 3298} 3299 3300EXPORT_SYMBOL_GPL(sdhci_add_host); 3301 3302void sdhci_remove_host(struct sdhci_host *host, int dead) 3303{ 3304 struct mmc_host *mmc = host->mmc; 3305 unsigned long flags; 3306 3307 if (dead) { 3308 spin_lock_irqsave(&host->lock, flags); 3309 3310 host->flags |= SDHCI_DEVICE_DEAD; 3311 3312 if (host->mrq) { 3313 pr_err("%s: Controller removed during " 3314 " transfer!\n", mmc_hostname(mmc)); 3315 3316 host->mrq->cmd->error = -ENOMEDIUM; 3317 tasklet_schedule(&host->finish_tasklet); 3318 } 3319 3320 spin_unlock_irqrestore(&host->lock, flags); 3321 } 3322 3323 sdhci_disable_card_detection(host); 3324 3325 mmc_remove_host(mmc); 3326 3327#ifdef SDHCI_USE_LEDS_CLASS 3328 led_classdev_unregister(&host->led); 3329#endif 3330 3331 if (!dead) 3332 sdhci_do_reset(host, SDHCI_RESET_ALL); 3333 3334 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3335 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3336 free_irq(host->irq, host); 3337 3338 del_timer_sync(&host->timer); 3339 3340 tasklet_kill(&host->finish_tasklet); 3341 3342 if (!IS_ERR(mmc->supply.vmmc)) 3343 regulator_disable(mmc->supply.vmmc); 3344 3345 if (!IS_ERR(mmc->supply.vqmmc)) 3346 regulator_disable(mmc->supply.vqmmc); 3347 3348 if (host->adma_desc) 3349 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE, 3350 host->adma_desc, host->adma_addr); 3351 kfree(host->align_buffer); 3352 3353 host->adma_desc = NULL; 3354 host->align_buffer = NULL; 3355} 3356 3357EXPORT_SYMBOL_GPL(sdhci_remove_host); 3358 3359void sdhci_free_host(struct sdhci_host *host) 3360{ 3361 mmc_free_host(host->mmc); 3362} 3363 3364EXPORT_SYMBOL_GPL(sdhci_free_host); 3365 3366/*****************************************************************************\ 3367 * * 3368 * Driver init/exit * 3369 * * 3370\*****************************************************************************/ 3371 3372static int __init sdhci_drv_init(void) 3373{ 3374 pr_info(DRIVER_NAME 3375 ": Secure Digital Host Controller Interface driver\n"); 3376 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3377 3378 return 0; 3379} 3380 3381static void __exit sdhci_drv_exit(void) 3382{ 3383} 3384 3385module_init(sdhci_drv_init); 3386module_exit(sdhci_drv_exit); 3387 3388module_param(debug_quirks, uint, 0444); 3389module_param(debug_quirks2, uint, 0444); 3390 3391MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3392MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3393MODULE_LICENSE("GPL"); 3394 3395MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3396MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3397