sdhci.c revision 20b92a30b5610a5222060417961bc4ccb42ea5a5
1/* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16#include <linux/delay.h> 17#include <linux/highmem.h> 18#include <linux/io.h> 19#include <linux/module.h> 20#include <linux/dma-mapping.h> 21#include <linux/slab.h> 22#include <linux/scatterlist.h> 23#include <linux/regulator/consumer.h> 24#include <linux/pm_runtime.h> 25 26#include <linux/leds.h> 27 28#include <linux/mmc/mmc.h> 29#include <linux/mmc/host.h> 30#include <linux/mmc/card.h> 31#include <linux/mmc/slot-gpio.h> 32 33#include "sdhci.h" 34 35#define DRIVER_NAME "sdhci" 36 37#define DBG(f, x...) \ 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 39 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41 defined(CONFIG_MMC_SDHCI_MODULE)) 42#define SDHCI_USE_LEDS_CLASS 43#endif 44 45#define MAX_TUNING_LOOP 40 46 47static unsigned int debug_quirks = 0; 48static unsigned int debug_quirks2; 49 50static void sdhci_finish_data(struct sdhci_host *); 51 52static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); 53static void sdhci_finish_command(struct sdhci_host *); 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 55static void sdhci_tuning_timer(unsigned long data); 56 57#ifdef CONFIG_PM_RUNTIME 58static int sdhci_runtime_pm_get(struct sdhci_host *host); 59static int sdhci_runtime_pm_put(struct sdhci_host *host); 60#else 61static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 62{ 63 return 0; 64} 65static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 66{ 67 return 0; 68} 69#endif 70 71static void sdhci_dumpregs(struct sdhci_host *host) 72{ 73 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 74 mmc_hostname(host->mmc)); 75 76 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 77 sdhci_readl(host, SDHCI_DMA_ADDRESS), 78 sdhci_readw(host, SDHCI_HOST_VERSION)); 79 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 80 sdhci_readw(host, SDHCI_BLOCK_SIZE), 81 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 82 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 83 sdhci_readl(host, SDHCI_ARGUMENT), 84 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 85 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 86 sdhci_readl(host, SDHCI_PRESENT_STATE), 87 sdhci_readb(host, SDHCI_HOST_CONTROL)); 88 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 89 sdhci_readb(host, SDHCI_POWER_CONTROL), 90 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 91 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 92 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 93 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 94 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 95 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 96 sdhci_readl(host, SDHCI_INT_STATUS)); 97 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 98 sdhci_readl(host, SDHCI_INT_ENABLE), 99 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 100 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 101 sdhci_readw(host, SDHCI_ACMD12_ERR), 102 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 103 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 104 sdhci_readl(host, SDHCI_CAPABILITIES), 105 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 106 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 107 sdhci_readw(host, SDHCI_COMMAND), 108 sdhci_readl(host, SDHCI_MAX_CURRENT)); 109 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 110 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 111 112 if (host->flags & SDHCI_USE_ADMA) 113 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 114 readl(host->ioaddr + SDHCI_ADMA_ERROR), 115 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 116 117 pr_debug(DRIVER_NAME ": ===========================================\n"); 118} 119 120/*****************************************************************************\ 121 * * 122 * Low level functions * 123 * * 124\*****************************************************************************/ 125 126static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) 127{ 128 u32 ier; 129 130 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 131 ier &= ~clear; 132 ier |= set; 133 sdhci_writel(host, ier, SDHCI_INT_ENABLE); 134 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 135} 136 137static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) 138{ 139 sdhci_clear_set_irqs(host, 0, irqs); 140} 141 142static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) 143{ 144 sdhci_clear_set_irqs(host, irqs, 0); 145} 146 147static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 148{ 149 u32 present, irqs; 150 151 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 152 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 153 return; 154 155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 156 SDHCI_CARD_PRESENT; 157 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; 158 159 if (enable) 160 sdhci_unmask_irqs(host, irqs); 161 else 162 sdhci_mask_irqs(host, irqs); 163} 164 165static void sdhci_enable_card_detection(struct sdhci_host *host) 166{ 167 sdhci_set_card_detection(host, true); 168} 169 170static void sdhci_disable_card_detection(struct sdhci_host *host) 171{ 172 sdhci_set_card_detection(host, false); 173} 174 175static void sdhci_reset(struct sdhci_host *host, u8 mask) 176{ 177 unsigned long timeout; 178 u32 uninitialized_var(ier); 179 180 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 181 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 182 SDHCI_CARD_PRESENT)) 183 return; 184 } 185 186 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 187 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 188 189 if (host->ops->platform_reset_enter) 190 host->ops->platform_reset_enter(host, mask); 191 192 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 193 194 if (mask & SDHCI_RESET_ALL) 195 host->clock = 0; 196 197 /* Wait max 100 ms */ 198 timeout = 100; 199 200 /* hw clears the bit when it's done */ 201 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 202 if (timeout == 0) { 203 pr_err("%s: Reset 0x%x never completed.\n", 204 mmc_hostname(host->mmc), (int)mask); 205 sdhci_dumpregs(host); 206 return; 207 } 208 timeout--; 209 mdelay(1); 210 } 211 212 if (host->ops->platform_reset_exit) 213 host->ops->platform_reset_exit(host, mask); 214 215 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 216 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); 217 218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 219 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) 220 host->ops->enable_dma(host); 221 } 222} 223 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 225 226static void sdhci_init(struct sdhci_host *host, int soft) 227{ 228 if (soft) 229 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 230 else 231 sdhci_reset(host, SDHCI_RESET_ALL); 232 233 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, 234 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 235 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 236 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 237 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); 238 239 if (soft) { 240 /* force clock reconfiguration */ 241 host->clock = 0; 242 sdhci_set_ios(host->mmc, &host->mmc->ios); 243 } 244} 245 246static void sdhci_reinit(struct sdhci_host *host) 247{ 248 sdhci_init(host, 0); 249 /* 250 * Retuning stuffs are affected by different cards inserted and only 251 * applicable to UHS-I cards. So reset these fields to their initial 252 * value when card is removed. 253 */ 254 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 255 host->flags &= ~SDHCI_USING_RETUNING_TIMER; 256 257 del_timer_sync(&host->tuning_timer); 258 host->flags &= ~SDHCI_NEEDS_RETUNING; 259 host->mmc->max_blk_count = 260 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 261 } 262 sdhci_enable_card_detection(host); 263} 264 265static void sdhci_activate_led(struct sdhci_host *host) 266{ 267 u8 ctrl; 268 269 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 270 ctrl |= SDHCI_CTRL_LED; 271 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 272} 273 274static void sdhci_deactivate_led(struct sdhci_host *host) 275{ 276 u8 ctrl; 277 278 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 279 ctrl &= ~SDHCI_CTRL_LED; 280 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 281} 282 283#ifdef SDHCI_USE_LEDS_CLASS 284static void sdhci_led_control(struct led_classdev *led, 285 enum led_brightness brightness) 286{ 287 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 288 unsigned long flags; 289 290 spin_lock_irqsave(&host->lock, flags); 291 292 if (host->runtime_suspended) 293 goto out; 294 295 if (brightness == LED_OFF) 296 sdhci_deactivate_led(host); 297 else 298 sdhci_activate_led(host); 299out: 300 spin_unlock_irqrestore(&host->lock, flags); 301} 302#endif 303 304/*****************************************************************************\ 305 * * 306 * Core functions * 307 * * 308\*****************************************************************************/ 309 310static void sdhci_read_block_pio(struct sdhci_host *host) 311{ 312 unsigned long flags; 313 size_t blksize, len, chunk; 314 u32 uninitialized_var(scratch); 315 u8 *buf; 316 317 DBG("PIO reading\n"); 318 319 blksize = host->data->blksz; 320 chunk = 0; 321 322 local_irq_save(flags); 323 324 while (blksize) { 325 if (!sg_miter_next(&host->sg_miter)) 326 BUG(); 327 328 len = min(host->sg_miter.length, blksize); 329 330 blksize -= len; 331 host->sg_miter.consumed = len; 332 333 buf = host->sg_miter.addr; 334 335 while (len) { 336 if (chunk == 0) { 337 scratch = sdhci_readl(host, SDHCI_BUFFER); 338 chunk = 4; 339 } 340 341 *buf = scratch & 0xFF; 342 343 buf++; 344 scratch >>= 8; 345 chunk--; 346 len--; 347 } 348 } 349 350 sg_miter_stop(&host->sg_miter); 351 352 local_irq_restore(flags); 353} 354 355static void sdhci_write_block_pio(struct sdhci_host *host) 356{ 357 unsigned long flags; 358 size_t blksize, len, chunk; 359 u32 scratch; 360 u8 *buf; 361 362 DBG("PIO writing\n"); 363 364 blksize = host->data->blksz; 365 chunk = 0; 366 scratch = 0; 367 368 local_irq_save(flags); 369 370 while (blksize) { 371 if (!sg_miter_next(&host->sg_miter)) 372 BUG(); 373 374 len = min(host->sg_miter.length, blksize); 375 376 blksize -= len; 377 host->sg_miter.consumed = len; 378 379 buf = host->sg_miter.addr; 380 381 while (len) { 382 scratch |= (u32)*buf << (chunk * 8); 383 384 buf++; 385 chunk++; 386 len--; 387 388 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 389 sdhci_writel(host, scratch, SDHCI_BUFFER); 390 chunk = 0; 391 scratch = 0; 392 } 393 } 394 } 395 396 sg_miter_stop(&host->sg_miter); 397 398 local_irq_restore(flags); 399} 400 401static void sdhci_transfer_pio(struct sdhci_host *host) 402{ 403 u32 mask; 404 405 BUG_ON(!host->data); 406 407 if (host->blocks == 0) 408 return; 409 410 if (host->data->flags & MMC_DATA_READ) 411 mask = SDHCI_DATA_AVAILABLE; 412 else 413 mask = SDHCI_SPACE_AVAILABLE; 414 415 /* 416 * Some controllers (JMicron JMB38x) mess up the buffer bits 417 * for transfers < 4 bytes. As long as it is just one block, 418 * we can ignore the bits. 419 */ 420 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 421 (host->data->blocks == 1)) 422 mask = ~0; 423 424 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 425 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 426 udelay(100); 427 428 if (host->data->flags & MMC_DATA_READ) 429 sdhci_read_block_pio(host); 430 else 431 sdhci_write_block_pio(host); 432 433 host->blocks--; 434 if (host->blocks == 0) 435 break; 436 } 437 438 DBG("PIO transfer complete.\n"); 439} 440 441static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 442{ 443 local_irq_save(*flags); 444 return kmap_atomic(sg_page(sg)) + sg->offset; 445} 446 447static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 448{ 449 kunmap_atomic(buffer); 450 local_irq_restore(*flags); 451} 452 453static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 454{ 455 __le32 *dataddr = (__le32 __force *)(desc + 4); 456 __le16 *cmdlen = (__le16 __force *)desc; 457 458 /* SDHCI specification says ADMA descriptors should be 4 byte 459 * aligned, so using 16 or 32bit operations should be safe. */ 460 461 cmdlen[0] = cpu_to_le16(cmd); 462 cmdlen[1] = cpu_to_le16(len); 463 464 dataddr[0] = cpu_to_le32(addr); 465} 466 467static int sdhci_adma_table_pre(struct sdhci_host *host, 468 struct mmc_data *data) 469{ 470 int direction; 471 472 u8 *desc; 473 u8 *align; 474 dma_addr_t addr; 475 dma_addr_t align_addr; 476 int len, offset; 477 478 struct scatterlist *sg; 479 int i; 480 char *buffer; 481 unsigned long flags; 482 483 /* 484 * The spec does not specify endianness of descriptor table. 485 * We currently guess that it is LE. 486 */ 487 488 if (data->flags & MMC_DATA_READ) 489 direction = DMA_FROM_DEVICE; 490 else 491 direction = DMA_TO_DEVICE; 492 493 /* 494 * The ADMA descriptor table is mapped further down as we 495 * need to fill it with data first. 496 */ 497 498 host->align_addr = dma_map_single(mmc_dev(host->mmc), 499 host->align_buffer, 128 * 4, direction); 500 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 501 goto fail; 502 BUG_ON(host->align_addr & 0x3); 503 504 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 505 data->sg, data->sg_len, direction); 506 if (host->sg_count == 0) 507 goto unmap_align; 508 509 desc = host->adma_desc; 510 align = host->align_buffer; 511 512 align_addr = host->align_addr; 513 514 for_each_sg(data->sg, sg, host->sg_count, i) { 515 addr = sg_dma_address(sg); 516 len = sg_dma_len(sg); 517 518 /* 519 * The SDHCI specification states that ADMA 520 * addresses must be 32-bit aligned. If they 521 * aren't, then we use a bounce buffer for 522 * the (up to three) bytes that screw up the 523 * alignment. 524 */ 525 offset = (4 - (addr & 0x3)) & 0x3; 526 if (offset) { 527 if (data->flags & MMC_DATA_WRITE) { 528 buffer = sdhci_kmap_atomic(sg, &flags); 529 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 530 memcpy(align, buffer, offset); 531 sdhci_kunmap_atomic(buffer, &flags); 532 } 533 534 /* tran, valid */ 535 sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 536 537 BUG_ON(offset > 65536); 538 539 align += 4; 540 align_addr += 4; 541 542 desc += 8; 543 544 addr += offset; 545 len -= offset; 546 } 547 548 BUG_ON(len > 65536); 549 550 /* tran, valid */ 551 sdhci_set_adma_desc(desc, addr, len, 0x21); 552 desc += 8; 553 554 /* 555 * If this triggers then we have a calculation bug 556 * somewhere. :/ 557 */ 558 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); 559 } 560 561 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 562 /* 563 * Mark the last descriptor as the terminating descriptor 564 */ 565 if (desc != host->adma_desc) { 566 desc -= 8; 567 desc[0] |= 0x2; /* end */ 568 } 569 } else { 570 /* 571 * Add a terminating entry. 572 */ 573 574 /* nop, end, valid */ 575 sdhci_set_adma_desc(desc, 0, 0, 0x3); 576 } 577 578 /* 579 * Resync align buffer as we might have changed it. 580 */ 581 if (data->flags & MMC_DATA_WRITE) { 582 dma_sync_single_for_device(mmc_dev(host->mmc), 583 host->align_addr, 128 * 4, direction); 584 } 585 586 host->adma_addr = dma_map_single(mmc_dev(host->mmc), 587 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); 588 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) 589 goto unmap_entries; 590 BUG_ON(host->adma_addr & 0x3); 591 592 return 0; 593 594unmap_entries: 595 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 596 data->sg_len, direction); 597unmap_align: 598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 599 128 * 4, direction); 600fail: 601 return -EINVAL; 602} 603 604static void sdhci_adma_table_post(struct sdhci_host *host, 605 struct mmc_data *data) 606{ 607 int direction; 608 609 struct scatterlist *sg; 610 int i, size; 611 u8 *align; 612 char *buffer; 613 unsigned long flags; 614 615 if (data->flags & MMC_DATA_READ) 616 direction = DMA_FROM_DEVICE; 617 else 618 direction = DMA_TO_DEVICE; 619 620 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, 621 (128 * 2 + 1) * 4, DMA_TO_DEVICE); 622 623 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 624 128 * 4, direction); 625 626 if (data->flags & MMC_DATA_READ) { 627 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 628 data->sg_len, direction); 629 630 align = host->align_buffer; 631 632 for_each_sg(data->sg, sg, host->sg_count, i) { 633 if (sg_dma_address(sg) & 0x3) { 634 size = 4 - (sg_dma_address(sg) & 0x3); 635 636 buffer = sdhci_kmap_atomic(sg, &flags); 637 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 638 memcpy(buffer, align, size); 639 sdhci_kunmap_atomic(buffer, &flags); 640 641 align += 4; 642 } 643 } 644 } 645 646 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 647 data->sg_len, direction); 648} 649 650static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 651{ 652 u8 count; 653 struct mmc_data *data = cmd->data; 654 unsigned target_timeout, current_timeout; 655 656 /* 657 * If the host controller provides us with an incorrect timeout 658 * value, just skip the check and use 0xE. The hardware may take 659 * longer to time out, but that's much better than having a too-short 660 * timeout value. 661 */ 662 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 663 return 0xE; 664 665 /* Unspecified timeout, assume max */ 666 if (!data && !cmd->cmd_timeout_ms) 667 return 0xE; 668 669 /* timeout in us */ 670 if (!data) 671 target_timeout = cmd->cmd_timeout_ms * 1000; 672 else { 673 target_timeout = data->timeout_ns / 1000; 674 if (host->clock) 675 target_timeout += data->timeout_clks / host->clock; 676 } 677 678 /* 679 * Figure out needed cycles. 680 * We do this in steps in order to fit inside a 32 bit int. 681 * The first step is the minimum timeout, which will have a 682 * minimum resolution of 6 bits: 683 * (1) 2^13*1000 > 2^22, 684 * (2) host->timeout_clk < 2^16 685 * => 686 * (1) / (2) > 2^6 687 */ 688 count = 0; 689 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 690 while (current_timeout < target_timeout) { 691 count++; 692 current_timeout <<= 1; 693 if (count >= 0xF) 694 break; 695 } 696 697 if (count >= 0xF) { 698 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 699 mmc_hostname(host->mmc), count, cmd->opcode); 700 count = 0xE; 701 } 702 703 return count; 704} 705 706static void sdhci_set_transfer_irqs(struct sdhci_host *host) 707{ 708 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 709 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 710 711 if (host->flags & SDHCI_REQ_USE_DMA) 712 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); 713 else 714 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); 715} 716 717static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 718{ 719 u8 count; 720 u8 ctrl; 721 struct mmc_data *data = cmd->data; 722 int ret; 723 724 WARN_ON(host->data); 725 726 if (data || (cmd->flags & MMC_RSP_BUSY)) { 727 count = sdhci_calc_timeout(host, cmd); 728 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 729 } 730 731 if (!data) 732 return; 733 734 /* Sanity checks */ 735 BUG_ON(data->blksz * data->blocks > 524288); 736 BUG_ON(data->blksz > host->mmc->max_blk_size); 737 BUG_ON(data->blocks > 65535); 738 739 host->data = data; 740 host->data_early = 0; 741 host->data->bytes_xfered = 0; 742 743 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 744 host->flags |= SDHCI_REQ_USE_DMA; 745 746 /* 747 * FIXME: This doesn't account for merging when mapping the 748 * scatterlist. 749 */ 750 if (host->flags & SDHCI_REQ_USE_DMA) { 751 int broken, i; 752 struct scatterlist *sg; 753 754 broken = 0; 755 if (host->flags & SDHCI_USE_ADMA) { 756 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 757 broken = 1; 758 } else { 759 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 760 broken = 1; 761 } 762 763 if (unlikely(broken)) { 764 for_each_sg(data->sg, sg, data->sg_len, i) { 765 if (sg->length & 0x3) { 766 DBG("Reverting to PIO because of " 767 "transfer size (%d)\n", 768 sg->length); 769 host->flags &= ~SDHCI_REQ_USE_DMA; 770 break; 771 } 772 } 773 } 774 } 775 776 /* 777 * The assumption here being that alignment is the same after 778 * translation to device address space. 779 */ 780 if (host->flags & SDHCI_REQ_USE_DMA) { 781 int broken, i; 782 struct scatterlist *sg; 783 784 broken = 0; 785 if (host->flags & SDHCI_USE_ADMA) { 786 /* 787 * As we use 3 byte chunks to work around 788 * alignment problems, we need to check this 789 * quirk. 790 */ 791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 792 broken = 1; 793 } else { 794 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 795 broken = 1; 796 } 797 798 if (unlikely(broken)) { 799 for_each_sg(data->sg, sg, data->sg_len, i) { 800 if (sg->offset & 0x3) { 801 DBG("Reverting to PIO because of " 802 "bad alignment\n"); 803 host->flags &= ~SDHCI_REQ_USE_DMA; 804 break; 805 } 806 } 807 } 808 } 809 810 if (host->flags & SDHCI_REQ_USE_DMA) { 811 if (host->flags & SDHCI_USE_ADMA) { 812 ret = sdhci_adma_table_pre(host, data); 813 if (ret) { 814 /* 815 * This only happens when someone fed 816 * us an invalid request. 817 */ 818 WARN_ON(1); 819 host->flags &= ~SDHCI_REQ_USE_DMA; 820 } else { 821 sdhci_writel(host, host->adma_addr, 822 SDHCI_ADMA_ADDRESS); 823 } 824 } else { 825 int sg_cnt; 826 827 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 828 data->sg, data->sg_len, 829 (data->flags & MMC_DATA_READ) ? 830 DMA_FROM_DEVICE : 831 DMA_TO_DEVICE); 832 if (sg_cnt == 0) { 833 /* 834 * This only happens when someone fed 835 * us an invalid request. 836 */ 837 WARN_ON(1); 838 host->flags &= ~SDHCI_REQ_USE_DMA; 839 } else { 840 WARN_ON(sg_cnt != 1); 841 sdhci_writel(host, sg_dma_address(data->sg), 842 SDHCI_DMA_ADDRESS); 843 } 844 } 845 } 846 847 /* 848 * Always adjust the DMA selection as some controllers 849 * (e.g. JMicron) can't do PIO properly when the selection 850 * is ADMA. 851 */ 852 if (host->version >= SDHCI_SPEC_200) { 853 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 854 ctrl &= ~SDHCI_CTRL_DMA_MASK; 855 if ((host->flags & SDHCI_REQ_USE_DMA) && 856 (host->flags & SDHCI_USE_ADMA)) 857 ctrl |= SDHCI_CTRL_ADMA32; 858 else 859 ctrl |= SDHCI_CTRL_SDMA; 860 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 861 } 862 863 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 864 int flags; 865 866 flags = SG_MITER_ATOMIC; 867 if (host->data->flags & MMC_DATA_READ) 868 flags |= SG_MITER_TO_SG; 869 else 870 flags |= SG_MITER_FROM_SG; 871 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 872 host->blocks = data->blocks; 873 } 874 875 sdhci_set_transfer_irqs(host); 876 877 /* Set the DMA boundary value and block size */ 878 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 879 data->blksz), SDHCI_BLOCK_SIZE); 880 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 881} 882 883static void sdhci_set_transfer_mode(struct sdhci_host *host, 884 struct mmc_command *cmd) 885{ 886 u16 mode; 887 struct mmc_data *data = cmd->data; 888 889 if (data == NULL) 890 return; 891 892 WARN_ON(!host->data); 893 894 mode = SDHCI_TRNS_BLK_CNT_EN; 895 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 896 mode |= SDHCI_TRNS_MULTI; 897 /* 898 * If we are sending CMD23, CMD12 never gets sent 899 * on successful completion (so no Auto-CMD12). 900 */ 901 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 902 mode |= SDHCI_TRNS_AUTO_CMD12; 903 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 904 mode |= SDHCI_TRNS_AUTO_CMD23; 905 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 906 } 907 } 908 909 if (data->flags & MMC_DATA_READ) 910 mode |= SDHCI_TRNS_READ; 911 if (host->flags & SDHCI_REQ_USE_DMA) 912 mode |= SDHCI_TRNS_DMA; 913 914 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 915} 916 917static void sdhci_finish_data(struct sdhci_host *host) 918{ 919 struct mmc_data *data; 920 921 BUG_ON(!host->data); 922 923 data = host->data; 924 host->data = NULL; 925 926 if (host->flags & SDHCI_REQ_USE_DMA) { 927 if (host->flags & SDHCI_USE_ADMA) 928 sdhci_adma_table_post(host, data); 929 else { 930 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 931 data->sg_len, (data->flags & MMC_DATA_READ) ? 932 DMA_FROM_DEVICE : DMA_TO_DEVICE); 933 } 934 } 935 936 /* 937 * The specification states that the block count register must 938 * be updated, but it does not specify at what point in the 939 * data flow. That makes the register entirely useless to read 940 * back so we have to assume that nothing made it to the card 941 * in the event of an error. 942 */ 943 if (data->error) 944 data->bytes_xfered = 0; 945 else 946 data->bytes_xfered = data->blksz * data->blocks; 947 948 /* 949 * Need to send CMD12 if - 950 * a) open-ended multiblock transfer (no CMD23) 951 * b) error in multiblock transfer 952 */ 953 if (data->stop && 954 (data->error || 955 !host->mrq->sbc)) { 956 957 /* 958 * The controller needs a reset of internal state machines 959 * upon error conditions. 960 */ 961 if (data->error) { 962 sdhci_reset(host, SDHCI_RESET_CMD); 963 sdhci_reset(host, SDHCI_RESET_DATA); 964 } 965 966 sdhci_send_command(host, data->stop); 967 } else 968 tasklet_schedule(&host->finish_tasklet); 969} 970 971static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 972{ 973 int flags; 974 u32 mask; 975 unsigned long timeout; 976 977 WARN_ON(host->cmd); 978 979 /* Wait max 10 ms */ 980 timeout = 10; 981 982 mask = SDHCI_CMD_INHIBIT; 983 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 984 mask |= SDHCI_DATA_INHIBIT; 985 986 /* We shouldn't wait for data inihibit for stop commands, even 987 though they might use busy signaling */ 988 if (host->mrq->data && (cmd == host->mrq->data->stop)) 989 mask &= ~SDHCI_DATA_INHIBIT; 990 991 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 992 if (timeout == 0) { 993 pr_err("%s: Controller never released " 994 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 995 sdhci_dumpregs(host); 996 cmd->error = -EIO; 997 tasklet_schedule(&host->finish_tasklet); 998 return; 999 } 1000 timeout--; 1001 mdelay(1); 1002 } 1003 1004 mod_timer(&host->timer, jiffies + 10 * HZ); 1005 1006 host->cmd = cmd; 1007 1008 sdhci_prepare_data(host, cmd); 1009 1010 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1011 1012 sdhci_set_transfer_mode(host, cmd); 1013 1014 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1015 pr_err("%s: Unsupported response type!\n", 1016 mmc_hostname(host->mmc)); 1017 cmd->error = -EINVAL; 1018 tasklet_schedule(&host->finish_tasklet); 1019 return; 1020 } 1021 1022 if (!(cmd->flags & MMC_RSP_PRESENT)) 1023 flags = SDHCI_CMD_RESP_NONE; 1024 else if (cmd->flags & MMC_RSP_136) 1025 flags = SDHCI_CMD_RESP_LONG; 1026 else if (cmd->flags & MMC_RSP_BUSY) 1027 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1028 else 1029 flags = SDHCI_CMD_RESP_SHORT; 1030 1031 if (cmd->flags & MMC_RSP_CRC) 1032 flags |= SDHCI_CMD_CRC; 1033 if (cmd->flags & MMC_RSP_OPCODE) 1034 flags |= SDHCI_CMD_INDEX; 1035 1036 /* CMD19 is special in that the Data Present Select should be set */ 1037 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1038 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1039 flags |= SDHCI_CMD_DATA; 1040 1041 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1042} 1043 1044static void sdhci_finish_command(struct sdhci_host *host) 1045{ 1046 int i; 1047 1048 BUG_ON(host->cmd == NULL); 1049 1050 if (host->cmd->flags & MMC_RSP_PRESENT) { 1051 if (host->cmd->flags & MMC_RSP_136) { 1052 /* CRC is stripped so we need to do some shifting. */ 1053 for (i = 0;i < 4;i++) { 1054 host->cmd->resp[i] = sdhci_readl(host, 1055 SDHCI_RESPONSE + (3-i)*4) << 8; 1056 if (i != 3) 1057 host->cmd->resp[i] |= 1058 sdhci_readb(host, 1059 SDHCI_RESPONSE + (3-i)*4-1); 1060 } 1061 } else { 1062 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1063 } 1064 } 1065 1066 host->cmd->error = 0; 1067 1068 /* Finished CMD23, now send actual command. */ 1069 if (host->cmd == host->mrq->sbc) { 1070 host->cmd = NULL; 1071 sdhci_send_command(host, host->mrq->cmd); 1072 } else { 1073 1074 /* Processed actual command. */ 1075 if (host->data && host->data_early) 1076 sdhci_finish_data(host); 1077 1078 if (!host->cmd->data) 1079 tasklet_schedule(&host->finish_tasklet); 1080 1081 host->cmd = NULL; 1082 } 1083} 1084 1085static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1086{ 1087 int div = 0; /* Initialized for compiler warning */ 1088 int real_div = div, clk_mul = 1; 1089 u16 clk = 0; 1090 unsigned long timeout; 1091 1092 if (clock && clock == host->clock) 1093 return; 1094 1095 host->mmc->actual_clock = 0; 1096 1097 if (host->ops->set_clock) { 1098 host->ops->set_clock(host, clock); 1099 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) 1100 return; 1101 } 1102 1103 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1104 1105 if (clock == 0) 1106 goto out; 1107 1108 if (host->version >= SDHCI_SPEC_300) { 1109 /* 1110 * Check if the Host Controller supports Programmable Clock 1111 * Mode. 1112 */ 1113 if (host->clk_mul) { 1114 u16 ctrl; 1115 1116 /* 1117 * We need to figure out whether the Host Driver needs 1118 * to select Programmable Clock Mode, or the value can 1119 * be set automatically by the Host Controller based on 1120 * the Preset Value registers. 1121 */ 1122 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1123 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1124 for (div = 1; div <= 1024; div++) { 1125 if (((host->max_clk * host->clk_mul) / 1126 div) <= clock) 1127 break; 1128 } 1129 /* 1130 * Set Programmable Clock Mode in the Clock 1131 * Control register. 1132 */ 1133 clk = SDHCI_PROG_CLOCK_MODE; 1134 real_div = div; 1135 clk_mul = host->clk_mul; 1136 div--; 1137 } 1138 } else { 1139 /* Version 3.00 divisors must be a multiple of 2. */ 1140 if (host->max_clk <= clock) 1141 div = 1; 1142 else { 1143 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1144 div += 2) { 1145 if ((host->max_clk / div) <= clock) 1146 break; 1147 } 1148 } 1149 real_div = div; 1150 div >>= 1; 1151 } 1152 } else { 1153 /* Version 2.00 divisors must be a power of 2. */ 1154 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1155 if ((host->max_clk / div) <= clock) 1156 break; 1157 } 1158 real_div = div; 1159 div >>= 1; 1160 } 1161 1162 if (real_div) 1163 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1164 1165 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1166 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1167 << SDHCI_DIVIDER_HI_SHIFT; 1168 clk |= SDHCI_CLOCK_INT_EN; 1169 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1170 1171 /* Wait max 20 ms */ 1172 timeout = 20; 1173 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1174 & SDHCI_CLOCK_INT_STABLE)) { 1175 if (timeout == 0) { 1176 pr_err("%s: Internal clock never " 1177 "stabilised.\n", mmc_hostname(host->mmc)); 1178 sdhci_dumpregs(host); 1179 return; 1180 } 1181 timeout--; 1182 mdelay(1); 1183 } 1184 1185 clk |= SDHCI_CLOCK_CARD_EN; 1186 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1187 1188out: 1189 host->clock = clock; 1190} 1191 1192static inline void sdhci_update_clock(struct sdhci_host *host) 1193{ 1194 unsigned int clock; 1195 1196 clock = host->clock; 1197 host->clock = 0; 1198 sdhci_set_clock(host, clock); 1199} 1200 1201static int sdhci_set_power(struct sdhci_host *host, unsigned short power) 1202{ 1203 u8 pwr = 0; 1204 1205 if (power != (unsigned short)-1) { 1206 switch (1 << power) { 1207 case MMC_VDD_165_195: 1208 pwr = SDHCI_POWER_180; 1209 break; 1210 case MMC_VDD_29_30: 1211 case MMC_VDD_30_31: 1212 pwr = SDHCI_POWER_300; 1213 break; 1214 case MMC_VDD_32_33: 1215 case MMC_VDD_33_34: 1216 pwr = SDHCI_POWER_330; 1217 break; 1218 default: 1219 BUG(); 1220 } 1221 } 1222 1223 if (host->pwr == pwr) 1224 return -1; 1225 1226 host->pwr = pwr; 1227 1228 if (pwr == 0) { 1229 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1230 return 0; 1231 } 1232 1233 /* 1234 * Spec says that we should clear the power reg before setting 1235 * a new value. Some controllers don't seem to like this though. 1236 */ 1237 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1238 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1239 1240 /* 1241 * At least the Marvell CaFe chip gets confused if we set the voltage 1242 * and set turn on power at the same time, so set the voltage first. 1243 */ 1244 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1245 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1246 1247 pwr |= SDHCI_POWER_ON; 1248 1249 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1250 1251 /* 1252 * Some controllers need an extra 10ms delay of 10ms before they 1253 * can apply clock after applying power 1254 */ 1255 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1256 mdelay(10); 1257 1258 return power; 1259} 1260 1261/*****************************************************************************\ 1262 * * 1263 * MMC callbacks * 1264 * * 1265\*****************************************************************************/ 1266 1267static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1268{ 1269 struct sdhci_host *host; 1270 int present; 1271 unsigned long flags; 1272 u32 tuning_opcode; 1273 1274 host = mmc_priv(mmc); 1275 1276 sdhci_runtime_pm_get(host); 1277 1278 spin_lock_irqsave(&host->lock, flags); 1279 1280 WARN_ON(host->mrq != NULL); 1281 1282#ifndef SDHCI_USE_LEDS_CLASS 1283 sdhci_activate_led(host); 1284#endif 1285 1286 /* 1287 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1288 * requests if Auto-CMD12 is enabled. 1289 */ 1290 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1291 if (mrq->stop) { 1292 mrq->data->stop = NULL; 1293 mrq->stop = NULL; 1294 } 1295 } 1296 1297 host->mrq = mrq; 1298 1299 /* 1300 * Firstly check card presence from cd-gpio. The return could 1301 * be one of the following possibilities: 1302 * negative: cd-gpio is not available 1303 * zero: cd-gpio is used, and card is removed 1304 * one: cd-gpio is used, and card is present 1305 */ 1306 present = mmc_gpio_get_cd(host->mmc); 1307 if (present < 0) { 1308 /* If polling, assume that the card is always present. */ 1309 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1310 present = 1; 1311 else 1312 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1313 SDHCI_CARD_PRESENT; 1314 } 1315 1316 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1317 host->mrq->cmd->error = -ENOMEDIUM; 1318 tasklet_schedule(&host->finish_tasklet); 1319 } else { 1320 u32 present_state; 1321 1322 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1323 /* 1324 * Check if the re-tuning timer has already expired and there 1325 * is no on-going data transfer. If so, we need to execute 1326 * tuning procedure before sending command. 1327 */ 1328 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1329 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 1330 if (mmc->card) { 1331 /* eMMC uses cmd21 but sd and sdio use cmd19 */ 1332 tuning_opcode = 1333 mmc->card->type == MMC_TYPE_MMC ? 1334 MMC_SEND_TUNING_BLOCK_HS200 : 1335 MMC_SEND_TUNING_BLOCK; 1336 spin_unlock_irqrestore(&host->lock, flags); 1337 sdhci_execute_tuning(mmc, tuning_opcode); 1338 spin_lock_irqsave(&host->lock, flags); 1339 1340 /* Restore original mmc_request structure */ 1341 host->mrq = mrq; 1342 } 1343 } 1344 1345 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1346 sdhci_send_command(host, mrq->sbc); 1347 else 1348 sdhci_send_command(host, mrq->cmd); 1349 } 1350 1351 mmiowb(); 1352 spin_unlock_irqrestore(&host->lock, flags); 1353} 1354 1355static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1356{ 1357 unsigned long flags; 1358 int vdd_bit = -1; 1359 u8 ctrl; 1360 1361 spin_lock_irqsave(&host->lock, flags); 1362 1363 if (host->flags & SDHCI_DEVICE_DEAD) { 1364 spin_unlock_irqrestore(&host->lock, flags); 1365 if (host->vmmc && ios->power_mode == MMC_POWER_OFF) 1366 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); 1367 return; 1368 } 1369 1370 /* 1371 * Reset the chip on each power off. 1372 * Should clear out any weird states. 1373 */ 1374 if (ios->power_mode == MMC_POWER_OFF) { 1375 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1376 sdhci_reinit(host); 1377 } 1378 1379 sdhci_set_clock(host, ios->clock); 1380 1381 if (ios->power_mode == MMC_POWER_OFF) 1382 vdd_bit = sdhci_set_power(host, -1); 1383 else 1384 vdd_bit = sdhci_set_power(host, ios->vdd); 1385 1386 if (host->vmmc && vdd_bit != -1) { 1387 spin_unlock_irqrestore(&host->lock, flags); 1388 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); 1389 spin_lock_irqsave(&host->lock, flags); 1390 } 1391 1392 if (host->ops->platform_send_init_74_clocks) 1393 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1394 1395 /* 1396 * If your platform has 8-bit width support but is not a v3 controller, 1397 * or if it requires special setup code, you should implement that in 1398 * platform_bus_width(). 1399 */ 1400 if (host->ops->platform_bus_width) { 1401 host->ops->platform_bus_width(host, ios->bus_width); 1402 } else { 1403 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1404 if (ios->bus_width == MMC_BUS_WIDTH_8) { 1405 ctrl &= ~SDHCI_CTRL_4BITBUS; 1406 if (host->version >= SDHCI_SPEC_300) 1407 ctrl |= SDHCI_CTRL_8BITBUS; 1408 } else { 1409 if (host->version >= SDHCI_SPEC_300) 1410 ctrl &= ~SDHCI_CTRL_8BITBUS; 1411 if (ios->bus_width == MMC_BUS_WIDTH_4) 1412 ctrl |= SDHCI_CTRL_4BITBUS; 1413 else 1414 ctrl &= ~SDHCI_CTRL_4BITBUS; 1415 } 1416 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1417 } 1418 1419 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1420 1421 if ((ios->timing == MMC_TIMING_SD_HS || 1422 ios->timing == MMC_TIMING_MMC_HS) 1423 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1424 ctrl |= SDHCI_CTRL_HISPD; 1425 else 1426 ctrl &= ~SDHCI_CTRL_HISPD; 1427 1428 if (host->version >= SDHCI_SPEC_300) { 1429 u16 clk, ctrl_2; 1430 1431 /* In case of UHS-I modes, set High Speed Enable */ 1432 if ((ios->timing == MMC_TIMING_MMC_HS200) || 1433 (ios->timing == MMC_TIMING_UHS_SDR50) || 1434 (ios->timing == MMC_TIMING_UHS_SDR104) || 1435 (ios->timing == MMC_TIMING_UHS_DDR50) || 1436 (ios->timing == MMC_TIMING_UHS_SDR25)) 1437 ctrl |= SDHCI_CTRL_HISPD; 1438 1439 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1440 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1441 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1442 /* 1443 * We only need to set Driver Strength if the 1444 * preset value enable is not set. 1445 */ 1446 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1447 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1448 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1449 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1450 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1451 1452 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1453 } else { 1454 /* 1455 * According to SDHC Spec v3.00, if the Preset Value 1456 * Enable in the Host Control 2 register is set, we 1457 * need to reset SD Clock Enable before changing High 1458 * Speed Enable to avoid generating clock gliches. 1459 */ 1460 1461 /* Reset SD Clock Enable */ 1462 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1463 clk &= ~SDHCI_CLOCK_CARD_EN; 1464 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1465 1466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1467 1468 /* Re-enable SD Clock */ 1469 sdhci_update_clock(host); 1470 } 1471 1472 1473 /* Reset SD Clock Enable */ 1474 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1475 clk &= ~SDHCI_CLOCK_CARD_EN; 1476 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1477 1478 if (host->ops->set_uhs_signaling) 1479 host->ops->set_uhs_signaling(host, ios->timing); 1480 else { 1481 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1482 /* Select Bus Speed Mode for host */ 1483 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1484 if (ios->timing == MMC_TIMING_MMC_HS200) 1485 ctrl_2 |= SDHCI_CTRL_HS_SDR200; 1486 else if (ios->timing == MMC_TIMING_UHS_SDR12) 1487 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1488 else if (ios->timing == MMC_TIMING_UHS_SDR25) 1489 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1490 else if (ios->timing == MMC_TIMING_UHS_SDR50) 1491 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1492 else if (ios->timing == MMC_TIMING_UHS_SDR104) 1493 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1494 else if (ios->timing == MMC_TIMING_UHS_DDR50) 1495 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1496 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1497 } 1498 1499 /* Re-enable SD Clock */ 1500 sdhci_update_clock(host); 1501 } else 1502 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1503 1504 /* 1505 * Some (ENE) controllers go apeshit on some ios operation, 1506 * signalling timeout and CRC errors even on CMD0. Resetting 1507 * it on each ios seems to solve the problem. 1508 */ 1509 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1510 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1511 1512 mmiowb(); 1513 spin_unlock_irqrestore(&host->lock, flags); 1514} 1515 1516static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1517{ 1518 struct sdhci_host *host = mmc_priv(mmc); 1519 1520 sdhci_runtime_pm_get(host); 1521 sdhci_do_set_ios(host, ios); 1522 sdhci_runtime_pm_put(host); 1523} 1524 1525static int sdhci_check_ro(struct sdhci_host *host) 1526{ 1527 unsigned long flags; 1528 int is_readonly; 1529 1530 spin_lock_irqsave(&host->lock, flags); 1531 1532 if (host->flags & SDHCI_DEVICE_DEAD) 1533 is_readonly = 0; 1534 else if (host->ops->get_ro) 1535 is_readonly = host->ops->get_ro(host); 1536 else 1537 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1538 & SDHCI_WRITE_PROTECT); 1539 1540 spin_unlock_irqrestore(&host->lock, flags); 1541 1542 /* This quirk needs to be replaced by a callback-function later */ 1543 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1544 !is_readonly : is_readonly; 1545} 1546 1547#define SAMPLE_COUNT 5 1548 1549static int sdhci_do_get_ro(struct sdhci_host *host) 1550{ 1551 int i, ro_count; 1552 1553 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1554 return sdhci_check_ro(host); 1555 1556 ro_count = 0; 1557 for (i = 0; i < SAMPLE_COUNT; i++) { 1558 if (sdhci_check_ro(host)) { 1559 if (++ro_count > SAMPLE_COUNT / 2) 1560 return 1; 1561 } 1562 msleep(30); 1563 } 1564 return 0; 1565} 1566 1567static void sdhci_hw_reset(struct mmc_host *mmc) 1568{ 1569 struct sdhci_host *host = mmc_priv(mmc); 1570 1571 if (host->ops && host->ops->hw_reset) 1572 host->ops->hw_reset(host); 1573} 1574 1575static int sdhci_get_ro(struct mmc_host *mmc) 1576{ 1577 struct sdhci_host *host = mmc_priv(mmc); 1578 int ret; 1579 1580 sdhci_runtime_pm_get(host); 1581 ret = sdhci_do_get_ro(host); 1582 sdhci_runtime_pm_put(host); 1583 return ret; 1584} 1585 1586static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1587{ 1588 if (host->flags & SDHCI_DEVICE_DEAD) 1589 goto out; 1590 1591 if (enable) 1592 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1593 else 1594 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1595 1596 /* SDIO IRQ will be enabled as appropriate in runtime resume */ 1597 if (host->runtime_suspended) 1598 goto out; 1599 1600 if (enable) 1601 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); 1602 else 1603 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); 1604out: 1605 mmiowb(); 1606} 1607 1608static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1609{ 1610 struct sdhci_host *host = mmc_priv(mmc); 1611 unsigned long flags; 1612 1613 spin_lock_irqsave(&host->lock, flags); 1614 sdhci_enable_sdio_irq_nolock(host, enable); 1615 spin_unlock_irqrestore(&host->lock, flags); 1616} 1617 1618static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1619 int signal_voltage) 1620{ 1621 u16 ctrl; 1622 int ret; 1623 1624 /* 1625 * Signal Voltage Switching is only applicable for Host Controllers 1626 * v3.00 and above. 1627 */ 1628 if (host->version < SDHCI_SPEC_300) 1629 return 0; 1630 1631 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1632 1633 switch (signal_voltage) { 1634 case MMC_SIGNAL_VOLTAGE_330: 1635 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1636 ctrl &= ~SDHCI_CTRL_VDD_180; 1637 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1638 1639 if (host->vqmmc) { 1640 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); 1641 if (ret) { 1642 pr_warning("%s: Switching to 3.3V signalling voltage " 1643 " failed\n", mmc_hostname(host->mmc)); 1644 return -EIO; 1645 } 1646 } 1647 /* Wait for 5ms */ 1648 usleep_range(5000, 5500); 1649 1650 /* 3.3V regulator output should be stable within 5 ms */ 1651 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1652 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1653 return 0; 1654 1655 pr_warning("%s: 3.3V regulator output did not became stable\n", 1656 mmc_hostname(host->mmc)); 1657 1658 return -EAGAIN; 1659 case MMC_SIGNAL_VOLTAGE_180: 1660 if (host->vqmmc) { 1661 ret = regulator_set_voltage(host->vqmmc, 1662 1700000, 1950000); 1663 if (ret) { 1664 pr_warning("%s: Switching to 1.8V signalling voltage " 1665 " failed\n", mmc_hostname(host->mmc)); 1666 return -EIO; 1667 } 1668 } 1669 1670 /* 1671 * Enable 1.8V Signal Enable in the Host Control2 1672 * register 1673 */ 1674 ctrl |= SDHCI_CTRL_VDD_180; 1675 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1676 1677 /* Wait for 5ms */ 1678 usleep_range(5000, 5500); 1679 1680 /* 1.8V regulator output should be stable within 5 ms */ 1681 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1682 if (ctrl & SDHCI_CTRL_VDD_180) 1683 return 0; 1684 1685 pr_warning("%s: 1.8V regulator output did not became stable\n", 1686 mmc_hostname(host->mmc)); 1687 1688 return -EAGAIN; 1689 case MMC_SIGNAL_VOLTAGE_120: 1690 if (host->vqmmc) { 1691 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000); 1692 if (ret) { 1693 pr_warning("%s: Switching to 1.2V signalling voltage " 1694 " failed\n", mmc_hostname(host->mmc)); 1695 return -EIO; 1696 } 1697 } 1698 return 0; 1699 default: 1700 /* No signal voltage switch required */ 1701 return 0; 1702 } 1703} 1704 1705static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1706 int signal_voltage) 1707{ 1708 struct sdhci_host *host = mmc_priv(mmc); 1709 int err; 1710 1711 if (host->version < SDHCI_SPEC_300) 1712 return 0; 1713 sdhci_runtime_pm_get(host); 1714 err = sdhci_do_start_signal_voltage_switch(host, signal_voltage); 1715 sdhci_runtime_pm_put(host); 1716 return err; 1717} 1718 1719static int sdhci_card_busy(struct mmc_host *mmc) 1720{ 1721 struct sdhci_host *host = mmc_priv(mmc); 1722 u32 present_state; 1723 1724 sdhci_runtime_pm_get(host); 1725 /* Check whether DAT[3:0] is 0000 */ 1726 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1727 sdhci_runtime_pm_put(host); 1728 1729 return !(present_state & SDHCI_DATA_LVL_MASK); 1730} 1731 1732static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1733{ 1734 struct sdhci_host *host; 1735 u16 ctrl; 1736 u32 ier; 1737 int tuning_loop_counter = MAX_TUNING_LOOP; 1738 unsigned long timeout; 1739 int err = 0; 1740 bool requires_tuning_nonuhs = false; 1741 1742 host = mmc_priv(mmc); 1743 1744 sdhci_runtime_pm_get(host); 1745 disable_irq(host->irq); 1746 spin_lock(&host->lock); 1747 1748 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1749 1750 /* 1751 * The Host Controller needs tuning only in case of SDR104 mode 1752 * and for SDR50 mode when Use Tuning for SDR50 is set in the 1753 * Capabilities register. 1754 * If the Host Controller supports the HS200 mode then the 1755 * tuning function has to be executed. 1756 */ 1757 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && 1758 (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1759 host->flags & SDHCI_HS200_NEEDS_TUNING)) 1760 requires_tuning_nonuhs = true; 1761 1762 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || 1763 requires_tuning_nonuhs) 1764 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1765 else { 1766 spin_unlock(&host->lock); 1767 enable_irq(host->irq); 1768 sdhci_runtime_pm_put(host); 1769 return 0; 1770 } 1771 1772 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1773 1774 /* 1775 * As per the Host Controller spec v3.00, tuning command 1776 * generates Buffer Read Ready interrupt, so enable that. 1777 * 1778 * Note: The spec clearly says that when tuning sequence 1779 * is being performed, the controller does not generate 1780 * interrupts other than Buffer Read Ready interrupt. But 1781 * to make sure we don't hit a controller bug, we _only_ 1782 * enable Buffer Read Ready interrupt here. 1783 */ 1784 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1785 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); 1786 1787 /* 1788 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1789 * of loops reaches 40 times or a timeout of 150ms occurs. 1790 */ 1791 timeout = 150; 1792 do { 1793 struct mmc_command cmd = {0}; 1794 struct mmc_request mrq = {NULL}; 1795 1796 if (!tuning_loop_counter && !timeout) 1797 break; 1798 1799 cmd.opcode = opcode; 1800 cmd.arg = 0; 1801 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1802 cmd.retries = 0; 1803 cmd.data = NULL; 1804 cmd.error = 0; 1805 1806 mrq.cmd = &cmd; 1807 host->mrq = &mrq; 1808 1809 /* 1810 * In response to CMD19, the card sends 64 bytes of tuning 1811 * block to the Host Controller. So we set the block size 1812 * to 64 here. 1813 */ 1814 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1815 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1816 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1817 SDHCI_BLOCK_SIZE); 1818 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1819 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1820 SDHCI_BLOCK_SIZE); 1821 } else { 1822 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1823 SDHCI_BLOCK_SIZE); 1824 } 1825 1826 /* 1827 * The tuning block is sent by the card to the host controller. 1828 * So we set the TRNS_READ bit in the Transfer Mode register. 1829 * This also takes care of setting DMA Enable and Multi Block 1830 * Select in the same register to 0. 1831 */ 1832 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1833 1834 sdhci_send_command(host, &cmd); 1835 1836 host->cmd = NULL; 1837 host->mrq = NULL; 1838 1839 spin_unlock(&host->lock); 1840 enable_irq(host->irq); 1841 1842 /* Wait for Buffer Read Ready interrupt */ 1843 wait_event_interruptible_timeout(host->buf_ready_int, 1844 (host->tuning_done == 1), 1845 msecs_to_jiffies(50)); 1846 disable_irq(host->irq); 1847 spin_lock(&host->lock); 1848 1849 if (!host->tuning_done) { 1850 pr_info(DRIVER_NAME ": Timeout waiting for " 1851 "Buffer Read Ready interrupt during tuning " 1852 "procedure, falling back to fixed sampling " 1853 "clock\n"); 1854 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1855 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1856 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1857 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1858 1859 err = -EIO; 1860 goto out; 1861 } 1862 1863 host->tuning_done = 0; 1864 1865 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1866 tuning_loop_counter--; 1867 timeout--; 1868 mdelay(1); 1869 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1870 1871 /* 1872 * The Host Driver has exhausted the maximum number of loops allowed, 1873 * so use fixed sampling frequency. 1874 */ 1875 if (!tuning_loop_counter || !timeout) { 1876 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1877 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1878 } else { 1879 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1880 pr_info(DRIVER_NAME ": Tuning procedure" 1881 " failed, falling back to fixed sampling" 1882 " clock\n"); 1883 err = -EIO; 1884 } 1885 } 1886 1887out: 1888 /* 1889 * If this is the very first time we are here, we start the retuning 1890 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 1891 * flag won't be set, we check this condition before actually starting 1892 * the timer. 1893 */ 1894 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 1895 (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 1896 host->flags |= SDHCI_USING_RETUNING_TIMER; 1897 mod_timer(&host->tuning_timer, jiffies + 1898 host->tuning_count * HZ); 1899 /* Tuning mode 1 limits the maximum data length to 4MB */ 1900 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 1901 } else { 1902 host->flags &= ~SDHCI_NEEDS_RETUNING; 1903 /* Reload the new initial value for timer */ 1904 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1905 mod_timer(&host->tuning_timer, jiffies + 1906 host->tuning_count * HZ); 1907 } 1908 1909 /* 1910 * In case tuning fails, host controllers which support re-tuning can 1911 * try tuning again at a later time, when the re-tuning timer expires. 1912 * So for these controllers, we return 0. Since there might be other 1913 * controllers who do not have this capability, we return error for 1914 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 1915 * a retuning timer to do the retuning for the card. 1916 */ 1917 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 1918 err = 0; 1919 1920 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); 1921 spin_unlock(&host->lock); 1922 enable_irq(host->irq); 1923 sdhci_runtime_pm_put(host); 1924 1925 return err; 1926} 1927 1928static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable) 1929{ 1930 u16 ctrl; 1931 unsigned long flags; 1932 1933 /* Host Controller v3.00 defines preset value registers */ 1934 if (host->version < SDHCI_SPEC_300) 1935 return; 1936 1937 spin_lock_irqsave(&host->lock, flags); 1938 1939 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1940 1941 /* 1942 * We only enable or disable Preset Value if they are not already 1943 * enabled or disabled respectively. Otherwise, we bail out. 1944 */ 1945 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1946 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 1947 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1948 host->flags |= SDHCI_PV_ENABLED; 1949 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1950 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 1951 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1952 host->flags &= ~SDHCI_PV_ENABLED; 1953 } 1954 1955 spin_unlock_irqrestore(&host->lock, flags); 1956} 1957 1958static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable) 1959{ 1960 struct sdhci_host *host = mmc_priv(mmc); 1961 1962 sdhci_runtime_pm_get(host); 1963 sdhci_do_enable_preset_value(host, enable); 1964 sdhci_runtime_pm_put(host); 1965} 1966 1967static void sdhci_card_event(struct mmc_host *mmc) 1968{ 1969 struct sdhci_host *host = mmc_priv(mmc); 1970 unsigned long flags; 1971 1972 spin_lock_irqsave(&host->lock, flags); 1973 1974 /* Check host->mrq first in case we are runtime suspended */ 1975 if (host->mrq && 1976 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { 1977 pr_err("%s: Card removed during transfer!\n", 1978 mmc_hostname(host->mmc)); 1979 pr_err("%s: Resetting controller.\n", 1980 mmc_hostname(host->mmc)); 1981 1982 sdhci_reset(host, SDHCI_RESET_CMD); 1983 sdhci_reset(host, SDHCI_RESET_DATA); 1984 1985 host->mrq->cmd->error = -ENOMEDIUM; 1986 tasklet_schedule(&host->finish_tasklet); 1987 } 1988 1989 spin_unlock_irqrestore(&host->lock, flags); 1990} 1991 1992static const struct mmc_host_ops sdhci_ops = { 1993 .request = sdhci_request, 1994 .set_ios = sdhci_set_ios, 1995 .get_ro = sdhci_get_ro, 1996 .hw_reset = sdhci_hw_reset, 1997 .enable_sdio_irq = sdhci_enable_sdio_irq, 1998 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 1999 .execute_tuning = sdhci_execute_tuning, 2000 .enable_preset_value = sdhci_enable_preset_value, 2001 .card_event = sdhci_card_event, 2002 .card_busy = sdhci_card_busy, 2003}; 2004 2005/*****************************************************************************\ 2006 * * 2007 * Tasklets * 2008 * * 2009\*****************************************************************************/ 2010 2011static void sdhci_tasklet_card(unsigned long param) 2012{ 2013 struct sdhci_host *host = (struct sdhci_host*)param; 2014 2015 sdhci_card_event(host->mmc); 2016 2017 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2018} 2019 2020static void sdhci_tasklet_finish(unsigned long param) 2021{ 2022 struct sdhci_host *host; 2023 unsigned long flags; 2024 struct mmc_request *mrq; 2025 2026 host = (struct sdhci_host*)param; 2027 2028 spin_lock_irqsave(&host->lock, flags); 2029 2030 /* 2031 * If this tasklet gets rescheduled while running, it will 2032 * be run again afterwards but without any active request. 2033 */ 2034 if (!host->mrq) { 2035 spin_unlock_irqrestore(&host->lock, flags); 2036 return; 2037 } 2038 2039 del_timer(&host->timer); 2040 2041 mrq = host->mrq; 2042 2043 /* 2044 * The controller needs a reset of internal state machines 2045 * upon error conditions. 2046 */ 2047 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2048 ((mrq->cmd && mrq->cmd->error) || 2049 (mrq->data && (mrq->data->error || 2050 (mrq->data->stop && mrq->data->stop->error))) || 2051 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2052 2053 /* Some controllers need this kick or reset won't work here */ 2054 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2055 /* This is to force an update */ 2056 sdhci_update_clock(host); 2057 2058 /* Spec says we should do both at the same time, but Ricoh 2059 controllers do not like that. */ 2060 sdhci_reset(host, SDHCI_RESET_CMD); 2061 sdhci_reset(host, SDHCI_RESET_DATA); 2062 } 2063 2064 host->mrq = NULL; 2065 host->cmd = NULL; 2066 host->data = NULL; 2067 2068#ifndef SDHCI_USE_LEDS_CLASS 2069 sdhci_deactivate_led(host); 2070#endif 2071 2072 mmiowb(); 2073 spin_unlock_irqrestore(&host->lock, flags); 2074 2075 mmc_request_done(host->mmc, mrq); 2076 sdhci_runtime_pm_put(host); 2077} 2078 2079static void sdhci_timeout_timer(unsigned long data) 2080{ 2081 struct sdhci_host *host; 2082 unsigned long flags; 2083 2084 host = (struct sdhci_host*)data; 2085 2086 spin_lock_irqsave(&host->lock, flags); 2087 2088 if (host->mrq) { 2089 pr_err("%s: Timeout waiting for hardware " 2090 "interrupt.\n", mmc_hostname(host->mmc)); 2091 sdhci_dumpregs(host); 2092 2093 if (host->data) { 2094 host->data->error = -ETIMEDOUT; 2095 sdhci_finish_data(host); 2096 } else { 2097 if (host->cmd) 2098 host->cmd->error = -ETIMEDOUT; 2099 else 2100 host->mrq->cmd->error = -ETIMEDOUT; 2101 2102 tasklet_schedule(&host->finish_tasklet); 2103 } 2104 } 2105 2106 mmiowb(); 2107 spin_unlock_irqrestore(&host->lock, flags); 2108} 2109 2110static void sdhci_tuning_timer(unsigned long data) 2111{ 2112 struct sdhci_host *host; 2113 unsigned long flags; 2114 2115 host = (struct sdhci_host *)data; 2116 2117 spin_lock_irqsave(&host->lock, flags); 2118 2119 host->flags |= SDHCI_NEEDS_RETUNING; 2120 2121 spin_unlock_irqrestore(&host->lock, flags); 2122} 2123 2124/*****************************************************************************\ 2125 * * 2126 * Interrupt handling * 2127 * * 2128\*****************************************************************************/ 2129 2130static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2131{ 2132 BUG_ON(intmask == 0); 2133 2134 if (!host->cmd) { 2135 pr_err("%s: Got command interrupt 0x%08x even " 2136 "though no command operation was in progress.\n", 2137 mmc_hostname(host->mmc), (unsigned)intmask); 2138 sdhci_dumpregs(host); 2139 return; 2140 } 2141 2142 if (intmask & SDHCI_INT_TIMEOUT) 2143 host->cmd->error = -ETIMEDOUT; 2144 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 2145 SDHCI_INT_INDEX)) 2146 host->cmd->error = -EILSEQ; 2147 2148 if (host->cmd->error) { 2149 tasklet_schedule(&host->finish_tasklet); 2150 return; 2151 } 2152 2153 /* 2154 * The host can send and interrupt when the busy state has 2155 * ended, allowing us to wait without wasting CPU cycles. 2156 * Unfortunately this is overloaded on the "data complete" 2157 * interrupt, so we need to take some care when handling 2158 * it. 2159 * 2160 * Note: The 1.0 specification is a bit ambiguous about this 2161 * feature so there might be some problems with older 2162 * controllers. 2163 */ 2164 if (host->cmd->flags & MMC_RSP_BUSY) { 2165 if (host->cmd->data) 2166 DBG("Cannot wait for busy signal when also " 2167 "doing a data transfer"); 2168 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2169 return; 2170 2171 /* The controller does not support the end-of-busy IRQ, 2172 * fall through and take the SDHCI_INT_RESPONSE */ 2173 } 2174 2175 if (intmask & SDHCI_INT_RESPONSE) 2176 sdhci_finish_command(host); 2177} 2178 2179#ifdef CONFIG_MMC_DEBUG 2180static void sdhci_show_adma_error(struct sdhci_host *host) 2181{ 2182 const char *name = mmc_hostname(host->mmc); 2183 u8 *desc = host->adma_desc; 2184 __le32 *dma; 2185 __le16 *len; 2186 u8 attr; 2187 2188 sdhci_dumpregs(host); 2189 2190 while (true) { 2191 dma = (__le32 *)(desc + 4); 2192 len = (__le16 *)(desc + 2); 2193 attr = *desc; 2194 2195 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2196 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 2197 2198 desc += 8; 2199 2200 if (attr & 2) 2201 break; 2202 } 2203} 2204#else 2205static void sdhci_show_adma_error(struct sdhci_host *host) { } 2206#endif 2207 2208static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2209{ 2210 u32 command; 2211 BUG_ON(intmask == 0); 2212 2213 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2214 if (intmask & SDHCI_INT_DATA_AVAIL) { 2215 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2216 if (command == MMC_SEND_TUNING_BLOCK || 2217 command == MMC_SEND_TUNING_BLOCK_HS200) { 2218 host->tuning_done = 1; 2219 wake_up(&host->buf_ready_int); 2220 return; 2221 } 2222 } 2223 2224 if (!host->data) { 2225 /* 2226 * The "data complete" interrupt is also used to 2227 * indicate that a busy state has ended. See comment 2228 * above in sdhci_cmd_irq(). 2229 */ 2230 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2231 if (intmask & SDHCI_INT_DATA_END) { 2232 sdhci_finish_command(host); 2233 return; 2234 } 2235 } 2236 2237 pr_err("%s: Got data interrupt 0x%08x even " 2238 "though no data operation was in progress.\n", 2239 mmc_hostname(host->mmc), (unsigned)intmask); 2240 sdhci_dumpregs(host); 2241 2242 return; 2243 } 2244 2245 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2246 host->data->error = -ETIMEDOUT; 2247 else if (intmask & SDHCI_INT_DATA_END_BIT) 2248 host->data->error = -EILSEQ; 2249 else if ((intmask & SDHCI_INT_DATA_CRC) && 2250 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2251 != MMC_BUS_TEST_R) 2252 host->data->error = -EILSEQ; 2253 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2254 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2255 sdhci_show_adma_error(host); 2256 host->data->error = -EIO; 2257 if (host->ops->adma_workaround) 2258 host->ops->adma_workaround(host, intmask); 2259 } 2260 2261 if (host->data->error) 2262 sdhci_finish_data(host); 2263 else { 2264 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2265 sdhci_transfer_pio(host); 2266 2267 /* 2268 * We currently don't do anything fancy with DMA 2269 * boundaries, but as we can't disable the feature 2270 * we need to at least restart the transfer. 2271 * 2272 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2273 * should return a valid address to continue from, but as 2274 * some controllers are faulty, don't trust them. 2275 */ 2276 if (intmask & SDHCI_INT_DMA_END) { 2277 u32 dmastart, dmanow; 2278 dmastart = sg_dma_address(host->data->sg); 2279 dmanow = dmastart + host->data->bytes_xfered; 2280 /* 2281 * Force update to the next DMA block boundary. 2282 */ 2283 dmanow = (dmanow & 2284 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2285 SDHCI_DEFAULT_BOUNDARY_SIZE; 2286 host->data->bytes_xfered = dmanow - dmastart; 2287 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2288 " next 0x%08x\n", 2289 mmc_hostname(host->mmc), dmastart, 2290 host->data->bytes_xfered, dmanow); 2291 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2292 } 2293 2294 if (intmask & SDHCI_INT_DATA_END) { 2295 if (host->cmd) { 2296 /* 2297 * Data managed to finish before the 2298 * command completed. Make sure we do 2299 * things in the proper order. 2300 */ 2301 host->data_early = 1; 2302 } else { 2303 sdhci_finish_data(host); 2304 } 2305 } 2306 } 2307} 2308 2309static irqreturn_t sdhci_irq(int irq, void *dev_id) 2310{ 2311 irqreturn_t result; 2312 struct sdhci_host *host = dev_id; 2313 u32 intmask, unexpected = 0; 2314 int cardint = 0, max_loops = 16; 2315 2316 spin_lock(&host->lock); 2317 2318 if (host->runtime_suspended) { 2319 spin_unlock(&host->lock); 2320 pr_warning("%s: got irq while runtime suspended\n", 2321 mmc_hostname(host->mmc)); 2322 return IRQ_HANDLED; 2323 } 2324 2325 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2326 2327 if (!intmask || intmask == 0xffffffff) { 2328 result = IRQ_NONE; 2329 goto out; 2330 } 2331 2332again: 2333 DBG("*** %s got interrupt: 0x%08x\n", 2334 mmc_hostname(host->mmc), intmask); 2335 2336 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2337 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2338 SDHCI_CARD_PRESENT; 2339 2340 /* 2341 * There is a observation on i.mx esdhc. INSERT bit will be 2342 * immediately set again when it gets cleared, if a card is 2343 * inserted. We have to mask the irq to prevent interrupt 2344 * storm which will freeze the system. And the REMOVE gets 2345 * the same situation. 2346 * 2347 * More testing are needed here to ensure it works for other 2348 * platforms though. 2349 */ 2350 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : 2351 SDHCI_INT_CARD_REMOVE); 2352 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : 2353 SDHCI_INT_CARD_INSERT); 2354 2355 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2356 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2357 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2358 tasklet_schedule(&host->card_tasklet); 2359 } 2360 2361 if (intmask & SDHCI_INT_CMD_MASK) { 2362 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, 2363 SDHCI_INT_STATUS); 2364 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2365 } 2366 2367 if (intmask & SDHCI_INT_DATA_MASK) { 2368 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, 2369 SDHCI_INT_STATUS); 2370 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2371 } 2372 2373 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 2374 2375 intmask &= ~SDHCI_INT_ERROR; 2376 2377 if (intmask & SDHCI_INT_BUS_POWER) { 2378 pr_err("%s: Card is consuming too much power!\n", 2379 mmc_hostname(host->mmc)); 2380 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); 2381 } 2382 2383 intmask &= ~SDHCI_INT_BUS_POWER; 2384 2385 if (intmask & SDHCI_INT_CARD_INT) 2386 cardint = 1; 2387 2388 intmask &= ~SDHCI_INT_CARD_INT; 2389 2390 if (intmask) { 2391 unexpected |= intmask; 2392 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2393 } 2394 2395 result = IRQ_HANDLED; 2396 2397 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2398 if (intmask && --max_loops) 2399 goto again; 2400out: 2401 spin_unlock(&host->lock); 2402 2403 if (unexpected) { 2404 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2405 mmc_hostname(host->mmc), unexpected); 2406 sdhci_dumpregs(host); 2407 } 2408 /* 2409 * We have to delay this as it calls back into the driver. 2410 */ 2411 if (cardint) 2412 mmc_signal_sdio_irq(host->mmc); 2413 2414 return result; 2415} 2416 2417/*****************************************************************************\ 2418 * * 2419 * Suspend/resume * 2420 * * 2421\*****************************************************************************/ 2422 2423#ifdef CONFIG_PM 2424void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2425{ 2426 u8 val; 2427 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2428 | SDHCI_WAKE_ON_INT; 2429 2430 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2431 val |= mask ; 2432 /* Avoid fake wake up */ 2433 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2434 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2435 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2436} 2437EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2438 2439void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2440{ 2441 u8 val; 2442 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2443 | SDHCI_WAKE_ON_INT; 2444 2445 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2446 val &= ~mask; 2447 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2448} 2449EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); 2450 2451int sdhci_suspend_host(struct sdhci_host *host) 2452{ 2453 int ret; 2454 2455 if (host->ops->platform_suspend) 2456 host->ops->platform_suspend(host); 2457 2458 sdhci_disable_card_detection(host); 2459 2460 /* Disable tuning since we are suspending */ 2461 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2462 del_timer_sync(&host->tuning_timer); 2463 host->flags &= ~SDHCI_NEEDS_RETUNING; 2464 } 2465 2466 ret = mmc_suspend_host(host->mmc); 2467 if (ret) { 2468 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2469 host->flags |= SDHCI_NEEDS_RETUNING; 2470 mod_timer(&host->tuning_timer, jiffies + 2471 host->tuning_count * HZ); 2472 } 2473 2474 sdhci_enable_card_detection(host); 2475 2476 return ret; 2477 } 2478 2479 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2480 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 2481 free_irq(host->irq, host); 2482 } else { 2483 sdhci_enable_irq_wakeups(host); 2484 enable_irq_wake(host->irq); 2485 } 2486 return ret; 2487} 2488 2489EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2490 2491int sdhci_resume_host(struct sdhci_host *host) 2492{ 2493 int ret; 2494 2495 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2496 if (host->ops->enable_dma) 2497 host->ops->enable_dma(host); 2498 } 2499 2500 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2501 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2502 mmc_hostname(host->mmc), host); 2503 if (ret) 2504 return ret; 2505 } else { 2506 sdhci_disable_irq_wakeups(host); 2507 disable_irq_wake(host->irq); 2508 } 2509 2510 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2511 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2512 /* Card keeps power but host controller does not */ 2513 sdhci_init(host, 0); 2514 host->pwr = 0; 2515 host->clock = 0; 2516 sdhci_do_set_ios(host, &host->mmc->ios); 2517 } else { 2518 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2519 mmiowb(); 2520 } 2521 2522 ret = mmc_resume_host(host->mmc); 2523 sdhci_enable_card_detection(host); 2524 2525 if (host->ops->platform_resume) 2526 host->ops->platform_resume(host); 2527 2528 /* Set the re-tuning expiration flag */ 2529 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2530 host->flags |= SDHCI_NEEDS_RETUNING; 2531 2532 return ret; 2533} 2534 2535EXPORT_SYMBOL_GPL(sdhci_resume_host); 2536#endif /* CONFIG_PM */ 2537 2538#ifdef CONFIG_PM_RUNTIME 2539 2540static int sdhci_runtime_pm_get(struct sdhci_host *host) 2541{ 2542 return pm_runtime_get_sync(host->mmc->parent); 2543} 2544 2545static int sdhci_runtime_pm_put(struct sdhci_host *host) 2546{ 2547 pm_runtime_mark_last_busy(host->mmc->parent); 2548 return pm_runtime_put_autosuspend(host->mmc->parent); 2549} 2550 2551int sdhci_runtime_suspend_host(struct sdhci_host *host) 2552{ 2553 unsigned long flags; 2554 int ret = 0; 2555 2556 /* Disable tuning since we are suspending */ 2557 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2558 del_timer_sync(&host->tuning_timer); 2559 host->flags &= ~SDHCI_NEEDS_RETUNING; 2560 } 2561 2562 spin_lock_irqsave(&host->lock, flags); 2563 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 2564 spin_unlock_irqrestore(&host->lock, flags); 2565 2566 synchronize_irq(host->irq); 2567 2568 spin_lock_irqsave(&host->lock, flags); 2569 host->runtime_suspended = true; 2570 spin_unlock_irqrestore(&host->lock, flags); 2571 2572 return ret; 2573} 2574EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2575 2576int sdhci_runtime_resume_host(struct sdhci_host *host) 2577{ 2578 unsigned long flags; 2579 int ret = 0, host_flags = host->flags; 2580 2581 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2582 if (host->ops->enable_dma) 2583 host->ops->enable_dma(host); 2584 } 2585 2586 sdhci_init(host, 0); 2587 2588 /* Force clock and power re-program */ 2589 host->pwr = 0; 2590 host->clock = 0; 2591 sdhci_do_set_ios(host, &host->mmc->ios); 2592 2593 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2594 if (host_flags & SDHCI_PV_ENABLED) 2595 sdhci_do_enable_preset_value(host, true); 2596 2597 /* Set the re-tuning expiration flag */ 2598 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2599 host->flags |= SDHCI_NEEDS_RETUNING; 2600 2601 spin_lock_irqsave(&host->lock, flags); 2602 2603 host->runtime_suspended = false; 2604 2605 /* Enable SDIO IRQ */ 2606 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED)) 2607 sdhci_enable_sdio_irq_nolock(host, true); 2608 2609 /* Enable Card Detection */ 2610 sdhci_enable_card_detection(host); 2611 2612 spin_unlock_irqrestore(&host->lock, flags); 2613 2614 return ret; 2615} 2616EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2617 2618#endif 2619 2620/*****************************************************************************\ 2621 * * 2622 * Device allocation/registration * 2623 * * 2624\*****************************************************************************/ 2625 2626struct sdhci_host *sdhci_alloc_host(struct device *dev, 2627 size_t priv_size) 2628{ 2629 struct mmc_host *mmc; 2630 struct sdhci_host *host; 2631 2632 WARN_ON(dev == NULL); 2633 2634 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2635 if (!mmc) 2636 return ERR_PTR(-ENOMEM); 2637 2638 host = mmc_priv(mmc); 2639 host->mmc = mmc; 2640 2641 return host; 2642} 2643 2644EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2645 2646int sdhci_add_host(struct sdhci_host *host) 2647{ 2648 struct mmc_host *mmc; 2649 u32 caps[2] = {0, 0}; 2650 u32 max_current_caps; 2651 unsigned int ocr_avail; 2652 int ret; 2653 2654 WARN_ON(host == NULL); 2655 if (host == NULL) 2656 return -EINVAL; 2657 2658 mmc = host->mmc; 2659 2660 if (debug_quirks) 2661 host->quirks = debug_quirks; 2662 if (debug_quirks2) 2663 host->quirks2 = debug_quirks2; 2664 2665 sdhci_reset(host, SDHCI_RESET_ALL); 2666 2667 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2668 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2669 >> SDHCI_SPEC_VER_SHIFT; 2670 if (host->version > SDHCI_SPEC_300) { 2671 pr_err("%s: Unknown controller version (%d). " 2672 "You may experience problems.\n", mmc_hostname(mmc), 2673 host->version); 2674 } 2675 2676 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2677 sdhci_readl(host, SDHCI_CAPABILITIES); 2678 2679 if (host->version >= SDHCI_SPEC_300) 2680 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2681 host->caps1 : 2682 sdhci_readl(host, SDHCI_CAPABILITIES_1); 2683 2684 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2685 host->flags |= SDHCI_USE_SDMA; 2686 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2687 DBG("Controller doesn't have SDMA capability\n"); 2688 else 2689 host->flags |= SDHCI_USE_SDMA; 2690 2691 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2692 (host->flags & SDHCI_USE_SDMA)) { 2693 DBG("Disabling DMA as it is marked broken\n"); 2694 host->flags &= ~SDHCI_USE_SDMA; 2695 } 2696 2697 if ((host->version >= SDHCI_SPEC_200) && 2698 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2699 host->flags |= SDHCI_USE_ADMA; 2700 2701 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2702 (host->flags & SDHCI_USE_ADMA)) { 2703 DBG("Disabling ADMA as it is marked broken\n"); 2704 host->flags &= ~SDHCI_USE_ADMA; 2705 } 2706 2707 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2708 if (host->ops->enable_dma) { 2709 if (host->ops->enable_dma(host)) { 2710 pr_warning("%s: No suitable DMA " 2711 "available. Falling back to PIO.\n", 2712 mmc_hostname(mmc)); 2713 host->flags &= 2714 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2715 } 2716 } 2717 } 2718 2719 if (host->flags & SDHCI_USE_ADMA) { 2720 /* 2721 * We need to allocate descriptors for all sg entries 2722 * (128) and potentially one alignment transfer for 2723 * each of those entries. 2724 */ 2725 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); 2726 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 2727 if (!host->adma_desc || !host->align_buffer) { 2728 kfree(host->adma_desc); 2729 kfree(host->align_buffer); 2730 pr_warning("%s: Unable to allocate ADMA " 2731 "buffers. Falling back to standard DMA.\n", 2732 mmc_hostname(mmc)); 2733 host->flags &= ~SDHCI_USE_ADMA; 2734 } 2735 } 2736 2737 /* 2738 * If we use DMA, then it's up to the caller to set the DMA 2739 * mask, but PIO does not need the hw shim so we set a new 2740 * mask here in that case. 2741 */ 2742 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2743 host->dma_mask = DMA_BIT_MASK(64); 2744 mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 2745 } 2746 2747 if (host->version >= SDHCI_SPEC_300) 2748 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2749 >> SDHCI_CLOCK_BASE_SHIFT; 2750 else 2751 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2752 >> SDHCI_CLOCK_BASE_SHIFT; 2753 2754 host->max_clk *= 1000000; 2755 if (host->max_clk == 0 || host->quirks & 2756 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2757 if (!host->ops->get_max_clock) { 2758 pr_err("%s: Hardware doesn't specify base clock " 2759 "frequency.\n", mmc_hostname(mmc)); 2760 return -ENODEV; 2761 } 2762 host->max_clk = host->ops->get_max_clock(host); 2763 } 2764 2765 /* 2766 * In case of Host Controller v3.00, find out whether clock 2767 * multiplier is supported. 2768 */ 2769 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2770 SDHCI_CLOCK_MUL_SHIFT; 2771 2772 /* 2773 * In case the value in Clock Multiplier is 0, then programmable 2774 * clock mode is not supported, otherwise the actual clock 2775 * multiplier is one more than the value of Clock Multiplier 2776 * in the Capabilities Register. 2777 */ 2778 if (host->clk_mul) 2779 host->clk_mul += 1; 2780 2781 /* 2782 * Set host parameters. 2783 */ 2784 mmc->ops = &sdhci_ops; 2785 mmc->f_max = host->max_clk; 2786 if (host->ops->get_min_clock) 2787 mmc->f_min = host->ops->get_min_clock(host); 2788 else if (host->version >= SDHCI_SPEC_300) { 2789 if (host->clk_mul) { 2790 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2791 mmc->f_max = host->max_clk * host->clk_mul; 2792 } else 2793 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2794 } else 2795 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 2796 2797 host->timeout_clk = 2798 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2799 if (host->timeout_clk == 0) { 2800 if (host->ops->get_timeout_clock) { 2801 host->timeout_clk = host->ops->get_timeout_clock(host); 2802 } else if (!(host->quirks & 2803 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2804 pr_err("%s: Hardware doesn't specify timeout clock " 2805 "frequency.\n", mmc_hostname(mmc)); 2806 return -ENODEV; 2807 } 2808 } 2809 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2810 host->timeout_clk *= 1000; 2811 2812 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 2813 host->timeout_clk = mmc->f_max / 1000; 2814 2815 mmc->max_discard_to = (1 << 27) / host->timeout_clk; 2816 2817 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2818 2819 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2820 host->flags |= SDHCI_AUTO_CMD12; 2821 2822 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 2823 if ((host->version >= SDHCI_SPEC_300) && 2824 ((host->flags & SDHCI_USE_ADMA) || 2825 !(host->flags & SDHCI_USE_SDMA))) { 2826 host->flags |= SDHCI_AUTO_CMD23; 2827 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 2828 } else { 2829 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 2830 } 2831 2832 /* 2833 * A controller may support 8-bit width, but the board itself 2834 * might not have the pins brought out. Boards that support 2835 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 2836 * their platform code before calling sdhci_add_host(), and we 2837 * won't assume 8-bit width for hosts without that CAP. 2838 */ 2839 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 2840 mmc->caps |= MMC_CAP_4_BIT_DATA; 2841 2842 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 2843 mmc->caps &= ~MMC_CAP_CMD23; 2844 2845 if (caps[0] & SDHCI_CAN_DO_HISPD) 2846 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2847 2848 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2849 !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) 2850 mmc->caps |= MMC_CAP_NEEDS_POLL; 2851 2852 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 2853 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc"); 2854 if (IS_ERR_OR_NULL(host->vqmmc)) { 2855 if (PTR_ERR(host->vqmmc) < 0) { 2856 pr_info("%s: no vqmmc regulator found\n", 2857 mmc_hostname(mmc)); 2858 host->vqmmc = NULL; 2859 } 2860 } else { 2861 regulator_enable(host->vqmmc); 2862 if (!regulator_is_supported_voltage(host->vqmmc, 1700000, 2863 1950000)) 2864 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 2865 SDHCI_SUPPORT_SDR50 | 2866 SDHCI_SUPPORT_DDR50); 2867 } 2868 2869 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 2870 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2871 SDHCI_SUPPORT_DDR50); 2872 2873 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 2874 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2875 SDHCI_SUPPORT_DDR50)) 2876 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 2877 2878 /* SDR104 supports also implies SDR50 support */ 2879 if (caps[1] & SDHCI_SUPPORT_SDR104) 2880 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 2881 else if (caps[1] & SDHCI_SUPPORT_SDR50) 2882 mmc->caps |= MMC_CAP_UHS_SDR50; 2883 2884 if (caps[1] & SDHCI_SUPPORT_DDR50) 2885 mmc->caps |= MMC_CAP_UHS_DDR50; 2886 2887 /* Does the host need tuning for SDR50? */ 2888 if (caps[1] & SDHCI_USE_SDR50_TUNING) 2889 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 2890 2891 /* Does the host need tuning for HS200? */ 2892 if (mmc->caps2 & MMC_CAP2_HS200) 2893 host->flags |= SDHCI_HS200_NEEDS_TUNING; 2894 2895 /* Driver Type(s) (A, C, D) supported by the host */ 2896 if (caps[1] & SDHCI_DRIVER_TYPE_A) 2897 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 2898 if (caps[1] & SDHCI_DRIVER_TYPE_C) 2899 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 2900 if (caps[1] & SDHCI_DRIVER_TYPE_D) 2901 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 2902 2903 /* Initial value for re-tuning timer count */ 2904 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 2905 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 2906 2907 /* 2908 * In case Re-tuning Timer is not disabled, the actual value of 2909 * re-tuning timer will be 2 ^ (n - 1). 2910 */ 2911 if (host->tuning_count) 2912 host->tuning_count = 1 << (host->tuning_count - 1); 2913 2914 /* Re-tuning mode supported by the Host Controller */ 2915 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 2916 SDHCI_RETUNING_MODE_SHIFT; 2917 2918 ocr_avail = 0; 2919 2920 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); 2921 if (IS_ERR_OR_NULL(host->vmmc)) { 2922 if (PTR_ERR(host->vmmc) < 0) { 2923 pr_info("%s: no vmmc regulator found\n", 2924 mmc_hostname(mmc)); 2925 host->vmmc = NULL; 2926 } 2927 } 2928 2929#ifdef CONFIG_REGULATOR 2930 if (host->vmmc) { 2931 ret = regulator_is_supported_voltage(host->vmmc, 2700000, 2932 3600000); 2933 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) 2934 caps[0] &= ~SDHCI_CAN_VDD_330; 2935 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) 2936 caps[0] &= ~SDHCI_CAN_VDD_300; 2937 ret = regulator_is_supported_voltage(host->vmmc, 1700000, 2938 1950000); 2939 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) 2940 caps[0] &= ~SDHCI_CAN_VDD_180; 2941 } 2942#endif /* CONFIG_REGULATOR */ 2943 2944 /* 2945 * According to SD Host Controller spec v3.00, if the Host System 2946 * can afford more than 150mA, Host Driver should set XPC to 1. Also 2947 * the value is meaningful only if Voltage Support in the Capabilities 2948 * register is set. The actual current value is 4 times the register 2949 * value. 2950 */ 2951 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 2952 if (!max_current_caps && host->vmmc) { 2953 u32 curr = regulator_get_current_limit(host->vmmc); 2954 if (curr > 0) { 2955 2956 /* convert to SDHCI_MAX_CURRENT format */ 2957 curr = curr/1000; /* convert to mA */ 2958 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 2959 2960 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 2961 max_current_caps = 2962 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 2963 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 2964 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 2965 } 2966 } 2967 2968 if (caps[0] & SDHCI_CAN_VDD_330) { 2969 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 2970 2971 mmc->max_current_330 = ((max_current_caps & 2972 SDHCI_MAX_CURRENT_330_MASK) >> 2973 SDHCI_MAX_CURRENT_330_SHIFT) * 2974 SDHCI_MAX_CURRENT_MULTIPLIER; 2975 } 2976 if (caps[0] & SDHCI_CAN_VDD_300) { 2977 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 2978 2979 mmc->max_current_300 = ((max_current_caps & 2980 SDHCI_MAX_CURRENT_300_MASK) >> 2981 SDHCI_MAX_CURRENT_300_SHIFT) * 2982 SDHCI_MAX_CURRENT_MULTIPLIER; 2983 } 2984 if (caps[0] & SDHCI_CAN_VDD_180) { 2985 ocr_avail |= MMC_VDD_165_195; 2986 2987 mmc->max_current_180 = ((max_current_caps & 2988 SDHCI_MAX_CURRENT_180_MASK) >> 2989 SDHCI_MAX_CURRENT_180_SHIFT) * 2990 SDHCI_MAX_CURRENT_MULTIPLIER; 2991 } 2992 2993 mmc->ocr_avail = ocr_avail; 2994 mmc->ocr_avail_sdio = ocr_avail; 2995 if (host->ocr_avail_sdio) 2996 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 2997 mmc->ocr_avail_sd = ocr_avail; 2998 if (host->ocr_avail_sd) 2999 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3000 else /* normal SD controllers don't support 1.8V */ 3001 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3002 mmc->ocr_avail_mmc = ocr_avail; 3003 if (host->ocr_avail_mmc) 3004 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3005 3006 if (mmc->ocr_avail == 0) { 3007 pr_err("%s: Hardware doesn't report any " 3008 "support voltages.\n", mmc_hostname(mmc)); 3009 return -ENODEV; 3010 } 3011 3012 spin_lock_init(&host->lock); 3013 3014 /* 3015 * Maximum number of segments. Depends on if the hardware 3016 * can do scatter/gather or not. 3017 */ 3018 if (host->flags & SDHCI_USE_ADMA) 3019 mmc->max_segs = 128; 3020 else if (host->flags & SDHCI_USE_SDMA) 3021 mmc->max_segs = 1; 3022 else /* PIO */ 3023 mmc->max_segs = 128; 3024 3025 /* 3026 * Maximum number of sectors in one transfer. Limited by DMA boundary 3027 * size (512KiB). 3028 */ 3029 mmc->max_req_size = 524288; 3030 3031 /* 3032 * Maximum segment size. Could be one segment with the maximum number 3033 * of bytes. When doing hardware scatter/gather, each entry cannot 3034 * be larger than 64 KiB though. 3035 */ 3036 if (host->flags & SDHCI_USE_ADMA) { 3037 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3038 mmc->max_seg_size = 65535; 3039 else 3040 mmc->max_seg_size = 65536; 3041 } else { 3042 mmc->max_seg_size = mmc->max_req_size; 3043 } 3044 3045 /* 3046 * Maximum block size. This varies from controller to controller and 3047 * is specified in the capabilities register. 3048 */ 3049 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3050 mmc->max_blk_size = 2; 3051 } else { 3052 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3053 SDHCI_MAX_BLOCK_SHIFT; 3054 if (mmc->max_blk_size >= 3) { 3055 pr_warning("%s: Invalid maximum block size, " 3056 "assuming 512 bytes\n", mmc_hostname(mmc)); 3057 mmc->max_blk_size = 0; 3058 } 3059 } 3060 3061 mmc->max_blk_size = 512 << mmc->max_blk_size; 3062 3063 /* 3064 * Maximum block count. 3065 */ 3066 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3067 3068 /* 3069 * Init tasklets. 3070 */ 3071 tasklet_init(&host->card_tasklet, 3072 sdhci_tasklet_card, (unsigned long)host); 3073 tasklet_init(&host->finish_tasklet, 3074 sdhci_tasklet_finish, (unsigned long)host); 3075 3076 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3077 3078 if (host->version >= SDHCI_SPEC_300) { 3079 init_waitqueue_head(&host->buf_ready_int); 3080 3081 /* Initialize re-tuning timer */ 3082 init_timer(&host->tuning_timer); 3083 host->tuning_timer.data = (unsigned long)host; 3084 host->tuning_timer.function = sdhci_tuning_timer; 3085 } 3086 3087 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 3088 mmc_hostname(mmc), host); 3089 if (ret) { 3090 pr_err("%s: Failed to request IRQ %d: %d\n", 3091 mmc_hostname(mmc), host->irq, ret); 3092 goto untasklet; 3093 } 3094 3095 sdhci_init(host, 0); 3096 3097#ifdef CONFIG_MMC_DEBUG 3098 sdhci_dumpregs(host); 3099#endif 3100 3101#ifdef SDHCI_USE_LEDS_CLASS 3102 snprintf(host->led_name, sizeof(host->led_name), 3103 "%s::", mmc_hostname(mmc)); 3104 host->led.name = host->led_name; 3105 host->led.brightness = LED_OFF; 3106 host->led.default_trigger = mmc_hostname(mmc); 3107 host->led.brightness_set = sdhci_led_control; 3108 3109 ret = led_classdev_register(mmc_dev(mmc), &host->led); 3110 if (ret) { 3111 pr_err("%s: Failed to register LED device: %d\n", 3112 mmc_hostname(mmc), ret); 3113 goto reset; 3114 } 3115#endif 3116 3117 mmiowb(); 3118 3119 mmc_add_host(mmc); 3120 3121 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3122 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3123 (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3124 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3125 3126 sdhci_enable_card_detection(host); 3127 3128 return 0; 3129 3130#ifdef SDHCI_USE_LEDS_CLASS 3131reset: 3132 sdhci_reset(host, SDHCI_RESET_ALL); 3133 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 3134 free_irq(host->irq, host); 3135#endif 3136untasklet: 3137 tasklet_kill(&host->card_tasklet); 3138 tasklet_kill(&host->finish_tasklet); 3139 3140 return ret; 3141} 3142 3143EXPORT_SYMBOL_GPL(sdhci_add_host); 3144 3145void sdhci_remove_host(struct sdhci_host *host, int dead) 3146{ 3147 unsigned long flags; 3148 3149 if (dead) { 3150 spin_lock_irqsave(&host->lock, flags); 3151 3152 host->flags |= SDHCI_DEVICE_DEAD; 3153 3154 if (host->mrq) { 3155 pr_err("%s: Controller removed during " 3156 " transfer!\n", mmc_hostname(host->mmc)); 3157 3158 host->mrq->cmd->error = -ENOMEDIUM; 3159 tasklet_schedule(&host->finish_tasklet); 3160 } 3161 3162 spin_unlock_irqrestore(&host->lock, flags); 3163 } 3164 3165 sdhci_disable_card_detection(host); 3166 3167 mmc_remove_host(host->mmc); 3168 3169#ifdef SDHCI_USE_LEDS_CLASS 3170 led_classdev_unregister(&host->led); 3171#endif 3172 3173 if (!dead) 3174 sdhci_reset(host, SDHCI_RESET_ALL); 3175 3176 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 3177 free_irq(host->irq, host); 3178 3179 del_timer_sync(&host->timer); 3180 3181 tasklet_kill(&host->card_tasklet); 3182 tasklet_kill(&host->finish_tasklet); 3183 3184 if (host->vmmc) { 3185 regulator_disable(host->vmmc); 3186 regulator_put(host->vmmc); 3187 } 3188 3189 if (host->vqmmc) { 3190 regulator_disable(host->vqmmc); 3191 regulator_put(host->vqmmc); 3192 } 3193 3194 kfree(host->adma_desc); 3195 kfree(host->align_buffer); 3196 3197 host->adma_desc = NULL; 3198 host->align_buffer = NULL; 3199} 3200 3201EXPORT_SYMBOL_GPL(sdhci_remove_host); 3202 3203void sdhci_free_host(struct sdhci_host *host) 3204{ 3205 mmc_free_host(host->mmc); 3206} 3207 3208EXPORT_SYMBOL_GPL(sdhci_free_host); 3209 3210/*****************************************************************************\ 3211 * * 3212 * Driver init/exit * 3213 * * 3214\*****************************************************************************/ 3215 3216static int __init sdhci_drv_init(void) 3217{ 3218 pr_info(DRIVER_NAME 3219 ": Secure Digital Host Controller Interface driver\n"); 3220 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3221 3222 return 0; 3223} 3224 3225static void __exit sdhci_drv_exit(void) 3226{ 3227} 3228 3229module_init(sdhci_drv_init); 3230module_exit(sdhci_drv_exit); 3231 3232module_param(debug_quirks, uint, 0444); 3233module_param(debug_quirks2, uint, 0444); 3234 3235MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3236MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3237MODULE_LICENSE("GPL"); 3238 3239MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3240MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3241