pxa3xx_nand.c revision 657f28f8811c92724db10d18bbbec70d540147d6
1/* 2 * drivers/mtd/nand/pxa3xx_nand.c 3 * 4 * Copyright © 2005 Intel Corporation 5 * Copyright © 2006 Marvell International Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/interrupt.h> 15#include <linux/platform_device.h> 16#include <linux/dma-mapping.h> 17#include <linux/delay.h> 18#include <linux/clk.h> 19#include <linux/mtd/mtd.h> 20#include <linux/mtd/nand.h> 21#include <linux/mtd/partitions.h> 22#include <linux/io.h> 23#include <linux/irq.h> 24#include <linux/slab.h> 25 26#include <mach/dma.h> 27#include <plat/pxa3xx_nand.h> 28 29#define CHIP_DELAY_TIMEOUT (2 * HZ/10) 30#define NAND_STOP_DELAY (2 * HZ/50) 31#define PAGE_CHUNK_SIZE (2048) 32 33/* registers and bit definitions */ 34#define NDCR (0x00) /* Control register */ 35#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ 36#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ 37#define NDSR (0x14) /* Status Register */ 38#define NDPCR (0x18) /* Page Count Register */ 39#define NDBDR0 (0x1C) /* Bad Block Register 0 */ 40#define NDBDR1 (0x20) /* Bad Block Register 1 */ 41#define NDDB (0x40) /* Data Buffer */ 42#define NDCB0 (0x48) /* Command Buffer0 */ 43#define NDCB1 (0x4C) /* Command Buffer1 */ 44#define NDCB2 (0x50) /* Command Buffer2 */ 45 46#define NDCR_SPARE_EN (0x1 << 31) 47#define NDCR_ECC_EN (0x1 << 30) 48#define NDCR_DMA_EN (0x1 << 29) 49#define NDCR_ND_RUN (0x1 << 28) 50#define NDCR_DWIDTH_C (0x1 << 27) 51#define NDCR_DWIDTH_M (0x1 << 26) 52#define NDCR_PAGE_SZ (0x1 << 24) 53#define NDCR_NCSX (0x1 << 23) 54#define NDCR_ND_MODE (0x3 << 21) 55#define NDCR_NAND_MODE (0x0) 56#define NDCR_CLR_PG_CNT (0x1 << 20) 57#define NDCR_STOP_ON_UNCOR (0x1 << 19) 58#define NDCR_RD_ID_CNT_MASK (0x7 << 16) 59#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) 60 61#define NDCR_RA_START (0x1 << 15) 62#define NDCR_PG_PER_BLK (0x1 << 14) 63#define NDCR_ND_ARB_EN (0x1 << 12) 64#define NDCR_INT_MASK (0xFFF) 65 66#define NDSR_MASK (0xfff) 67#define NDSR_RDY (0x1 << 12) 68#define NDSR_FLASH_RDY (0x1 << 11) 69#define NDSR_CS0_PAGED (0x1 << 10) 70#define NDSR_CS1_PAGED (0x1 << 9) 71#define NDSR_CS0_CMDD (0x1 << 8) 72#define NDSR_CS1_CMDD (0x1 << 7) 73#define NDSR_CS0_BBD (0x1 << 6) 74#define NDSR_CS1_BBD (0x1 << 5) 75#define NDSR_DBERR (0x1 << 4) 76#define NDSR_SBERR (0x1 << 3) 77#define NDSR_WRDREQ (0x1 << 2) 78#define NDSR_RDDREQ (0x1 << 1) 79#define NDSR_WRCMDREQ (0x1) 80 81#define NDCB0_ST_ROW_EN (0x1 << 26) 82#define NDCB0_AUTO_RS (0x1 << 25) 83#define NDCB0_CSEL (0x1 << 24) 84#define NDCB0_CMD_TYPE_MASK (0x7 << 21) 85#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) 86#define NDCB0_NC (0x1 << 20) 87#define NDCB0_DBC (0x1 << 19) 88#define NDCB0_ADDR_CYC_MASK (0x7 << 16) 89#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) 90#define NDCB0_CMD2_MASK (0xff << 8) 91#define NDCB0_CMD1_MASK (0xff) 92#define NDCB0_ADDR_CYC_SHIFT (16) 93 94/* macros for registers read/write */ 95#define nand_writel(info, off, val) \ 96 __raw_writel((val), (info)->mmio_base + (off)) 97 98#define nand_readl(info, off) \ 99 __raw_readl((info)->mmio_base + (off)) 100 101/* error code and state */ 102enum { 103 ERR_NONE = 0, 104 ERR_DMABUSERR = -1, 105 ERR_SENDCMD = -2, 106 ERR_DBERR = -3, 107 ERR_BBERR = -4, 108 ERR_SBERR = -5, 109}; 110 111enum { 112 STATE_IDLE = 0, 113 STATE_PREPARED, 114 STATE_CMD_HANDLE, 115 STATE_DMA_READING, 116 STATE_DMA_WRITING, 117 STATE_DMA_DONE, 118 STATE_PIO_READING, 119 STATE_PIO_WRITING, 120 STATE_CMD_DONE, 121 STATE_READY, 122}; 123 124struct pxa3xx_nand_host { 125 struct nand_chip chip; 126 struct pxa3xx_nand_cmdset *cmdset; 127 struct mtd_info *mtd; 128 void *info_data; 129 130 /* page size of attached chip */ 131 unsigned int page_size; 132 int use_ecc; 133 int cs; 134 135 /* calculated from pxa3xx_nand_flash data */ 136 unsigned int col_addr_cycles; 137 unsigned int row_addr_cycles; 138 size_t read_id_bytes; 139 140 /* cached register value */ 141 uint32_t reg_ndcr; 142 uint32_t ndtr0cs0; 143 uint32_t ndtr1cs0; 144}; 145 146struct pxa3xx_nand_info { 147 struct nand_hw_control controller; 148 struct platform_device *pdev; 149 150 struct clk *clk; 151 void __iomem *mmio_base; 152 unsigned long mmio_phys; 153 struct completion cmd_complete; 154 155 unsigned int buf_start; 156 unsigned int buf_count; 157 158 /* DMA information */ 159 int drcmr_dat; 160 int drcmr_cmd; 161 162 unsigned char *data_buff; 163 unsigned char *oob_buff; 164 dma_addr_t data_buff_phys; 165 int data_dma_ch; 166 struct pxa_dma_desc *data_desc; 167 dma_addr_t data_desc_addr; 168 169 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT]; 170 unsigned int state; 171 172 int cs; 173 int use_ecc; /* use HW ECC ? */ 174 int use_dma; /* use DMA ? */ 175 int is_ready; 176 177 unsigned int page_size; /* page size of attached chip */ 178 unsigned int data_size; /* data size in FIFO */ 179 unsigned int oob_size; 180 int retcode; 181 182 /* generated NDCBx register values */ 183 uint32_t ndcb0; 184 uint32_t ndcb1; 185 uint32_t ndcb2; 186}; 187 188static bool use_dma = 1; 189module_param(use_dma, bool, 0444); 190MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW"); 191 192/* 193 * Default NAND flash controller configuration setup by the 194 * bootloader. This configuration is used only when pdata->keep_config is set 195 */ 196static struct pxa3xx_nand_cmdset default_cmdset = { 197 .read1 = 0x3000, 198 .read2 = 0x0050, 199 .program = 0x1080, 200 .read_status = 0x0070, 201 .read_id = 0x0090, 202 .erase = 0xD060, 203 .reset = 0x00FF, 204 .lock = 0x002A, 205 .unlock = 0x2423, 206 .lock_status = 0x007A, 207}; 208 209static struct pxa3xx_nand_timing timing[] = { 210 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, 211 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, 212 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, 213 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, 214}; 215 216static struct pxa3xx_nand_flash builtin_flash_types[] = { 217{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] }, 218{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] }, 219{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] }, 220{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, 221{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] }, 222{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] }, 223{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] }, 224{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] }, 225{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] }, 226}; 227 228/* Define a default flash type setting serve as flash detecting only */ 229#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) 230 231const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL}; 232 233#define NDTR0_tCH(c) (min((c), 7) << 19) 234#define NDTR0_tCS(c) (min((c), 7) << 16) 235#define NDTR0_tWH(c) (min((c), 7) << 11) 236#define NDTR0_tWP(c) (min((c), 7) << 8) 237#define NDTR0_tRH(c) (min((c), 7) << 3) 238#define NDTR0_tRP(c) (min((c), 7) << 0) 239 240#define NDTR1_tR(c) (min((c), 65535) << 16) 241#define NDTR1_tWHR(c) (min((c), 15) << 4) 242#define NDTR1_tAR(c) (min((c), 15) << 0) 243 244/* convert nano-seconds to nand flash controller clock cycles */ 245#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) 246 247static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, 248 const struct pxa3xx_nand_timing *t) 249{ 250 struct pxa3xx_nand_info *info = host->info_data; 251 unsigned long nand_clk = clk_get_rate(info->clk); 252 uint32_t ndtr0, ndtr1; 253 254 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | 255 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | 256 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | 257 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | 258 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | 259 NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); 260 261 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | 262 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | 263 NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); 264 265 host->ndtr0cs0 = ndtr0; 266 host->ndtr1cs0 = ndtr1; 267 nand_writel(info, NDTR0CS0, ndtr0); 268 nand_writel(info, NDTR1CS0, ndtr1); 269} 270 271static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) 272{ 273 struct pxa3xx_nand_host *host = info->host[info->cs]; 274 int oob_enable = host->reg_ndcr & NDCR_SPARE_EN; 275 276 info->data_size = host->page_size; 277 if (!oob_enable) { 278 info->oob_size = 0; 279 return; 280 } 281 282 switch (host->page_size) { 283 case 2048: 284 info->oob_size = (info->use_ecc) ? 40 : 64; 285 break; 286 case 512: 287 info->oob_size = (info->use_ecc) ? 8 : 16; 288 break; 289 } 290} 291 292/** 293 * NOTE: it is a must to set ND_RUN firstly, then write 294 * command buffer, otherwise, it does not work. 295 * We enable all the interrupt at the same time, and 296 * let pxa3xx_nand_irq to handle all logic. 297 */ 298static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) 299{ 300 struct pxa3xx_nand_host *host = info->host[info->cs]; 301 uint32_t ndcr; 302 303 ndcr = host->reg_ndcr; 304 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0; 305 ndcr |= info->use_dma ? NDCR_DMA_EN : 0; 306 ndcr |= NDCR_ND_RUN; 307 308 /* clear status bits and run */ 309 nand_writel(info, NDCR, 0); 310 nand_writel(info, NDSR, NDSR_MASK); 311 nand_writel(info, NDCR, ndcr); 312} 313 314static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) 315{ 316 uint32_t ndcr; 317 int timeout = NAND_STOP_DELAY; 318 319 /* wait RUN bit in NDCR become 0 */ 320 ndcr = nand_readl(info, NDCR); 321 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) { 322 ndcr = nand_readl(info, NDCR); 323 udelay(1); 324 } 325 326 if (timeout <= 0) { 327 ndcr &= ~NDCR_ND_RUN; 328 nand_writel(info, NDCR, ndcr); 329 } 330 /* clear status bits */ 331 nand_writel(info, NDSR, NDSR_MASK); 332} 333 334static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) 335{ 336 uint32_t ndcr; 337 338 ndcr = nand_readl(info, NDCR); 339 nand_writel(info, NDCR, ndcr & ~int_mask); 340} 341 342static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) 343{ 344 uint32_t ndcr; 345 346 ndcr = nand_readl(info, NDCR); 347 nand_writel(info, NDCR, ndcr | int_mask); 348} 349 350static void handle_data_pio(struct pxa3xx_nand_info *info) 351{ 352 switch (info->state) { 353 case STATE_PIO_WRITING: 354 __raw_writesl(info->mmio_base + NDDB, info->data_buff, 355 DIV_ROUND_UP(info->data_size, 4)); 356 if (info->oob_size > 0) 357 __raw_writesl(info->mmio_base + NDDB, info->oob_buff, 358 DIV_ROUND_UP(info->oob_size, 4)); 359 break; 360 case STATE_PIO_READING: 361 __raw_readsl(info->mmio_base + NDDB, info->data_buff, 362 DIV_ROUND_UP(info->data_size, 4)); 363 if (info->oob_size > 0) 364 __raw_readsl(info->mmio_base + NDDB, info->oob_buff, 365 DIV_ROUND_UP(info->oob_size, 4)); 366 break; 367 default: 368 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, 369 info->state); 370 BUG(); 371 } 372} 373 374static void start_data_dma(struct pxa3xx_nand_info *info) 375{ 376 struct pxa_dma_desc *desc = info->data_desc; 377 int dma_len = ALIGN(info->data_size + info->oob_size, 32); 378 379 desc->ddadr = DDADR_STOP; 380 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len; 381 382 switch (info->state) { 383 case STATE_DMA_WRITING: 384 desc->dsadr = info->data_buff_phys; 385 desc->dtadr = info->mmio_phys + NDDB; 386 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; 387 break; 388 case STATE_DMA_READING: 389 desc->dtadr = info->data_buff_phys; 390 desc->dsadr = info->mmio_phys + NDDB; 391 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; 392 break; 393 default: 394 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, 395 info->state); 396 BUG(); 397 } 398 399 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; 400 DDADR(info->data_dma_ch) = info->data_desc_addr; 401 DCSR(info->data_dma_ch) |= DCSR_RUN; 402} 403 404static void pxa3xx_nand_data_dma_irq(int channel, void *data) 405{ 406 struct pxa3xx_nand_info *info = data; 407 uint32_t dcsr; 408 409 dcsr = DCSR(channel); 410 DCSR(channel) = dcsr; 411 412 if (dcsr & DCSR_BUSERR) { 413 info->retcode = ERR_DMABUSERR; 414 } 415 416 info->state = STATE_DMA_DONE; 417 enable_int(info, NDCR_INT_MASK); 418 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); 419} 420 421static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) 422{ 423 struct pxa3xx_nand_info *info = devid; 424 unsigned int status, is_completed = 0; 425 unsigned int ready, cmd_done; 426 427 if (info->cs == 0) { 428 ready = NDSR_FLASH_RDY; 429 cmd_done = NDSR_CS0_CMDD; 430 } else { 431 ready = NDSR_RDY; 432 cmd_done = NDSR_CS1_CMDD; 433 } 434 435 status = nand_readl(info, NDSR); 436 437 if (status & NDSR_DBERR) 438 info->retcode = ERR_DBERR; 439 if (status & NDSR_SBERR) 440 info->retcode = ERR_SBERR; 441 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { 442 /* whether use dma to transfer data */ 443 if (info->use_dma) { 444 disable_int(info, NDCR_INT_MASK); 445 info->state = (status & NDSR_RDDREQ) ? 446 STATE_DMA_READING : STATE_DMA_WRITING; 447 start_data_dma(info); 448 goto NORMAL_IRQ_EXIT; 449 } else { 450 info->state = (status & NDSR_RDDREQ) ? 451 STATE_PIO_READING : STATE_PIO_WRITING; 452 handle_data_pio(info); 453 } 454 } 455 if (status & cmd_done) { 456 info->state = STATE_CMD_DONE; 457 is_completed = 1; 458 } 459 if (status & ready) { 460 info->is_ready = 1; 461 info->state = STATE_READY; 462 } 463 464 if (status & NDSR_WRCMDREQ) { 465 nand_writel(info, NDSR, NDSR_WRCMDREQ); 466 status &= ~NDSR_WRCMDREQ; 467 info->state = STATE_CMD_HANDLE; 468 nand_writel(info, NDCB0, info->ndcb0); 469 nand_writel(info, NDCB0, info->ndcb1); 470 nand_writel(info, NDCB0, info->ndcb2); 471 } 472 473 /* clear NDSR to let the controller exit the IRQ */ 474 nand_writel(info, NDSR, status); 475 if (is_completed) 476 complete(&info->cmd_complete); 477NORMAL_IRQ_EXIT: 478 return IRQ_HANDLED; 479} 480 481static inline int is_buf_blank(uint8_t *buf, size_t len) 482{ 483 for (; len > 0; len--) 484 if (*buf++ != 0xff) 485 return 0; 486 return 1; 487} 488 489static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, 490 uint16_t column, int page_addr) 491{ 492 uint16_t cmd; 493 int addr_cycle, exec_cmd; 494 struct pxa3xx_nand_host *host; 495 struct mtd_info *mtd; 496 497 host = info->host[info->cs]; 498 mtd = host->mtd; 499 addr_cycle = 0; 500 exec_cmd = 1; 501 502 /* reset data and oob column point to handle data */ 503 info->buf_start = 0; 504 info->buf_count = 0; 505 info->oob_size = 0; 506 info->use_ecc = 0; 507 info->is_ready = 0; 508 info->retcode = ERR_NONE; 509 if (info->cs != 0) 510 info->ndcb0 = NDCB0_CSEL; 511 else 512 info->ndcb0 = 0; 513 514 switch (command) { 515 case NAND_CMD_READ0: 516 case NAND_CMD_PAGEPROG: 517 info->use_ecc = 1; 518 case NAND_CMD_READOOB: 519 pxa3xx_set_datasize(info); 520 break; 521 case NAND_CMD_SEQIN: 522 exec_cmd = 0; 523 break; 524 default: 525 info->ndcb1 = 0; 526 info->ndcb2 = 0; 527 break; 528 } 529 530 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles 531 + host->col_addr_cycles); 532 533 switch (command) { 534 case NAND_CMD_READOOB: 535 case NAND_CMD_READ0: 536 cmd = host->cmdset->read1; 537 if (command == NAND_CMD_READOOB) 538 info->buf_start = mtd->writesize + column; 539 else 540 info->buf_start = column; 541 542 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) 543 info->ndcb0 |= NDCB0_CMD_TYPE(0) 544 | addr_cycle 545 | (cmd & NDCB0_CMD1_MASK); 546 else 547 info->ndcb0 |= NDCB0_CMD_TYPE(0) 548 | NDCB0_DBC 549 | addr_cycle 550 | cmd; 551 552 case NAND_CMD_SEQIN: 553 /* small page addr setting */ 554 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) { 555 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) 556 | (column & 0xFF); 557 558 info->ndcb2 = 0; 559 } else { 560 info->ndcb1 = ((page_addr & 0xFFFF) << 16) 561 | (column & 0xFFFF); 562 563 if (page_addr & 0xFF0000) 564 info->ndcb2 = (page_addr & 0xFF0000) >> 16; 565 else 566 info->ndcb2 = 0; 567 } 568 569 info->buf_count = mtd->writesize + mtd->oobsize; 570 memset(info->data_buff, 0xFF, info->buf_count); 571 572 break; 573 574 case NAND_CMD_PAGEPROG: 575 if (is_buf_blank(info->data_buff, 576 (mtd->writesize + mtd->oobsize))) { 577 exec_cmd = 0; 578 break; 579 } 580 581 cmd = host->cmdset->program; 582 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) 583 | NDCB0_AUTO_RS 584 | NDCB0_ST_ROW_EN 585 | NDCB0_DBC 586 | cmd 587 | addr_cycle; 588 break; 589 590 case NAND_CMD_READID: 591 cmd = host->cmdset->read_id; 592 info->buf_count = host->read_id_bytes; 593 info->ndcb0 |= NDCB0_CMD_TYPE(3) 594 | NDCB0_ADDR_CYC(1) 595 | cmd; 596 597 info->data_size = 8; 598 break; 599 case NAND_CMD_STATUS: 600 cmd = host->cmdset->read_status; 601 info->buf_count = 1; 602 info->ndcb0 |= NDCB0_CMD_TYPE(4) 603 | NDCB0_ADDR_CYC(1) 604 | cmd; 605 606 info->data_size = 8; 607 break; 608 609 case NAND_CMD_ERASE1: 610 cmd = host->cmdset->erase; 611 info->ndcb0 |= NDCB0_CMD_TYPE(2) 612 | NDCB0_AUTO_RS 613 | NDCB0_ADDR_CYC(3) 614 | NDCB0_DBC 615 | cmd; 616 info->ndcb1 = page_addr; 617 info->ndcb2 = 0; 618 619 break; 620 case NAND_CMD_RESET: 621 cmd = host->cmdset->reset; 622 info->ndcb0 |= NDCB0_CMD_TYPE(5) 623 | cmd; 624 625 break; 626 627 case NAND_CMD_ERASE2: 628 exec_cmd = 0; 629 break; 630 631 default: 632 exec_cmd = 0; 633 dev_err(&info->pdev->dev, "non-supported command %x\n", 634 command); 635 break; 636 } 637 638 return exec_cmd; 639} 640 641static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, 642 int column, int page_addr) 643{ 644 struct pxa3xx_nand_host *host = mtd->priv; 645 struct pxa3xx_nand_info *info = host->info_data; 646 int ret, exec_cmd; 647 648 /* 649 * if this is a x16 device ,then convert the input 650 * "byte" address into a "word" address appropriate 651 * for indexing a word-oriented device 652 */ 653 if (host->reg_ndcr & NDCR_DWIDTH_M) 654 column /= 2; 655 656 /* 657 * There may be different NAND chip hooked to 658 * different chip select, so check whether 659 * chip select has been changed, if yes, reset the timing 660 */ 661 if (info->cs != host->cs) { 662 info->cs = host->cs; 663 nand_writel(info, NDTR0CS0, host->ndtr0cs0); 664 nand_writel(info, NDTR1CS0, host->ndtr1cs0); 665 } 666 667 info->state = STATE_PREPARED; 668 exec_cmd = prepare_command_pool(info, command, column, page_addr); 669 if (exec_cmd) { 670 init_completion(&info->cmd_complete); 671 pxa3xx_nand_start(info); 672 673 ret = wait_for_completion_timeout(&info->cmd_complete, 674 CHIP_DELAY_TIMEOUT); 675 if (!ret) { 676 dev_err(&info->pdev->dev, "Wait time out!!!\n"); 677 /* Stop State Machine for next command cycle */ 678 pxa3xx_nand_stop(info); 679 } 680 } 681 info->state = STATE_IDLE; 682} 683 684static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, 685 struct nand_chip *chip, const uint8_t *buf, int oob_required) 686{ 687 chip->write_buf(mtd, buf, mtd->writesize); 688 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 689 690 return 0; 691} 692 693static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, 694 struct nand_chip *chip, uint8_t *buf, int oob_required, 695 int page) 696{ 697 struct pxa3xx_nand_host *host = mtd->priv; 698 struct pxa3xx_nand_info *info = host->info_data; 699 700 chip->read_buf(mtd, buf, mtd->writesize); 701 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 702 703 if (info->retcode == ERR_SBERR) { 704 switch (info->use_ecc) { 705 case 1: 706 mtd->ecc_stats.corrected++; 707 break; 708 case 0: 709 default: 710 break; 711 } 712 } else if (info->retcode == ERR_DBERR) { 713 /* 714 * for blank page (all 0xff), HW will calculate its ECC as 715 * 0, which is different from the ECC information within 716 * OOB, ignore such double bit errors 717 */ 718 if (is_buf_blank(buf, mtd->writesize)) 719 info->retcode = ERR_NONE; 720 else 721 mtd->ecc_stats.failed++; 722 } 723 724 return 0; 725} 726 727static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) 728{ 729 struct pxa3xx_nand_host *host = mtd->priv; 730 struct pxa3xx_nand_info *info = host->info_data; 731 char retval = 0xFF; 732 733 if (info->buf_start < info->buf_count) 734 /* Has just send a new command? */ 735 retval = info->data_buff[info->buf_start++]; 736 737 return retval; 738} 739 740static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) 741{ 742 struct pxa3xx_nand_host *host = mtd->priv; 743 struct pxa3xx_nand_info *info = host->info_data; 744 u16 retval = 0xFFFF; 745 746 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { 747 retval = *((u16 *)(info->data_buff+info->buf_start)); 748 info->buf_start += 2; 749 } 750 return retval; 751} 752 753static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 754{ 755 struct pxa3xx_nand_host *host = mtd->priv; 756 struct pxa3xx_nand_info *info = host->info_data; 757 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); 758 759 memcpy(buf, info->data_buff + info->buf_start, real_len); 760 info->buf_start += real_len; 761} 762 763static void pxa3xx_nand_write_buf(struct mtd_info *mtd, 764 const uint8_t *buf, int len) 765{ 766 struct pxa3xx_nand_host *host = mtd->priv; 767 struct pxa3xx_nand_info *info = host->info_data; 768 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); 769 770 memcpy(info->data_buff + info->buf_start, buf, real_len); 771 info->buf_start += real_len; 772} 773 774static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) 775{ 776 return; 777} 778 779static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) 780{ 781 struct pxa3xx_nand_host *host = mtd->priv; 782 struct pxa3xx_nand_info *info = host->info_data; 783 784 /* pxa3xx_nand_send_command has waited for command complete */ 785 if (this->state == FL_WRITING || this->state == FL_ERASING) { 786 if (info->retcode == ERR_NONE) 787 return 0; 788 else { 789 /* 790 * any error make it return 0x01 which will tell 791 * the caller the erase and write fail 792 */ 793 return 0x01; 794 } 795 } 796 797 return 0; 798} 799 800static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, 801 const struct pxa3xx_nand_flash *f) 802{ 803 struct platform_device *pdev = info->pdev; 804 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; 805 struct pxa3xx_nand_host *host = info->host[info->cs]; 806 uint32_t ndcr = 0x0; /* enable all interrupts */ 807 808 if (f->page_size != 2048 && f->page_size != 512) { 809 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n"); 810 return -EINVAL; 811 } 812 813 if (f->flash_width != 16 && f->flash_width != 8) { 814 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n"); 815 return -EINVAL; 816 } 817 818 /* calculate flash information */ 819 host->cmdset = &default_cmdset; 820 host->page_size = f->page_size; 821 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; 822 823 /* calculate addressing information */ 824 host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; 825 826 if (f->num_blocks * f->page_per_block > 65536) 827 host->row_addr_cycles = 3; 828 else 829 host->row_addr_cycles = 2; 830 831 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; 832 ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; 833 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; 834 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; 835 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; 836 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; 837 838 ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); 839 ndcr |= NDCR_SPARE_EN; /* enable spare by default */ 840 841 host->reg_ndcr = ndcr; 842 843 pxa3xx_nand_set_timing(host, f->timing); 844 return 0; 845} 846 847static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) 848{ 849 /* 850 * We set 0 by hard coding here, for we don't support keep_config 851 * when there is more than one chip attached to the controller 852 */ 853 struct pxa3xx_nand_host *host = info->host[0]; 854 uint32_t ndcr = nand_readl(info, NDCR); 855 856 if (ndcr & NDCR_PAGE_SZ) { 857 host->page_size = 2048; 858 host->read_id_bytes = 4; 859 } else { 860 host->page_size = 512; 861 host->read_id_bytes = 2; 862 } 863 864 host->reg_ndcr = ndcr & ~NDCR_INT_MASK; 865 host->cmdset = &default_cmdset; 866 867 host->ndtr0cs0 = nand_readl(info, NDTR0CS0); 868 host->ndtr1cs0 = nand_readl(info, NDTR1CS0); 869 870 return 0; 871} 872 873/* the maximum possible buffer size for large page with OOB data 874 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the 875 * data buffer and the DMA descriptor 876 */ 877#define MAX_BUFF_SIZE PAGE_SIZE 878 879static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) 880{ 881 struct platform_device *pdev = info->pdev; 882 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc); 883 884 if (use_dma == 0) { 885 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL); 886 if (info->data_buff == NULL) 887 return -ENOMEM; 888 return 0; 889 } 890 891 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE, 892 &info->data_buff_phys, GFP_KERNEL); 893 if (info->data_buff == NULL) { 894 dev_err(&pdev->dev, "failed to allocate dma buffer\n"); 895 return -ENOMEM; 896 } 897 898 info->data_desc = (void *)info->data_buff + data_desc_offset; 899 info->data_desc_addr = info->data_buff_phys + data_desc_offset; 900 901 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW, 902 pxa3xx_nand_data_dma_irq, info); 903 if (info->data_dma_ch < 0) { 904 dev_err(&pdev->dev, "failed to request data dma\n"); 905 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE, 906 info->data_buff, info->data_buff_phys); 907 return info->data_dma_ch; 908 } 909 910 return 0; 911} 912 913static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) 914{ 915 struct mtd_info *mtd; 916 int ret; 917 mtd = info->host[info->cs]->mtd; 918 /* use the common timing to make a try */ 919 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]); 920 if (ret) 921 return ret; 922 923 pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0); 924 if (info->is_ready) 925 return 0; 926 927 return -ENODEV; 928} 929 930static int pxa3xx_nand_scan(struct mtd_info *mtd) 931{ 932 struct pxa3xx_nand_host *host = mtd->priv; 933 struct pxa3xx_nand_info *info = host->info_data; 934 struct platform_device *pdev = info->pdev; 935 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; 936 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL; 937 const struct pxa3xx_nand_flash *f = NULL; 938 struct nand_chip *chip = mtd->priv; 939 uint32_t id = -1; 940 uint64_t chipsize; 941 int i, ret, num; 942 943 if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) 944 goto KEEP_CONFIG; 945 946 ret = pxa3xx_nand_sensing(info); 947 if (ret) { 948 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", 949 info->cs); 950 951 return ret; 952 } 953 954 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0); 955 id = *((uint16_t *)(info->data_buff)); 956 if (id != 0) 957 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id); 958 else { 959 dev_warn(&info->pdev->dev, 960 "Read out ID 0, potential timing set wrong!!\n"); 961 962 return -EINVAL; 963 } 964 965 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; 966 for (i = 0; i < num; i++) { 967 if (i < pdata->num_flash) 968 f = pdata->flash + i; 969 else 970 f = &builtin_flash_types[i - pdata->num_flash + 1]; 971 972 /* find the chip in default list */ 973 if (f->chip_id == id) 974 break; 975 } 976 977 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) { 978 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n"); 979 980 return -EINVAL; 981 } 982 983 ret = pxa3xx_nand_config_flash(info, f); 984 if (ret) { 985 dev_err(&info->pdev->dev, "ERROR! Configure failed\n"); 986 return ret; 987 } 988 989 pxa3xx_flash_ids[0].name = f->name; 990 pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff; 991 pxa3xx_flash_ids[0].pagesize = f->page_size; 992 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size; 993 pxa3xx_flash_ids[0].chipsize = chipsize >> 20; 994 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; 995 if (f->flash_width == 16) 996 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16; 997 pxa3xx_flash_ids[1].name = NULL; 998 def = pxa3xx_flash_ids; 999KEEP_CONFIG: 1000 chip->ecc.mode = NAND_ECC_HW; 1001 chip->ecc.size = host->page_size; 1002 chip->ecc.strength = 1; 1003 1004 if (host->reg_ndcr & NDCR_DWIDTH_M) 1005 chip->options |= NAND_BUSWIDTH_16; 1006 1007 if (nand_scan_ident(mtd, 1, def)) 1008 return -ENODEV; 1009 /* calculate addressing information */ 1010 if (mtd->writesize >= 2048) 1011 host->col_addr_cycles = 2; 1012 else 1013 host->col_addr_cycles = 1; 1014 1015 info->oob_buff = info->data_buff + mtd->writesize; 1016 if ((mtd->size >> chip->page_shift) > 65536) 1017 host->row_addr_cycles = 3; 1018 else 1019 host->row_addr_cycles = 2; 1020 1021 mtd->name = mtd_names[0]; 1022 return nand_scan_tail(mtd); 1023} 1024 1025static int alloc_nand_resource(struct platform_device *pdev) 1026{ 1027 struct pxa3xx_nand_platform_data *pdata; 1028 struct pxa3xx_nand_info *info; 1029 struct pxa3xx_nand_host *host; 1030 struct nand_chip *chip; 1031 struct mtd_info *mtd; 1032 struct resource *r; 1033 int ret, irq, cs; 1034 1035 pdata = pdev->dev.platform_data; 1036 info = kzalloc(sizeof(*info) + (sizeof(*mtd) + 1037 sizeof(*host)) * pdata->num_cs, GFP_KERNEL); 1038 if (!info) { 1039 dev_err(&pdev->dev, "failed to allocate memory\n"); 1040 return -ENOMEM; 1041 } 1042 1043 info->pdev = pdev; 1044 for (cs = 0; cs < pdata->num_cs; cs++) { 1045 mtd = (struct mtd_info *)((unsigned int)&info[1] + 1046 (sizeof(*mtd) + sizeof(*host)) * cs); 1047 chip = (struct nand_chip *)(&mtd[1]); 1048 host = (struct pxa3xx_nand_host *)chip; 1049 info->host[cs] = host; 1050 host->mtd = mtd; 1051 host->cs = cs; 1052 host->info_data = info; 1053 mtd->priv = host; 1054 mtd->owner = THIS_MODULE; 1055 1056 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; 1057 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; 1058 chip->controller = &info->controller; 1059 chip->waitfunc = pxa3xx_nand_waitfunc; 1060 chip->select_chip = pxa3xx_nand_select_chip; 1061 chip->cmdfunc = pxa3xx_nand_cmdfunc; 1062 chip->read_word = pxa3xx_nand_read_word; 1063 chip->read_byte = pxa3xx_nand_read_byte; 1064 chip->read_buf = pxa3xx_nand_read_buf; 1065 chip->write_buf = pxa3xx_nand_write_buf; 1066 } 1067 1068 spin_lock_init(&chip->controller->lock); 1069 init_waitqueue_head(&chip->controller->wq); 1070 info->clk = clk_get(&pdev->dev, NULL); 1071 if (IS_ERR(info->clk)) { 1072 dev_err(&pdev->dev, "failed to get nand clock\n"); 1073 ret = PTR_ERR(info->clk); 1074 goto fail_free_mtd; 1075 } 1076 clk_enable(info->clk); 1077 1078 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1079 if (r == NULL) { 1080 dev_err(&pdev->dev, "no resource defined for data DMA\n"); 1081 ret = -ENXIO; 1082 goto fail_put_clk; 1083 } 1084 info->drcmr_dat = r->start; 1085 1086 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1087 if (r == NULL) { 1088 dev_err(&pdev->dev, "no resource defined for command DMA\n"); 1089 ret = -ENXIO; 1090 goto fail_put_clk; 1091 } 1092 info->drcmr_cmd = r->start; 1093 1094 irq = platform_get_irq(pdev, 0); 1095 if (irq < 0) { 1096 dev_err(&pdev->dev, "no IRQ resource defined\n"); 1097 ret = -ENXIO; 1098 goto fail_put_clk; 1099 } 1100 1101 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1102 if (r == NULL) { 1103 dev_err(&pdev->dev, "no IO memory resource defined\n"); 1104 ret = -ENODEV; 1105 goto fail_put_clk; 1106 } 1107 1108 r = request_mem_region(r->start, resource_size(r), pdev->name); 1109 if (r == NULL) { 1110 dev_err(&pdev->dev, "failed to request memory resource\n"); 1111 ret = -EBUSY; 1112 goto fail_put_clk; 1113 } 1114 1115 info->mmio_base = ioremap(r->start, resource_size(r)); 1116 if (info->mmio_base == NULL) { 1117 dev_err(&pdev->dev, "ioremap() failed\n"); 1118 ret = -ENODEV; 1119 goto fail_free_res; 1120 } 1121 info->mmio_phys = r->start; 1122 1123 ret = pxa3xx_nand_init_buff(info); 1124 if (ret) 1125 goto fail_free_io; 1126 1127 /* initialize all interrupts to be disabled */ 1128 disable_int(info, NDSR_MASK); 1129 1130 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED, 1131 pdev->name, info); 1132 if (ret < 0) { 1133 dev_err(&pdev->dev, "failed to request IRQ\n"); 1134 goto fail_free_buf; 1135 } 1136 1137 platform_set_drvdata(pdev, info); 1138 1139 return 0; 1140 1141fail_free_buf: 1142 free_irq(irq, info); 1143 if (use_dma) { 1144 pxa_free_dma(info->data_dma_ch); 1145 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE, 1146 info->data_buff, info->data_buff_phys); 1147 } else 1148 kfree(info->data_buff); 1149fail_free_io: 1150 iounmap(info->mmio_base); 1151fail_free_res: 1152 release_mem_region(r->start, resource_size(r)); 1153fail_put_clk: 1154 clk_disable(info->clk); 1155 clk_put(info->clk); 1156fail_free_mtd: 1157 kfree(info); 1158 return ret; 1159} 1160 1161static int pxa3xx_nand_remove(struct platform_device *pdev) 1162{ 1163 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); 1164 struct pxa3xx_nand_platform_data *pdata; 1165 struct resource *r; 1166 int irq, cs; 1167 1168 if (!info) 1169 return 0; 1170 1171 pdata = pdev->dev.platform_data; 1172 platform_set_drvdata(pdev, NULL); 1173 1174 irq = platform_get_irq(pdev, 0); 1175 if (irq >= 0) 1176 free_irq(irq, info); 1177 if (use_dma) { 1178 pxa_free_dma(info->data_dma_ch); 1179 dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE, 1180 info->data_buff, info->data_buff_phys); 1181 } else 1182 kfree(info->data_buff); 1183 1184 iounmap(info->mmio_base); 1185 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1186 release_mem_region(r->start, resource_size(r)); 1187 1188 clk_disable(info->clk); 1189 clk_put(info->clk); 1190 1191 for (cs = 0; cs < pdata->num_cs; cs++) 1192 nand_release(info->host[cs]->mtd); 1193 kfree(info); 1194 return 0; 1195} 1196 1197static int pxa3xx_nand_probe(struct platform_device *pdev) 1198{ 1199 struct pxa3xx_nand_platform_data *pdata; 1200 struct pxa3xx_nand_info *info; 1201 int ret, cs, probe_success; 1202 1203 pdata = pdev->dev.platform_data; 1204 if (!pdata) { 1205 dev_err(&pdev->dev, "no platform data defined\n"); 1206 return -ENODEV; 1207 } 1208 1209 ret = alloc_nand_resource(pdev); 1210 if (ret) { 1211 dev_err(&pdev->dev, "alloc nand resource failed\n"); 1212 return ret; 1213 } 1214 1215 info = platform_get_drvdata(pdev); 1216 probe_success = 0; 1217 for (cs = 0; cs < pdata->num_cs; cs++) { 1218 info->cs = cs; 1219 ret = pxa3xx_nand_scan(info->host[cs]->mtd); 1220 if (ret) { 1221 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n", 1222 cs); 1223 continue; 1224 } 1225 1226 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL, 1227 NULL, pdata->parts[cs], 1228 pdata->nr_parts[cs]); 1229 if (!ret) 1230 probe_success = 1; 1231 } 1232 1233 if (!probe_success) { 1234 pxa3xx_nand_remove(pdev); 1235 return -ENODEV; 1236 } 1237 1238 return 0; 1239} 1240 1241#ifdef CONFIG_PM 1242static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state) 1243{ 1244 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); 1245 struct pxa3xx_nand_platform_data *pdata; 1246 struct mtd_info *mtd; 1247 int cs; 1248 1249 pdata = pdev->dev.platform_data; 1250 if (info->state) { 1251 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); 1252 return -EAGAIN; 1253 } 1254 1255 for (cs = 0; cs < pdata->num_cs; cs++) { 1256 mtd = info->host[cs]->mtd; 1257 mtd_suspend(mtd); 1258 } 1259 1260 return 0; 1261} 1262 1263static int pxa3xx_nand_resume(struct platform_device *pdev) 1264{ 1265 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); 1266 struct pxa3xx_nand_platform_data *pdata; 1267 struct mtd_info *mtd; 1268 int cs; 1269 1270 pdata = pdev->dev.platform_data; 1271 /* We don't want to handle interrupt without calling mtd routine */ 1272 disable_int(info, NDCR_INT_MASK); 1273 1274 /* 1275 * Directly set the chip select to a invalid value, 1276 * then the driver would reset the timing according 1277 * to current chip select at the beginning of cmdfunc 1278 */ 1279 info->cs = 0xff; 1280 1281 /* 1282 * As the spec says, the NDSR would be updated to 0x1800 when 1283 * doing the nand_clk disable/enable. 1284 * To prevent it damaging state machine of the driver, clear 1285 * all status before resume 1286 */ 1287 nand_writel(info, NDSR, NDSR_MASK); 1288 for (cs = 0; cs < pdata->num_cs; cs++) { 1289 mtd = info->host[cs]->mtd; 1290 mtd_resume(mtd); 1291 } 1292 1293 return 0; 1294} 1295#else 1296#define pxa3xx_nand_suspend NULL 1297#define pxa3xx_nand_resume NULL 1298#endif 1299 1300static struct platform_driver pxa3xx_nand_driver = { 1301 .driver = { 1302 .name = "pxa3xx-nand", 1303 }, 1304 .probe = pxa3xx_nand_probe, 1305 .remove = pxa3xx_nand_remove, 1306 .suspend = pxa3xx_nand_suspend, 1307 .resume = pxa3xx_nand_resume, 1308}; 1309 1310module_platform_driver(pxa3xx_nand_driver); 1311 1312MODULE_LICENSE("GPL"); 1313MODULE_DESCRIPTION("PXA3xx NAND controller driver"); 1314