1/* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22#ifndef __XGENE_ENET_HW_H__ 23#define __XGENE_ENET_HW_H__ 24 25#include "xgene_enet_main.h" 26 27struct xgene_enet_pdata; 28struct xgene_enet_stats; 29 30/* clears and then set bits */ 31static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) 32{ 33 u32 end = start + len - 1; 34 u32 mask = GENMASK(end, start); 35 36 *dst &= ~mask; 37 *dst |= (val << start) & mask; 38} 39 40static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) 41{ 42 return (val & GENMASK(end, start)) >> start; 43} 44 45enum xgene_enet_rm { 46 RM0, 47 RM1, 48 RM3 = 3 49}; 50 51#define CSR_RING_ID 0x0008 52#define OVERWRITE BIT(31) 53#define IS_BUFFER_POOL BIT(20) 54#define PREFETCH_BUF_EN BIT(21) 55#define CSR_RING_ID_BUF 0x000c 56#define CSR_RING_NE_INT_MODE 0x017c 57#define CSR_RING_CONFIG 0x006c 58#define CSR_RING_WR_BASE 0x0070 59#define NUM_RING_CONFIG 5 60#define BUFPOOL_MODE 3 61#define INC_DEC_CMD_ADDR 0x002c 62#define UDP_HDR_SIZE 2 63#define BUF_LEN_CODE_2K 0x5000 64 65#define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos)) 66#define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) 67 68/* Empty slot soft signature */ 69#define EMPTY_SLOT_INDEX 1 70#define EMPTY_SLOT ~0ULL 71 72#define WORK_DESC_SIZE 32 73#define BUFPOOL_DESC_SIZE 16 74 75#define RING_OWNER_MASK GENMASK(9, 6) 76#define RING_BUFNUM_MASK GENMASK(5, 0) 77 78#define SELTHRSH_POS 3 79#define SELTHRSH_LEN 3 80#define RINGADDRL_POS 5 81#define RINGADDRL_LEN 27 82#define RINGADDRH_POS 0 83#define RINGADDRH_LEN 6 84#define RINGSIZE_POS 23 85#define RINGSIZE_LEN 3 86#define RINGTYPE_POS 19 87#define RINGTYPE_LEN 2 88#define RINGMODE_POS 20 89#define RINGMODE_LEN 3 90#define RECOMTIMEOUTL_POS 28 91#define RECOMTIMEOUTL_LEN 3 92#define RECOMTIMEOUTH_POS 0 93#define RECOMTIMEOUTH_LEN 2 94#define NUMMSGSINQ_POS 1 95#define NUMMSGSINQ_LEN 16 96#define ACCEPTLERR BIT(19) 97#define QCOHERENT BIT(4) 98#define RECOMBBUF BIT(27) 99 100#define BLOCK_ETH_CSR_OFFSET 0x2000 101#define BLOCK_ETH_RING_IF_OFFSET 0x9000 102#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 103 104#define BLOCK_ETH_MAC_OFFSET 0x0000 105#define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 106 107#define CLKEN_ADDR 0xc208 108#define SRST_ADDR 0xc200 109 110#define MAC_ADDR_REG_OFFSET 0x00 111#define MAC_COMMAND_REG_OFFSET 0x04 112#define MAC_WRITE_REG_OFFSET 0x08 113#define MAC_READ_REG_OFFSET 0x0c 114#define MAC_COMMAND_DONE_REG_OFFSET 0x10 115 116#define MII_MGMT_CONFIG_ADDR 0x20 117#define MII_MGMT_COMMAND_ADDR 0x24 118#define MII_MGMT_ADDRESS_ADDR 0x28 119#define MII_MGMT_CONTROL_ADDR 0x2c 120#define MII_MGMT_STATUS_ADDR 0x30 121#define MII_MGMT_INDICATORS_ADDR 0x34 122 123#define BUSY_MASK BIT(0) 124#define READ_CYCLE_MASK BIT(0) 125#define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 126 127#define ENET_SPARE_CFG_REG_ADDR 0x0750 128#define RSIF_CONFIG_REG_ADDR 0x0010 129#define RSIF_RAM_DBG_REG0_ADDR 0x0048 130#define RGMII_REG_0_ADDR 0x07e0 131#define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8 132#define DEBUG_REG_ADDR 0x0700 133#define CFG_BYPASS_ADDR 0x0294 134#define CLE_BYPASS_REG0_0_ADDR 0x0490 135#define CLE_BYPASS_REG1_0_ADDR 0x0494 136#define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) 137#define RESUME_TX BIT(0) 138#define CFG_SPEED_1250 BIT(24) 139#define TX_PORT0 BIT(0) 140#define CFG_BYPASS_UNISEC_TX BIT(2) 141#define CFG_BYPASS_UNISEC_RX BIT(1) 142#define CFG_CLE_BYPASS_EN0 BIT(31) 143#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) 144 145#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) 146#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) 147#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) 148#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) 149#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 150#define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0)) 151#define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16)) 152#define ICM_CONFIG0_REG_0_ADDR 0x0400 153#define ICM_CONFIG2_REG_0_ADDR 0x0410 154#define RX_DV_GATE_REG_0_ADDR 0x05fc 155#define TX_DV_GATE_EN0 BIT(2) 156#define RX_DV_GATE_EN0 BIT(1) 157#define RESUME_RX0 BIT(0) 158#define ENET_CFGSSQMIWQASSOC_ADDR 0xe0 159#define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc 160#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0 161#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4 162#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 163#define ENET_BLOCK_MEM_RDY_ADDR 0x74 164#define MAC_CONFIG_1_ADDR 0x00 165#define MAC_CONFIG_2_ADDR 0x04 166#define MAX_FRAME_LEN_ADDR 0x10 167#define INTERFACE_CONTROL_ADDR 0x38 168#define STATION_ADDR0_ADDR 0x40 169#define STATION_ADDR1_ADDR 0x44 170#define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) 171#define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) 172#define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) 173#define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) 174#define SOFT_RESET1 BIT(31) 175#define TX_EN BIT(0) 176#define RX_EN BIT(2) 177#define ENET_LHD_MODE BIT(25) 178#define ENET_GHD_MODE BIT(26) 179#define FULL_DUPLEX2 BIT(0) 180#define SCAN_AUTO_INCR BIT(5) 181#define TBYT_ADDR 0x38 182#define TPKT_ADDR 0x39 183#define TDRP_ADDR 0x45 184#define TFCS_ADDR 0x47 185#define TUND_ADDR 0x4a 186 187#define TSO_IPPROTO_TCP 1 188 189#define USERINFO_POS 0 190#define USERINFO_LEN 32 191#define FPQNUM_POS 32 192#define FPQNUM_LEN 12 193#define LERR_POS 60 194#define LERR_LEN 3 195#define STASH_POS 52 196#define STASH_LEN 2 197#define BUFDATALEN_POS 48 198#define BUFDATALEN_LEN 12 199#define DATAADDR_POS 0 200#define DATAADDR_LEN 42 201#define COHERENT_POS 63 202#define HENQNUM_POS 48 203#define HENQNUM_LEN 12 204#define TYPESEL_POS 44 205#define TYPESEL_LEN 4 206#define ETHHDR_POS 12 207#define ETHHDR_LEN 8 208#define IC_POS 35 /* Insert CRC */ 209#define TCPHDR_POS 0 210#define TCPHDR_LEN 6 211#define IPHDR_POS 6 212#define IPHDR_LEN 6 213#define EC_POS 22 /* Enable checksum */ 214#define EC_LEN 1 215#define IS_POS 24 /* IP protocol select */ 216#define IS_LEN 1 217#define TYPE_ETH_WORK_MESSAGE_POS 44 218 219struct xgene_enet_raw_desc { 220 __le64 m0; 221 __le64 m1; 222 __le64 m2; 223 __le64 m3; 224}; 225 226struct xgene_enet_raw_desc16 { 227 __le64 m0; 228 __le64 m1; 229}; 230 231static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr) 232{ 233 __le64 *desc_slot = desc_slot_ptr; 234 235 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT); 236} 237 238static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr) 239{ 240 __le64 *desc_slot = desc_slot_ptr; 241 242 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT)); 243} 244 245enum xgene_enet_ring_cfgsize { 246 RING_CFGSIZE_512B, 247 RING_CFGSIZE_2KB, 248 RING_CFGSIZE_16KB, 249 RING_CFGSIZE_64KB, 250 RING_CFGSIZE_512KB, 251 RING_CFGSIZE_INVALID 252}; 253 254enum xgene_enet_ring_type { 255 RING_DISABLED, 256 RING_REGULAR, 257 RING_BUFPOOL 258}; 259 260enum xgene_ring_owner { 261 RING_OWNER_ETH0, 262 RING_OWNER_CPU = 15, 263 RING_OWNER_INVALID 264}; 265 266enum xgene_enet_ring_bufnum { 267 RING_BUFNUM_REGULAR = 0x0, 268 RING_BUFNUM_BUFPOOL = 0x20, 269 RING_BUFNUM_INVALID 270}; 271 272enum xgene_enet_cmd { 273 XGENE_ENET_WR_CMD = BIT(31), 274 XGENE_ENET_RD_CMD = BIT(30) 275}; 276 277enum xgene_enet_err_code { 278 HBF_READ_DATA = 3, 279 HBF_LL_READ = 4, 280 BAD_WORK_MSG = 6, 281 BUFPOOL_TIMEOUT = 15, 282 INGRESS_CRC = 16, 283 INGRESS_CHECKSUM = 17, 284 INGRESS_TRUNC_FRAME = 18, 285 INGRESS_PKT_LEN = 19, 286 INGRESS_PKT_UNDER = 20, 287 INGRESS_FIFO_OVERRUN = 21, 288 INGRESS_CHECKSUM_COMPUTE = 26, 289 ERR_CODE_INVALID 290}; 291 292static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id) 293{ 294 return (id & RING_OWNER_MASK) >> 6; 295} 296 297static inline u8 xgene_enet_ring_bufnum(u16 id) 298{ 299 return id & RING_BUFNUM_MASK; 300} 301 302static inline bool xgene_enet_is_bufpool(u16 id) 303{ 304 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; 305} 306 307static inline u16 xgene_enet_get_numslots(u16 id, u32 size) 308{ 309 bool is_bufpool = xgene_enet_is_bufpool(id); 310 311 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE : 312 size / WORK_DESC_SIZE; 313} 314 315struct xgene_enet_desc_ring *xgene_enet_setup_ring( 316 struct xgene_enet_desc_ring *ring); 317void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring); 318void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, 319 struct xgene_enet_pdata *pdata, 320 enum xgene_enet_err_code status); 321 322int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); 323void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); 324bool xgene_ring_mgr_init(struct xgene_enet_pdata *p); 325 326extern struct xgene_mac_ops xgene_gmac_ops; 327extern struct xgene_port_ops xgene_gport_ops; 328 329#endif /* __XGENE_ENET_HW_H__ */ 330