atl1c_hw.h revision 7f5544d6693ab2593b4f13521a577387f3be6b2f
1/* 2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. 3 * 4 * Derived from Intel e1000 driver 5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 59 19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22#ifndef _ATL1C_HW_H_ 23#define _ATL1C_HW_H_ 24 25#include <linux/types.h> 26#include <linux/mii.h> 27 28#define FIELD_GETX(_x, _name) ((_x) >> (_name##_SHIFT) & (_name##_MASK)) 29#define FIELD_SETX(_x, _name, _v) \ 30(((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\ 31(((_v) & (_name##_MASK)) << (_name##_SHIFT))) 32#define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT)) 33 34struct atl1c_adapter; 35struct atl1c_hw; 36 37/* function prototype */ 38void atl1c_phy_disable(struct atl1c_hw *hw); 39void atl1c_hw_set_mac_addr(struct atl1c_hw *hw); 40int atl1c_phy_reset(struct atl1c_hw *hw); 41int atl1c_read_mac_addr(struct atl1c_hw *hw); 42int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex); 43u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr); 44void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value); 45int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); 46int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data); 47bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value); 48int atl1c_phy_init(struct atl1c_hw *hw); 49int atl1c_check_eeprom_exist(struct atl1c_hw *hw); 50int atl1c_restart_autoneg(struct atl1c_hw *hw); 51int atl1c_phy_power_saving(struct atl1c_hw *hw); 52/* register definition */ 53#define REG_DEVICE_CAP 0x5C 54#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7 55#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0 56 57#define DEVICE_CTRL_MAXRRS_MIN 2 58 59#define REG_LINK_CTRL 0x68 60#define LINK_CTRL_L0S_EN 0x01 61#define LINK_CTRL_L1_EN 0x02 62#define LINK_CTRL_EXT_SYNC 0x80 63 64#define REG_DEV_SERIALNUM_CTRL 0x200 65#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */ 66#define REG_DEV_MAC_SEL_SHIFT 0 67#define REG_DEV_SERIAL_NUM_EN_MASK 0x1 68#define REG_DEV_SERIAL_NUM_EN_SHIFT 1 69 70#define REG_TWSI_CTRL 0x218 71#define TWSI_CTRL_LD_OFFSET_MASK 0xFF 72#define TWSI_CTRL_LD_OFFSET_SHIFT 0 73#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 74#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 75#define TWSI_CTRL_SW_LDSTART 0x800 76#define TWSI_CTRL_HW_LDSTART 0x1000 77#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F 78#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 79#define TWSI_CTRL_LD_EXIST 0x400000 80#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 81#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 82#define TWSI_CTRL_FREQ_SEL_100K 0 83#define TWSI_CTRL_FREQ_SEL_200K 1 84#define TWSI_CTRL_FREQ_SEL_300K 2 85#define TWSI_CTRL_FREQ_SEL_400K 3 86#define TWSI_CTRL_SMB_SLV_ADDR 87#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 88#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 89 90 91#define REG_PCIE_DEV_MISC_CTRL 0x21C 92#define PCIE_DEV_MISC_EXT_PIPE 0x2 93#define PCIE_DEV_MISC_RETRY_BUFDIS 0x1 94#define PCIE_DEV_MISC_SPIROM_EXIST 0x4 95#define PCIE_DEV_MISC_SERDES_ENDIAN 0x8 96#define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10 97 98#define REG_PCIE_PHYMISC 0x1000 99#define PCIE_PHYMISC_FORCE_RCV_DET 0x4 100 101#define REG_PCIE_PHYMISC2 0x1004 102#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x3 103#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 104#define PCIE_PHYMISC2_SERDES_TH_MASK 0x3 105#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 106 107#define REG_TWSI_DEBUG 0x1108 108#define TWSI_DEBUG_DEV_EXIST 0x20000000 109 110#define REG_EEPROM_CTRL 0x12C0 111#define EEPROM_CTRL_DATA_HI_MASK 0xFFFF 112#define EEPROM_CTRL_DATA_HI_SHIFT 0 113#define EEPROM_CTRL_ADDR_MASK 0x3FF 114#define EEPROM_CTRL_ADDR_SHIFT 16 115#define EEPROM_CTRL_ACK 0x40000000 116#define EEPROM_CTRL_RW 0x80000000 117 118#define REG_EEPROM_DATA_LO 0x12C4 119 120#define REG_OTP_CTRL 0x12F0 121#define OTP_CTRL_CLK_EN 0x0002 122 123#define REG_PM_CTRL 0x12F8 124#define PM_CTRL_SDES_EN 0x00000001 125#define PM_CTRL_RBER_EN 0x00000002 126#define PM_CTRL_CLK_REQ_EN 0x00000004 127#define PM_CTRL_ASPM_L1_EN 0x00000008 128#define PM_CTRL_SERDES_L1_EN 0x00000010 129#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020 130#define PM_CTRL_SERDES_PD_EX_L1 0x00000040 131#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080 132#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF 133#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8 134#define PM_CTRL_ASPM_L0S_EN 0x00001000 135#define PM_CTRL_CLK_SWH_L1 0x00002000 136#define PM_CTRL_CLK_PWM_VER1_1 0x00004000 137#define PM_CTRL_RCVR_WT_TIMER 0x00008000 138#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF 139#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16 140#define PM_CTRL_PM_REQ_TIMER_MASK 0xF 141#define PM_CTRL_PM_REQ_TIMER_SHIFT 20 142#define PM_CTRL_LCKDET_TIMER_MASK 0xF 143#define PM_CTRL_LCKDET_TIMER_SHIFT 24 144#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000 145#define PM_CTRL_SA_DLY_EN 0x20000000 146#define PM_CTRL_MAC_ASPM_CHK 0x40000000 147#define PM_CTRL_HOTRST 0x80000000 148 149#define REG_LTSSM_ID_CTRL 0x12FC 150#define LTSSM_ID_EN_WRO 0x1000 151 152 153/* Selene Master Control Register */ 154#define REG_MASTER_CTRL 0x1400 155#define MASTER_CTRL_OTP_SEL BIT(31) 156#define MASTER_DEV_NUM_MASK 0x7FUL 157#define MASTER_DEV_NUM_SHIFT 24 158#define MASTER_REV_NUM_MASK 0xFFUL 159#define MASTER_REV_NUM_SHIFT 16 160#define MASTER_CTRL_INT_RDCLR BIT(14) 161#define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from 162 * serdes, not sw to 25M */ 163#define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */ 164#define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */ 165#define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */ 166#define MASTER_CTRL_MANUTIMER_EN BIT(8) 167#define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */ 168#define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */ 169#define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */ 170#define MASTER_CTRL_BERT_START BIT(4) 171#define MASTER_PCIE_TSTMOD_MASK 3UL 172#define MASTER_PCIE_TSTMOD_SHIFT 2 173#define MASTER_PCIE_RST BIT(1) 174#define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */ 175#define DMA_MAC_RST_TO 50 176 177/* Timer Initial Value Register */ 178#define REG_MANUAL_TIMER_INIT 0x1404 179 180/* IRQ ModeratorTimer Initial Value Register */ 181#define REG_IRQ_MODRT_TIMER_INIT 0x1408 182#define IRQ_MODRT_TIMER_MASK 0xffff 183#define IRQ_MODRT_TX_TIMER_SHIFT 0 184#define IRQ_MODRT_RX_TIMER_SHIFT 16 185 186#define REG_GPHY_CTRL 0x140C 187#define GPHY_CTRL_EXT_RESET 0x1 188#define GPHY_CTRL_RTL_MODE 0x2 189#define GPHY_CTRL_LED_MODE 0x4 190#define GPHY_CTRL_ANEG_NOW 0x8 191#define GPHY_CTRL_REV_ANEG 0x10 192#define GPHY_CTRL_GATE_25M_EN 0x20 193#define GPHY_CTRL_LPW_EXIT 0x40 194#define GPHY_CTRL_PHY_IDDQ 0x80 195#define GPHY_CTRL_PHY_IDDQ_DIS 0x100 196#define GPHY_CTRL_GIGA_DIS 0x200 197#define GPHY_CTRL_HIB_EN 0x400 198#define GPHY_CTRL_HIB_PULSE 0x800 199#define GPHY_CTRL_SEL_ANA_RST 0x1000 200#define GPHY_CTRL_PHY_PLL_ON 0x2000 201#define GPHY_CTRL_PWDOWN_HW 0x4000 202#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000 203 204#define GPHY_CTRL_DEFAULT ( \ 205 GPHY_CTRL_SEL_ANA_RST |\ 206 GPHY_CTRL_HIB_PULSE |\ 207 GPHY_CTRL_HIB_EN) 208 209#define GPHY_CTRL_PW_WOL_DIS ( \ 210 GPHY_CTRL_SEL_ANA_RST |\ 211 GPHY_CTRL_HIB_PULSE |\ 212 GPHY_CTRL_HIB_EN |\ 213 GPHY_CTRL_PWDOWN_HW |\ 214 GPHY_CTRL_PHY_IDDQ) 215 216#define GPHY_CTRL_POWER_SAVING ( \ 217 GPHY_CTRL_SEL_ANA_RST |\ 218 GPHY_CTRL_HIB_EN |\ 219 GPHY_CTRL_HIB_PULSE |\ 220 GPHY_CTRL_PWDOWN_HW |\ 221 GPHY_CTRL_PHY_IDDQ) 222 223/* Block IDLE Status Register */ 224#define REG_IDLE_STATUS 0x1410 225#define IDLE_STATUS_SFORCE_MASK 0xFUL 226#define IDLE_STATUS_SFORCE_SHIFT 14 227#define IDLE_STATUS_CALIB_DONE BIT(13) 228#define IDLE_STATUS_CALIB_RES_MASK 0x1FUL 229#define IDLE_STATUS_CALIB_RES_SHIFT 8 230#define IDLE_STATUS_CALIBERR_MASK 0xFUL 231#define IDLE_STATUS_CALIBERR_SHIFT 4 232#define IDLE_STATUS_TXQ_BUSY BIT(3) 233#define IDLE_STATUS_RXQ_BUSY BIT(2) 234#define IDLE_STATUS_TXMAC_BUSY BIT(1) 235#define IDLE_STATUS_RXMAC_BUSY BIT(0) 236#define IDLE_STATUS_MASK (\ 237 IDLE_STATUS_TXQ_BUSY |\ 238 IDLE_STATUS_RXQ_BUSY |\ 239 IDLE_STATUS_TXMAC_BUSY |\ 240 IDLE_STATUS_RXMAC_BUSY) 241 242/* MDIO Control Register */ 243#define REG_MDIO_CTRL 0x1414 244#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit 245 * control data to write to PHY 246 * MII management register */ 247#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit 248 * status data that was read 249 * from the PHY MII management register */ 250#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */ 251#define MDIO_REG_ADDR_SHIFT 16 252#define MDIO_RW 0x200000 /* 1: read, 0: write */ 253#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */ 254#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO 255 * master. And this bit is self 256 * cleared after one cycle */ 257#define MDIO_CLK_SEL_SHIFT 24 258#define MDIO_CLK_25_4 0 259#define MDIO_CLK_25_6 2 260#define MDIO_CLK_25_8 3 261#define MDIO_CLK_25_10 4 262#define MDIO_CLK_25_14 5 263#define MDIO_CLK_25_20 6 264#define MDIO_CLK_25_28 7 265#define MDIO_BUSY 0x8000000 266#define MDIO_AP_EN 0x10000000 267#define MDIO_WAIT_TIMES 10 268 269/* MII PHY Status Register */ 270#define REG_PHY_STATUS 0x1418 271#define PHY_GENERAL_STATUS_MASK 0xFFFF 272#define PHY_STATUS_RECV_ENABLE 0x0001 273#define PHY_OE_PWSP_STATUS_MASK 0x07FF 274#define PHY_OE_PWSP_STATUS_SHIFT 16 275#define PHY_STATUS_LPW_STATE 0x80000000 276/* BIST Control and Status Register0 (for the Packet Memory) */ 277#define REG_BIST0_CTRL 0x141c 278#define BIST0_NOW 0x1 279#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is 280 * un-repairable because 281 * it has address decoder 282 * failure or more than 1 cell 283 * stuck-to-x failure */ 284#define BIST0_FUSE_FLAG 0x4 285 286/* BIST Control and Status Register1(for the retry buffer of PCI Express) */ 287#define REG_BIST1_CTRL 0x1420 288#define BIST1_NOW 0x1 289#define BIST1_SRAM_FAIL 0x2 290#define BIST1_FUSE_FLAG 0x4 291 292/* SerDes Lock Detect Control and Status Register */ 293#define REG_SERDES_LOCK 0x1424 294#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal 295 * comes from Analog SerDes */ 296#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */ 297#define SERDES_LOCK_STS_SELFB_PLL_SHIFT 0xE 298#define SERDES_LOCK_STS_SELFB_PLL_MASK 0x3 299#define SERDES_OVCLK_18_25 0x0 300#define SERDES_OVCLK_12_18 0x1 301#define SERDES_OVCLK_0_4 0x2 302#define SERDES_OVCLK_4_12 0x3 303#define SERDES_MAC_CLK_SLOWDOWN 0x20000 304#define SERDES_PYH_CLK_SLOWDOWN 0x40000 305 306/* MAC Control Register */ 307#define REG_MAC_CTRL 0x1480 308#define MAC_CTRL_TX_EN 0x1 309#define MAC_CTRL_RX_EN 0x2 310#define MAC_CTRL_TX_FLOW 0x4 311#define MAC_CTRL_RX_FLOW 0x8 312#define MAC_CTRL_LOOPBACK 0x10 313#define MAC_CTRL_DUPLX 0x20 314#define MAC_CTRL_ADD_CRC 0x40 315#define MAC_CTRL_PAD 0x80 316#define MAC_CTRL_LENCHK 0x100 317#define MAC_CTRL_HUGE_EN 0x200 318#define MAC_CTRL_PRMLEN_SHIFT 10 319#define MAC_CTRL_PRMLEN_MASK 0xf 320#define MAC_CTRL_RMV_VLAN 0x4000 321#define MAC_CTRL_PROMIS_EN 0x8000 322#define MAC_CTRL_TX_PAUSE 0x10000 323#define MAC_CTRL_SCNT 0x20000 324#define MAC_CTRL_SRST_TX 0x40000 325#define MAC_CTRL_TX_SIMURST 0x80000 326#define MAC_CTRL_SPEED_SHIFT 20 327#define MAC_CTRL_SPEED_MASK 0x3 328#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 329#define MAC_CTRL_TX_HUGE 0x800000 330#define MAC_CTRL_RX_CHKSUM_EN 0x1000000 331#define MAC_CTRL_MC_ALL_EN 0x2000000 332#define MAC_CTRL_BC_EN 0x4000000 333#define MAC_CTRL_DBG 0x8000000 334#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000 335#define MAC_CTRL_HASH_ALG_CRC32 0x20000000 336#define MAC_CTRL_SPEED_MODE_SW 0x40000000 337 338/* MAC IPG/IFG Control Register */ 339#define REG_MAC_IPG_IFG 0x1484 340#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back 341 * inter-packet gap. The 342 * default is 96-bit time */ 343#define MAC_IPG_IFG_IPGT_MASK 0x7f 344#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to 345 * enforce in between RX frames */ 346#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */ 347#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ 348#define MAC_IPG_IFG_IPGR1_MASK 0x7f 349#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ 350#define MAC_IPG_IFG_IPGR2_MASK 0x7f 351 352/* MAC STATION ADDRESS */ 353#define REG_MAC_STA_ADDR 0x1488 354 355/* Hash table for multicast address */ 356#define REG_RX_HASH_TABLE 0x1490 357 358/* MAC Half-Duplex Control Register */ 359#define REG_MAC_HALF_DUPLX_CTRL 0x1498 360#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */ 361#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff 362#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 363#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf 364#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 365#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 366#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure, 367 * immediately start the 368 * transmission after back pressure */ 369#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ 370#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */ 371#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf 372#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ 373#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */ 374 375/* Maximum Frame Length Control Register */ 376#define REG_MTU 0x149c 377 378/* Wake-On-Lan control register */ 379#define REG_WOL_CTRL 0x14a0 380#define WOL_PATTERN_EN 0x00000001 381#define WOL_PATTERN_PME_EN 0x00000002 382#define WOL_MAGIC_EN 0x00000004 383#define WOL_MAGIC_PME_EN 0x00000008 384#define WOL_LINK_CHG_EN 0x00000010 385#define WOL_LINK_CHG_PME_EN 0x00000020 386#define WOL_PATTERN_ST 0x00000100 387#define WOL_MAGIC_ST 0x00000200 388#define WOL_LINKCHG_ST 0x00000400 389#define WOL_CLK_SWITCH_EN 0x00008000 390#define WOL_PT0_EN 0x00010000 391#define WOL_PT1_EN 0x00020000 392#define WOL_PT2_EN 0x00040000 393#define WOL_PT3_EN 0x00080000 394#define WOL_PT4_EN 0x00100000 395#define WOL_PT5_EN 0x00200000 396#define WOL_PT6_EN 0x00400000 397 398/* WOL Length ( 2 DWORD ) */ 399#define REG_WOL_PATTERN_LEN 0x14a4 400#define WOL_PT_LEN_MASK 0x7f 401#define WOL_PT0_LEN_SHIFT 0 402#define WOL_PT1_LEN_SHIFT 8 403#define WOL_PT2_LEN_SHIFT 16 404#define WOL_PT3_LEN_SHIFT 24 405#define WOL_PT4_LEN_SHIFT 0 406#define WOL_PT5_LEN_SHIFT 8 407#define WOL_PT6_LEN_SHIFT 16 408 409/* Internal SRAM Partition Register */ 410#define RFDX_HEAD_ADDR_MASK 0x03FF 411#define RFDX_HARD_ADDR_SHIFT 0 412#define RFDX_TAIL_ADDR_MASK 0x03FF 413#define RFDX_TAIL_ADDR_SHIFT 16 414 415#define REG_SRAM_RFD0_INFO 0x1500 416#define REG_SRAM_RFD1_INFO 0x1504 417#define REG_SRAM_RFD2_INFO 0x1508 418#define REG_SRAM_RFD3_INFO 0x150C 419 420#define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */ 421#define RFD_NIC_LEN_MASK 0x03FF 422 423#define REG_SRAM_TRD_ADDR 0x1518 424#define TPD_HEAD_ADDR_MASK 0x03FF 425#define TPD_HEAD_ADDR_SHIFT 0 426#define TPD_TAIL_ADDR_MASK 0x03FF 427#define TPD_TAIL_ADDR_SHIFT 16 428 429#define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */ 430#define TPD_NIC_LEN_MASK 0x03FF 431 432#define REG_SRAM_RXF_ADDR 0x1520 433#define REG_SRAM_RXF_LEN 0x1524 434#define REG_SRAM_TXF_ADDR 0x1528 435#define REG_SRAM_TXF_LEN 0x152C 436#define REG_SRAM_TCPH_ADDR 0x1530 437#define REG_SRAM_PKTH_ADDR 0x1532 438 439/* 440 * Load Ptr Register 441 * Software sets this bit after the initialization of the head and tail */ 442#define REG_LOAD_PTR 0x1534 443 444/* 445 * addresses of all descriptors, as well as the following descriptor 446 * control register, which triggers each function block to load the head 447 * pointer to prepare for the operation. This bit is then self-cleared 448 * after one cycle. 449 */ 450#define REG_RX_BASE_ADDR_HI 0x1540 451#define REG_TX_BASE_ADDR_HI 0x1544 452#define REG_RFD0_HEAD_ADDR_LO 0x1550 453#define REG_RFD_RING_SIZE 0x1560 454#define RFD_RING_SIZE_MASK 0x0FFF 455#define REG_RX_BUF_SIZE 0x1564 456#define RX_BUF_SIZE_MASK 0xFFFF 457#define REG_RRD0_HEAD_ADDR_LO 0x1568 458#define REG_RRD_RING_SIZE 0x1578 459#define RRD_RING_SIZE_MASK 0x0FFF 460#define REG_TPD_PRI1_ADDR_LO 0x157C 461#define REG_TPD_PRI0_ADDR_LO 0x1580 462#define REG_TPD_RING_SIZE 0x1584 463#define TPD_RING_SIZE_MASK 0xFFFF 464 465/* TXQ Control Register */ 466#define REG_TXQ_CTRL 0x1590 467#define TXQ_TXF_BURST_NUM_MASK 0xFFFFUL 468#define TXQ_TXF_BURST_NUM_SHIFT 16 469#define L1C_TXQ_TXF_BURST_PREF 0x200 470#define L2CB_TXQ_TXF_BURST_PREF 0x40 471#define TXQ_CTRL_PEDING_CLR BIT(8) 472#define TXQ_CTRL_LS_8023_EN BIT(7) 473#define TXQ_CTRL_ENH_MODE BIT(6) 474#define TXQ_CTRL_EN BIT(5) 475#define TXQ_CTRL_IP_OPTION_EN BIT(4) 476#define TXQ_NUM_TPD_BURST_MASK 0xFUL 477#define TXQ_NUM_TPD_BURST_SHIFT 0 478#define TXQ_NUM_TPD_BURST_DEF 5 479#define TXQ_CFGV (\ 480 FIELDX(TXQ_NUM_TPD_BURST, TXQ_NUM_TPD_BURST_DEF) |\ 481 TXQ_CTRL_ENH_MODE |\ 482 TXQ_CTRL_LS_8023_EN |\ 483 TXQ_CTRL_IP_OPTION_EN) 484#define L1C_TXQ_CFGV (\ 485 TXQ_CFGV |\ 486 FIELDX(TXQ_TXF_BURST_NUM, L1C_TXQ_TXF_BURST_PREF)) 487#define L2CB_TXQ_CFGV (\ 488 TXQ_CFGV |\ 489 FIELDX(TXQ_TXF_BURST_NUM, L2CB_TXQ_TXF_BURST_PREF)) 490 491 492/* Jumbo packet Threshold for task offload */ 493#define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */ 494#define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF 495#define MAX_TSO_FRAME_SIZE (7*1024) 496 497#define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */ 498#define TXF_WATER_MARK_MASK 0x0FFF 499#define TXF_LOW_WATER_MARK_SHIFT 0 500#define TXF_HIGH_WATER_MARK_SHIFT 16 501#define TXQ_CTRL_BURST_MODE_EN 0x80000000 502 503#define REG_THRUPUT_MON_CTRL 0x159C 504#define THRUPUT_MON_RATE_MASK 0x3 505#define THRUPUT_MON_RATE_SHIFT 0 506#define THRUPUT_MON_EN 0x80 507 508/* RXQ Control Register */ 509#define REG_RXQ_CTRL 0x15A0 510#define ASPM_THRUPUT_LIMIT_MASK 0x3 511#define ASPM_THRUPUT_LIMIT_SHIFT 0 512#define ASPM_THRUPUT_LIMIT_NO 0x00 513#define ASPM_THRUPUT_LIMIT_1M 0x01 514#define ASPM_THRUPUT_LIMIT_10M 0x02 515#define ASPM_THRUPUT_LIMIT_100M 0x03 516#define IPV6_CHKSUM_CTRL_EN BIT(7) 517#define RXQ_RFD_BURST_NUM_MASK 0x003F 518#define RXQ_RFD_BURST_NUM_SHIFT 20 519#define RXQ_NUM_RFD_PREF_DEF 8 520#define RSS_MODE_MASK 3UL 521#define RSS_MODE_SHIFT 26 522#define RSS_MODE_DIS 0 523#define RSS_MODE_SQSI 1 524#define RSS_MODE_MQSI 2 525#define RSS_MODE_MQMI 3 526#define RSS_NIP_QUEUE_SEL BIT(28) /* 0:q0, 1:table */ 527#define RRS_HASH_CTRL_EN BIT(29) 528#define RX_CUT_THRU_EN BIT(30) 529#define RXQ_CTRL_EN BIT(31) 530 531#define REG_RFD_FREE_THRESH 0x15A4 532#define RFD_FREE_THRESH_MASK 0x003F 533#define RFD_FREE_HI_THRESH_SHIFT 0 534#define RFD_FREE_LO_THRESH_SHIFT 6 535 536/* RXF flow control register */ 537#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 538#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0 539#define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF 540#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16 541#define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF 542 543#define REG_RXD_DMA_CTRL 0x15AC 544#define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */ 545#define RXD_DMA_THRESH_SHIFT 0 546#define RXD_DMA_DOWN_TIMER_MASK 0xFFFF 547#define RXD_DMA_DOWN_TIMER_SHIFT 16 548 549/* DMA Engine Control Register */ 550#define REG_DMA_CTRL 0x15C0 551#define DMA_CTRL_SMB_NOW BIT(31) 552#define DMA_CTRL_WPEND_CLR BIT(30) 553#define DMA_CTRL_RPEND_CLR BIT(29) 554#define DMA_CTRL_WDLY_CNT_MASK 0xFUL 555#define DMA_CTRL_WDLY_CNT_SHIFT 16 556#define DMA_CTRL_WDLY_CNT_DEF 4 557#define DMA_CTRL_RDLY_CNT_MASK 0x1FUL 558#define DMA_CTRL_RDLY_CNT_SHIFT 11 559#define DMA_CTRL_RDLY_CNT_DEF 15 560#define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */ 561#define DMA_CTRL_WREQ_BLEN_MASK 7UL 562#define DMA_CTRL_WREQ_BLEN_SHIFT 7 563#define DMA_CTRL_RREQ_BLEN_MASK 7UL 564#define DMA_CTRL_RREQ_BLEN_SHIFT 4 565#define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */ 566#define DMA_CTRL_RORDER_MODE_MASK 7UL 567#define DMA_CTRL_RORDER_MODE_SHIFT 0 568#define DMA_CTRL_RORDER_MODE_OUT 4 569#define DMA_CTRL_RORDER_MODE_ENHANCE 2 570#define DMA_CTRL_RORDER_MODE_IN 1 571 572/* INT-triggle/SMB Control Register */ 573#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */ 574#define SMB_STAT_TIMER_MASK 0xFFFFFF 575#define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */ 576 577/* Mail box */ 578#define MB_RFDX_PROD_IDX_MASK 0xFFFF 579#define REG_MB_RFD0_PROD_IDX 0x15E0 580 581#define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */ 582#define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */ 583#define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */ 584#define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */ 585 586#define REG_MB_RFD01_CONS_IDX 0x15F8 587#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF 588#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000 589 590/* Interrupt Status Register */ 591#define REG_ISR 0x1600 592#define ISR_SMB 0x00000001 593#define ISR_TIMER 0x00000002 594/* 595 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set 596 * in Table 51 Selene Master Control Register (Offset 0x1400). 597 */ 598#define ISR_MANUAL 0x00000004 599#define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */ 600#define ISR_RFD0_UR 0x00000010 /* RFD0 under run */ 601#define ISR_RFD1_UR 0x00000020 602#define ISR_RFD2_UR 0x00000040 603#define ISR_RFD3_UR 0x00000080 604#define ISR_TXF_UR 0x00000100 605#define ISR_DMAR_TO_RST 0x00000200 606#define ISR_DMAW_TO_RST 0x00000400 607#define ISR_TX_CREDIT 0x00000800 608#define ISR_GPHY 0x00001000 609/* GPHY low power state interrupt */ 610#define ISR_GPHY_LPW 0x00002000 611#define ISR_TXQ_TO_RST 0x00004000 612#define ISR_TX_PKT 0x00008000 613#define ISR_RX_PKT_0 0x00010000 614#define ISR_RX_PKT_1 0x00020000 615#define ISR_RX_PKT_2 0x00040000 616#define ISR_RX_PKT_3 0x00080000 617#define ISR_MAC_RX 0x00100000 618#define ISR_MAC_TX 0x00200000 619#define ISR_UR_DETECTED 0x00400000 620#define ISR_FERR_DETECTED 0x00800000 621#define ISR_NFERR_DETECTED 0x01000000 622#define ISR_CERR_DETECTED 0x02000000 623#define ISR_PHY_LINKDOWN 0x04000000 624#define ISR_DIS_INT 0x80000000 625 626/* Interrupt Mask Register */ 627#define REG_IMR 0x1604 628 629#define IMR_NORMAL_MASK (\ 630 ISR_MANUAL |\ 631 ISR_HW_RXF_OV |\ 632 ISR_RFD0_UR |\ 633 ISR_TXF_UR |\ 634 ISR_DMAR_TO_RST |\ 635 ISR_TXQ_TO_RST |\ 636 ISR_DMAW_TO_RST |\ 637 ISR_GPHY |\ 638 ISR_TX_PKT |\ 639 ISR_RX_PKT_0 |\ 640 ISR_GPHY_LPW |\ 641 ISR_PHY_LINKDOWN) 642 643#define ISR_RX_PKT (\ 644 ISR_RX_PKT_0 |\ 645 ISR_RX_PKT_1 |\ 646 ISR_RX_PKT_2 |\ 647 ISR_RX_PKT_3) 648 649#define ISR_OVER (\ 650 ISR_RFD0_UR |\ 651 ISR_RFD1_UR |\ 652 ISR_RFD2_UR |\ 653 ISR_RFD3_UR |\ 654 ISR_HW_RXF_OV |\ 655 ISR_TXF_UR) 656 657#define ISR_ERROR (\ 658 ISR_DMAR_TO_RST |\ 659 ISR_TXQ_TO_RST |\ 660 ISR_DMAW_TO_RST |\ 661 ISR_PHY_LINKDOWN) 662 663#define REG_INT_RETRIG_TIMER 0x1608 664#define INT_RETRIG_TIMER_MASK 0xFFFF 665 666#define REG_MAC_RX_STATUS_BIN 0x1700 667#define REG_MAC_RX_STATUS_END 0x175c 668#define REG_MAC_TX_STATUS_BIN 0x1760 669#define REG_MAC_TX_STATUS_END 0x17c0 670 671#define REG_CLK_GATING_CTRL 0x1814 672#define CLK_GATING_DMAW_EN 0x0001 673#define CLK_GATING_DMAR_EN 0x0002 674#define CLK_GATING_TXQ_EN 0x0004 675#define CLK_GATING_RXQ_EN 0x0008 676#define CLK_GATING_TXMAC_EN 0x0010 677#define CLK_GATING_RXMAC_EN 0x0020 678 679#define CLK_GATING_EN_ALL (CLK_GATING_DMAW_EN |\ 680 CLK_GATING_DMAR_EN |\ 681 CLK_GATING_TXQ_EN |\ 682 CLK_GATING_RXQ_EN |\ 683 CLK_GATING_TXMAC_EN|\ 684 CLK_GATING_RXMAC_EN) 685 686/* DEBUG ADDR */ 687#define REG_DEBUG_DATA0 0x1900 688#define REG_DEBUG_DATA1 0x1904 689 690#define L1D_MPW_PHYID1 0xD01C /* V7 */ 691#define L1D_MPW_PHYID2 0xD01D /* V1-V6 */ 692#define L1D_MPW_PHYID3 0xD01E /* V8 */ 693 694 695/* Autoneg Advertisement Register */ 696#define ADVERTISE_DEFAULT_CAP \ 697 (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM) 698 699/* 1000BASE-T Control Register */ 700#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */ 701 702#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 703#define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 704#define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 705#define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 706#define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 707#define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 708#define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 709#define GIGA_CR_1000T_SPEED_MASK 0x0300 710#define GIGA_CR_1000T_DEFAULT_CAP 0x0300 711 712/* PHY Specific Status Register */ 713#define MII_GIGA_PSSR 0x11 714#define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 715#define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 716#define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 717#define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */ 718#define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */ 719#define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 720 721/* PHY Interrupt Enable Register */ 722#define MII_IER 0x12 723#define IER_LINK_UP 0x0400 724#define IER_LINK_DOWN 0x0800 725 726/* PHY Interrupt Status Register */ 727#define MII_ISR 0x13 728#define ISR_LINK_UP 0x0400 729#define ISR_LINK_DOWN 0x0800 730 731/* Cable-Detect-Test Control Register */ 732#define MII_CDTC 0x16 733#define CDTC_EN_OFF 0 /* sc */ 734#define CDTC_EN_BITS 1 735#define CDTC_PAIR_OFF 8 736#define CDTC_PAIR_BIT 2 737 738/* Cable-Detect-Test Status Register */ 739#define MII_CDTS 0x1C 740#define CDTS_STATUS_OFF 8 741#define CDTS_STATUS_BITS 2 742#define CDTS_STATUS_NORMAL 0 743#define CDTS_STATUS_SHORT 1 744#define CDTS_STATUS_OPEN 2 745#define CDTS_STATUS_INVALID 3 746 747#define MII_DBG_ADDR 0x1D 748#define MII_DBG_DATA 0x1E 749 750#define MII_ANA_CTRL_0 0x0 751#define ANA_RESTART_CAL 0x0001 752#define ANA_MANUL_SWICH_ON_SHIFT 0x1 753#define ANA_MANUL_SWICH_ON_MASK 0xF 754#define ANA_MAN_ENABLE 0x0020 755#define ANA_SEL_HSP 0x0040 756#define ANA_EN_HB 0x0080 757#define ANA_EN_HBIAS 0x0100 758#define ANA_OEN_125M 0x0200 759#define ANA_EN_LCKDT 0x0400 760#define ANA_LCKDT_PHY 0x0800 761#define ANA_AFE_MODE 0x1000 762#define ANA_VCO_SLOW 0x2000 763#define ANA_VCO_FAST 0x4000 764#define ANA_SEL_CLK125M_DSP 0x8000 765 766#define MII_ANA_CTRL_4 0x4 767#define ANA_IECHO_ADJ_MASK 0xF 768#define ANA_IECHO_ADJ_3_SHIFT 0 769#define ANA_IECHO_ADJ_2_SHIFT 4 770#define ANA_IECHO_ADJ_1_SHIFT 8 771#define ANA_IECHO_ADJ_0_SHIFT 12 772 773#define MII_ANA_CTRL_5 0x5 774#define ANA_SERDES_CDR_BW_SHIFT 0 775#define ANA_SERDES_CDR_BW_MASK 0x3 776#define ANA_MS_PAD_DBG 0x0004 777#define ANA_SPEEDUP_DBG 0x0008 778#define ANA_SERDES_TH_LOS_SHIFT 4 779#define ANA_SERDES_TH_LOS_MASK 0x3 780#define ANA_SERDES_EN_DEEM 0x0040 781#define ANA_SERDES_TXELECIDLE 0x0080 782#define ANA_SERDES_BEACON 0x0100 783#define ANA_SERDES_HALFTXDR 0x0200 784#define ANA_SERDES_SEL_HSP 0x0400 785#define ANA_SERDES_EN_PLL 0x0800 786#define ANA_SERDES_EN 0x1000 787#define ANA_SERDES_EN_LCKDT 0x2000 788 789#define MII_ANA_CTRL_11 0xB 790#define ANA_PS_HIB_EN 0x8000 791 792#define MII_ANA_CTRL_18 0x12 793#define ANA_TEST_MODE_10BT_01SHIFT 0 794#define ANA_TEST_MODE_10BT_01MASK 0x3 795#define ANA_LOOP_SEL_10BT 0x0004 796#define ANA_RGMII_MODE_SW 0x0008 797#define ANA_EN_LONGECABLE 0x0010 798#define ANA_TEST_MODE_10BT_2 0x0020 799#define ANA_EN_10BT_IDLE 0x0400 800#define ANA_EN_MASK_TB 0x0800 801#define ANA_TRIGGER_SEL_TIMER_SHIFT 12 802#define ANA_TRIGGER_SEL_TIMER_MASK 0x3 803#define ANA_INTERVAL_SEL_TIMER_SHIFT 14 804#define ANA_INTERVAL_SEL_TIMER_MASK 0x3 805 806#define MII_ANA_CTRL_41 0x29 807#define ANA_TOP_PS_EN 0x8000 808 809#define MII_ANA_CTRL_54 0x36 810#define ANA_LONG_CABLE_TH_100_SHIFT 0 811#define ANA_LONG_CABLE_TH_100_MASK 0x3F 812#define ANA_DESERVED 0x0040 813#define ANA_EN_LIT_CH 0x0080 814#define ANA_SHORT_CABLE_TH_100_SHIFT 8 815#define ANA_SHORT_CABLE_TH_100_MASK 0x3F 816#define ANA_BP_BAD_LINK_ACCUM 0x4000 817#define ANA_BP_SMALL_BW 0x8000 818 819#endif /*_ATL1C_HW_H_*/ 820