| fa0afcd10951afad2022dda09777d2bf70cdab3d |
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19-Jul-2012 |
Cloud Ren <cjren@qca.qualcomm.com> |
atl1c: fix issue of io access mode for AR8152 v2.1
When io access mode is enabled by BOOTROM or BIOS for AR8152 v2.1,
the register can't be read/write by memory access mode.
Clearing Bit 8 of Register 0x21c could fixed the issue.
Signed-off-by: Cloud Ren <cjren@qca.qualcomm.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| f56fa56737291df19cd1a9089ade76c59f231212 |
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30-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: enlarge L1 response waiting timer
The hardware incorrectly process L0S/L1 entrance if the chipset/root
response after specific/shorter timer and cause system hang.
Enlarge the timeout value to avoid this issue.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 229e6b6e9cdc615abb10336792bcb94a34ba6532 |
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30-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: refine mac address related code
On some platform with EEPROM/OTP existing, the BIOS could overwrite
a new MAC address for the NIC. so, the permanent mac address should
be from BIOS. the address is restored when driver removing.
Voltage raising isn't applicable for l1d.
Replace swab32 with htonl for big/little endian platform.
related Registers are refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 903d7ce0cc9a45dd29d6f7690b2e3534c61ef326 |
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30-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: add PHY link event(up/down) patch
On some platforms the PHY settings need to change depending on the
cable link status to get better stability.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 319d013af0d47e1137ac02f94ad069312514ddfa |
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25-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: add function atl1c_power_saving
This function is used for suspend of S1/S3/S4 and driver remove.
It sets MAC/PHY based on the WoL configuation to get lower power
consumption.
atl1c_phy_power_saving is renamed to atl1c_phy_to_ps_link, this
function is just make PHY enter a link/speed mode to eat less
power.
REG_MAC_CTRL register is refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| ce5b972bc840d024289c73a096d61cfdf57eff2e |
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25-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: update PHY reset related routine
Many magic data are re-configured for PHY during its reset operation
based on chip type to get better compability and stability.
REG_PHY_CTRL register may be configured by BIOS before enter OS.
so, the driver can't directly write to it without any Read-Op.
this change also affect suspend and phy_disable routines.
PHY debug ports and extension registers are refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 7737fd96450236accb4856916366240a96de97be |
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25-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: refine SERDES-clock related code
bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause
the write-reg operation fail without cable connected.
so, please do connect the cable when apply this patch to the driver
to make sure these 2bits are cleared by new driver.
The revised code is move to al1c_reset_mac.
SERDES register definition is refined as well.
when do reset MAC, speed/duplex control right should be transferred
to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW.
SERDES register definition is refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 929a5e9318f090e190b67343fb37533e58aec3a3 |
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25-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: refine phy-register read/write function
phy register is read/write via MDIO control module ---
that module will be affected by the hibernate status,
to access phy regs in hib stutus, slow frequency clk must
be selected.
To access phy extension register, the MDIO related
registers are refined/updated, a _core function is
re-wroted for both regular PHY regs and extension regs.
existing PHY r/w function is revised based on the _core.
PHY extension registers will be used for the comming
patches.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 8f33ab913456654b2bfc75b90893dce9561cab9a |
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25-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: remove REG_PHY_STATUS
this register is used for l1e(dev=1026)
l1c/l1d/l2cb don't use it.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| d163ff7b10d8d09bdaec394c19c50da1af813832 |
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19-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: fix WoL(magic) issue for l2cb 1.1
l2cb 1.1 hardware has a bug for magic wakeup,
the workaround is to add pattern enable.
WoL related registers are refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| ebe22ed960024385d935620910c1dd9d2c36bf23 |
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19-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: refine atl1c_pcie_patch
bit PCIE_PHYMISC_FORCE_RCV_DET is only for l1c&l2c to fix WoL issue,
other chips set bit5 of REG_MASTER_CTRL --- this way could save more
power than the former, and the bit should be kept all time.
l2cb 1.x has special setting for L0S/L1
l2cb 1.x & l1d 1.x should clear Vendor Message on some platforms,
otherwise it will cause the root complex hang.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 024e1e4dcde98eff0fa5bf2881e4b304c147bd86 |
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19-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: refine/update ASPM configuration
some platforms(BIOS or OS) may change ASPM configuration in
PCI Express Link Control Register directly and dynamically
regardless the device driver installation.
Checking if ASPM support during the driver init phase by reading
PCI Express Link Contrl Register doesn't make sense.
This refine/update assume L0S/L1 is defalut enabled as hw->ctrl_flags
inited. atl1c_set_aspm will set real configuration based on chip
capability to hardware register.
atl1c_disable_l0s_l1 and register definition of REG_PM_CTRL are
refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 7f5544d6693ab2593b4f13521a577387f3be6b2f |
|
19-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: refine reg definition of REG_MASTER_CTRL
refine/update register REG_MASTER_CTRL definition according with
hardware spec.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 95f9aea76943af35b4720c61d27fa09c30f237dd |
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19-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: clear PCIE error status in atl1c_reset_pcie
clear PCIE error status (error log is write-1-clear).
REG_PCIE_UC_SEVERITY is removed as it's a standard pcie register,
and using kernle API to access it.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| c08b9b2a5b3f0fd83e7f72da03f0a0df12c67e3a |
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19-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: update right threshold for TSO
atl1c_configure_tx used a wrong value of MAX_TX_OFFLOAD_THRESH(9KB)
for TSO threshold.
the right value should be 7KB
Fast Ethernet controller doesn't support Jumbo frame.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 969a7ee2a8398fb705f9836dc11d9e307d3ac89c |
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19-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: add module parameter for l1c_wait_until_idle
l1c_wait_until_idle is called for serval modules (TXQ/RXQ/TXMAC/RXMAC).
specific moudle have specific idle/busy status in reg REG_IDLE_STATUS.
the previous code return wrongly if all modules are in idle status,
regardless the 'stop' action is applied on individual module.
Refine the reg REG_IDLE_STATUS definition as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 59e26eff48745287d648ed4606fe2cc66a75991f |
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17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: restore max-read-request-size in Device Conrol Register
in some platforms, we found the max-read-request-size in Device Control
Register is set to 0 by (BIOS?) during bootup, this will cause the
performance(throughput) very bad.
Restore it to a min-value.
register definition of REG_DEVICE_CTRL is removed, using kernel API to
access it as it's a standard pcie register.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| c24588afc536a35c924d014f13b669b20ccf8553 |
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17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: using fixed TXQ configuration for l2cb and l1c
using fixed TXQ config for l2cb and l1c regardless dmar_block
to make tx-DMA more stable.
register REG_TXQ_CTRL is refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 37bfccb595ffc1fe4030aa06659d287c1463076e |
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17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: correct wrong definition of REG_DMA_CTRL
some fields of REG_DMA_CTRL(15C0) are wrong, replace with the newest one.
haredware uses fixed dma-write-block size, remove dmaw_block related code
in function atl1c_configure_dma.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 027392c2d6fe4960eb41fad2baf77c4df651a9cb |
|
17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: remove code related to rxq 1/2/3
remove code related to rxq 1/2/3 since multi-q not support.
refine REG_RXQ_CTRL definition as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 0af48336704e5b3870e03699b3acf5dd7d7cb8ab |
|
17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: split 2 32bit registers of TPD to 4 16bit registers
TPD producer/consumer index is 16bit wide.
16bit read/write reduce the dependency of the 2 tpd rings (hi and lo)
rename reg(157C/1580) to keep name coninsistency.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 8d5c68362f7d77cdffdf12ab7516a6eb77a5dd90 |
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17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: remove SMB/CMB DMA related code
l1c & later chips don't support DMA for SMB.
CMB is removed from hardware.
reg(15C8) is used to trig interrupt by tpd threshold.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| 864ad85f77dc10055c7d5016e99bb201766a737d |
|
17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: remove VPD register
VPD register is only used for L1(devid=PCI_DEVICE_ID_ATTANSIC_L1) to
access external NV-memory.
l1c & later chip doesn't use it any more.
PHY 0/1 registers occupy the last 2 slots of the dump table.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| f4e5db2bb7596ffbe758632e2128a0d8a9ea34fe |
|
17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: remove HDS register
remove HDS register as it doesn't exist in hardware.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| 9f1fd0ef65fcf6ee40e6fd3a7f1a4a16bfa9443a |
|
17-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: remove multiple-RX-Q code
the multiple-RX-Q in hardware doesn't work,
all related register definition & code are removed.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 2b133ad6e9e96798007e64eb912c42fa00adef0a |
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20-May-2011 |
Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
atl*: Move the Atheros drivers
Move the Atheros drivers into drivers/net/ethernet/atheros/ and
make the necessary Kconfig and Makefile changes.
CC: Jay Cliburn <jcliburn@gmail.com>
CC: Chris Snook <chris.snook@gmail.com>
CC: Jie Yang <jie.yang@atheros.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
|