atl1c_hw.h revision 8d5c68362f7d77cdffdf12ab7516a6eb77a5dd90
1/* 2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. 3 * 4 * Derived from Intel e1000 driver 5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 59 19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22#ifndef _ATL1C_HW_H_ 23#define _ATL1C_HW_H_ 24 25#include <linux/types.h> 26#include <linux/mii.h> 27 28struct atl1c_adapter; 29struct atl1c_hw; 30 31/* function prototype */ 32void atl1c_phy_disable(struct atl1c_hw *hw); 33void atl1c_hw_set_mac_addr(struct atl1c_hw *hw); 34int atl1c_phy_reset(struct atl1c_hw *hw); 35int atl1c_read_mac_addr(struct atl1c_hw *hw); 36int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex); 37u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr); 38void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value); 39int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); 40int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data); 41bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value); 42int atl1c_phy_init(struct atl1c_hw *hw); 43int atl1c_check_eeprom_exist(struct atl1c_hw *hw); 44int atl1c_restart_autoneg(struct atl1c_hw *hw); 45int atl1c_phy_power_saving(struct atl1c_hw *hw); 46/* register definition */ 47#define REG_DEVICE_CAP 0x5C 48#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7 49#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0 50 51#define REG_DEVICE_CTRL 0x60 52#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7 53#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5 54#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7 55#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12 56 57#define REG_LINK_CTRL 0x68 58#define LINK_CTRL_L0S_EN 0x01 59#define LINK_CTRL_L1_EN 0x02 60#define LINK_CTRL_EXT_SYNC 0x80 61 62#define REG_PCIE_UC_SEVERITY 0x10C 63#define PCIE_UC_SERVRITY_TRN 0x00000001 64#define PCIE_UC_SERVRITY_DLP 0x00000010 65#define PCIE_UC_SERVRITY_PSN_TLP 0x00001000 66#define PCIE_UC_SERVRITY_FCP 0x00002000 67#define PCIE_UC_SERVRITY_CPL_TO 0x00004000 68#define PCIE_UC_SERVRITY_CA 0x00008000 69#define PCIE_UC_SERVRITY_UC 0x00010000 70#define PCIE_UC_SERVRITY_ROV 0x00020000 71#define PCIE_UC_SERVRITY_MLFP 0x00040000 72#define PCIE_UC_SERVRITY_ECRC 0x00080000 73#define PCIE_UC_SERVRITY_UR 0x00100000 74 75#define REG_DEV_SERIALNUM_CTRL 0x200 76#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */ 77#define REG_DEV_MAC_SEL_SHIFT 0 78#define REG_DEV_SERIAL_NUM_EN_MASK 0x1 79#define REG_DEV_SERIAL_NUM_EN_SHIFT 1 80 81#define REG_TWSI_CTRL 0x218 82#define TWSI_CTRL_LD_OFFSET_MASK 0xFF 83#define TWSI_CTRL_LD_OFFSET_SHIFT 0 84#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 85#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 86#define TWSI_CTRL_SW_LDSTART 0x800 87#define TWSI_CTRL_HW_LDSTART 0x1000 88#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F 89#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 90#define TWSI_CTRL_LD_EXIST 0x400000 91#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 92#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 93#define TWSI_CTRL_FREQ_SEL_100K 0 94#define TWSI_CTRL_FREQ_SEL_200K 1 95#define TWSI_CTRL_FREQ_SEL_300K 2 96#define TWSI_CTRL_FREQ_SEL_400K 3 97#define TWSI_CTRL_SMB_SLV_ADDR 98#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 99#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 100 101 102#define REG_PCIE_DEV_MISC_CTRL 0x21C 103#define PCIE_DEV_MISC_EXT_PIPE 0x2 104#define PCIE_DEV_MISC_RETRY_BUFDIS 0x1 105#define PCIE_DEV_MISC_SPIROM_EXIST 0x4 106#define PCIE_DEV_MISC_SERDES_ENDIAN 0x8 107#define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10 108 109#define REG_PCIE_PHYMISC 0x1000 110#define PCIE_PHYMISC_FORCE_RCV_DET 0x4 111 112#define REG_PCIE_PHYMISC2 0x1004 113#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x3 114#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 115#define PCIE_PHYMISC2_SERDES_TH_MASK 0x3 116#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 117 118#define REG_TWSI_DEBUG 0x1108 119#define TWSI_DEBUG_DEV_EXIST 0x20000000 120 121#define REG_EEPROM_CTRL 0x12C0 122#define EEPROM_CTRL_DATA_HI_MASK 0xFFFF 123#define EEPROM_CTRL_DATA_HI_SHIFT 0 124#define EEPROM_CTRL_ADDR_MASK 0x3FF 125#define EEPROM_CTRL_ADDR_SHIFT 16 126#define EEPROM_CTRL_ACK 0x40000000 127#define EEPROM_CTRL_RW 0x80000000 128 129#define REG_EEPROM_DATA_LO 0x12C4 130 131#define REG_OTP_CTRL 0x12F0 132#define OTP_CTRL_CLK_EN 0x0002 133 134#define REG_PM_CTRL 0x12F8 135#define PM_CTRL_SDES_EN 0x00000001 136#define PM_CTRL_RBER_EN 0x00000002 137#define PM_CTRL_CLK_REQ_EN 0x00000004 138#define PM_CTRL_ASPM_L1_EN 0x00000008 139#define PM_CTRL_SERDES_L1_EN 0x00000010 140#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020 141#define PM_CTRL_SERDES_PD_EX_L1 0x00000040 142#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080 143#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF 144#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8 145#define PM_CTRL_ASPM_L0S_EN 0x00001000 146#define PM_CTRL_CLK_SWH_L1 0x00002000 147#define PM_CTRL_CLK_PWM_VER1_1 0x00004000 148#define PM_CTRL_RCVR_WT_TIMER 0x00008000 149#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF 150#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16 151#define PM_CTRL_PM_REQ_TIMER_MASK 0xF 152#define PM_CTRL_PM_REQ_TIMER_SHIFT 20 153#define PM_CTRL_LCKDET_TIMER_MASK 0xF 154#define PM_CTRL_LCKDET_TIMER_SHIFT 24 155#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000 156#define PM_CTRL_SA_DLY_EN 0x20000000 157#define PM_CTRL_MAC_ASPM_CHK 0x40000000 158#define PM_CTRL_HOTRST 0x80000000 159 160#define REG_LTSSM_ID_CTRL 0x12FC 161#define LTSSM_ID_EN_WRO 0x1000 162/* Selene Master Control Register */ 163#define REG_MASTER_CTRL 0x1400 164#define MASTER_CTRL_SOFT_RST 0x1 165#define MASTER_CTRL_TEST_MODE_MASK 0x3 166#define MASTER_CTRL_TEST_MODE_SHIFT 2 167#define MASTER_CTRL_BERT_START 0x10 168#define MASTER_CTRL_OOB_DIS_OFF 0x40 169#define MASTER_CTRL_SA_TIMER_EN 0x80 170#define MASTER_CTRL_MTIMER_EN 0x100 171#define MASTER_CTRL_MANUAL_INT 0x200 172#define MASTER_CTRL_TX_ITIMER_EN 0x400 173#define MASTER_CTRL_RX_ITIMER_EN 0x800 174#define MASTER_CTRL_CLK_SEL_DIS 0x1000 175#define MASTER_CTRL_CLK_SWH_MODE 0x2000 176#define MASTER_CTRL_INT_RDCLR 0x4000 177#define MASTER_CTRL_REV_NUM_SHIFT 16 178#define MASTER_CTRL_REV_NUM_MASK 0xff 179#define MASTER_CTRL_DEV_ID_SHIFT 24 180#define MASTER_CTRL_DEV_ID_MASK 0x7f 181#define MASTER_CTRL_OTP_SEL 0x80000000 182 183/* Timer Initial Value Register */ 184#define REG_MANUAL_TIMER_INIT 0x1404 185 186/* IRQ ModeratorTimer Initial Value Register */ 187#define REG_IRQ_MODRT_TIMER_INIT 0x1408 188#define IRQ_MODRT_TIMER_MASK 0xffff 189#define IRQ_MODRT_TX_TIMER_SHIFT 0 190#define IRQ_MODRT_RX_TIMER_SHIFT 16 191 192#define REG_GPHY_CTRL 0x140C 193#define GPHY_CTRL_EXT_RESET 0x1 194#define GPHY_CTRL_RTL_MODE 0x2 195#define GPHY_CTRL_LED_MODE 0x4 196#define GPHY_CTRL_ANEG_NOW 0x8 197#define GPHY_CTRL_REV_ANEG 0x10 198#define GPHY_CTRL_GATE_25M_EN 0x20 199#define GPHY_CTRL_LPW_EXIT 0x40 200#define GPHY_CTRL_PHY_IDDQ 0x80 201#define GPHY_CTRL_PHY_IDDQ_DIS 0x100 202#define GPHY_CTRL_GIGA_DIS 0x200 203#define GPHY_CTRL_HIB_EN 0x400 204#define GPHY_CTRL_HIB_PULSE 0x800 205#define GPHY_CTRL_SEL_ANA_RST 0x1000 206#define GPHY_CTRL_PHY_PLL_ON 0x2000 207#define GPHY_CTRL_PWDOWN_HW 0x4000 208#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000 209 210#define GPHY_CTRL_DEFAULT ( \ 211 GPHY_CTRL_SEL_ANA_RST |\ 212 GPHY_CTRL_HIB_PULSE |\ 213 GPHY_CTRL_HIB_EN) 214 215#define GPHY_CTRL_PW_WOL_DIS ( \ 216 GPHY_CTRL_SEL_ANA_RST |\ 217 GPHY_CTRL_HIB_PULSE |\ 218 GPHY_CTRL_HIB_EN |\ 219 GPHY_CTRL_PWDOWN_HW |\ 220 GPHY_CTRL_PHY_IDDQ) 221 222#define GPHY_CTRL_POWER_SAVING ( \ 223 GPHY_CTRL_SEL_ANA_RST |\ 224 GPHY_CTRL_HIB_EN |\ 225 GPHY_CTRL_HIB_PULSE |\ 226 GPHY_CTRL_PWDOWN_HW |\ 227 GPHY_CTRL_PHY_IDDQ) 228/* Block IDLE Status Register */ 229#define REG_IDLE_STATUS 0x1410 230#define IDLE_STATUS_MASK 0x00FF 231#define IDLE_STATUS_RXMAC_NO_IDLE 0x1 232#define IDLE_STATUS_TXMAC_NO_IDLE 0x2 233#define IDLE_STATUS_RXQ_NO_IDLE 0x4 234#define IDLE_STATUS_TXQ_NO_IDLE 0x8 235#define IDLE_STATUS_DMAR_NO_IDLE 0x10 236#define IDLE_STATUS_DMAW_NO_IDLE 0x20 237#define IDLE_STATUS_SMB_NO_IDLE 0x40 238#define IDLE_STATUS_CMB_NO_IDLE 0x80 239 240/* MDIO Control Register */ 241#define REG_MDIO_CTRL 0x1414 242#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit 243 * control data to write to PHY 244 * MII management register */ 245#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit 246 * status data that was read 247 * from the PHY MII management register */ 248#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */ 249#define MDIO_REG_ADDR_SHIFT 16 250#define MDIO_RW 0x200000 /* 1: read, 0: write */ 251#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */ 252#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO 253 * master. And this bit is self 254 * cleared after one cycle */ 255#define MDIO_CLK_SEL_SHIFT 24 256#define MDIO_CLK_25_4 0 257#define MDIO_CLK_25_6 2 258#define MDIO_CLK_25_8 3 259#define MDIO_CLK_25_10 4 260#define MDIO_CLK_25_14 5 261#define MDIO_CLK_25_20 6 262#define MDIO_CLK_25_28 7 263#define MDIO_BUSY 0x8000000 264#define MDIO_AP_EN 0x10000000 265#define MDIO_WAIT_TIMES 10 266 267/* MII PHY Status Register */ 268#define REG_PHY_STATUS 0x1418 269#define PHY_GENERAL_STATUS_MASK 0xFFFF 270#define PHY_STATUS_RECV_ENABLE 0x0001 271#define PHY_OE_PWSP_STATUS_MASK 0x07FF 272#define PHY_OE_PWSP_STATUS_SHIFT 16 273#define PHY_STATUS_LPW_STATE 0x80000000 274/* BIST Control and Status Register0 (for the Packet Memory) */ 275#define REG_BIST0_CTRL 0x141c 276#define BIST0_NOW 0x1 277#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is 278 * un-repairable because 279 * it has address decoder 280 * failure or more than 1 cell 281 * stuck-to-x failure */ 282#define BIST0_FUSE_FLAG 0x4 283 284/* BIST Control and Status Register1(for the retry buffer of PCI Express) */ 285#define REG_BIST1_CTRL 0x1420 286#define BIST1_NOW 0x1 287#define BIST1_SRAM_FAIL 0x2 288#define BIST1_FUSE_FLAG 0x4 289 290/* SerDes Lock Detect Control and Status Register */ 291#define REG_SERDES_LOCK 0x1424 292#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal 293 * comes from Analog SerDes */ 294#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */ 295#define SERDES_LOCK_STS_SELFB_PLL_SHIFT 0xE 296#define SERDES_LOCK_STS_SELFB_PLL_MASK 0x3 297#define SERDES_OVCLK_18_25 0x0 298#define SERDES_OVCLK_12_18 0x1 299#define SERDES_OVCLK_0_4 0x2 300#define SERDES_OVCLK_4_12 0x3 301#define SERDES_MAC_CLK_SLOWDOWN 0x20000 302#define SERDES_PYH_CLK_SLOWDOWN 0x40000 303 304/* MAC Control Register */ 305#define REG_MAC_CTRL 0x1480 306#define MAC_CTRL_TX_EN 0x1 307#define MAC_CTRL_RX_EN 0x2 308#define MAC_CTRL_TX_FLOW 0x4 309#define MAC_CTRL_RX_FLOW 0x8 310#define MAC_CTRL_LOOPBACK 0x10 311#define MAC_CTRL_DUPLX 0x20 312#define MAC_CTRL_ADD_CRC 0x40 313#define MAC_CTRL_PAD 0x80 314#define MAC_CTRL_LENCHK 0x100 315#define MAC_CTRL_HUGE_EN 0x200 316#define MAC_CTRL_PRMLEN_SHIFT 10 317#define MAC_CTRL_PRMLEN_MASK 0xf 318#define MAC_CTRL_RMV_VLAN 0x4000 319#define MAC_CTRL_PROMIS_EN 0x8000 320#define MAC_CTRL_TX_PAUSE 0x10000 321#define MAC_CTRL_SCNT 0x20000 322#define MAC_CTRL_SRST_TX 0x40000 323#define MAC_CTRL_TX_SIMURST 0x80000 324#define MAC_CTRL_SPEED_SHIFT 20 325#define MAC_CTRL_SPEED_MASK 0x3 326#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 327#define MAC_CTRL_TX_HUGE 0x800000 328#define MAC_CTRL_RX_CHKSUM_EN 0x1000000 329#define MAC_CTRL_MC_ALL_EN 0x2000000 330#define MAC_CTRL_BC_EN 0x4000000 331#define MAC_CTRL_DBG 0x8000000 332#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000 333#define MAC_CTRL_HASH_ALG_CRC32 0x20000000 334#define MAC_CTRL_SPEED_MODE_SW 0x40000000 335 336/* MAC IPG/IFG Control Register */ 337#define REG_MAC_IPG_IFG 0x1484 338#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back 339 * inter-packet gap. The 340 * default is 96-bit time */ 341#define MAC_IPG_IFG_IPGT_MASK 0x7f 342#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to 343 * enforce in between RX frames */ 344#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */ 345#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ 346#define MAC_IPG_IFG_IPGR1_MASK 0x7f 347#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ 348#define MAC_IPG_IFG_IPGR2_MASK 0x7f 349 350/* MAC STATION ADDRESS */ 351#define REG_MAC_STA_ADDR 0x1488 352 353/* Hash table for multicast address */ 354#define REG_RX_HASH_TABLE 0x1490 355 356/* MAC Half-Duplex Control Register */ 357#define REG_MAC_HALF_DUPLX_CTRL 0x1498 358#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */ 359#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff 360#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 361#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf 362#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 363#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 364#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure, 365 * immediately start the 366 * transmission after back pressure */ 367#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ 368#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */ 369#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf 370#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ 371#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */ 372 373/* Maximum Frame Length Control Register */ 374#define REG_MTU 0x149c 375 376/* Wake-On-Lan control register */ 377#define REG_WOL_CTRL 0x14a0 378#define WOL_PATTERN_EN 0x00000001 379#define WOL_PATTERN_PME_EN 0x00000002 380#define WOL_MAGIC_EN 0x00000004 381#define WOL_MAGIC_PME_EN 0x00000008 382#define WOL_LINK_CHG_EN 0x00000010 383#define WOL_LINK_CHG_PME_EN 0x00000020 384#define WOL_PATTERN_ST 0x00000100 385#define WOL_MAGIC_ST 0x00000200 386#define WOL_LINKCHG_ST 0x00000400 387#define WOL_CLK_SWITCH_EN 0x00008000 388#define WOL_PT0_EN 0x00010000 389#define WOL_PT1_EN 0x00020000 390#define WOL_PT2_EN 0x00040000 391#define WOL_PT3_EN 0x00080000 392#define WOL_PT4_EN 0x00100000 393#define WOL_PT5_EN 0x00200000 394#define WOL_PT6_EN 0x00400000 395 396/* WOL Length ( 2 DWORD ) */ 397#define REG_WOL_PATTERN_LEN 0x14a4 398#define WOL_PT_LEN_MASK 0x7f 399#define WOL_PT0_LEN_SHIFT 0 400#define WOL_PT1_LEN_SHIFT 8 401#define WOL_PT2_LEN_SHIFT 16 402#define WOL_PT3_LEN_SHIFT 24 403#define WOL_PT4_LEN_SHIFT 0 404#define WOL_PT5_LEN_SHIFT 8 405#define WOL_PT6_LEN_SHIFT 16 406 407/* Internal SRAM Partition Register */ 408#define RFDX_HEAD_ADDR_MASK 0x03FF 409#define RFDX_HARD_ADDR_SHIFT 0 410#define RFDX_TAIL_ADDR_MASK 0x03FF 411#define RFDX_TAIL_ADDR_SHIFT 16 412 413#define REG_SRAM_RFD0_INFO 0x1500 414#define REG_SRAM_RFD1_INFO 0x1504 415#define REG_SRAM_RFD2_INFO 0x1508 416#define REG_SRAM_RFD3_INFO 0x150C 417 418#define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */ 419#define RFD_NIC_LEN_MASK 0x03FF 420 421#define REG_SRAM_TRD_ADDR 0x1518 422#define TPD_HEAD_ADDR_MASK 0x03FF 423#define TPD_HEAD_ADDR_SHIFT 0 424#define TPD_TAIL_ADDR_MASK 0x03FF 425#define TPD_TAIL_ADDR_SHIFT 16 426 427#define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */ 428#define TPD_NIC_LEN_MASK 0x03FF 429 430#define REG_SRAM_RXF_ADDR 0x1520 431#define REG_SRAM_RXF_LEN 0x1524 432#define REG_SRAM_TXF_ADDR 0x1528 433#define REG_SRAM_TXF_LEN 0x152C 434#define REG_SRAM_TCPH_ADDR 0x1530 435#define REG_SRAM_PKTH_ADDR 0x1532 436 437/* 438 * Load Ptr Register 439 * Software sets this bit after the initialization of the head and tail */ 440#define REG_LOAD_PTR 0x1534 441 442/* 443 * addresses of all descriptors, as well as the following descriptor 444 * control register, which triggers each function block to load the head 445 * pointer to prepare for the operation. This bit is then self-cleared 446 * after one cycle. 447 */ 448#define REG_RX_BASE_ADDR_HI 0x1540 449#define REG_TX_BASE_ADDR_HI 0x1544 450#define REG_RFD0_HEAD_ADDR_LO 0x1550 451#define REG_RFD_RING_SIZE 0x1560 452#define RFD_RING_SIZE_MASK 0x0FFF 453#define REG_RX_BUF_SIZE 0x1564 454#define RX_BUF_SIZE_MASK 0xFFFF 455#define REG_RRD0_HEAD_ADDR_LO 0x1568 456#define REG_RRD_RING_SIZE 0x1578 457#define RRD_RING_SIZE_MASK 0x0FFF 458#define REG_HTPD_HEAD_ADDR_LO 0x157C 459#define REG_NTPD_HEAD_ADDR_LO 0x1580 460#define REG_TPD_RING_SIZE 0x1584 461#define TPD_RING_SIZE_MASK 0xFFFF 462 463/* TXQ Control Register */ 464#define REG_TXQ_CTRL 0x1590 465#define TXQ_NUM_TPD_BURST_MASK 0xF 466#define TXQ_NUM_TPD_BURST_SHIFT 0 467#define TXQ_CTRL_IP_OPTION_EN 0x10 468#define TXQ_CTRL_EN 0x20 469#define TXQ_CTRL_ENH_MODE 0x40 470#define TXQ_CTRL_LS_8023_EN 0x80 471#define TXQ_TXF_BURST_NUM_SHIFT 16 472#define TXQ_TXF_BURST_NUM_MASK 0xFFFF 473 474/* Jumbo packet Threshold for task offload */ 475#define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */ 476#define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF 477 478#define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */ 479#define TXF_WATER_MARK_MASK 0x0FFF 480#define TXF_LOW_WATER_MARK_SHIFT 0 481#define TXF_HIGH_WATER_MARK_SHIFT 16 482#define TXQ_CTRL_BURST_MODE_EN 0x80000000 483 484#define REG_THRUPUT_MON_CTRL 0x159C 485#define THRUPUT_MON_RATE_MASK 0x3 486#define THRUPUT_MON_RATE_SHIFT 0 487#define THRUPUT_MON_EN 0x80 488 489/* RXQ Control Register */ 490#define REG_RXQ_CTRL 0x15A0 491#define ASPM_THRUPUT_LIMIT_MASK 0x3 492#define ASPM_THRUPUT_LIMIT_SHIFT 0 493#define ASPM_THRUPUT_LIMIT_NO 0x00 494#define ASPM_THRUPUT_LIMIT_1M 0x01 495#define ASPM_THRUPUT_LIMIT_10M 0x02 496#define ASPM_THRUPUT_LIMIT_100M 0x04 497#define RXQ1_CTRL_EN 0x10 498#define RXQ2_CTRL_EN 0x20 499#define RXQ3_CTRL_EN 0x40 500#define IPV6_CHKSUM_CTRL_EN 0x80 501#define RSS_HASH_BITS_MASK 0x00FF 502#define RSS_HASH_BITS_SHIFT 8 503#define RSS_HASH_IPV4 0x10000 504#define RSS_HASH_IPV4_TCP 0x20000 505#define RSS_HASH_IPV6 0x40000 506#define RSS_HASH_IPV6_TCP 0x80000 507#define RXQ_RFD_BURST_NUM_MASK 0x003F 508#define RXQ_RFD_BURST_NUM_SHIFT 20 509#define RSS_MODE_MASK 0x0003 510#define RSS_MODE_SHIFT 26 511#define RSS_NIP_QUEUE_SEL_MASK 0x1 512#define RSS_NIP_QUEUE_SEL_SHIFT 28 513#define RRS_HASH_CTRL_EN 0x20000000 514#define RX_CUT_THRU_EN 0x40000000 515#define RXQ_CTRL_EN 0x80000000 516 517#define REG_RFD_FREE_THRESH 0x15A4 518#define RFD_FREE_THRESH_MASK 0x003F 519#define RFD_FREE_HI_THRESH_SHIFT 0 520#define RFD_FREE_LO_THRESH_SHIFT 6 521 522/* RXF flow control register */ 523#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 524#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0 525#define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF 526#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16 527#define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF 528 529#define REG_RXD_DMA_CTRL 0x15AC 530#define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */ 531#define RXD_DMA_THRESH_SHIFT 0 532#define RXD_DMA_DOWN_TIMER_MASK 0xFFFF 533#define RXD_DMA_DOWN_TIMER_SHIFT 16 534 535/* DMA Engine Control Register */ 536#define REG_DMA_CTRL 0x15C0 537#define DMA_CTRL_DMAR_IN_ORDER 0x1 538#define DMA_CTRL_DMAR_ENH_ORDER 0x2 539#define DMA_CTRL_DMAR_OUT_ORDER 0x4 540#define DMA_CTRL_RCB_VALUE 0x8 541#define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007 542#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4 543#define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007 544#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7 545#define DMA_CTRL_DMAR_REQ_PRI 0x400 546#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F 547#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11 548#define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F 549#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16 550#define DMA_CTRL_CMB_EN 0x100000 551#define DMA_CTRL_SMB_EN 0x200000 552#define DMA_CTRL_CMB_NOW 0x400000 553#define MAC_CTRL_SMB_DIS 0x1000000 554#define DMA_CTRL_SMB_NOW 0x80000000 555 556/* INT-triggle/SMB Control Register */ 557#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */ 558#define SMB_STAT_TIMER_MASK 0xFFFFFF 559#define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */ 560 561/* Mail box */ 562#define MB_RFDX_PROD_IDX_MASK 0xFFFF 563#define REG_MB_RFD0_PROD_IDX 0x15E0 564 565#define MB_PRIO_PROD_IDX_MASK 0xFFFF 566#define REG_MB_PRIO_PROD_IDX 0x15F0 567#define MB_HTPD_PROD_IDX_SHIFT 0 568#define MB_NTPD_PROD_IDX_SHIFT 16 569 570#define MB_PRIO_CONS_IDX_MASK 0xFFFF 571#define REG_MB_PRIO_CONS_IDX 0x15F4 572#define MB_HTPD_CONS_IDX_SHIFT 0 573#define MB_NTPD_CONS_IDX_SHIFT 16 574 575#define REG_MB_RFD01_CONS_IDX 0x15F8 576#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF 577#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000 578 579/* Interrupt Status Register */ 580#define REG_ISR 0x1600 581#define ISR_SMB 0x00000001 582#define ISR_TIMER 0x00000002 583/* 584 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set 585 * in Table 51 Selene Master Control Register (Offset 0x1400). 586 */ 587#define ISR_MANUAL 0x00000004 588#define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */ 589#define ISR_RFD0_UR 0x00000010 /* RFD0 under run */ 590#define ISR_RFD1_UR 0x00000020 591#define ISR_RFD2_UR 0x00000040 592#define ISR_RFD3_UR 0x00000080 593#define ISR_TXF_UR 0x00000100 594#define ISR_DMAR_TO_RST 0x00000200 595#define ISR_DMAW_TO_RST 0x00000400 596#define ISR_TX_CREDIT 0x00000800 597#define ISR_GPHY 0x00001000 598/* GPHY low power state interrupt */ 599#define ISR_GPHY_LPW 0x00002000 600#define ISR_TXQ_TO_RST 0x00004000 601#define ISR_TX_PKT 0x00008000 602#define ISR_RX_PKT_0 0x00010000 603#define ISR_RX_PKT_1 0x00020000 604#define ISR_RX_PKT_2 0x00040000 605#define ISR_RX_PKT_3 0x00080000 606#define ISR_MAC_RX 0x00100000 607#define ISR_MAC_TX 0x00200000 608#define ISR_UR_DETECTED 0x00400000 609#define ISR_FERR_DETECTED 0x00800000 610#define ISR_NFERR_DETECTED 0x01000000 611#define ISR_CERR_DETECTED 0x02000000 612#define ISR_PHY_LINKDOWN 0x04000000 613#define ISR_DIS_INT 0x80000000 614 615/* Interrupt Mask Register */ 616#define REG_IMR 0x1604 617 618#define IMR_NORMAL_MASK (\ 619 ISR_MANUAL |\ 620 ISR_HW_RXF_OV |\ 621 ISR_RFD0_UR |\ 622 ISR_TXF_UR |\ 623 ISR_DMAR_TO_RST |\ 624 ISR_TXQ_TO_RST |\ 625 ISR_DMAW_TO_RST |\ 626 ISR_GPHY |\ 627 ISR_TX_PKT |\ 628 ISR_RX_PKT_0 |\ 629 ISR_GPHY_LPW |\ 630 ISR_PHY_LINKDOWN) 631 632#define ISR_RX_PKT (\ 633 ISR_RX_PKT_0 |\ 634 ISR_RX_PKT_1 |\ 635 ISR_RX_PKT_2 |\ 636 ISR_RX_PKT_3) 637 638#define ISR_OVER (\ 639 ISR_RFD0_UR |\ 640 ISR_RFD1_UR |\ 641 ISR_RFD2_UR |\ 642 ISR_RFD3_UR |\ 643 ISR_HW_RXF_OV |\ 644 ISR_TXF_UR) 645 646#define ISR_ERROR (\ 647 ISR_DMAR_TO_RST |\ 648 ISR_TXQ_TO_RST |\ 649 ISR_DMAW_TO_RST |\ 650 ISR_PHY_LINKDOWN) 651 652#define REG_INT_RETRIG_TIMER 0x1608 653#define INT_RETRIG_TIMER_MASK 0xFFFF 654 655#define REG_MAC_RX_STATUS_BIN 0x1700 656#define REG_MAC_RX_STATUS_END 0x175c 657#define REG_MAC_TX_STATUS_BIN 0x1760 658#define REG_MAC_TX_STATUS_END 0x17c0 659 660#define REG_CLK_GATING_CTRL 0x1814 661#define CLK_GATING_DMAW_EN 0x0001 662#define CLK_GATING_DMAR_EN 0x0002 663#define CLK_GATING_TXQ_EN 0x0004 664#define CLK_GATING_RXQ_EN 0x0008 665#define CLK_GATING_TXMAC_EN 0x0010 666#define CLK_GATING_RXMAC_EN 0x0020 667 668#define CLK_GATING_EN_ALL (CLK_GATING_DMAW_EN |\ 669 CLK_GATING_DMAR_EN |\ 670 CLK_GATING_TXQ_EN |\ 671 CLK_GATING_RXQ_EN |\ 672 CLK_GATING_TXMAC_EN|\ 673 CLK_GATING_RXMAC_EN) 674 675/* DEBUG ADDR */ 676#define REG_DEBUG_DATA0 0x1900 677#define REG_DEBUG_DATA1 0x1904 678 679#define L1D_MPW_PHYID1 0xD01C /* V7 */ 680#define L1D_MPW_PHYID2 0xD01D /* V1-V6 */ 681#define L1D_MPW_PHYID3 0xD01E /* V8 */ 682 683 684/* Autoneg Advertisement Register */ 685#define ADVERTISE_DEFAULT_CAP \ 686 (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM) 687 688/* 1000BASE-T Control Register */ 689#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */ 690 691#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 692#define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 693#define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 694#define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 695#define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 696#define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 697#define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 698#define GIGA_CR_1000T_SPEED_MASK 0x0300 699#define GIGA_CR_1000T_DEFAULT_CAP 0x0300 700 701/* PHY Specific Status Register */ 702#define MII_GIGA_PSSR 0x11 703#define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 704#define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 705#define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 706#define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */ 707#define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */ 708#define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 709 710/* PHY Interrupt Enable Register */ 711#define MII_IER 0x12 712#define IER_LINK_UP 0x0400 713#define IER_LINK_DOWN 0x0800 714 715/* PHY Interrupt Status Register */ 716#define MII_ISR 0x13 717#define ISR_LINK_UP 0x0400 718#define ISR_LINK_DOWN 0x0800 719 720/* Cable-Detect-Test Control Register */ 721#define MII_CDTC 0x16 722#define CDTC_EN_OFF 0 /* sc */ 723#define CDTC_EN_BITS 1 724#define CDTC_PAIR_OFF 8 725#define CDTC_PAIR_BIT 2 726 727/* Cable-Detect-Test Status Register */ 728#define MII_CDTS 0x1C 729#define CDTS_STATUS_OFF 8 730#define CDTS_STATUS_BITS 2 731#define CDTS_STATUS_NORMAL 0 732#define CDTS_STATUS_SHORT 1 733#define CDTS_STATUS_OPEN 2 734#define CDTS_STATUS_INVALID 3 735 736#define MII_DBG_ADDR 0x1D 737#define MII_DBG_DATA 0x1E 738 739#define MII_ANA_CTRL_0 0x0 740#define ANA_RESTART_CAL 0x0001 741#define ANA_MANUL_SWICH_ON_SHIFT 0x1 742#define ANA_MANUL_SWICH_ON_MASK 0xF 743#define ANA_MAN_ENABLE 0x0020 744#define ANA_SEL_HSP 0x0040 745#define ANA_EN_HB 0x0080 746#define ANA_EN_HBIAS 0x0100 747#define ANA_OEN_125M 0x0200 748#define ANA_EN_LCKDT 0x0400 749#define ANA_LCKDT_PHY 0x0800 750#define ANA_AFE_MODE 0x1000 751#define ANA_VCO_SLOW 0x2000 752#define ANA_VCO_FAST 0x4000 753#define ANA_SEL_CLK125M_DSP 0x8000 754 755#define MII_ANA_CTRL_4 0x4 756#define ANA_IECHO_ADJ_MASK 0xF 757#define ANA_IECHO_ADJ_3_SHIFT 0 758#define ANA_IECHO_ADJ_2_SHIFT 4 759#define ANA_IECHO_ADJ_1_SHIFT 8 760#define ANA_IECHO_ADJ_0_SHIFT 12 761 762#define MII_ANA_CTRL_5 0x5 763#define ANA_SERDES_CDR_BW_SHIFT 0 764#define ANA_SERDES_CDR_BW_MASK 0x3 765#define ANA_MS_PAD_DBG 0x0004 766#define ANA_SPEEDUP_DBG 0x0008 767#define ANA_SERDES_TH_LOS_SHIFT 4 768#define ANA_SERDES_TH_LOS_MASK 0x3 769#define ANA_SERDES_EN_DEEM 0x0040 770#define ANA_SERDES_TXELECIDLE 0x0080 771#define ANA_SERDES_BEACON 0x0100 772#define ANA_SERDES_HALFTXDR 0x0200 773#define ANA_SERDES_SEL_HSP 0x0400 774#define ANA_SERDES_EN_PLL 0x0800 775#define ANA_SERDES_EN 0x1000 776#define ANA_SERDES_EN_LCKDT 0x2000 777 778#define MII_ANA_CTRL_11 0xB 779#define ANA_PS_HIB_EN 0x8000 780 781#define MII_ANA_CTRL_18 0x12 782#define ANA_TEST_MODE_10BT_01SHIFT 0 783#define ANA_TEST_MODE_10BT_01MASK 0x3 784#define ANA_LOOP_SEL_10BT 0x0004 785#define ANA_RGMII_MODE_SW 0x0008 786#define ANA_EN_LONGECABLE 0x0010 787#define ANA_TEST_MODE_10BT_2 0x0020 788#define ANA_EN_10BT_IDLE 0x0400 789#define ANA_EN_MASK_TB 0x0800 790#define ANA_TRIGGER_SEL_TIMER_SHIFT 12 791#define ANA_TRIGGER_SEL_TIMER_MASK 0x3 792#define ANA_INTERVAL_SEL_TIMER_SHIFT 14 793#define ANA_INTERVAL_SEL_TIMER_MASK 0x3 794 795#define MII_ANA_CTRL_41 0x29 796#define ANA_TOP_PS_EN 0x8000 797 798#define MII_ANA_CTRL_54 0x36 799#define ANA_LONG_CABLE_TH_100_SHIFT 0 800#define ANA_LONG_CABLE_TH_100_MASK 0x3F 801#define ANA_DESERVED 0x0040 802#define ANA_EN_LIT_CH 0x0080 803#define ANA_SHORT_CABLE_TH_100_SHIFT 8 804#define ANA_SHORT_CABLE_TH_100_MASK 0x3F 805#define ANA_BP_BAD_LINK_ACCUM 0x4000 806#define ANA_BP_SMALL_BW 0x8000 807 808#endif /*_ATL1C_HW_H_*/ 809