bnx2x_main.c revision 259afa1f725dc7ec1626835b9ac54827a46cdf80
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_dcb.h" 63#include "bnx2x_sp.h" 64 65#include <linux/firmware.h> 66#include "bnx2x_fw_file_hdr.h" 67/* FW files */ 68#define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77/* Time in jiffies before concluding the transmitter is hung */ 78#define TX_TIMEOUT (5*HZ) 79 80static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84MODULE_AUTHOR("Eliezer Tamir"); 85MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89MODULE_LICENSE("GPL"); 90MODULE_VERSION(DRV_MODULE_VERSION); 91MODULE_FIRMWARE(FW_FILE_NAME_E1); 92MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95static int multi_mode = 1; 96module_param(multi_mode, int, 0); 97MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100int num_queues; 101module_param(num_queues, int, 0); 102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105static int disable_tpa; 106module_param(disable_tpa, int, 0); 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109#define INT_MODE_INTx 1 110#define INT_MODE_MSI 2 111static int int_mode; 112module_param(int_mode, int, 0); 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116static int dropless_fc; 117module_param(dropless_fc, int, 0); 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120static int mrrs = -1; 121module_param(mrrs, int, 0); 122MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 123 124static int debug; 125module_param(debug, int, 0); 126MODULE_PARM_DESC(debug, " Default debug msglevel"); 127 128 129 130struct workqueue_struct *bnx2x_wq; 131 132enum bnx2x_board_type { 133 BCM57710 = 0, 134 BCM57711, 135 BCM57711E, 136 BCM57712, 137 BCM57712_MF, 138 BCM57800, 139 BCM57800_MF, 140 BCM57810, 141 BCM57810_MF, 142 BCM57840, 143 BCM57840_MF 144}; 145 146/* indexed by board_type, above */ 147static struct { 148 char *name; 149} board_info[] __devinitdata = { 150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 161 "Ethernet Multi Function"} 162}; 163 164#ifndef PCI_DEVICE_ID_NX2_57710 165#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 166#endif 167#ifndef PCI_DEVICE_ID_NX2_57711 168#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 169#endif 170#ifndef PCI_DEVICE_ID_NX2_57711E 171#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 172#endif 173#ifndef PCI_DEVICE_ID_NX2_57712 174#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 175#endif 176#ifndef PCI_DEVICE_ID_NX2_57712_MF 177#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 178#endif 179#ifndef PCI_DEVICE_ID_NX2_57800 180#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 181#endif 182#ifndef PCI_DEVICE_ID_NX2_57800_MF 183#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 184#endif 185#ifndef PCI_DEVICE_ID_NX2_57810 186#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 187#endif 188#ifndef PCI_DEVICE_ID_NX2_57810_MF 189#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 190#endif 191#ifndef PCI_DEVICE_ID_NX2_57840 192#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 193#endif 194#ifndef PCI_DEVICE_ID_NX2_57840_MF 195#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 196#endif 197static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 209 { 0 } 210}; 211 212MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 213 214/**************************************************************************** 215* General service functions 216****************************************************************************/ 217 218static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 219 u32 addr, dma_addr_t mapping) 220{ 221 REG_WR(bp, addr, U64_LO(mapping)); 222 REG_WR(bp, addr + 4, U64_HI(mapping)); 223} 224 225static inline void storm_memset_spq_addr(struct bnx2x *bp, 226 dma_addr_t mapping, u16 abs_fid) 227{ 228 u32 addr = XSEM_REG_FAST_MEMORY + 229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 230 231 __storm_memset_dma_mapping(bp, addr, mapping); 232} 233 234static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 235 u16 pf_id) 236{ 237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 238 pf_id); 239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 240 pf_id); 241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245} 246 247static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 248 u8 enable) 249{ 250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 251 enable); 252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 253 enable); 254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258} 259 260static inline void storm_memset_eq_data(struct bnx2x *bp, 261 struct event_ring_data *eq_data, 262 u16 pfid) 263{ 264 size_t size = sizeof(struct event_ring_data); 265 266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 267 268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 269} 270 271static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 272 u16 pfid) 273{ 274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 275 REG_WR16(bp, addr, eq_prod); 276} 277 278/* used only at init 279 * locking is done by mcp 280 */ 281static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 282{ 283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 286 PCICFG_VENDOR_ID_OFFSET); 287} 288 289static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 290{ 291 u32 val; 292 293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 296 PCICFG_VENDOR_ID_OFFSET); 297 298 return val; 299} 300 301#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 302#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 303#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 304#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 305#define DMAE_DP_DST_NONE "dst_addr [none]" 306 307static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 308 int msglvl) 309{ 310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 311 312 switch (dmae->opcode & DMAE_COMMAND_DST) { 313 case DMAE_CMD_DST_PCI: 314 if (src_type == DMAE_CMD_SRC_PCI) 315 DP(msglvl, "DMAE: opcode 0x%08x\n" 316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 317 "comp_addr [%x:%08x], comp_val 0x%08x\n", 318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 320 dmae->comp_addr_hi, dmae->comp_addr_lo, 321 dmae->comp_val); 322 else 323 DP(msglvl, "DMAE: opcode 0x%08x\n" 324 "src [%08x], len [%d*4], dst [%x:%08x]\n" 325 "comp_addr [%x:%08x], comp_val 0x%08x\n", 326 dmae->opcode, dmae->src_addr_lo >> 2, 327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 328 dmae->comp_addr_hi, dmae->comp_addr_lo, 329 dmae->comp_val); 330 break; 331 case DMAE_CMD_DST_GRC: 332 if (src_type == DMAE_CMD_SRC_PCI) 333 DP(msglvl, "DMAE: opcode 0x%08x\n" 334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 335 "comp_addr [%x:%08x], comp_val 0x%08x\n", 336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 337 dmae->len, dmae->dst_addr_lo >> 2, 338 dmae->comp_addr_hi, dmae->comp_addr_lo, 339 dmae->comp_val); 340 else 341 DP(msglvl, "DMAE: opcode 0x%08x\n" 342 "src [%08x], len [%d*4], dst [%08x]\n" 343 "comp_addr [%x:%08x], comp_val 0x%08x\n", 344 dmae->opcode, dmae->src_addr_lo >> 2, 345 dmae->len, dmae->dst_addr_lo >> 2, 346 dmae->comp_addr_hi, dmae->comp_addr_lo, 347 dmae->comp_val); 348 break; 349 default: 350 if (src_type == DMAE_CMD_SRC_PCI) 351 DP(msglvl, "DMAE: opcode 0x%08x\n" 352 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 353 "comp_addr [%x:%08x] comp_val 0x%08x\n", 354 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 355 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 356 dmae->comp_val); 357 else 358 DP(msglvl, "DMAE: opcode 0x%08x\n" 359 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 360 "comp_addr [%x:%08x] comp_val 0x%08x\n", 361 dmae->opcode, dmae->src_addr_lo >> 2, 362 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 363 dmae->comp_val); 364 break; 365 } 366 367} 368 369/* copy command into DMAE command memory and set DMAE command go */ 370void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 371{ 372 u32 cmd_offset; 373 int i; 374 375 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 376 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 377 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 378 379 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 380 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 381 } 382 REG_WR(bp, dmae_reg_go_c[idx], 1); 383} 384 385u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 386{ 387 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 388 DMAE_CMD_C_ENABLE); 389} 390 391u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 392{ 393 return opcode & ~DMAE_CMD_SRC_RESET; 394} 395 396u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 397 bool with_comp, u8 comp_type) 398{ 399 u32 opcode = 0; 400 401 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 402 (dst_type << DMAE_COMMAND_DST_SHIFT)); 403 404 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 405 406 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 407 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 408 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 409 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 410 411#ifdef __BIG_ENDIAN 412 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 413#else 414 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 415#endif 416 if (with_comp) 417 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 418 return opcode; 419} 420 421static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 422 struct dmae_command *dmae, 423 u8 src_type, u8 dst_type) 424{ 425 memset(dmae, 0, sizeof(struct dmae_command)); 426 427 /* set the opcode */ 428 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 429 true, DMAE_COMP_PCI); 430 431 /* fill in the completion parameters */ 432 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 433 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 434 dmae->comp_val = DMAE_COMP_VAL; 435} 436 437/* issue a dmae command over the init-channel and wailt for completion */ 438static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 439 struct dmae_command *dmae) 440{ 441 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 442 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 443 int rc = 0; 444 445 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 446 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 447 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 448 449 /* 450 * Lock the dmae channel. Disable BHs to prevent a dead-lock 451 * as long as this code is called both from syscall context and 452 * from ndo_set_rx_mode() flow that may be called from BH. 453 */ 454 spin_lock_bh(&bp->dmae_lock); 455 456 /* reset completion */ 457 *wb_comp = 0; 458 459 /* post the command on the channel used for initializations */ 460 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 461 462 /* wait for completion */ 463 udelay(5); 464 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 465 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 466 467 if (!cnt || 468 (bp->recovery_state != BNX2X_RECOVERY_DONE && 469 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 470 BNX2X_ERR("DMAE timeout!\n"); 471 rc = DMAE_TIMEOUT; 472 goto unlock; 473 } 474 cnt--; 475 udelay(50); 476 } 477 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 478 BNX2X_ERR("DMAE PCI error!\n"); 479 rc = DMAE_PCI_ERROR; 480 } 481 482 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 483 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 484 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 485 486unlock: 487 spin_unlock_bh(&bp->dmae_lock); 488 return rc; 489} 490 491void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 492 u32 len32) 493{ 494 struct dmae_command dmae; 495 496 if (!bp->dmae_ready) { 497 u32 *data = bnx2x_sp(bp, wb_data[0]); 498 499 DP(BNX2X_MSG_OFF, 500 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n", 501 dst_addr, len32); 502 if (CHIP_IS_E1(bp)) 503 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 504 else 505 bnx2x_init_str_wr(bp, dst_addr, data, len32); 506 return; 507 } 508 509 /* set opcode and fixed command fields */ 510 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 511 512 /* fill in addresses and len */ 513 dmae.src_addr_lo = U64_LO(dma_addr); 514 dmae.src_addr_hi = U64_HI(dma_addr); 515 dmae.dst_addr_lo = dst_addr >> 2; 516 dmae.dst_addr_hi = 0; 517 dmae.len = len32; 518 519 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 520 521 /* issue the command and wait for completion */ 522 bnx2x_issue_dmae_with_comp(bp, &dmae); 523} 524 525void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 526{ 527 struct dmae_command dmae; 528 529 if (!bp->dmae_ready) { 530 u32 *data = bnx2x_sp(bp, wb_data[0]); 531 int i; 532 533 if (CHIP_IS_E1(bp)) { 534 DP(BNX2X_MSG_OFF, 535 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n", 536 src_addr, len32); 537 for (i = 0; i < len32; i++) 538 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 539 } else 540 for (i = 0; i < len32; i++) 541 data[i] = REG_RD(bp, src_addr + i*4); 542 543 return; 544 } 545 546 /* set opcode and fixed command fields */ 547 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 548 549 /* fill in addresses and len */ 550 dmae.src_addr_lo = src_addr >> 2; 551 dmae.src_addr_hi = 0; 552 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 553 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 554 dmae.len = len32; 555 556 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 557 558 /* issue the command and wait for completion */ 559 bnx2x_issue_dmae_with_comp(bp, &dmae); 560} 561 562static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 563 u32 addr, u32 len) 564{ 565 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 566 int offset = 0; 567 568 while (len > dmae_wr_max) { 569 bnx2x_write_dmae(bp, phys_addr + offset, 570 addr + offset, dmae_wr_max); 571 offset += dmae_wr_max * 4; 572 len -= dmae_wr_max; 573 } 574 575 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 576} 577 578/* used only for slowpath so not inlined */ 579static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 580{ 581 u32 wb_write[2]; 582 583 wb_write[0] = val_hi; 584 wb_write[1] = val_lo; 585 REG_WR_DMAE(bp, reg, wb_write, 2); 586} 587 588#ifdef USE_WB_RD 589static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 590{ 591 u32 wb_data[2]; 592 593 REG_RD_DMAE(bp, reg, wb_data, 2); 594 595 return HILO_U64(wb_data[0], wb_data[1]); 596} 597#endif 598 599static int bnx2x_mc_assert(struct bnx2x *bp) 600{ 601 char last_idx; 602 int i, rc = 0; 603 u32 row0, row1, row2, row3; 604 605 /* XSTORM */ 606 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 607 XSTORM_ASSERT_LIST_INDEX_OFFSET); 608 if (last_idx) 609 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 610 611 /* print the asserts */ 612 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 613 614 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 615 XSTORM_ASSERT_LIST_OFFSET(i)); 616 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 617 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 618 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 619 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 620 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 621 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 622 623 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 624 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 625 " 0x%08x 0x%08x 0x%08x\n", 626 i, row3, row2, row1, row0); 627 rc++; 628 } else { 629 break; 630 } 631 } 632 633 /* TSTORM */ 634 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 635 TSTORM_ASSERT_LIST_INDEX_OFFSET); 636 if (last_idx) 637 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 638 639 /* print the asserts */ 640 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 641 642 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 643 TSTORM_ASSERT_LIST_OFFSET(i)); 644 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 645 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 646 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 647 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 648 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 649 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 650 651 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 652 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 653 " 0x%08x 0x%08x 0x%08x\n", 654 i, row3, row2, row1, row0); 655 rc++; 656 } else { 657 break; 658 } 659 } 660 661 /* CSTORM */ 662 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 663 CSTORM_ASSERT_LIST_INDEX_OFFSET); 664 if (last_idx) 665 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 666 667 /* print the asserts */ 668 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 669 670 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 671 CSTORM_ASSERT_LIST_OFFSET(i)); 672 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 673 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 674 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 675 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 676 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 677 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 678 679 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 680 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 681 " 0x%08x 0x%08x 0x%08x\n", 682 i, row3, row2, row1, row0); 683 rc++; 684 } else { 685 break; 686 } 687 } 688 689 /* USTORM */ 690 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 691 USTORM_ASSERT_LIST_INDEX_OFFSET); 692 if (last_idx) 693 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 694 695 /* print the asserts */ 696 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 697 698 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 699 USTORM_ASSERT_LIST_OFFSET(i)); 700 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 701 USTORM_ASSERT_LIST_OFFSET(i) + 4); 702 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 703 USTORM_ASSERT_LIST_OFFSET(i) + 8); 704 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 705 USTORM_ASSERT_LIST_OFFSET(i) + 12); 706 707 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 708 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 709 " 0x%08x 0x%08x 0x%08x\n", 710 i, row3, row2, row1, row0); 711 rc++; 712 } else { 713 break; 714 } 715 } 716 717 return rc; 718} 719 720void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 721{ 722 u32 addr, val; 723 u32 mark, offset; 724 __be32 data[9]; 725 int word; 726 u32 trace_shmem_base; 727 if (BP_NOMCP(bp)) { 728 BNX2X_ERR("NO MCP - can not dump\n"); 729 return; 730 } 731 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 732 (bp->common.bc_ver & 0xff0000) >> 16, 733 (bp->common.bc_ver & 0xff00) >> 8, 734 (bp->common.bc_ver & 0xff)); 735 736 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 737 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 738 printk("%s" "MCP PC at 0x%x\n", lvl, val); 739 740 if (BP_PATH(bp) == 0) 741 trace_shmem_base = bp->common.shmem_base; 742 else 743 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 744 addr = trace_shmem_base - 0x0800 + 4; 745 mark = REG_RD(bp, addr); 746 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 747 + ((mark + 0x3) & ~0x3) - 0x08000000; 748 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 749 750 printk("%s", lvl); 751 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 752 for (word = 0; word < 8; word++) 753 data[word] = htonl(REG_RD(bp, offset + 4*word)); 754 data[8] = 0x0; 755 pr_cont("%s", (char *)data); 756 } 757 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 758 for (word = 0; word < 8; word++) 759 data[word] = htonl(REG_RD(bp, offset + 4*word)); 760 data[8] = 0x0; 761 pr_cont("%s", (char *)data); 762 } 763 printk("%s" "end of fw dump\n", lvl); 764} 765 766static inline void bnx2x_fw_dump(struct bnx2x *bp) 767{ 768 bnx2x_fw_dump_lvl(bp, KERN_ERR); 769} 770 771void bnx2x_panic_dump(struct bnx2x *bp) 772{ 773 int i; 774 u16 j; 775 struct hc_sp_status_block_data sp_sb_data; 776 int func = BP_FUNC(bp); 777#ifdef BNX2X_STOP_ON_ERROR 778 u16 start = 0, end = 0; 779 u8 cos; 780#endif 781 782 bp->stats_state = STATS_STATE_DISABLED; 783 bp->eth_stats.unrecoverable_error++; 784 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 785 786 BNX2X_ERR("begin crash dump -----------------\n"); 787 788 /* Indices */ 789 /* Common */ 790 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 791 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 792 bp->def_idx, bp->def_att_idx, bp->attn_state, 793 bp->spq_prod_idx, bp->stats_counter); 794 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 795 bp->def_status_blk->atten_status_block.attn_bits, 796 bp->def_status_blk->atten_status_block.attn_bits_ack, 797 bp->def_status_blk->atten_status_block.status_block_id, 798 bp->def_status_blk->atten_status_block.attn_bits_index); 799 BNX2X_ERR(" def ("); 800 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 801 pr_cont("0x%x%s", 802 bp->def_status_blk->sp_sb.index_values[i], 803 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 804 805 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 806 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 807 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 808 i*sizeof(u32)); 809 810 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 811 sp_sb_data.igu_sb_id, 812 sp_sb_data.igu_seg_id, 813 sp_sb_data.p_func.pf_id, 814 sp_sb_data.p_func.vnic_id, 815 sp_sb_data.p_func.vf_id, 816 sp_sb_data.p_func.vf_valid, 817 sp_sb_data.state); 818 819 820 for_each_eth_queue(bp, i) { 821 struct bnx2x_fastpath *fp = &bp->fp[i]; 822 int loop; 823 struct hc_status_block_data_e2 sb_data_e2; 824 struct hc_status_block_data_e1x sb_data_e1x; 825 struct hc_status_block_sm *hc_sm_p = 826 CHIP_IS_E1x(bp) ? 827 sb_data_e1x.common.state_machine : 828 sb_data_e2.common.state_machine; 829 struct hc_index_data *hc_index_p = 830 CHIP_IS_E1x(bp) ? 831 sb_data_e1x.index_data : 832 sb_data_e2.index_data; 833 u8 data_size, cos; 834 u32 *sb_data_p; 835 struct bnx2x_fp_txdata txdata; 836 837 /* Rx */ 838 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 839 " rx_comp_prod(0x%x)" 840 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 841 i, fp->rx_bd_prod, fp->rx_bd_cons, 842 fp->rx_comp_prod, 843 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 844 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 845 " fp_hc_idx(0x%x)\n", 846 fp->rx_sge_prod, fp->last_max_sge, 847 le16_to_cpu(fp->fp_hc_idx)); 848 849 /* Tx */ 850 for_each_cos_in_tx_queue(fp, cos) 851 { 852 txdata = fp->txdata[cos]; 853 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 854 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 855 " *tx_cons_sb(0x%x)\n", 856 i, txdata.tx_pkt_prod, 857 txdata.tx_pkt_cons, txdata.tx_bd_prod, 858 txdata.tx_bd_cons, 859 le16_to_cpu(*txdata.tx_cons_sb)); 860 } 861 862 loop = CHIP_IS_E1x(bp) ? 863 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 864 865 /* host sb data */ 866 867#ifdef BCM_CNIC 868 if (IS_FCOE_FP(fp)) 869 continue; 870#endif 871 BNX2X_ERR(" run indexes ("); 872 for (j = 0; j < HC_SB_MAX_SM; j++) 873 pr_cont("0x%x%s", 874 fp->sb_running_index[j], 875 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 876 877 BNX2X_ERR(" indexes ("); 878 for (j = 0; j < loop; j++) 879 pr_cont("0x%x%s", 880 fp->sb_index_values[j], 881 (j == loop - 1) ? ")" : " "); 882 /* fw sb data */ 883 data_size = CHIP_IS_E1x(bp) ? 884 sizeof(struct hc_status_block_data_e1x) : 885 sizeof(struct hc_status_block_data_e2); 886 data_size /= sizeof(u32); 887 sb_data_p = CHIP_IS_E1x(bp) ? 888 (u32 *)&sb_data_e1x : 889 (u32 *)&sb_data_e2; 890 /* copy sb data in here */ 891 for (j = 0; j < data_size; j++) 892 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 893 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 894 j * sizeof(u32)); 895 896 if (!CHIP_IS_E1x(bp)) { 897 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 898 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 899 "state(0x%x)\n", 900 sb_data_e2.common.p_func.pf_id, 901 sb_data_e2.common.p_func.vf_id, 902 sb_data_e2.common.p_func.vf_valid, 903 sb_data_e2.common.p_func.vnic_id, 904 sb_data_e2.common.same_igu_sb_1b, 905 sb_data_e2.common.state); 906 } else { 907 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 908 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 909 "state(0x%x)\n", 910 sb_data_e1x.common.p_func.pf_id, 911 sb_data_e1x.common.p_func.vf_id, 912 sb_data_e1x.common.p_func.vf_valid, 913 sb_data_e1x.common.p_func.vnic_id, 914 sb_data_e1x.common.same_igu_sb_1b, 915 sb_data_e1x.common.state); 916 } 917 918 /* SB_SMs data */ 919 for (j = 0; j < HC_SB_MAX_SM; j++) { 920 pr_cont("SM[%d] __flags (0x%x) " 921 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 922 "time_to_expire (0x%x) " 923 "timer_value(0x%x)\n", j, 924 hc_sm_p[j].__flags, 925 hc_sm_p[j].igu_sb_id, 926 hc_sm_p[j].igu_seg_id, 927 hc_sm_p[j].time_to_expire, 928 hc_sm_p[j].timer_value); 929 } 930 931 /* Indecies data */ 932 for (j = 0; j < loop; j++) { 933 pr_cont("INDEX[%d] flags (0x%x) " 934 "timeout (0x%x)\n", j, 935 hc_index_p[j].flags, 936 hc_index_p[j].timeout); 937 } 938 } 939 940#ifdef BNX2X_STOP_ON_ERROR 941 /* Rings */ 942 /* Rx */ 943 for_each_rx_queue(bp, i) { 944 struct bnx2x_fastpath *fp = &bp->fp[i]; 945 946 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 947 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 948 for (j = start; j != end; j = RX_BD(j + 1)) { 949 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 950 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 951 952 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 953 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 954 } 955 956 start = RX_SGE(fp->rx_sge_prod); 957 end = RX_SGE(fp->last_max_sge); 958 for (j = start; j != end; j = RX_SGE(j + 1)) { 959 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 960 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 961 962 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 963 i, j, rx_sge[1], rx_sge[0], sw_page->page); 964 } 965 966 start = RCQ_BD(fp->rx_comp_cons - 10); 967 end = RCQ_BD(fp->rx_comp_cons + 503); 968 for (j = start; j != end; j = RCQ_BD(j + 1)) { 969 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 970 971 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 972 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 973 } 974 } 975 976 /* Tx */ 977 for_each_tx_queue(bp, i) { 978 struct bnx2x_fastpath *fp = &bp->fp[i]; 979 for_each_cos_in_tx_queue(fp, cos) { 980 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 981 982 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 983 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 984 for (j = start; j != end; j = TX_BD(j + 1)) { 985 struct sw_tx_bd *sw_bd = 986 &txdata->tx_buf_ring[j]; 987 988 BNX2X_ERR("fp%d: txdata %d, " 989 "packet[%x]=[%p,%x]\n", 990 i, cos, j, sw_bd->skb, 991 sw_bd->first_bd); 992 } 993 994 start = TX_BD(txdata->tx_bd_cons - 10); 995 end = TX_BD(txdata->tx_bd_cons + 254); 996 for (j = start; j != end; j = TX_BD(j + 1)) { 997 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 998 999 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 1000 "[%x:%x:%x:%x]\n", 1001 i, cos, j, tx_bd[0], tx_bd[1], 1002 tx_bd[2], tx_bd[3]); 1003 } 1004 } 1005 } 1006#endif 1007 bnx2x_fw_dump(bp); 1008 bnx2x_mc_assert(bp); 1009 BNX2X_ERR("end crash dump -----------------\n"); 1010} 1011 1012/* 1013 * FLR Support for E2 1014 * 1015 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1016 * initialization. 1017 */ 1018#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1019#define FLR_WAIT_INTERVAL 50 /* usec */ 1020#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1021 1022struct pbf_pN_buf_regs { 1023 int pN; 1024 u32 init_crd; 1025 u32 crd; 1026 u32 crd_freed; 1027}; 1028 1029struct pbf_pN_cmd_regs { 1030 int pN; 1031 u32 lines_occup; 1032 u32 lines_freed; 1033}; 1034 1035static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1036 struct pbf_pN_buf_regs *regs, 1037 u32 poll_count) 1038{ 1039 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1040 u32 cur_cnt = poll_count; 1041 1042 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1043 crd = crd_start = REG_RD(bp, regs->crd); 1044 init_crd = REG_RD(bp, regs->init_crd); 1045 1046 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1047 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1048 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1049 1050 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1051 (init_crd - crd_start))) { 1052 if (cur_cnt--) { 1053 udelay(FLR_WAIT_INTERVAL); 1054 crd = REG_RD(bp, regs->crd); 1055 crd_freed = REG_RD(bp, regs->crd_freed); 1056 } else { 1057 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1058 regs->pN); 1059 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1060 regs->pN, crd); 1061 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1062 regs->pN, crd_freed); 1063 break; 1064 } 1065 } 1066 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1067 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1068} 1069 1070static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1071 struct pbf_pN_cmd_regs *regs, 1072 u32 poll_count) 1073{ 1074 u32 occup, to_free, freed, freed_start; 1075 u32 cur_cnt = poll_count; 1076 1077 occup = to_free = REG_RD(bp, regs->lines_occup); 1078 freed = freed_start = REG_RD(bp, regs->lines_freed); 1079 1080 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1081 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1082 1083 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1084 if (cur_cnt--) { 1085 udelay(FLR_WAIT_INTERVAL); 1086 occup = REG_RD(bp, regs->lines_occup); 1087 freed = REG_RD(bp, regs->lines_freed); 1088 } else { 1089 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1090 regs->pN); 1091 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1092 regs->pN, occup); 1093 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1094 regs->pN, freed); 1095 break; 1096 } 1097 } 1098 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1099 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1100} 1101 1102static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1103 u32 expected, u32 poll_count) 1104{ 1105 u32 cur_cnt = poll_count; 1106 u32 val; 1107 1108 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1109 udelay(FLR_WAIT_INTERVAL); 1110 1111 return val; 1112} 1113 1114static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1115 char *msg, u32 poll_cnt) 1116{ 1117 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1118 if (val != 0) { 1119 BNX2X_ERR("%s usage count=%d\n", msg, val); 1120 return 1; 1121 } 1122 return 0; 1123} 1124 1125static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1126{ 1127 /* adjust polling timeout */ 1128 if (CHIP_REV_IS_EMUL(bp)) 1129 return FLR_POLL_CNT * 2000; 1130 1131 if (CHIP_REV_IS_FPGA(bp)) 1132 return FLR_POLL_CNT * 120; 1133 1134 return FLR_POLL_CNT; 1135} 1136 1137static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1138{ 1139 struct pbf_pN_cmd_regs cmd_regs[] = { 1140 {0, (CHIP_IS_E3B0(bp)) ? 1141 PBF_REG_TQ_OCCUPANCY_Q0 : 1142 PBF_REG_P0_TQ_OCCUPANCY, 1143 (CHIP_IS_E3B0(bp)) ? 1144 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1145 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1146 {1, (CHIP_IS_E3B0(bp)) ? 1147 PBF_REG_TQ_OCCUPANCY_Q1 : 1148 PBF_REG_P1_TQ_OCCUPANCY, 1149 (CHIP_IS_E3B0(bp)) ? 1150 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1151 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1152 {4, (CHIP_IS_E3B0(bp)) ? 1153 PBF_REG_TQ_OCCUPANCY_LB_Q : 1154 PBF_REG_P4_TQ_OCCUPANCY, 1155 (CHIP_IS_E3B0(bp)) ? 1156 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1157 PBF_REG_P4_TQ_LINES_FREED_CNT} 1158 }; 1159 1160 struct pbf_pN_buf_regs buf_regs[] = { 1161 {0, (CHIP_IS_E3B0(bp)) ? 1162 PBF_REG_INIT_CRD_Q0 : 1163 PBF_REG_P0_INIT_CRD , 1164 (CHIP_IS_E3B0(bp)) ? 1165 PBF_REG_CREDIT_Q0 : 1166 PBF_REG_P0_CREDIT, 1167 (CHIP_IS_E3B0(bp)) ? 1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1169 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1170 {1, (CHIP_IS_E3B0(bp)) ? 1171 PBF_REG_INIT_CRD_Q1 : 1172 PBF_REG_P1_INIT_CRD, 1173 (CHIP_IS_E3B0(bp)) ? 1174 PBF_REG_CREDIT_Q1 : 1175 PBF_REG_P1_CREDIT, 1176 (CHIP_IS_E3B0(bp)) ? 1177 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1178 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1179 {4, (CHIP_IS_E3B0(bp)) ? 1180 PBF_REG_INIT_CRD_LB_Q : 1181 PBF_REG_P4_INIT_CRD, 1182 (CHIP_IS_E3B0(bp)) ? 1183 PBF_REG_CREDIT_LB_Q : 1184 PBF_REG_P4_CREDIT, 1185 (CHIP_IS_E3B0(bp)) ? 1186 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1187 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1188 }; 1189 1190 int i; 1191 1192 /* Verify the command queues are flushed P0, P1, P4 */ 1193 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1194 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1195 1196 1197 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1198 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1199 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1200} 1201 1202#define OP_GEN_PARAM(param) \ 1203 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1204 1205#define OP_GEN_TYPE(type) \ 1206 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1207 1208#define OP_GEN_AGG_VECT(index) \ 1209 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1210 1211 1212static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1213 u32 poll_cnt) 1214{ 1215 struct sdm_op_gen op_gen = {0}; 1216 1217 u32 comp_addr = BAR_CSTRORM_INTMEM + 1218 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1219 int ret = 0; 1220 1221 if (REG_RD(bp, comp_addr)) { 1222 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1223 return 1; 1224 } 1225 1226 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1227 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1228 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1229 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1230 1231 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1232 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1233 1234 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1235 BNX2X_ERR("FW final cleanup did not succeed\n"); 1236 ret = 1; 1237 } 1238 /* Zero completion for nxt FLR */ 1239 REG_WR(bp, comp_addr, 0); 1240 1241 return ret; 1242} 1243 1244static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1245{ 1246 int pos; 1247 u16 status; 1248 1249 pos = pci_pcie_cap(dev); 1250 if (!pos) 1251 return false; 1252 1253 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1254 return status & PCI_EXP_DEVSTA_TRPND; 1255} 1256 1257/* PF FLR specific routines 1258*/ 1259static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1260{ 1261 1262 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1263 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1264 CFC_REG_NUM_LCIDS_INSIDE_PF, 1265 "CFC PF usage counter timed out", 1266 poll_cnt)) 1267 return 1; 1268 1269 1270 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1271 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1272 DORQ_REG_PF_USAGE_CNT, 1273 "DQ PF usage counter timed out", 1274 poll_cnt)) 1275 return 1; 1276 1277 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1278 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1279 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1280 "QM PF usage counter timed out", 1281 poll_cnt)) 1282 return 1; 1283 1284 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1285 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1286 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1287 "Timers VNIC usage counter timed out", 1288 poll_cnt)) 1289 return 1; 1290 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1291 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1292 "Timers NUM_SCANS usage counter timed out", 1293 poll_cnt)) 1294 return 1; 1295 1296 /* Wait DMAE PF usage counter to zero */ 1297 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1298 dmae_reg_go_c[INIT_DMAE_C(bp)], 1299 "DMAE dommand register timed out", 1300 poll_cnt)) 1301 return 1; 1302 1303 return 0; 1304} 1305 1306static void bnx2x_hw_enable_status(struct bnx2x *bp) 1307{ 1308 u32 val; 1309 1310 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1311 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1312 1313 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1314 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1315 1316 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1317 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1318 1319 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1320 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1321 1322 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1323 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1324 1325 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1326 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1327 1328 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1329 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1330 1331 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1332 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1333 val); 1334} 1335 1336static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1337{ 1338 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1339 1340 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1341 1342 /* Re-enable PF target read access */ 1343 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1344 1345 /* Poll HW usage counters */ 1346 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1347 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1348 return -EBUSY; 1349 1350 /* Zero the igu 'trailing edge' and 'leading edge' */ 1351 1352 /* Send the FW cleanup command */ 1353 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1354 return -EBUSY; 1355 1356 /* ATC cleanup */ 1357 1358 /* Verify TX hw is flushed */ 1359 bnx2x_tx_hw_flushed(bp, poll_cnt); 1360 1361 /* Wait 100ms (not adjusted according to platform) */ 1362 msleep(100); 1363 1364 /* Verify no pending pci transactions */ 1365 if (bnx2x_is_pcie_pending(bp->pdev)) 1366 BNX2X_ERR("PCIE Transactions still pending\n"); 1367 1368 /* Debug */ 1369 bnx2x_hw_enable_status(bp); 1370 1371 /* 1372 * Master enable - Due to WB DMAE writes performed before this 1373 * register is re-initialized as part of the regular function init 1374 */ 1375 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1376 1377 return 0; 1378} 1379 1380static void bnx2x_hc_int_enable(struct bnx2x *bp) 1381{ 1382 int port = BP_PORT(bp); 1383 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1384 u32 val = REG_RD(bp, addr); 1385 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1386 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1387 1388 if (msix) { 1389 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1390 HC_CONFIG_0_REG_INT_LINE_EN_0); 1391 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1393 } else if (msi) { 1394 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1395 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1396 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1397 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1398 } else { 1399 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1400 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1401 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1402 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1403 1404 if (!CHIP_IS_E1(bp)) { 1405 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1406 val, port, addr); 1407 1408 REG_WR(bp, addr, val); 1409 1410 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1411 } 1412 } 1413 1414 if (CHIP_IS_E1(bp)) 1415 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1416 1417 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1418 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1419 1420 REG_WR(bp, addr, val); 1421 /* 1422 * Ensure that HC_CONFIG is written before leading/trailing edge config 1423 */ 1424 mmiowb(); 1425 barrier(); 1426 1427 if (!CHIP_IS_E1(bp)) { 1428 /* init leading/trailing edge */ 1429 if (IS_MF(bp)) { 1430 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1431 if (bp->port.pmf) 1432 /* enable nig and gpio3 attention */ 1433 val |= 0x1100; 1434 } else 1435 val = 0xffff; 1436 1437 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1438 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1439 } 1440 1441 /* Make sure that interrupts are indeed enabled from here on */ 1442 mmiowb(); 1443} 1444 1445static void bnx2x_igu_int_enable(struct bnx2x *bp) 1446{ 1447 u32 val; 1448 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1449 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1450 1451 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1452 1453 if (msix) { 1454 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1455 IGU_PF_CONF_SINGLE_ISR_EN); 1456 val |= (IGU_PF_CONF_FUNC_EN | 1457 IGU_PF_CONF_MSI_MSIX_EN | 1458 IGU_PF_CONF_ATTN_BIT_EN); 1459 } else if (msi) { 1460 val &= ~IGU_PF_CONF_INT_LINE_EN; 1461 val |= (IGU_PF_CONF_FUNC_EN | 1462 IGU_PF_CONF_MSI_MSIX_EN | 1463 IGU_PF_CONF_ATTN_BIT_EN | 1464 IGU_PF_CONF_SINGLE_ISR_EN); 1465 } else { 1466 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1467 val |= (IGU_PF_CONF_FUNC_EN | 1468 IGU_PF_CONF_INT_LINE_EN | 1469 IGU_PF_CONF_ATTN_BIT_EN | 1470 IGU_PF_CONF_SINGLE_ISR_EN); 1471 } 1472 1473 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1474 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1475 1476 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1477 1478 barrier(); 1479 1480 /* init leading/trailing edge */ 1481 if (IS_MF(bp)) { 1482 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1483 if (bp->port.pmf) 1484 /* enable nig and gpio3 attention */ 1485 val |= 0x1100; 1486 } else 1487 val = 0xffff; 1488 1489 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1490 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1491 1492 /* Make sure that interrupts are indeed enabled from here on */ 1493 mmiowb(); 1494} 1495 1496void bnx2x_int_enable(struct bnx2x *bp) 1497{ 1498 if (bp->common.int_block == INT_BLOCK_HC) 1499 bnx2x_hc_int_enable(bp); 1500 else 1501 bnx2x_igu_int_enable(bp); 1502} 1503 1504static void bnx2x_hc_int_disable(struct bnx2x *bp) 1505{ 1506 int port = BP_PORT(bp); 1507 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1508 u32 val = REG_RD(bp, addr); 1509 1510 /* 1511 * in E1 we must use only PCI configuration space to disable 1512 * MSI/MSIX capablility 1513 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1514 */ 1515 if (CHIP_IS_E1(bp)) { 1516 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1517 * Use mask register to prevent from HC sending interrupts 1518 * after we exit the function 1519 */ 1520 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1521 1522 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1523 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1524 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1525 } else 1526 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1527 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1528 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1529 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1530 1531 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1532 val, port, addr); 1533 1534 /* flush all outstanding writes */ 1535 mmiowb(); 1536 1537 REG_WR(bp, addr, val); 1538 if (REG_RD(bp, addr) != val) 1539 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1540} 1541 1542static void bnx2x_igu_int_disable(struct bnx2x *bp) 1543{ 1544 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1545 1546 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1547 IGU_PF_CONF_INT_LINE_EN | 1548 IGU_PF_CONF_ATTN_BIT_EN); 1549 1550 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1551 1552 /* flush all outstanding writes */ 1553 mmiowb(); 1554 1555 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1556 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1557 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1558} 1559 1560void bnx2x_int_disable(struct bnx2x *bp) 1561{ 1562 if (bp->common.int_block == INT_BLOCK_HC) 1563 bnx2x_hc_int_disable(bp); 1564 else 1565 bnx2x_igu_int_disable(bp); 1566} 1567 1568void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1569{ 1570 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1571 int i, offset; 1572 1573 if (disable_hw) 1574 /* prevent the HW from sending interrupts */ 1575 bnx2x_int_disable(bp); 1576 1577 /* make sure all ISRs are done */ 1578 if (msix) { 1579 synchronize_irq(bp->msix_table[0].vector); 1580 offset = 1; 1581#ifdef BCM_CNIC 1582 offset++; 1583#endif 1584 for_each_eth_queue(bp, i) 1585 synchronize_irq(bp->msix_table[offset++].vector); 1586 } else 1587 synchronize_irq(bp->pdev->irq); 1588 1589 /* make sure sp_task is not running */ 1590 cancel_delayed_work(&bp->sp_task); 1591 cancel_delayed_work(&bp->period_task); 1592 flush_workqueue(bnx2x_wq); 1593} 1594 1595/* fast path */ 1596 1597/* 1598 * General service functions 1599 */ 1600 1601/* Return true if succeeded to acquire the lock */ 1602static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1603{ 1604 u32 lock_status; 1605 u32 resource_bit = (1 << resource); 1606 int func = BP_FUNC(bp); 1607 u32 hw_lock_control_reg; 1608 1609 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1610 1611 /* Validating that the resource is within range */ 1612 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1613 DP(NETIF_MSG_HW, 1614 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1615 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1616 return false; 1617 } 1618 1619 if (func <= 5) 1620 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1621 else 1622 hw_lock_control_reg = 1623 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1624 1625 /* Try to acquire the lock */ 1626 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1627 lock_status = REG_RD(bp, hw_lock_control_reg); 1628 if (lock_status & resource_bit) 1629 return true; 1630 1631 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1632 return false; 1633} 1634 1635/** 1636 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1637 * 1638 * @bp: driver handle 1639 * 1640 * Returns the recovery leader resource id according to the engine this function 1641 * belongs to. Currently only only 2 engines is supported. 1642 */ 1643static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1644{ 1645 if (BP_PATH(bp)) 1646 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1647 else 1648 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1649} 1650 1651/** 1652 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1653 * 1654 * @bp: driver handle 1655 * 1656 * Tries to aquire a leader lock for cuurent engine. 1657 */ 1658static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1659{ 1660 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1661} 1662 1663#ifdef BCM_CNIC 1664static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1665#endif 1666 1667void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1668{ 1669 struct bnx2x *bp = fp->bp; 1670 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1671 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1672 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1673 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1674 1675 DP(BNX2X_MSG_SP, 1676 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1677 fp->index, cid, command, bp->state, 1678 rr_cqe->ramrod_cqe.ramrod_type); 1679 1680 switch (command) { 1681 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1682 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1683 drv_cmd = BNX2X_Q_CMD_UPDATE; 1684 break; 1685 1686 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1687 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1688 drv_cmd = BNX2X_Q_CMD_SETUP; 1689 break; 1690 1691 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1692 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1693 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1694 break; 1695 1696 case (RAMROD_CMD_ID_ETH_HALT): 1697 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1698 drv_cmd = BNX2X_Q_CMD_HALT; 1699 break; 1700 1701 case (RAMROD_CMD_ID_ETH_TERMINATE): 1702 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1703 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1704 break; 1705 1706 case (RAMROD_CMD_ID_ETH_EMPTY): 1707 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1708 drv_cmd = BNX2X_Q_CMD_EMPTY; 1709 break; 1710 1711 default: 1712 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1713 command, fp->index); 1714 return; 1715 } 1716 1717 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1718 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1719 /* q_obj->complete_cmd() failure means that this was 1720 * an unexpected completion. 1721 * 1722 * In this case we don't want to increase the bp->spq_left 1723 * because apparently we haven't sent this command the first 1724 * place. 1725 */ 1726#ifdef BNX2X_STOP_ON_ERROR 1727 bnx2x_panic(); 1728#else 1729 return; 1730#endif 1731 1732 smp_mb__before_atomic_inc(); 1733 atomic_inc(&bp->cq_spq_left); 1734 /* push the change in bp->spq_left and towards the memory */ 1735 smp_mb__after_atomic_inc(); 1736 1737 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1738 1739 return; 1740} 1741 1742void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1743 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1744{ 1745 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1746 1747 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1748 start); 1749} 1750 1751irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1752{ 1753 struct bnx2x *bp = netdev_priv(dev_instance); 1754 u16 status = bnx2x_ack_int(bp); 1755 u16 mask; 1756 int i; 1757 u8 cos; 1758 1759 /* Return here if interrupt is shared and it's not for us */ 1760 if (unlikely(status == 0)) { 1761 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1762 return IRQ_NONE; 1763 } 1764 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1765 1766#ifdef BNX2X_STOP_ON_ERROR 1767 if (unlikely(bp->panic)) 1768 return IRQ_HANDLED; 1769#endif 1770 1771 for_each_eth_queue(bp, i) { 1772 struct bnx2x_fastpath *fp = &bp->fp[i]; 1773 1774 mask = 0x2 << (fp->index + CNIC_PRESENT); 1775 if (status & mask) { 1776 /* Handle Rx or Tx according to SB id */ 1777 prefetch(fp->rx_cons_sb); 1778 for_each_cos_in_tx_queue(fp, cos) 1779 prefetch(fp->txdata[cos].tx_cons_sb); 1780 prefetch(&fp->sb_running_index[SM_RX_ID]); 1781 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1782 status &= ~mask; 1783 } 1784 } 1785 1786#ifdef BCM_CNIC 1787 mask = 0x2; 1788 if (status & (mask | 0x1)) { 1789 struct cnic_ops *c_ops = NULL; 1790 1791 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1792 rcu_read_lock(); 1793 c_ops = rcu_dereference(bp->cnic_ops); 1794 if (c_ops) 1795 c_ops->cnic_handler(bp->cnic_data, NULL); 1796 rcu_read_unlock(); 1797 } 1798 1799 status &= ~mask; 1800 } 1801#endif 1802 1803 if (unlikely(status & 0x1)) { 1804 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1805 1806 status &= ~0x1; 1807 if (!status) 1808 return IRQ_HANDLED; 1809 } 1810 1811 if (unlikely(status)) 1812 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1813 status); 1814 1815 return IRQ_HANDLED; 1816} 1817 1818/* Link */ 1819 1820/* 1821 * General service functions 1822 */ 1823 1824int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1825{ 1826 u32 lock_status; 1827 u32 resource_bit = (1 << resource); 1828 int func = BP_FUNC(bp); 1829 u32 hw_lock_control_reg; 1830 int cnt; 1831 1832 /* Validating that the resource is within range */ 1833 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1834 DP(NETIF_MSG_HW, 1835 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1836 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1837 return -EINVAL; 1838 } 1839 1840 if (func <= 5) { 1841 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1842 } else { 1843 hw_lock_control_reg = 1844 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1845 } 1846 1847 /* Validating that the resource is not already taken */ 1848 lock_status = REG_RD(bp, hw_lock_control_reg); 1849 if (lock_status & resource_bit) { 1850 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1851 lock_status, resource_bit); 1852 return -EEXIST; 1853 } 1854 1855 /* Try for 5 second every 5ms */ 1856 for (cnt = 0; cnt < 1000; cnt++) { 1857 /* Try to acquire the lock */ 1858 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1859 lock_status = REG_RD(bp, hw_lock_control_reg); 1860 if (lock_status & resource_bit) 1861 return 0; 1862 1863 msleep(5); 1864 } 1865 DP(NETIF_MSG_HW, "Timeout\n"); 1866 return -EAGAIN; 1867} 1868 1869int bnx2x_release_leader_lock(struct bnx2x *bp) 1870{ 1871 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1872} 1873 1874int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1875{ 1876 u32 lock_status; 1877 u32 resource_bit = (1 << resource); 1878 int func = BP_FUNC(bp); 1879 u32 hw_lock_control_reg; 1880 1881 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1882 1883 /* Validating that the resource is within range */ 1884 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1885 DP(NETIF_MSG_HW, 1886 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1887 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1888 return -EINVAL; 1889 } 1890 1891 if (func <= 5) { 1892 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1893 } else { 1894 hw_lock_control_reg = 1895 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1896 } 1897 1898 /* Validating that the resource is currently taken */ 1899 lock_status = REG_RD(bp, hw_lock_control_reg); 1900 if (!(lock_status & resource_bit)) { 1901 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1902 lock_status, resource_bit); 1903 return -EFAULT; 1904 } 1905 1906 REG_WR(bp, hw_lock_control_reg, resource_bit); 1907 return 0; 1908} 1909 1910 1911int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1912{ 1913 /* The GPIO should be swapped if swap register is set and active */ 1914 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1915 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1916 int gpio_shift = gpio_num + 1917 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1918 u32 gpio_mask = (1 << gpio_shift); 1919 u32 gpio_reg; 1920 int value; 1921 1922 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1923 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1924 return -EINVAL; 1925 } 1926 1927 /* read GPIO value */ 1928 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1929 1930 /* get the requested pin value */ 1931 if ((gpio_reg & gpio_mask) == gpio_mask) 1932 value = 1; 1933 else 1934 value = 0; 1935 1936 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1937 1938 return value; 1939} 1940 1941int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1942{ 1943 /* The GPIO should be swapped if swap register is set and active */ 1944 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1945 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1946 int gpio_shift = gpio_num + 1947 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1948 u32 gpio_mask = (1 << gpio_shift); 1949 u32 gpio_reg; 1950 1951 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1952 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1953 return -EINVAL; 1954 } 1955 1956 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1957 /* read GPIO and mask except the float bits */ 1958 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1959 1960 switch (mode) { 1961 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1963 gpio_num, gpio_shift); 1964 /* clear FLOAT and set CLR */ 1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1966 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1967 break; 1968 1969 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1971 gpio_num, gpio_shift); 1972 /* clear FLOAT and set SET */ 1973 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1974 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1975 break; 1976 1977 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1978 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1979 gpio_num, gpio_shift); 1980 /* set FLOAT */ 1981 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1982 break; 1983 1984 default: 1985 break; 1986 } 1987 1988 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1989 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1990 1991 return 0; 1992} 1993 1994int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1995{ 1996 u32 gpio_reg = 0; 1997 int rc = 0; 1998 1999 /* Any port swapping should be handled by caller. */ 2000 2001 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2002 /* read GPIO and mask except the float bits */ 2003 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2004 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2005 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2006 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2007 2008 switch (mode) { 2009 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2010 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2011 /* set CLR */ 2012 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2013 break; 2014 2015 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2016 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2017 /* set SET */ 2018 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2019 break; 2020 2021 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2022 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2023 /* set FLOAT */ 2024 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2025 break; 2026 2027 default: 2028 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2029 rc = -EINVAL; 2030 break; 2031 } 2032 2033 if (rc == 0) 2034 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2035 2036 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2037 2038 return rc; 2039} 2040 2041int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2042{ 2043 /* The GPIO should be swapped if swap register is set and active */ 2044 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2045 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2046 int gpio_shift = gpio_num + 2047 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2048 u32 gpio_mask = (1 << gpio_shift); 2049 u32 gpio_reg; 2050 2051 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2052 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2053 return -EINVAL; 2054 } 2055 2056 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2057 /* read GPIO int */ 2058 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2059 2060 switch (mode) { 2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2062 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2063 "output low\n", gpio_num, gpio_shift); 2064 /* clear SET and set CLR */ 2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2067 break; 2068 2069 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2070 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2071 "output high\n", gpio_num, gpio_shift); 2072 /* clear CLR and set SET */ 2073 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2074 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2075 break; 2076 2077 default: 2078 break; 2079 } 2080 2081 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2082 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2083 2084 return 0; 2085} 2086 2087static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2088{ 2089 u32 spio_mask = (1 << spio_num); 2090 u32 spio_reg; 2091 2092 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2093 (spio_num > MISC_REGISTERS_SPIO_7)) { 2094 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2095 return -EINVAL; 2096 } 2097 2098 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2099 /* read SPIO and mask except the float bits */ 2100 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2101 2102 switch (mode) { 2103 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2104 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2105 /* clear FLOAT and set CLR */ 2106 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2107 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2108 break; 2109 2110 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2111 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2112 /* clear FLOAT and set SET */ 2113 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2114 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2115 break; 2116 2117 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2118 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2119 /* set FLOAT */ 2120 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2121 break; 2122 2123 default: 2124 break; 2125 } 2126 2127 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2128 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2129 2130 return 0; 2131} 2132 2133void bnx2x_calc_fc_adv(struct bnx2x *bp) 2134{ 2135 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2136 switch (bp->link_vars.ieee_fc & 2137 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2139 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2140 ADVERTISED_Pause); 2141 break; 2142 2143 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2144 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2145 ADVERTISED_Pause); 2146 break; 2147 2148 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2149 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2150 break; 2151 2152 default: 2153 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2154 ADVERTISED_Pause); 2155 break; 2156 } 2157} 2158 2159u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2160{ 2161 if (!BP_NOMCP(bp)) { 2162 u8 rc; 2163 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2164 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2165 /* 2166 * Initialize link parameters structure variables 2167 * It is recommended to turn off RX FC for jumbo frames 2168 * for better performance 2169 */ 2170 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2171 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2172 else 2173 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2174 2175 bnx2x_acquire_phy_lock(bp); 2176 2177 if (load_mode == LOAD_DIAG) { 2178 struct link_params *lp = &bp->link_params; 2179 lp->loopback_mode = LOOPBACK_XGXS; 2180 /* do PHY loopback at 10G speed, if possible */ 2181 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2182 if (lp->speed_cap_mask[cfx_idx] & 2183 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2184 lp->req_line_speed[cfx_idx] = 2185 SPEED_10000; 2186 else 2187 lp->req_line_speed[cfx_idx] = 2188 SPEED_1000; 2189 } 2190 } 2191 2192 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2193 2194 bnx2x_release_phy_lock(bp); 2195 2196 bnx2x_calc_fc_adv(bp); 2197 2198 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2199 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2200 bnx2x_link_report(bp); 2201 } else 2202 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2203 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2204 return rc; 2205 } 2206 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2207 return -EINVAL; 2208} 2209 2210void bnx2x_link_set(struct bnx2x *bp) 2211{ 2212 if (!BP_NOMCP(bp)) { 2213 bnx2x_acquire_phy_lock(bp); 2214 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2215 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2216 bnx2x_release_phy_lock(bp); 2217 2218 bnx2x_calc_fc_adv(bp); 2219 } else 2220 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2221} 2222 2223static void bnx2x__link_reset(struct bnx2x *bp) 2224{ 2225 if (!BP_NOMCP(bp)) { 2226 bnx2x_acquire_phy_lock(bp); 2227 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2228 bnx2x_release_phy_lock(bp); 2229 } else 2230 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2231} 2232 2233u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2234{ 2235 u8 rc = 0; 2236 2237 if (!BP_NOMCP(bp)) { 2238 bnx2x_acquire_phy_lock(bp); 2239 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2240 is_serdes); 2241 bnx2x_release_phy_lock(bp); 2242 } else 2243 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2244 2245 return rc; 2246} 2247 2248static void bnx2x_init_port_minmax(struct bnx2x *bp) 2249{ 2250 u32 r_param = bp->link_vars.line_speed / 8; 2251 u32 fair_periodic_timeout_usec; 2252 u32 t_fair; 2253 2254 memset(&(bp->cmng.rs_vars), 0, 2255 sizeof(struct rate_shaping_vars_per_port)); 2256 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2257 2258 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2259 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2260 2261 /* this is the threshold below which no timer arming will occur 2262 1.25 coefficient is for the threshold to be a little bigger 2263 than the real time, to compensate for timer in-accuracy */ 2264 bp->cmng.rs_vars.rs_threshold = 2265 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2266 2267 /* resolution of fairness timer */ 2268 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2269 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2270 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2271 2272 /* this is the threshold below which we won't arm the timer anymore */ 2273 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2274 2275 /* we multiply by 1e3/8 to get bytes/msec. 2276 We don't want the credits to pass a credit 2277 of the t_fair*FAIR_MEM (algorithm resolution) */ 2278 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2279 /* since each tick is 4 usec */ 2280 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2281} 2282 2283/* Calculates the sum of vn_min_rates. 2284 It's needed for further normalizing of the min_rates. 2285 Returns: 2286 sum of vn_min_rates. 2287 or 2288 0 - if all the min_rates are 0. 2289 In the later case fainess algorithm should be deactivated. 2290 If not all min_rates are zero then those that are zeroes will be set to 1. 2291 */ 2292static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2293{ 2294 int all_zero = 1; 2295 int vn; 2296 2297 bp->vn_weight_sum = 0; 2298 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2299 u32 vn_cfg = bp->mf_config[vn]; 2300 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2301 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2302 2303 /* Skip hidden vns */ 2304 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2305 continue; 2306 2307 /* If min rate is zero - set it to 1 */ 2308 if (!vn_min_rate) 2309 vn_min_rate = DEF_MIN_RATE; 2310 else 2311 all_zero = 0; 2312 2313 bp->vn_weight_sum += vn_min_rate; 2314 } 2315 2316 /* if ETS or all min rates are zeros - disable fairness */ 2317 if (BNX2X_IS_ETS_ENABLED(bp)) { 2318 bp->cmng.flags.cmng_enables &= 2319 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2320 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2321 } else if (all_zero) { 2322 bp->cmng.flags.cmng_enables &= 2323 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2324 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2325 " fairness will be disabled\n"); 2326 } else 2327 bp->cmng.flags.cmng_enables |= 2328 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2329} 2330 2331static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2332{ 2333 struct rate_shaping_vars_per_vn m_rs_vn; 2334 struct fairness_vars_per_vn m_fair_vn; 2335 u32 vn_cfg = bp->mf_config[vn]; 2336 int func = func_by_vn(bp, vn); 2337 u16 vn_min_rate, vn_max_rate; 2338 int i; 2339 2340 /* If function is hidden - set min and max to zeroes */ 2341 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2342 vn_min_rate = 0; 2343 vn_max_rate = 0; 2344 2345 } else { 2346 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2347 2348 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2349 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2350 /* If fairness is enabled (not all min rates are zeroes) and 2351 if current min rate is zero - set it to 1. 2352 This is a requirement of the algorithm. */ 2353 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2354 vn_min_rate = DEF_MIN_RATE; 2355 2356 if (IS_MF_SI(bp)) 2357 /* maxCfg in percents of linkspeed */ 2358 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2359 else 2360 /* maxCfg is absolute in 100Mb units */ 2361 vn_max_rate = maxCfg * 100; 2362 } 2363 2364 DP(NETIF_MSG_IFUP, 2365 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2366 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2367 2368 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2369 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2370 2371 /* global vn counter - maximal Mbps for this vn */ 2372 m_rs_vn.vn_counter.rate = vn_max_rate; 2373 2374 /* quota - number of bytes transmitted in this period */ 2375 m_rs_vn.vn_counter.quota = 2376 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2377 2378 if (bp->vn_weight_sum) { 2379 /* credit for each period of the fairness algorithm: 2380 number of bytes in T_FAIR (the vn share the port rate). 2381 vn_weight_sum should not be larger than 10000, thus 2382 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2383 than zero */ 2384 m_fair_vn.vn_credit_delta = 2385 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2386 (8 * bp->vn_weight_sum))), 2387 (bp->cmng.fair_vars.fair_threshold + 2388 MIN_ABOVE_THRESH)); 2389 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2390 m_fair_vn.vn_credit_delta); 2391 } 2392 2393 /* Store it to internal memory */ 2394 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2395 REG_WR(bp, BAR_XSTRORM_INTMEM + 2396 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2397 ((u32 *)(&m_rs_vn))[i]); 2398 2399 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2400 REG_WR(bp, BAR_XSTRORM_INTMEM + 2401 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2402 ((u32 *)(&m_fair_vn))[i]); 2403} 2404 2405static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2406{ 2407 if (CHIP_REV_IS_SLOW(bp)) 2408 return CMNG_FNS_NONE; 2409 if (IS_MF(bp)) 2410 return CMNG_FNS_MINMAX; 2411 2412 return CMNG_FNS_NONE; 2413} 2414 2415void bnx2x_read_mf_cfg(struct bnx2x *bp) 2416{ 2417 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2418 2419 if (BP_NOMCP(bp)) 2420 return; /* what should be the default bvalue in this case */ 2421 2422 /* For 2 port configuration the absolute function number formula 2423 * is: 2424 * abs_func = 2 * vn + BP_PORT + BP_PATH 2425 * 2426 * and there are 4 functions per port 2427 * 2428 * For 4 port configuration it is 2429 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2430 * 2431 * and there are 2 functions per port 2432 */ 2433 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2434 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2435 2436 if (func >= E1H_FUNC_MAX) 2437 break; 2438 2439 bp->mf_config[vn] = 2440 MF_CFG_RD(bp, func_mf_config[func].config); 2441 } 2442} 2443 2444static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2445{ 2446 2447 if (cmng_type == CMNG_FNS_MINMAX) { 2448 int vn; 2449 2450 /* clear cmng_enables */ 2451 bp->cmng.flags.cmng_enables = 0; 2452 2453 /* read mf conf from shmem */ 2454 if (read_cfg) 2455 bnx2x_read_mf_cfg(bp); 2456 2457 /* Init rate shaping and fairness contexts */ 2458 bnx2x_init_port_minmax(bp); 2459 2460 /* vn_weight_sum and enable fairness if not 0 */ 2461 bnx2x_calc_vn_weight_sum(bp); 2462 2463 /* calculate and set min-max rate for each vn */ 2464 if (bp->port.pmf) 2465 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2466 bnx2x_init_vn_minmax(bp, vn); 2467 2468 /* always enable rate shaping and fairness */ 2469 bp->cmng.flags.cmng_enables |= 2470 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2471 if (!bp->vn_weight_sum) 2472 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2473 " fairness will be disabled\n"); 2474 return; 2475 } 2476 2477 /* rate shaping and fairness are disabled */ 2478 DP(NETIF_MSG_IFUP, 2479 "rate shaping and fairness are disabled\n"); 2480} 2481 2482/* This function is called upon link interrupt */ 2483static void bnx2x_link_attn(struct bnx2x *bp) 2484{ 2485 /* Make sure that we are synced with the current statistics */ 2486 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2487 2488 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2489 2490 if (bp->link_vars.link_up) { 2491 2492 /* dropless flow control */ 2493 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2494 int port = BP_PORT(bp); 2495 u32 pause_enabled = 0; 2496 2497 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2498 pause_enabled = 1; 2499 2500 REG_WR(bp, BAR_USTRORM_INTMEM + 2501 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2502 pause_enabled); 2503 } 2504 2505 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2506 struct host_port_stats *pstats; 2507 2508 pstats = bnx2x_sp(bp, port_stats); 2509 /* reset old mac stats */ 2510 memset(&(pstats->mac_stx[0]), 0, 2511 sizeof(struct mac_stx)); 2512 } 2513 if (bp->state == BNX2X_STATE_OPEN) 2514 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2515 } 2516 2517 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2518 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2519 2520 if (cmng_fns != CMNG_FNS_NONE) { 2521 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2522 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2523 } else 2524 /* rate shaping and fairness are disabled */ 2525 DP(NETIF_MSG_IFUP, 2526 "single function mode without fairness\n"); 2527 } 2528 2529 __bnx2x_link_report(bp); 2530 2531 if (IS_MF(bp)) 2532 bnx2x_link_sync_notify(bp); 2533} 2534 2535void bnx2x__link_status_update(struct bnx2x *bp) 2536{ 2537 if (bp->state != BNX2X_STATE_OPEN) 2538 return; 2539 2540 /* read updated dcb configuration */ 2541 bnx2x_dcbx_pmf_update(bp); 2542 2543 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2544 2545 if (bp->link_vars.link_up) 2546 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2547 else 2548 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2549 2550 /* indicate link status */ 2551 bnx2x_link_report(bp); 2552} 2553 2554static void bnx2x_pmf_update(struct bnx2x *bp) 2555{ 2556 int port = BP_PORT(bp); 2557 u32 val; 2558 2559 bp->port.pmf = 1; 2560 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2561 2562 /* 2563 * We need the mb() to ensure the ordering between the writing to 2564 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2565 */ 2566 smp_mb(); 2567 2568 /* queue a periodic task */ 2569 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2570 2571 bnx2x_dcbx_pmf_update(bp); 2572 2573 /* enable nig attention */ 2574 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2575 if (bp->common.int_block == INT_BLOCK_HC) { 2576 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2577 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2578 } else if (!CHIP_IS_E1x(bp)) { 2579 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2580 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2581 } 2582 2583 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2584} 2585 2586/* end of Link */ 2587 2588/* slow path */ 2589 2590/* 2591 * General service functions 2592 */ 2593 2594/* send the MCP a request, block until there is a reply */ 2595u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2596{ 2597 int mb_idx = BP_FW_MB_IDX(bp); 2598 u32 seq; 2599 u32 rc = 0; 2600 u32 cnt = 1; 2601 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2602 2603 mutex_lock(&bp->fw_mb_mutex); 2604 seq = ++bp->fw_seq; 2605 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2606 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2607 2608 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2609 (command | seq), param); 2610 2611 do { 2612 /* let the FW do it's magic ... */ 2613 msleep(delay); 2614 2615 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2616 2617 /* Give the FW up to 5 second (500*10ms) */ 2618 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2619 2620 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2621 cnt*delay, rc, seq); 2622 2623 /* is this a reply to our command? */ 2624 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2625 rc &= FW_MSG_CODE_MASK; 2626 else { 2627 /* FW BUG! */ 2628 BNX2X_ERR("FW failed to respond!\n"); 2629 bnx2x_fw_dump(bp); 2630 rc = 0; 2631 } 2632 mutex_unlock(&bp->fw_mb_mutex); 2633 2634 return rc; 2635} 2636 2637 2638void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2639{ 2640 if (CHIP_IS_E1x(bp)) { 2641 struct tstorm_eth_function_common_config tcfg = {0}; 2642 2643 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2644 } 2645 2646 /* Enable the function in the FW */ 2647 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2648 storm_memset_func_en(bp, p->func_id, 1); 2649 2650 /* spq */ 2651 if (p->func_flgs & FUNC_FLG_SPQ) { 2652 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2653 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2654 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2655 } 2656} 2657 2658/** 2659 * bnx2x_get_tx_only_flags - Return common flags 2660 * 2661 * @bp device handle 2662 * @fp queue handle 2663 * @zero_stats TRUE if statistics zeroing is needed 2664 * 2665 * Return the flags that are common for the Tx-only and not normal connections. 2666 */ 2667static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2668 struct bnx2x_fastpath *fp, 2669 bool zero_stats) 2670{ 2671 unsigned long flags = 0; 2672 2673 /* PF driver will always initialize the Queue to an ACTIVE state */ 2674 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2675 2676 /* tx only connections collect statistics (on the same index as the 2677 * parent connection). The statistics are zeroed when the parent 2678 * connection is initialized. 2679 */ 2680 2681 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2682 if (zero_stats) 2683 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2684 2685 2686 return flags; 2687} 2688 2689static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2690 struct bnx2x_fastpath *fp, 2691 bool leading) 2692{ 2693 unsigned long flags = 0; 2694 2695 /* calculate other queue flags */ 2696 if (IS_MF_SD(bp)) 2697 __set_bit(BNX2X_Q_FLG_OV, &flags); 2698 2699 if (IS_FCOE_FP(fp)) 2700 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2701 2702 if (!fp->disable_tpa) { 2703 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2704 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2705 if (fp->mode == TPA_MODE_GRO) 2706 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 2707 } 2708 2709 if (leading) { 2710 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2711 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2712 } 2713 2714 /* Always set HW VLAN stripping */ 2715 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2716 2717 2718 return flags | bnx2x_get_common_flags(bp, fp, true); 2719} 2720 2721static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2722 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2723 u8 cos) 2724{ 2725 gen_init->stat_id = bnx2x_stats_id(fp); 2726 gen_init->spcl_id = fp->cl_id; 2727 2728 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2729 if (IS_FCOE_FP(fp)) 2730 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2731 else 2732 gen_init->mtu = bp->dev->mtu; 2733 2734 gen_init->cos = cos; 2735} 2736 2737static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2738 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2739 struct bnx2x_rxq_setup_params *rxq_init) 2740{ 2741 u8 max_sge = 0; 2742 u16 sge_sz = 0; 2743 u16 tpa_agg_size = 0; 2744 2745 if (!fp->disable_tpa) { 2746 pause->sge_th_lo = SGE_TH_LO(bp); 2747 pause->sge_th_hi = SGE_TH_HI(bp); 2748 2749 /* validate SGE ring has enough to cross high threshold */ 2750 WARN_ON(bp->dropless_fc && 2751 pause->sge_th_hi + FW_PREFETCH_CNT > 2752 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2753 2754 tpa_agg_size = min_t(u32, 2755 (min_t(u32, 8, MAX_SKB_FRAGS) * 2756 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2757 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2758 SGE_PAGE_SHIFT; 2759 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2760 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2761 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2762 0xffff); 2763 } 2764 2765 /* pause - not for e1 */ 2766 if (!CHIP_IS_E1(bp)) { 2767 pause->bd_th_lo = BD_TH_LO(bp); 2768 pause->bd_th_hi = BD_TH_HI(bp); 2769 2770 pause->rcq_th_lo = RCQ_TH_LO(bp); 2771 pause->rcq_th_hi = RCQ_TH_HI(bp); 2772 /* 2773 * validate that rings have enough entries to cross 2774 * high thresholds 2775 */ 2776 WARN_ON(bp->dropless_fc && 2777 pause->bd_th_hi + FW_PREFETCH_CNT > 2778 bp->rx_ring_size); 2779 WARN_ON(bp->dropless_fc && 2780 pause->rcq_th_hi + FW_PREFETCH_CNT > 2781 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2782 2783 pause->pri_map = 1; 2784 } 2785 2786 /* rxq setup */ 2787 rxq_init->dscr_map = fp->rx_desc_mapping; 2788 rxq_init->sge_map = fp->rx_sge_mapping; 2789 rxq_init->rcq_map = fp->rx_comp_mapping; 2790 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2791 2792 /* This should be a maximum number of data bytes that may be 2793 * placed on the BD (not including paddings). 2794 */ 2795 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2796 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2797 2798 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2799 rxq_init->tpa_agg_sz = tpa_agg_size; 2800 rxq_init->sge_buf_sz = sge_sz; 2801 rxq_init->max_sges_pkt = max_sge; 2802 rxq_init->rss_engine_id = BP_FUNC(bp); 2803 rxq_init->mcast_engine_id = BP_FUNC(bp); 2804 2805 /* Maximum number or simultaneous TPA aggregation for this Queue. 2806 * 2807 * For PF Clients it should be the maximum avaliable number. 2808 * VF driver(s) may want to define it to a smaller value. 2809 */ 2810 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2811 2812 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2813 rxq_init->fw_sb_id = fp->fw_sb_id; 2814 2815 if (IS_FCOE_FP(fp)) 2816 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2817 else 2818 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2819} 2820 2821static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2822 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2823 u8 cos) 2824{ 2825 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2826 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2827 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2828 txq_init->fw_sb_id = fp->fw_sb_id; 2829 2830 /* 2831 * set the tss leading client id for TX classfication == 2832 * leading RSS client id 2833 */ 2834 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2835 2836 if (IS_FCOE_FP(fp)) { 2837 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2838 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2839 } 2840} 2841 2842static void bnx2x_pf_init(struct bnx2x *bp) 2843{ 2844 struct bnx2x_func_init_params func_init = {0}; 2845 struct event_ring_data eq_data = { {0} }; 2846 u16 flags; 2847 2848 if (!CHIP_IS_E1x(bp)) { 2849 /* reset IGU PF statistics: MSIX + ATTN */ 2850 /* PF */ 2851 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2852 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2853 (CHIP_MODE_IS_4_PORT(bp) ? 2854 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2855 /* ATTN */ 2856 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2857 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2858 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2859 (CHIP_MODE_IS_4_PORT(bp) ? 2860 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2861 } 2862 2863 /* function setup flags */ 2864 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2865 2866 /* This flag is relevant for E1x only. 2867 * E2 doesn't have a TPA configuration in a function level. 2868 */ 2869 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2870 2871 func_init.func_flgs = flags; 2872 func_init.pf_id = BP_FUNC(bp); 2873 func_init.func_id = BP_FUNC(bp); 2874 func_init.spq_map = bp->spq_mapping; 2875 func_init.spq_prod = bp->spq_prod_idx; 2876 2877 bnx2x_func_init(bp, &func_init); 2878 2879 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2880 2881 /* 2882 * Congestion management values depend on the link rate 2883 * There is no active link so initial link rate is set to 10 Gbps. 2884 * When the link comes up The congestion management values are 2885 * re-calculated according to the actual link rate. 2886 */ 2887 bp->link_vars.line_speed = SPEED_10000; 2888 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2889 2890 /* Only the PMF sets the HW */ 2891 if (bp->port.pmf) 2892 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2893 2894 /* init Event Queue */ 2895 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2896 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2897 eq_data.producer = bp->eq_prod; 2898 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2899 eq_data.sb_id = DEF_SB_ID; 2900 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2901} 2902 2903 2904static void bnx2x_e1h_disable(struct bnx2x *bp) 2905{ 2906 int port = BP_PORT(bp); 2907 2908 bnx2x_tx_disable(bp); 2909 2910 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2911} 2912 2913static void bnx2x_e1h_enable(struct bnx2x *bp) 2914{ 2915 int port = BP_PORT(bp); 2916 2917 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2918 2919 /* Tx queue should be only reenabled */ 2920 netif_tx_wake_all_queues(bp->dev); 2921 2922 /* 2923 * Should not call netif_carrier_on since it will be called if the link 2924 * is up when checking for link state 2925 */ 2926} 2927 2928#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2929 2930static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2931{ 2932 struct eth_stats_info *ether_stat = 2933 &bp->slowpath->drv_info_to_mcp.ether_stat; 2934 2935 /* leave last char as NULL */ 2936 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2937 ETH_STAT_INFO_VERSION_LEN - 1); 2938 2939 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2940 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2941 ether_stat->mac_local); 2942 2943 ether_stat->mtu_size = bp->dev->mtu; 2944 2945 if (bp->dev->features & NETIF_F_RXCSUM) 2946 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2947 if (bp->dev->features & NETIF_F_TSO) 2948 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2949 ether_stat->feature_flags |= bp->common.boot_mode; 2950 2951 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2952 2953 ether_stat->txq_size = bp->tx_ring_size; 2954 ether_stat->rxq_size = bp->rx_ring_size; 2955} 2956 2957static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2958{ 2959#ifdef BCM_CNIC 2960 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2961 struct fcoe_stats_info *fcoe_stat = 2962 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2963 2964 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2965 2966 fcoe_stat->qos_priority = 2967 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2968 2969 /* insert FCoE stats from ramrod response */ 2970 if (!NO_FCOE(bp)) { 2971 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2972 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2973 tstorm_queue_statistics; 2974 2975 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2976 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2977 xstorm_queue_statistics; 2978 2979 struct fcoe_statistics_params *fw_fcoe_stat = 2980 &bp->fw_stats_data->fcoe; 2981 2982 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2983 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2984 2985 ADD_64(fcoe_stat->rx_bytes_hi, 2986 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2987 fcoe_stat->rx_bytes_lo, 2988 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2989 2990 ADD_64(fcoe_stat->rx_bytes_hi, 2991 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2992 fcoe_stat->rx_bytes_lo, 2993 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2994 2995 ADD_64(fcoe_stat->rx_bytes_hi, 2996 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2997 fcoe_stat->rx_bytes_lo, 2998 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 2999 3000 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3001 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3002 3003 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3004 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3005 3006 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3007 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3008 3009 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3010 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3011 3012 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 3013 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3014 3015 ADD_64(fcoe_stat->tx_bytes_hi, 3016 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3017 fcoe_stat->tx_bytes_lo, 3018 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3019 3020 ADD_64(fcoe_stat->tx_bytes_hi, 3021 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3022 fcoe_stat->tx_bytes_lo, 3023 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3024 3025 ADD_64(fcoe_stat->tx_bytes_hi, 3026 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3027 fcoe_stat->tx_bytes_lo, 3028 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3029 3030 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3031 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3032 3033 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3034 fcoe_q_xstorm_stats->ucast_pkts_sent); 3035 3036 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3037 fcoe_q_xstorm_stats->bcast_pkts_sent); 3038 3039 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3040 fcoe_q_xstorm_stats->mcast_pkts_sent); 3041 } 3042 3043 /* ask L5 driver to add data to the struct */ 3044 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3045#endif 3046} 3047 3048static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3049{ 3050#ifdef BCM_CNIC 3051 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3052 struct iscsi_stats_info *iscsi_stat = 3053 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3054 3055 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3056 3057 iscsi_stat->qos_priority = 3058 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3059 3060 /* ask L5 driver to add data to the struct */ 3061 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3062#endif 3063} 3064 3065/* called due to MCP event (on pmf): 3066 * reread new bandwidth configuration 3067 * configure FW 3068 * notify others function about the change 3069 */ 3070static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3071{ 3072 if (bp->link_vars.link_up) { 3073 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3074 bnx2x_link_sync_notify(bp); 3075 } 3076 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3077} 3078 3079static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3080{ 3081 bnx2x_config_mf_bw(bp); 3082 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3083} 3084 3085static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3086{ 3087 enum drv_info_opcode op_code; 3088 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3089 3090 /* if drv_info version supported by MFW doesn't match - send NACK */ 3091 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3092 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3093 return; 3094 } 3095 3096 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3097 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3098 3099 memset(&bp->slowpath->drv_info_to_mcp, 0, 3100 sizeof(union drv_info_to_mcp)); 3101 3102 switch (op_code) { 3103 case ETH_STATS_OPCODE: 3104 bnx2x_drv_info_ether_stat(bp); 3105 break; 3106 case FCOE_STATS_OPCODE: 3107 bnx2x_drv_info_fcoe_stat(bp); 3108 break; 3109 case ISCSI_STATS_OPCODE: 3110 bnx2x_drv_info_iscsi_stat(bp); 3111 break; 3112 default: 3113 /* if op code isn't supported - send NACK */ 3114 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3115 return; 3116 } 3117 3118 /* if we got drv_info attn from MFW then these fields are defined in 3119 * shmem2 for sure 3120 */ 3121 SHMEM2_WR(bp, drv_info_host_addr_lo, 3122 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3123 SHMEM2_WR(bp, drv_info_host_addr_hi, 3124 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3125 3126 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3127} 3128 3129static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3130{ 3131 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3132 3133 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3134 3135 /* 3136 * This is the only place besides the function initialization 3137 * where the bp->flags can change so it is done without any 3138 * locks 3139 */ 3140 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3141 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 3142 bp->flags |= MF_FUNC_DIS; 3143 3144 bnx2x_e1h_disable(bp); 3145 } else { 3146 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 3147 bp->flags &= ~MF_FUNC_DIS; 3148 3149 bnx2x_e1h_enable(bp); 3150 } 3151 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3152 } 3153 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3154 bnx2x_config_mf_bw(bp); 3155 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3156 } 3157 3158 /* Report results to MCP */ 3159 if (dcc_event) 3160 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3161 else 3162 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3163} 3164 3165/* must be called under the spq lock */ 3166static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3167{ 3168 struct eth_spe *next_spe = bp->spq_prod_bd; 3169 3170 if (bp->spq_prod_bd == bp->spq_last_bd) { 3171 bp->spq_prod_bd = bp->spq; 3172 bp->spq_prod_idx = 0; 3173 DP(NETIF_MSG_TIMER, "end of spq\n"); 3174 } else { 3175 bp->spq_prod_bd++; 3176 bp->spq_prod_idx++; 3177 } 3178 return next_spe; 3179} 3180 3181/* must be called under the spq lock */ 3182static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3183{ 3184 int func = BP_FUNC(bp); 3185 3186 /* 3187 * Make sure that BD data is updated before writing the producer: 3188 * BD data is written to the memory, the producer is read from the 3189 * memory, thus we need a full memory barrier to ensure the ordering. 3190 */ 3191 mb(); 3192 3193 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3194 bp->spq_prod_idx); 3195 mmiowb(); 3196} 3197 3198/** 3199 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3200 * 3201 * @cmd: command to check 3202 * @cmd_type: command type 3203 */ 3204static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3205{ 3206 if ((cmd_type == NONE_CONNECTION_TYPE) || 3207 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3208 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3209 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3210 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3211 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3212 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3213 return true; 3214 else 3215 return false; 3216 3217} 3218 3219 3220/** 3221 * bnx2x_sp_post - place a single command on an SP ring 3222 * 3223 * @bp: driver handle 3224 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3225 * @cid: SW CID the command is related to 3226 * @data_hi: command private data address (high 32 bits) 3227 * @data_lo: command private data address (low 32 bits) 3228 * @cmd_type: command type (e.g. NONE, ETH) 3229 * 3230 * SP data is handled as if it's always an address pair, thus data fields are 3231 * not swapped to little endian in upper functions. Instead this function swaps 3232 * data as if it's two u32 fields. 3233 */ 3234int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3235 u32 data_hi, u32 data_lo, int cmd_type) 3236{ 3237 struct eth_spe *spe; 3238 u16 type; 3239 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3240 3241#ifdef BNX2X_STOP_ON_ERROR 3242 if (unlikely(bp->panic)) 3243 return -EIO; 3244#endif 3245 3246 spin_lock_bh(&bp->spq_lock); 3247 3248 if (common) { 3249 if (!atomic_read(&bp->eq_spq_left)) { 3250 BNX2X_ERR("BUG! EQ ring full!\n"); 3251 spin_unlock_bh(&bp->spq_lock); 3252 bnx2x_panic(); 3253 return -EBUSY; 3254 } 3255 } else if (!atomic_read(&bp->cq_spq_left)) { 3256 BNX2X_ERR("BUG! SPQ ring full!\n"); 3257 spin_unlock_bh(&bp->spq_lock); 3258 bnx2x_panic(); 3259 return -EBUSY; 3260 } 3261 3262 spe = bnx2x_sp_get_next(bp); 3263 3264 /* CID needs port number to be encoded int it */ 3265 spe->hdr.conn_and_cmd_data = 3266 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3267 HW_CID(bp, cid)); 3268 3269 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3270 3271 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3272 SPE_HDR_FUNCTION_ID); 3273 3274 spe->hdr.type = cpu_to_le16(type); 3275 3276 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3277 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3278 3279 /* 3280 * It's ok if the actual decrement is issued towards the memory 3281 * somewhere between the spin_lock and spin_unlock. Thus no 3282 * more explict memory barrier is needed. 3283 */ 3284 if (common) 3285 atomic_dec(&bp->eq_spq_left); 3286 else 3287 atomic_dec(&bp->cq_spq_left); 3288 3289 3290 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3291 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3292 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3293 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3294 (u32)(U64_LO(bp->spq_mapping) + 3295 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3296 HW_CID(bp, cid), data_hi, data_lo, type, 3297 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3298 3299 bnx2x_sp_prod_update(bp); 3300 spin_unlock_bh(&bp->spq_lock); 3301 return 0; 3302} 3303 3304/* acquire split MCP access lock register */ 3305static int bnx2x_acquire_alr(struct bnx2x *bp) 3306{ 3307 u32 j, val; 3308 int rc = 0; 3309 3310 might_sleep(); 3311 for (j = 0; j < 1000; j++) { 3312 val = (1UL << 31); 3313 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3314 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3315 if (val & (1L << 31)) 3316 break; 3317 3318 msleep(5); 3319 } 3320 if (!(val & (1L << 31))) { 3321 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3322 rc = -EBUSY; 3323 } 3324 3325 return rc; 3326} 3327 3328/* release split MCP access lock register */ 3329static void bnx2x_release_alr(struct bnx2x *bp) 3330{ 3331 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3332} 3333 3334#define BNX2X_DEF_SB_ATT_IDX 0x0001 3335#define BNX2X_DEF_SB_IDX 0x0002 3336 3337static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3338{ 3339 struct host_sp_status_block *def_sb = bp->def_status_blk; 3340 u16 rc = 0; 3341 3342 barrier(); /* status block is written to by the chip */ 3343 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3344 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3345 rc |= BNX2X_DEF_SB_ATT_IDX; 3346 } 3347 3348 if (bp->def_idx != def_sb->sp_sb.running_index) { 3349 bp->def_idx = def_sb->sp_sb.running_index; 3350 rc |= BNX2X_DEF_SB_IDX; 3351 } 3352 3353 /* Do not reorder: indecies reading should complete before handling */ 3354 barrier(); 3355 return rc; 3356} 3357 3358/* 3359 * slow path service functions 3360 */ 3361 3362static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3363{ 3364 int port = BP_PORT(bp); 3365 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3366 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3367 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3368 NIG_REG_MASK_INTERRUPT_PORT0; 3369 u32 aeu_mask; 3370 u32 nig_mask = 0; 3371 u32 reg_addr; 3372 3373 if (bp->attn_state & asserted) 3374 BNX2X_ERR("IGU ERROR\n"); 3375 3376 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3377 aeu_mask = REG_RD(bp, aeu_addr); 3378 3379 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3380 aeu_mask, asserted); 3381 aeu_mask &= ~(asserted & 0x3ff); 3382 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3383 3384 REG_WR(bp, aeu_addr, aeu_mask); 3385 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3386 3387 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3388 bp->attn_state |= asserted; 3389 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3390 3391 if (asserted & ATTN_HARD_WIRED_MASK) { 3392 if (asserted & ATTN_NIG_FOR_FUNC) { 3393 3394 bnx2x_acquire_phy_lock(bp); 3395 3396 /* save nig interrupt mask */ 3397 nig_mask = REG_RD(bp, nig_int_mask_addr); 3398 3399 /* If nig_mask is not set, no need to call the update 3400 * function. 3401 */ 3402 if (nig_mask) { 3403 REG_WR(bp, nig_int_mask_addr, 0); 3404 3405 bnx2x_link_attn(bp); 3406 } 3407 3408 /* handle unicore attn? */ 3409 } 3410 if (asserted & ATTN_SW_TIMER_4_FUNC) 3411 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3412 3413 if (asserted & GPIO_2_FUNC) 3414 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3415 3416 if (asserted & GPIO_3_FUNC) 3417 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3418 3419 if (asserted & GPIO_4_FUNC) 3420 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3421 3422 if (port == 0) { 3423 if (asserted & ATTN_GENERAL_ATTN_1) { 3424 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3425 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3426 } 3427 if (asserted & ATTN_GENERAL_ATTN_2) { 3428 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3429 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3430 } 3431 if (asserted & ATTN_GENERAL_ATTN_3) { 3432 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3433 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3434 } 3435 } else { 3436 if (asserted & ATTN_GENERAL_ATTN_4) { 3437 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3438 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3439 } 3440 if (asserted & ATTN_GENERAL_ATTN_5) { 3441 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3442 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3443 } 3444 if (asserted & ATTN_GENERAL_ATTN_6) { 3445 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3446 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3447 } 3448 } 3449 3450 } /* if hardwired */ 3451 3452 if (bp->common.int_block == INT_BLOCK_HC) 3453 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3454 COMMAND_REG_ATTN_BITS_SET); 3455 else 3456 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3457 3458 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3459 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3460 REG_WR(bp, reg_addr, asserted); 3461 3462 /* now set back the mask */ 3463 if (asserted & ATTN_NIG_FOR_FUNC) { 3464 REG_WR(bp, nig_int_mask_addr, nig_mask); 3465 bnx2x_release_phy_lock(bp); 3466 } 3467} 3468 3469static inline void bnx2x_fan_failure(struct bnx2x *bp) 3470{ 3471 int port = BP_PORT(bp); 3472 u32 ext_phy_config; 3473 /* mark the failure */ 3474 ext_phy_config = 3475 SHMEM_RD(bp, 3476 dev_info.port_hw_config[port].external_phy_config); 3477 3478 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3479 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3480 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3481 ext_phy_config); 3482 3483 /* log the failure */ 3484 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3485 " the driver to shutdown the card to prevent permanent" 3486 " damage. Please contact OEM Support for assistance\n"); 3487 3488 /* 3489 * Scheudle device reset (unload) 3490 * This is due to some boards consuming sufficient power when driver is 3491 * up to overheat if fan fails. 3492 */ 3493 smp_mb__before_clear_bit(); 3494 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3495 smp_mb__after_clear_bit(); 3496 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3497 3498} 3499 3500static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3501{ 3502 int port = BP_PORT(bp); 3503 int reg_offset; 3504 u32 val; 3505 3506 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3507 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3508 3509 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3510 3511 val = REG_RD(bp, reg_offset); 3512 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3513 REG_WR(bp, reg_offset, val); 3514 3515 BNX2X_ERR("SPIO5 hw attention\n"); 3516 3517 /* Fan failure attention */ 3518 bnx2x_hw_reset_phy(&bp->link_params); 3519 bnx2x_fan_failure(bp); 3520 } 3521 3522 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3523 bnx2x_acquire_phy_lock(bp); 3524 bnx2x_handle_module_detect_int(&bp->link_params); 3525 bnx2x_release_phy_lock(bp); 3526 } 3527 3528 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3529 3530 val = REG_RD(bp, reg_offset); 3531 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3532 REG_WR(bp, reg_offset, val); 3533 3534 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3535 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3536 bnx2x_panic(); 3537 } 3538} 3539 3540static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3541{ 3542 u32 val; 3543 3544 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3545 3546 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3547 BNX2X_ERR("DB hw attention 0x%x\n", val); 3548 /* DORQ discard attention */ 3549 if (val & 0x2) 3550 BNX2X_ERR("FATAL error from DORQ\n"); 3551 } 3552 3553 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3554 3555 int port = BP_PORT(bp); 3556 int reg_offset; 3557 3558 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3559 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3560 3561 val = REG_RD(bp, reg_offset); 3562 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3563 REG_WR(bp, reg_offset, val); 3564 3565 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3566 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3567 bnx2x_panic(); 3568 } 3569} 3570 3571static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3572{ 3573 u32 val; 3574 3575 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3576 3577 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3578 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3579 /* CFC error attention */ 3580 if (val & 0x2) 3581 BNX2X_ERR("FATAL error from CFC\n"); 3582 } 3583 3584 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3585 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3586 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3587 /* RQ_USDMDP_FIFO_OVERFLOW */ 3588 if (val & 0x18000) 3589 BNX2X_ERR("FATAL error from PXP\n"); 3590 3591 if (!CHIP_IS_E1x(bp)) { 3592 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3593 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3594 } 3595 } 3596 3597 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3598 3599 int port = BP_PORT(bp); 3600 int reg_offset; 3601 3602 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3603 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3604 3605 val = REG_RD(bp, reg_offset); 3606 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3607 REG_WR(bp, reg_offset, val); 3608 3609 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3610 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3611 bnx2x_panic(); 3612 } 3613} 3614 3615static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3616{ 3617 u32 val; 3618 3619 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3620 3621 if (attn & BNX2X_PMF_LINK_ASSERT) { 3622 int func = BP_FUNC(bp); 3623 3624 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3625 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3626 func_mf_config[BP_ABS_FUNC(bp)].config); 3627 val = SHMEM_RD(bp, 3628 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3629 if (val & DRV_STATUS_DCC_EVENT_MASK) 3630 bnx2x_dcc_event(bp, 3631 (val & DRV_STATUS_DCC_EVENT_MASK)); 3632 3633 if (val & DRV_STATUS_SET_MF_BW) 3634 bnx2x_set_mf_bw(bp); 3635 3636 if (val & DRV_STATUS_DRV_INFO_REQ) 3637 bnx2x_handle_drv_info_req(bp); 3638 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3639 bnx2x_pmf_update(bp); 3640 3641 if (bp->port.pmf && 3642 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3643 bp->dcbx_enabled > 0) 3644 /* start dcbx state machine */ 3645 bnx2x_dcbx_set_params(bp, 3646 BNX2X_DCBX_STATE_NEG_RECEIVED); 3647 if (bp->link_vars.periodic_flags & 3648 PERIODIC_FLAGS_LINK_EVENT) { 3649 /* sync with link */ 3650 bnx2x_acquire_phy_lock(bp); 3651 bp->link_vars.periodic_flags &= 3652 ~PERIODIC_FLAGS_LINK_EVENT; 3653 bnx2x_release_phy_lock(bp); 3654 if (IS_MF(bp)) 3655 bnx2x_link_sync_notify(bp); 3656 bnx2x_link_report(bp); 3657 } 3658 /* Always call it here: bnx2x_link_report() will 3659 * prevent the link indication duplication. 3660 */ 3661 bnx2x__link_status_update(bp); 3662 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3663 3664 BNX2X_ERR("MC assert!\n"); 3665 bnx2x_mc_assert(bp); 3666 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3667 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3668 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3669 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3670 bnx2x_panic(); 3671 3672 } else if (attn & BNX2X_MCP_ASSERT) { 3673 3674 BNX2X_ERR("MCP assert!\n"); 3675 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3676 bnx2x_fw_dump(bp); 3677 3678 } else 3679 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3680 } 3681 3682 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3683 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3684 if (attn & BNX2X_GRC_TIMEOUT) { 3685 val = CHIP_IS_E1(bp) ? 0 : 3686 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3687 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3688 } 3689 if (attn & BNX2X_GRC_RSV) { 3690 val = CHIP_IS_E1(bp) ? 0 : 3691 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3692 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3693 } 3694 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3695 } 3696} 3697 3698/* 3699 * Bits map: 3700 * 0-7 - Engine0 load counter. 3701 * 8-15 - Engine1 load counter. 3702 * 16 - Engine0 RESET_IN_PROGRESS bit. 3703 * 17 - Engine1 RESET_IN_PROGRESS bit. 3704 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3705 * on the engine 3706 * 19 - Engine1 ONE_IS_LOADED. 3707 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3708 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3709 * just the one belonging to its engine). 3710 * 3711 */ 3712#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3713 3714#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3715#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3716#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3717#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3718#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3719#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3720#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3721 3722/* 3723 * Set the GLOBAL_RESET bit. 3724 * 3725 * Should be run under rtnl lock 3726 */ 3727void bnx2x_set_reset_global(struct bnx2x *bp) 3728{ 3729 u32 val; 3730 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3731 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3732 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3733 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3734} 3735 3736/* 3737 * Clear the GLOBAL_RESET bit. 3738 * 3739 * Should be run under rtnl lock 3740 */ 3741static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3742{ 3743 u32 val; 3744 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3745 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3746 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3747 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3748} 3749 3750/* 3751 * Checks the GLOBAL_RESET bit. 3752 * 3753 * should be run under rtnl lock 3754 */ 3755static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3756{ 3757 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3758 3759 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3760 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3761} 3762 3763/* 3764 * Clear RESET_IN_PROGRESS bit for the current engine. 3765 * 3766 * Should be run under rtnl lock 3767 */ 3768static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3769{ 3770 u32 val; 3771 u32 bit = BP_PATH(bp) ? 3772 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3773 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3774 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3775 3776 /* Clear the bit */ 3777 val &= ~bit; 3778 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3779 3780 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3781} 3782 3783/* 3784 * Set RESET_IN_PROGRESS for the current engine. 3785 * 3786 * should be run under rtnl lock 3787 */ 3788void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3789{ 3790 u32 val; 3791 u32 bit = BP_PATH(bp) ? 3792 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3793 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3794 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3795 3796 /* Set the bit */ 3797 val |= bit; 3798 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3799 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3800} 3801 3802/* 3803 * Checks the RESET_IN_PROGRESS bit for the given engine. 3804 * should be run under rtnl lock 3805 */ 3806bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3807{ 3808 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3809 u32 bit = engine ? 3810 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3811 3812 /* return false if bit is set */ 3813 return (val & bit) ? false : true; 3814} 3815 3816/* 3817 * set pf load for the current pf. 3818 * 3819 * should be run under rtnl lock 3820 */ 3821void bnx2x_set_pf_load(struct bnx2x *bp) 3822{ 3823 u32 val1, val; 3824 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3825 BNX2X_PATH0_LOAD_CNT_MASK; 3826 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3827 BNX2X_PATH0_LOAD_CNT_SHIFT; 3828 3829 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3830 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3831 3832 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3833 3834 /* get the current counter value */ 3835 val1 = (val & mask) >> shift; 3836 3837 /* set bit of that PF */ 3838 val1 |= (1 << bp->pf_num); 3839 3840 /* clear the old value */ 3841 val &= ~mask; 3842 3843 /* set the new one */ 3844 val |= ((val1 << shift) & mask); 3845 3846 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3847 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3848} 3849 3850/** 3851 * bnx2x_clear_pf_load - clear pf load mark 3852 * 3853 * @bp: driver handle 3854 * 3855 * Should be run under rtnl lock. 3856 * Decrements the load counter for the current engine. Returns 3857 * whether other functions are still loaded 3858 */ 3859bool bnx2x_clear_pf_load(struct bnx2x *bp) 3860{ 3861 u32 val1, val; 3862 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3863 BNX2X_PATH0_LOAD_CNT_MASK; 3864 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3865 BNX2X_PATH0_LOAD_CNT_SHIFT; 3866 3867 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3868 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3869 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3870 3871 /* get the current counter value */ 3872 val1 = (val & mask) >> shift; 3873 3874 /* clear bit of that PF */ 3875 val1 &= ~(1 << bp->pf_num); 3876 3877 /* clear the old value */ 3878 val &= ~mask; 3879 3880 /* set the new one */ 3881 val |= ((val1 << shift) & mask); 3882 3883 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3884 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3885 return val1 != 0; 3886} 3887 3888/* 3889 * Read the load status for the current engine. 3890 * 3891 * should be run under rtnl lock 3892 */ 3893static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 3894{ 3895 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3896 BNX2X_PATH0_LOAD_CNT_MASK); 3897 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3898 BNX2X_PATH0_LOAD_CNT_SHIFT); 3899 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3900 3901 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3902 3903 val = (val & mask) >> shift; 3904 3905 DP(NETIF_MSG_HW, "load mask for engine %d = 0x%x\n", engine, val); 3906 3907 return val != 0; 3908} 3909 3910/* 3911 * Reset the load status for the current engine. 3912 */ 3913static inline void bnx2x_clear_load_status(struct bnx2x *bp) 3914{ 3915 u32 val; 3916 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3917 BNX2X_PATH0_LOAD_CNT_MASK); 3918 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3919 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3920 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3921 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3922} 3923 3924static inline void _print_next_block(int idx, const char *blk) 3925{ 3926 pr_cont("%s%s", idx ? ", " : "", blk); 3927} 3928 3929static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3930 bool print) 3931{ 3932 int i = 0; 3933 u32 cur_bit = 0; 3934 for (i = 0; sig; i++) { 3935 cur_bit = ((u32)0x1 << i); 3936 if (sig & cur_bit) { 3937 switch (cur_bit) { 3938 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3939 if (print) 3940 _print_next_block(par_num++, "BRB"); 3941 break; 3942 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3943 if (print) 3944 _print_next_block(par_num++, "PARSER"); 3945 break; 3946 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3947 if (print) 3948 _print_next_block(par_num++, "TSDM"); 3949 break; 3950 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3951 if (print) 3952 _print_next_block(par_num++, 3953 "SEARCHER"); 3954 break; 3955 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3956 if (print) 3957 _print_next_block(par_num++, "TCM"); 3958 break; 3959 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3960 if (print) 3961 _print_next_block(par_num++, "TSEMI"); 3962 break; 3963 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3964 if (print) 3965 _print_next_block(par_num++, "XPB"); 3966 break; 3967 } 3968 3969 /* Clear the bit */ 3970 sig &= ~cur_bit; 3971 } 3972 } 3973 3974 return par_num; 3975} 3976 3977static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3978 bool *global, bool print) 3979{ 3980 int i = 0; 3981 u32 cur_bit = 0; 3982 for (i = 0; sig; i++) { 3983 cur_bit = ((u32)0x1 << i); 3984 if (sig & cur_bit) { 3985 switch (cur_bit) { 3986 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3987 if (print) 3988 _print_next_block(par_num++, "PBF"); 3989 break; 3990 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3991 if (print) 3992 _print_next_block(par_num++, "QM"); 3993 break; 3994 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3995 if (print) 3996 _print_next_block(par_num++, "TM"); 3997 break; 3998 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3999 if (print) 4000 _print_next_block(par_num++, "XSDM"); 4001 break; 4002 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4003 if (print) 4004 _print_next_block(par_num++, "XCM"); 4005 break; 4006 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4007 if (print) 4008 _print_next_block(par_num++, "XSEMI"); 4009 break; 4010 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4011 if (print) 4012 _print_next_block(par_num++, 4013 "DOORBELLQ"); 4014 break; 4015 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4016 if (print) 4017 _print_next_block(par_num++, "NIG"); 4018 break; 4019 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4020 if (print) 4021 _print_next_block(par_num++, 4022 "VAUX PCI CORE"); 4023 *global = true; 4024 break; 4025 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4026 if (print) 4027 _print_next_block(par_num++, "DEBUG"); 4028 break; 4029 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4030 if (print) 4031 _print_next_block(par_num++, "USDM"); 4032 break; 4033 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4034 if (print) 4035 _print_next_block(par_num++, "UCM"); 4036 break; 4037 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4038 if (print) 4039 _print_next_block(par_num++, "USEMI"); 4040 break; 4041 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4042 if (print) 4043 _print_next_block(par_num++, "UPB"); 4044 break; 4045 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4046 if (print) 4047 _print_next_block(par_num++, "CSDM"); 4048 break; 4049 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4050 if (print) 4051 _print_next_block(par_num++, "CCM"); 4052 break; 4053 } 4054 4055 /* Clear the bit */ 4056 sig &= ~cur_bit; 4057 } 4058 } 4059 4060 return par_num; 4061} 4062 4063static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4064 bool print) 4065{ 4066 int i = 0; 4067 u32 cur_bit = 0; 4068 for (i = 0; sig; i++) { 4069 cur_bit = ((u32)0x1 << i); 4070 if (sig & cur_bit) { 4071 switch (cur_bit) { 4072 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4073 if (print) 4074 _print_next_block(par_num++, "CSEMI"); 4075 break; 4076 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4077 if (print) 4078 _print_next_block(par_num++, "PXP"); 4079 break; 4080 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4081 if (print) 4082 _print_next_block(par_num++, 4083 "PXPPCICLOCKCLIENT"); 4084 break; 4085 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4086 if (print) 4087 _print_next_block(par_num++, "CFC"); 4088 break; 4089 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4090 if (print) 4091 _print_next_block(par_num++, "CDU"); 4092 break; 4093 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4094 if (print) 4095 _print_next_block(par_num++, "DMAE"); 4096 break; 4097 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4098 if (print) 4099 _print_next_block(par_num++, "IGU"); 4100 break; 4101 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4102 if (print) 4103 _print_next_block(par_num++, "MISC"); 4104 break; 4105 } 4106 4107 /* Clear the bit */ 4108 sig &= ~cur_bit; 4109 } 4110 } 4111 4112 return par_num; 4113} 4114 4115static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4116 bool *global, bool print) 4117{ 4118 int i = 0; 4119 u32 cur_bit = 0; 4120 for (i = 0; sig; i++) { 4121 cur_bit = ((u32)0x1 << i); 4122 if (sig & cur_bit) { 4123 switch (cur_bit) { 4124 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4125 if (print) 4126 _print_next_block(par_num++, "MCP ROM"); 4127 *global = true; 4128 break; 4129 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4130 if (print) 4131 _print_next_block(par_num++, 4132 "MCP UMP RX"); 4133 *global = true; 4134 break; 4135 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4136 if (print) 4137 _print_next_block(par_num++, 4138 "MCP UMP TX"); 4139 *global = true; 4140 break; 4141 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4142 if (print) 4143 _print_next_block(par_num++, 4144 "MCP SCPAD"); 4145 *global = true; 4146 break; 4147 } 4148 4149 /* Clear the bit */ 4150 sig &= ~cur_bit; 4151 } 4152 } 4153 4154 return par_num; 4155} 4156 4157static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4158 bool print) 4159{ 4160 int i = 0; 4161 u32 cur_bit = 0; 4162 for (i = 0; sig; i++) { 4163 cur_bit = ((u32)0x1 << i); 4164 if (sig & cur_bit) { 4165 switch (cur_bit) { 4166 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4167 if (print) 4168 _print_next_block(par_num++, "PGLUE_B"); 4169 break; 4170 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4171 if (print) 4172 _print_next_block(par_num++, "ATC"); 4173 break; 4174 } 4175 4176 /* Clear the bit */ 4177 sig &= ~cur_bit; 4178 } 4179 } 4180 4181 return par_num; 4182} 4183 4184static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4185 u32 *sig) 4186{ 4187 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4188 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4189 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4190 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4191 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4192 int par_num = 0; 4193 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4194 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4195 "[4]:0x%08x\n", 4196 sig[0] & HW_PRTY_ASSERT_SET_0, 4197 sig[1] & HW_PRTY_ASSERT_SET_1, 4198 sig[2] & HW_PRTY_ASSERT_SET_2, 4199 sig[3] & HW_PRTY_ASSERT_SET_3, 4200 sig[4] & HW_PRTY_ASSERT_SET_4); 4201 if (print) 4202 netdev_err(bp->dev, 4203 "Parity errors detected in blocks: "); 4204 par_num = bnx2x_check_blocks_with_parity0( 4205 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4206 par_num = bnx2x_check_blocks_with_parity1( 4207 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4208 par_num = bnx2x_check_blocks_with_parity2( 4209 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4210 par_num = bnx2x_check_blocks_with_parity3( 4211 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4212 par_num = bnx2x_check_blocks_with_parity4( 4213 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4214 4215 if (print) 4216 pr_cont("\n"); 4217 4218 return true; 4219 } else 4220 return false; 4221} 4222 4223/** 4224 * bnx2x_chk_parity_attn - checks for parity attentions. 4225 * 4226 * @bp: driver handle 4227 * @global: true if there was a global attention 4228 * @print: show parity attention in syslog 4229 */ 4230bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4231{ 4232 struct attn_route attn = { {0} }; 4233 int port = BP_PORT(bp); 4234 4235 attn.sig[0] = REG_RD(bp, 4236 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4237 port*4); 4238 attn.sig[1] = REG_RD(bp, 4239 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4240 port*4); 4241 attn.sig[2] = REG_RD(bp, 4242 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4243 port*4); 4244 attn.sig[3] = REG_RD(bp, 4245 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4246 port*4); 4247 4248 if (!CHIP_IS_E1x(bp)) 4249 attn.sig[4] = REG_RD(bp, 4250 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4251 port*4); 4252 4253 return bnx2x_parity_attn(bp, global, print, attn.sig); 4254} 4255 4256 4257static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4258{ 4259 u32 val; 4260 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4261 4262 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4263 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4264 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4265 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4266 "ADDRESS_ERROR\n"); 4267 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4268 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4269 "INCORRECT_RCV_BEHAVIOR\n"); 4270 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4271 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4272 "WAS_ERROR_ATTN\n"); 4273 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4274 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4275 "VF_LENGTH_VIOLATION_ATTN\n"); 4276 if (val & 4277 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4278 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4279 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4280 if (val & 4281 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4282 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4283 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4284 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4285 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4286 "TCPL_ERROR_ATTN\n"); 4287 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4288 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4289 "TCPL_IN_TWO_RCBS_ATTN\n"); 4290 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4291 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4292 "CSSNOOP_FIFO_OVERFLOW\n"); 4293 } 4294 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4295 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4296 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4297 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4298 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4299 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4300 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4301 "_ATC_TCPL_TO_NOT_PEND\n"); 4302 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4303 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4304 "ATC_GPA_MULTIPLE_HITS\n"); 4305 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4306 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4307 "ATC_RCPL_TO_EMPTY_CNT\n"); 4308 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4309 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4310 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4311 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4312 "ATC_IREQ_LESS_THAN_STU\n"); 4313 } 4314 4315 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4316 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4317 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4318 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4319 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4320 } 4321 4322} 4323 4324static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4325{ 4326 struct attn_route attn, *group_mask; 4327 int port = BP_PORT(bp); 4328 int index; 4329 u32 reg_addr; 4330 u32 val; 4331 u32 aeu_mask; 4332 bool global = false; 4333 4334 /* need to take HW lock because MCP or other port might also 4335 try to handle this event */ 4336 bnx2x_acquire_alr(bp); 4337 4338 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4339#ifndef BNX2X_STOP_ON_ERROR 4340 bp->recovery_state = BNX2X_RECOVERY_INIT; 4341 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4342 /* Disable HW interrupts */ 4343 bnx2x_int_disable(bp); 4344 /* In case of parity errors don't handle attentions so that 4345 * other function would "see" parity errors. 4346 */ 4347#else 4348 bnx2x_panic(); 4349#endif 4350 bnx2x_release_alr(bp); 4351 return; 4352 } 4353 4354 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4355 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4356 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4357 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4358 if (!CHIP_IS_E1x(bp)) 4359 attn.sig[4] = 4360 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4361 else 4362 attn.sig[4] = 0; 4363 4364 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4365 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4366 4367 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4368 if (deasserted & (1 << index)) { 4369 group_mask = &bp->attn_group[index]; 4370 4371 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4372 "%08x %08x %08x\n", 4373 index, 4374 group_mask->sig[0], group_mask->sig[1], 4375 group_mask->sig[2], group_mask->sig[3], 4376 group_mask->sig[4]); 4377 4378 bnx2x_attn_int_deasserted4(bp, 4379 attn.sig[4] & group_mask->sig[4]); 4380 bnx2x_attn_int_deasserted3(bp, 4381 attn.sig[3] & group_mask->sig[3]); 4382 bnx2x_attn_int_deasserted1(bp, 4383 attn.sig[1] & group_mask->sig[1]); 4384 bnx2x_attn_int_deasserted2(bp, 4385 attn.sig[2] & group_mask->sig[2]); 4386 bnx2x_attn_int_deasserted0(bp, 4387 attn.sig[0] & group_mask->sig[0]); 4388 } 4389 } 4390 4391 bnx2x_release_alr(bp); 4392 4393 if (bp->common.int_block == INT_BLOCK_HC) 4394 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4395 COMMAND_REG_ATTN_BITS_CLR); 4396 else 4397 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4398 4399 val = ~deasserted; 4400 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4401 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4402 REG_WR(bp, reg_addr, val); 4403 4404 if (~bp->attn_state & deasserted) 4405 BNX2X_ERR("IGU ERROR\n"); 4406 4407 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4408 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4409 4410 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4411 aeu_mask = REG_RD(bp, reg_addr); 4412 4413 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4414 aeu_mask, deasserted); 4415 aeu_mask |= (deasserted & 0x3ff); 4416 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4417 4418 REG_WR(bp, reg_addr, aeu_mask); 4419 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4420 4421 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4422 bp->attn_state &= ~deasserted; 4423 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4424} 4425 4426static void bnx2x_attn_int(struct bnx2x *bp) 4427{ 4428 /* read local copy of bits */ 4429 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4430 attn_bits); 4431 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4432 attn_bits_ack); 4433 u32 attn_state = bp->attn_state; 4434 4435 /* look for changed bits */ 4436 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4437 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4438 4439 DP(NETIF_MSG_HW, 4440 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4441 attn_bits, attn_ack, asserted, deasserted); 4442 4443 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4444 BNX2X_ERR("BAD attention state\n"); 4445 4446 /* handle bits that were raised */ 4447 if (asserted) 4448 bnx2x_attn_int_asserted(bp, asserted); 4449 4450 if (deasserted) 4451 bnx2x_attn_int_deasserted(bp, deasserted); 4452} 4453 4454void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4455 u16 index, u8 op, u8 update) 4456{ 4457 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4458 4459 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4460 igu_addr); 4461} 4462 4463static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4464{ 4465 /* No memory barriers */ 4466 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4467 mmiowb(); /* keep prod updates ordered */ 4468} 4469 4470#ifdef BCM_CNIC 4471static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4472 union event_ring_elem *elem) 4473{ 4474 u8 err = elem->message.error; 4475 4476 if (!bp->cnic_eth_dev.starting_cid || 4477 (cid < bp->cnic_eth_dev.starting_cid && 4478 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4479 return 1; 4480 4481 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4482 4483 if (unlikely(err)) { 4484 4485 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4486 cid); 4487 bnx2x_panic_dump(bp); 4488 } 4489 bnx2x_cnic_cfc_comp(bp, cid, err); 4490 return 0; 4491} 4492#endif 4493 4494static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4495{ 4496 struct bnx2x_mcast_ramrod_params rparam; 4497 int rc; 4498 4499 memset(&rparam, 0, sizeof(rparam)); 4500 4501 rparam.mcast_obj = &bp->mcast_obj; 4502 4503 netif_addr_lock_bh(bp->dev); 4504 4505 /* Clear pending state for the last command */ 4506 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4507 4508 /* If there are pending mcast commands - send them */ 4509 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4510 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4511 if (rc < 0) 4512 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4513 rc); 4514 } 4515 4516 netif_addr_unlock_bh(bp->dev); 4517} 4518 4519static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4520 union event_ring_elem *elem) 4521{ 4522 unsigned long ramrod_flags = 0; 4523 int rc = 0; 4524 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4525 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4526 4527 /* Always push next commands out, don't wait here */ 4528 __set_bit(RAMROD_CONT, &ramrod_flags); 4529 4530 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4531 case BNX2X_FILTER_MAC_PENDING: 4532#ifdef BCM_CNIC 4533 if (cid == BNX2X_ISCSI_ETH_CID) 4534 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4535 else 4536#endif 4537 vlan_mac_obj = &bp->fp[cid].mac_obj; 4538 4539 break; 4540 case BNX2X_FILTER_MCAST_PENDING: 4541 /* This is only relevant for 57710 where multicast MACs are 4542 * configured as unicast MACs using the same ramrod. 4543 */ 4544 bnx2x_handle_mcast_eqe(bp); 4545 return; 4546 default: 4547 BNX2X_ERR("Unsupported classification command: %d\n", 4548 elem->message.data.eth_event.echo); 4549 return; 4550 } 4551 4552 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4553 4554 if (rc < 0) 4555 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4556 else if (rc > 0) 4557 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4558 4559} 4560 4561#ifdef BCM_CNIC 4562static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4563#endif 4564 4565static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4566{ 4567 netif_addr_lock_bh(bp->dev); 4568 4569 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4570 4571 /* Send rx_mode command again if was requested */ 4572 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4573 bnx2x_set_storm_rx_mode(bp); 4574#ifdef BCM_CNIC 4575 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4576 &bp->sp_state)) 4577 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4578 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4579 &bp->sp_state)) 4580 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4581#endif 4582 4583 netif_addr_unlock_bh(bp->dev); 4584} 4585 4586static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4587 struct bnx2x *bp, u32 cid) 4588{ 4589 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4590#ifdef BCM_CNIC 4591 if (cid == BNX2X_FCOE_ETH_CID) 4592 return &bnx2x_fcoe(bp, q_obj); 4593 else 4594#endif 4595 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4596} 4597 4598static void bnx2x_eq_int(struct bnx2x *bp) 4599{ 4600 u16 hw_cons, sw_cons, sw_prod; 4601 union event_ring_elem *elem; 4602 u32 cid; 4603 u8 opcode; 4604 int spqe_cnt = 0; 4605 struct bnx2x_queue_sp_obj *q_obj; 4606 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4607 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4608 4609 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4610 4611 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4612 * when we get the the next-page we nned to adjust so the loop 4613 * condition below will be met. The next element is the size of a 4614 * regular element and hence incrementing by 1 4615 */ 4616 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4617 hw_cons++; 4618 4619 /* This function may never run in parallel with itself for a 4620 * specific bp, thus there is no need in "paired" read memory 4621 * barrier here. 4622 */ 4623 sw_cons = bp->eq_cons; 4624 sw_prod = bp->eq_prod; 4625 4626 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4627 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4628 4629 for (; sw_cons != hw_cons; 4630 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4631 4632 4633 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4634 4635 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4636 opcode = elem->message.opcode; 4637 4638 4639 /* handle eq element */ 4640 switch (opcode) { 4641 case EVENT_RING_OPCODE_STAT_QUERY: 4642 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4643 bp->stats_comp++); 4644 /* nothing to do with stats comp */ 4645 goto next_spqe; 4646 4647 case EVENT_RING_OPCODE_CFC_DEL: 4648 /* handle according to cid range */ 4649 /* 4650 * we may want to verify here that the bp state is 4651 * HALTING 4652 */ 4653 DP(BNX2X_MSG_SP, 4654 "got delete ramrod for MULTI[%d]\n", cid); 4655#ifdef BCM_CNIC 4656 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4657 goto next_spqe; 4658#endif 4659 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4660 4661 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4662 break; 4663 4664 4665 4666 goto next_spqe; 4667 4668 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4669 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4670 if (f_obj->complete_cmd(bp, f_obj, 4671 BNX2X_F_CMD_TX_STOP)) 4672 break; 4673 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4674 goto next_spqe; 4675 4676 case EVENT_RING_OPCODE_START_TRAFFIC: 4677 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4678 if (f_obj->complete_cmd(bp, f_obj, 4679 BNX2X_F_CMD_TX_START)) 4680 break; 4681 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4682 goto next_spqe; 4683 case EVENT_RING_OPCODE_FUNCTION_START: 4684 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4685 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4686 break; 4687 4688 goto next_spqe; 4689 4690 case EVENT_RING_OPCODE_FUNCTION_STOP: 4691 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4692 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4693 break; 4694 4695 goto next_spqe; 4696 } 4697 4698 switch (opcode | bp->state) { 4699 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4700 BNX2X_STATE_OPEN): 4701 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4702 BNX2X_STATE_OPENING_WAIT4_PORT): 4703 cid = elem->message.data.eth_event.echo & 4704 BNX2X_SWCID_MASK; 4705 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4706 cid); 4707 rss_raw->clear_pending(rss_raw); 4708 break; 4709 4710 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4711 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4712 case (EVENT_RING_OPCODE_SET_MAC | 4713 BNX2X_STATE_CLOSING_WAIT4_HALT): 4714 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4715 BNX2X_STATE_OPEN): 4716 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4717 BNX2X_STATE_DIAG): 4718 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4719 BNX2X_STATE_CLOSING_WAIT4_HALT): 4720 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4721 bnx2x_handle_classification_eqe(bp, elem); 4722 break; 4723 4724 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4725 BNX2X_STATE_OPEN): 4726 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4727 BNX2X_STATE_DIAG): 4728 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4729 BNX2X_STATE_CLOSING_WAIT4_HALT): 4730 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4731 bnx2x_handle_mcast_eqe(bp); 4732 break; 4733 4734 case (EVENT_RING_OPCODE_FILTERS_RULES | 4735 BNX2X_STATE_OPEN): 4736 case (EVENT_RING_OPCODE_FILTERS_RULES | 4737 BNX2X_STATE_DIAG): 4738 case (EVENT_RING_OPCODE_FILTERS_RULES | 4739 BNX2X_STATE_CLOSING_WAIT4_HALT): 4740 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4741 bnx2x_handle_rx_mode_eqe(bp); 4742 break; 4743 default: 4744 /* unknown event log error and continue */ 4745 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4746 elem->message.opcode, bp->state); 4747 } 4748next_spqe: 4749 spqe_cnt++; 4750 } /* for */ 4751 4752 smp_mb__before_atomic_inc(); 4753 atomic_add(spqe_cnt, &bp->eq_spq_left); 4754 4755 bp->eq_cons = sw_cons; 4756 bp->eq_prod = sw_prod; 4757 /* Make sure that above mem writes were issued towards the memory */ 4758 smp_wmb(); 4759 4760 /* update producer */ 4761 bnx2x_update_eq_prod(bp, bp->eq_prod); 4762} 4763 4764static void bnx2x_sp_task(struct work_struct *work) 4765{ 4766 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4767 u16 status; 4768 4769 status = bnx2x_update_dsb_idx(bp); 4770/* if (status == 0) */ 4771/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4772 4773 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4774 4775 /* HW attentions */ 4776 if (status & BNX2X_DEF_SB_ATT_IDX) { 4777 bnx2x_attn_int(bp); 4778 status &= ~BNX2X_DEF_SB_ATT_IDX; 4779 } 4780 4781 /* SP events: STAT_QUERY and others */ 4782 if (status & BNX2X_DEF_SB_IDX) { 4783#ifdef BCM_CNIC 4784 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4785 4786 if ((!NO_FCOE(bp)) && 4787 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4788 /* 4789 * Prevent local bottom-halves from running as 4790 * we are going to change the local NAPI list. 4791 */ 4792 local_bh_disable(); 4793 napi_schedule(&bnx2x_fcoe(bp, napi)); 4794 local_bh_enable(); 4795 } 4796#endif 4797 /* Handle EQ completions */ 4798 bnx2x_eq_int(bp); 4799 4800 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4801 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4802 4803 status &= ~BNX2X_DEF_SB_IDX; 4804 } 4805 4806 if (unlikely(status)) 4807 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4808 status); 4809 4810 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4811 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4812} 4813 4814irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4815{ 4816 struct net_device *dev = dev_instance; 4817 struct bnx2x *bp = netdev_priv(dev); 4818 4819 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4820 IGU_INT_DISABLE, 0); 4821 4822#ifdef BNX2X_STOP_ON_ERROR 4823 if (unlikely(bp->panic)) 4824 return IRQ_HANDLED; 4825#endif 4826 4827#ifdef BCM_CNIC 4828 { 4829 struct cnic_ops *c_ops; 4830 4831 rcu_read_lock(); 4832 c_ops = rcu_dereference(bp->cnic_ops); 4833 if (c_ops) 4834 c_ops->cnic_handler(bp->cnic_data, NULL); 4835 rcu_read_unlock(); 4836 } 4837#endif 4838 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4839 4840 return IRQ_HANDLED; 4841} 4842 4843/* end of slow path */ 4844 4845 4846void bnx2x_drv_pulse(struct bnx2x *bp) 4847{ 4848 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4849 bp->fw_drv_pulse_wr_seq); 4850} 4851 4852 4853static void bnx2x_timer(unsigned long data) 4854{ 4855 struct bnx2x *bp = (struct bnx2x *) data; 4856 4857 if (!netif_running(bp->dev)) 4858 return; 4859 4860 if (!BP_NOMCP(bp)) { 4861 int mb_idx = BP_FW_MB_IDX(bp); 4862 u32 drv_pulse; 4863 u32 mcp_pulse; 4864 4865 ++bp->fw_drv_pulse_wr_seq; 4866 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4867 /* TBD - add SYSTEM_TIME */ 4868 drv_pulse = bp->fw_drv_pulse_wr_seq; 4869 bnx2x_drv_pulse(bp); 4870 4871 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4872 MCP_PULSE_SEQ_MASK); 4873 /* The delta between driver pulse and mcp response 4874 * should be 1 (before mcp response) or 0 (after mcp response) 4875 */ 4876 if ((drv_pulse != mcp_pulse) && 4877 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4878 /* someone lost a heartbeat... */ 4879 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4880 drv_pulse, mcp_pulse); 4881 } 4882 } 4883 4884 if (bp->state == BNX2X_STATE_OPEN) 4885 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4886 4887 mod_timer(&bp->timer, jiffies + bp->current_interval); 4888} 4889 4890/* end of Statistics */ 4891 4892/* nic init */ 4893 4894/* 4895 * nic init service functions 4896 */ 4897 4898static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4899{ 4900 u32 i; 4901 if (!(len%4) && !(addr%4)) 4902 for (i = 0; i < len; i += 4) 4903 REG_WR(bp, addr + i, fill); 4904 else 4905 for (i = 0; i < len; i++) 4906 REG_WR8(bp, addr + i, fill); 4907 4908} 4909 4910/* helper: writes FP SP data to FW - data_size in dwords */ 4911static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4912 int fw_sb_id, 4913 u32 *sb_data_p, 4914 u32 data_size) 4915{ 4916 int index; 4917 for (index = 0; index < data_size; index++) 4918 REG_WR(bp, BAR_CSTRORM_INTMEM + 4919 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4920 sizeof(u32)*index, 4921 *(sb_data_p + index)); 4922} 4923 4924static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4925{ 4926 u32 *sb_data_p; 4927 u32 data_size = 0; 4928 struct hc_status_block_data_e2 sb_data_e2; 4929 struct hc_status_block_data_e1x sb_data_e1x; 4930 4931 /* disable the function first */ 4932 if (!CHIP_IS_E1x(bp)) { 4933 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4934 sb_data_e2.common.state = SB_DISABLED; 4935 sb_data_e2.common.p_func.vf_valid = false; 4936 sb_data_p = (u32 *)&sb_data_e2; 4937 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4938 } else { 4939 memset(&sb_data_e1x, 0, 4940 sizeof(struct hc_status_block_data_e1x)); 4941 sb_data_e1x.common.state = SB_DISABLED; 4942 sb_data_e1x.common.p_func.vf_valid = false; 4943 sb_data_p = (u32 *)&sb_data_e1x; 4944 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4945 } 4946 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4947 4948 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4949 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4950 CSTORM_STATUS_BLOCK_SIZE); 4951 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4952 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4953 CSTORM_SYNC_BLOCK_SIZE); 4954} 4955 4956/* helper: writes SP SB data to FW */ 4957static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4958 struct hc_sp_status_block_data *sp_sb_data) 4959{ 4960 int func = BP_FUNC(bp); 4961 int i; 4962 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4963 REG_WR(bp, BAR_CSTRORM_INTMEM + 4964 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4965 i*sizeof(u32), 4966 *((u32 *)sp_sb_data + i)); 4967} 4968 4969static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4970{ 4971 int func = BP_FUNC(bp); 4972 struct hc_sp_status_block_data sp_sb_data; 4973 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4974 4975 sp_sb_data.state = SB_DISABLED; 4976 sp_sb_data.p_func.vf_valid = false; 4977 4978 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4979 4980 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4981 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4982 CSTORM_SP_STATUS_BLOCK_SIZE); 4983 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4984 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4985 CSTORM_SP_SYNC_BLOCK_SIZE); 4986 4987} 4988 4989 4990static inline 4991void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4992 int igu_sb_id, int igu_seg_id) 4993{ 4994 hc_sm->igu_sb_id = igu_sb_id; 4995 hc_sm->igu_seg_id = igu_seg_id; 4996 hc_sm->timer_value = 0xFF; 4997 hc_sm->time_to_expire = 0xFFFFFFFF; 4998} 4999 5000 5001/* allocates state machine ids. */ 5002static inline 5003void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5004{ 5005 /* zero out state machine indices */ 5006 /* rx indices */ 5007 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5008 5009 /* tx indices */ 5010 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5011 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5012 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5013 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5014 5015 /* map indices */ 5016 /* rx indices */ 5017 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5018 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5019 5020 /* tx indices */ 5021 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5022 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5023 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5024 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5025 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5026 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5027 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5028 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5029} 5030 5031static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5032 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5033{ 5034 int igu_seg_id; 5035 5036 struct hc_status_block_data_e2 sb_data_e2; 5037 struct hc_status_block_data_e1x sb_data_e1x; 5038 struct hc_status_block_sm *hc_sm_p; 5039 int data_size; 5040 u32 *sb_data_p; 5041 5042 if (CHIP_INT_MODE_IS_BC(bp)) 5043 igu_seg_id = HC_SEG_ACCESS_NORM; 5044 else 5045 igu_seg_id = IGU_SEG_ACCESS_NORM; 5046 5047 bnx2x_zero_fp_sb(bp, fw_sb_id); 5048 5049 if (!CHIP_IS_E1x(bp)) { 5050 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5051 sb_data_e2.common.state = SB_ENABLED; 5052 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5053 sb_data_e2.common.p_func.vf_id = vfid; 5054 sb_data_e2.common.p_func.vf_valid = vf_valid; 5055 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5056 sb_data_e2.common.same_igu_sb_1b = true; 5057 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5058 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5059 hc_sm_p = sb_data_e2.common.state_machine; 5060 sb_data_p = (u32 *)&sb_data_e2; 5061 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5062 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5063 } else { 5064 memset(&sb_data_e1x, 0, 5065 sizeof(struct hc_status_block_data_e1x)); 5066 sb_data_e1x.common.state = SB_ENABLED; 5067 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5068 sb_data_e1x.common.p_func.vf_id = 0xff; 5069 sb_data_e1x.common.p_func.vf_valid = false; 5070 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5071 sb_data_e1x.common.same_igu_sb_1b = true; 5072 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5073 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5074 hc_sm_p = sb_data_e1x.common.state_machine; 5075 sb_data_p = (u32 *)&sb_data_e1x; 5076 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5077 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5078 } 5079 5080 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5081 igu_sb_id, igu_seg_id); 5082 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5083 igu_sb_id, igu_seg_id); 5084 5085 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 5086 5087 /* write indecies to HW */ 5088 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5089} 5090 5091static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5092 u16 tx_usec, u16 rx_usec) 5093{ 5094 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5095 false, rx_usec); 5096 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5097 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5098 tx_usec); 5099 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5100 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5101 tx_usec); 5102 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5103 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5104 tx_usec); 5105} 5106 5107static void bnx2x_init_def_sb(struct bnx2x *bp) 5108{ 5109 struct host_sp_status_block *def_sb = bp->def_status_blk; 5110 dma_addr_t mapping = bp->def_status_blk_mapping; 5111 int igu_sp_sb_index; 5112 int igu_seg_id; 5113 int port = BP_PORT(bp); 5114 int func = BP_FUNC(bp); 5115 int reg_offset, reg_offset_en5; 5116 u64 section; 5117 int index; 5118 struct hc_sp_status_block_data sp_sb_data; 5119 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5120 5121 if (CHIP_INT_MODE_IS_BC(bp)) { 5122 igu_sp_sb_index = DEF_SB_IGU_ID; 5123 igu_seg_id = HC_SEG_ACCESS_DEF; 5124 } else { 5125 igu_sp_sb_index = bp->igu_dsb_id; 5126 igu_seg_id = IGU_SEG_ACCESS_DEF; 5127 } 5128 5129 /* ATTN */ 5130 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5131 atten_status_block); 5132 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5133 5134 bp->attn_state = 0; 5135 5136 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5137 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5138 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5139 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5140 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5141 int sindex; 5142 /* take care of sig[0]..sig[4] */ 5143 for (sindex = 0; sindex < 4; sindex++) 5144 bp->attn_group[index].sig[sindex] = 5145 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5146 5147 if (!CHIP_IS_E1x(bp)) 5148 /* 5149 * enable5 is separate from the rest of the registers, 5150 * and therefore the address skip is 4 5151 * and not 16 between the different groups 5152 */ 5153 bp->attn_group[index].sig[4] = REG_RD(bp, 5154 reg_offset_en5 + 0x4*index); 5155 else 5156 bp->attn_group[index].sig[4] = 0; 5157 } 5158 5159 if (bp->common.int_block == INT_BLOCK_HC) { 5160 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5161 HC_REG_ATTN_MSG0_ADDR_L); 5162 5163 REG_WR(bp, reg_offset, U64_LO(section)); 5164 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5165 } else if (!CHIP_IS_E1x(bp)) { 5166 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5167 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5168 } 5169 5170 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5171 sp_sb); 5172 5173 bnx2x_zero_sp_sb(bp); 5174 5175 sp_sb_data.state = SB_ENABLED; 5176 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5177 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5178 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5179 sp_sb_data.igu_seg_id = igu_seg_id; 5180 sp_sb_data.p_func.pf_id = func; 5181 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5182 sp_sb_data.p_func.vf_id = 0xff; 5183 5184 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5185 5186 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5187} 5188 5189void bnx2x_update_coalesce(struct bnx2x *bp) 5190{ 5191 int i; 5192 5193 for_each_eth_queue(bp, i) 5194 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5195 bp->tx_ticks, bp->rx_ticks); 5196} 5197 5198static void bnx2x_init_sp_ring(struct bnx2x *bp) 5199{ 5200 spin_lock_init(&bp->spq_lock); 5201 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5202 5203 bp->spq_prod_idx = 0; 5204 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5205 bp->spq_prod_bd = bp->spq; 5206 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5207} 5208 5209static void bnx2x_init_eq_ring(struct bnx2x *bp) 5210{ 5211 int i; 5212 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5213 union event_ring_elem *elem = 5214 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5215 5216 elem->next_page.addr.hi = 5217 cpu_to_le32(U64_HI(bp->eq_mapping + 5218 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5219 elem->next_page.addr.lo = 5220 cpu_to_le32(U64_LO(bp->eq_mapping + 5221 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5222 } 5223 bp->eq_cons = 0; 5224 bp->eq_prod = NUM_EQ_DESC; 5225 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5226 /* we want a warning message before it gets rought... */ 5227 atomic_set(&bp->eq_spq_left, 5228 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5229} 5230 5231 5232/* called with netif_addr_lock_bh() */ 5233void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5234 unsigned long rx_mode_flags, 5235 unsigned long rx_accept_flags, 5236 unsigned long tx_accept_flags, 5237 unsigned long ramrod_flags) 5238{ 5239 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5240 int rc; 5241 5242 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5243 5244 /* Prepare ramrod parameters */ 5245 ramrod_param.cid = 0; 5246 ramrod_param.cl_id = cl_id; 5247 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5248 ramrod_param.func_id = BP_FUNC(bp); 5249 5250 ramrod_param.pstate = &bp->sp_state; 5251 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5252 5253 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5254 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5255 5256 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5257 5258 ramrod_param.ramrod_flags = ramrod_flags; 5259 ramrod_param.rx_mode_flags = rx_mode_flags; 5260 5261 ramrod_param.rx_accept_flags = rx_accept_flags; 5262 ramrod_param.tx_accept_flags = tx_accept_flags; 5263 5264 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5265 if (rc < 0) { 5266 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5267 return; 5268 } 5269} 5270 5271/* called with netif_addr_lock_bh() */ 5272void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5273{ 5274 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5275 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5276 5277#ifdef BCM_CNIC 5278 if (!NO_FCOE(bp)) 5279 5280 /* Configure rx_mode of FCoE Queue */ 5281 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5282#endif 5283 5284 switch (bp->rx_mode) { 5285 case BNX2X_RX_MODE_NONE: 5286 /* 5287 * 'drop all' supersedes any accept flags that may have been 5288 * passed to the function. 5289 */ 5290 break; 5291 case BNX2X_RX_MODE_NORMAL: 5292 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5293 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5294 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5295 5296 /* internal switching mode */ 5297 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5298 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5299 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5300 5301 break; 5302 case BNX2X_RX_MODE_ALLMULTI: 5303 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5304 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5305 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5306 5307 /* internal switching mode */ 5308 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5309 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5310 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5311 5312 break; 5313 case BNX2X_RX_MODE_PROMISC: 5314 /* According to deffinition of SI mode, iface in promisc mode 5315 * should receive matched and unmatched (in resolution of port) 5316 * unicast packets. 5317 */ 5318 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5319 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5320 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5321 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5322 5323 /* internal switching mode */ 5324 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5325 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5326 5327 if (IS_MF_SI(bp)) 5328 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5329 else 5330 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5331 5332 break; 5333 default: 5334 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5335 return; 5336 } 5337 5338 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5339 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5340 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5341 } 5342 5343 __set_bit(RAMROD_RX, &ramrod_flags); 5344 __set_bit(RAMROD_TX, &ramrod_flags); 5345 5346 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5347 tx_accept_flags, ramrod_flags); 5348} 5349 5350static void bnx2x_init_internal_common(struct bnx2x *bp) 5351{ 5352 int i; 5353 5354 if (IS_MF_SI(bp)) 5355 /* 5356 * In switch independent mode, the TSTORM needs to accept 5357 * packets that failed classification, since approximate match 5358 * mac addresses aren't written to NIG LLH 5359 */ 5360 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5361 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5362 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5363 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5364 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5365 5366 /* Zero this manually as its initialization is 5367 currently missing in the initTool */ 5368 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5369 REG_WR(bp, BAR_USTRORM_INTMEM + 5370 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5371 if (!CHIP_IS_E1x(bp)) { 5372 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5373 CHIP_INT_MODE_IS_BC(bp) ? 5374 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5375 } 5376} 5377 5378static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5379{ 5380 switch (load_code) { 5381 case FW_MSG_CODE_DRV_LOAD_COMMON: 5382 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5383 bnx2x_init_internal_common(bp); 5384 /* no break */ 5385 5386 case FW_MSG_CODE_DRV_LOAD_PORT: 5387 /* nothing to do */ 5388 /* no break */ 5389 5390 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5391 /* internal memory per function is 5392 initialized inside bnx2x_pf_init */ 5393 break; 5394 5395 default: 5396 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5397 break; 5398 } 5399} 5400 5401static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5402{ 5403 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5404} 5405 5406static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5407{ 5408 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5409} 5410 5411static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5412{ 5413 if (CHIP_IS_E1x(fp->bp)) 5414 return BP_L_ID(fp->bp) + fp->index; 5415 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5416 return bnx2x_fp_igu_sb_id(fp); 5417} 5418 5419static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5420{ 5421 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5422 u8 cos; 5423 unsigned long q_type = 0; 5424 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5425 fp->rx_queue = fp_idx; 5426 fp->cid = fp_idx; 5427 fp->cl_id = bnx2x_fp_cl_id(fp); 5428 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5429 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5430 /* qZone id equals to FW (per path) client id */ 5431 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5432 5433 /* init shortcut */ 5434 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5435 5436 /* Setup SB indicies */ 5437 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5438 5439 /* Configure Queue State object */ 5440 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5441 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5442 5443 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5444 5445 /* init tx data */ 5446 for_each_cos_in_tx_queue(fp, cos) { 5447 bnx2x_init_txdata(bp, &fp->txdata[cos], 5448 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5449 FP_COS_TO_TXQ(fp, cos), 5450 BNX2X_TX_SB_INDEX_BASE + cos); 5451 cids[cos] = fp->txdata[cos].cid; 5452 } 5453 5454 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5455 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5456 bnx2x_sp_mapping(bp, q_rdata), q_type); 5457 5458 /** 5459 * Configure classification DBs: Always enable Tx switching 5460 */ 5461 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5462 5463 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5464 "cl_id %d fw_sb %d igu_sb %d\n", 5465 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5466 fp->igu_sb_id); 5467 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5468 fp->fw_sb_id, fp->igu_sb_id); 5469 5470 bnx2x_update_fpsb_idx(fp); 5471} 5472 5473void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5474{ 5475 int i; 5476 5477 for_each_eth_queue(bp, i) 5478 bnx2x_init_eth_fp(bp, i); 5479#ifdef BCM_CNIC 5480 if (!NO_FCOE(bp)) 5481 bnx2x_init_fcoe_fp(bp); 5482 5483 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5484 BNX2X_VF_ID_INVALID, false, 5485 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5486 5487#endif 5488 5489 /* Initialize MOD_ABS interrupts */ 5490 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5491 bp->common.shmem_base, bp->common.shmem2_base, 5492 BP_PORT(bp)); 5493 /* ensure status block indices were read */ 5494 rmb(); 5495 5496 bnx2x_init_def_sb(bp); 5497 bnx2x_update_dsb_idx(bp); 5498 bnx2x_init_rx_rings(bp); 5499 bnx2x_init_tx_rings(bp); 5500 bnx2x_init_sp_ring(bp); 5501 bnx2x_init_eq_ring(bp); 5502 bnx2x_init_internal(bp, load_code); 5503 bnx2x_pf_init(bp); 5504 bnx2x_stats_init(bp); 5505 5506 /* flush all before enabling interrupts */ 5507 mb(); 5508 mmiowb(); 5509 5510 bnx2x_int_enable(bp); 5511 5512 /* Check for SPIO5 */ 5513 bnx2x_attn_int_deasserted0(bp, 5514 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5515 AEU_INPUTS_ATTN_BITS_SPIO5); 5516} 5517 5518/* end of nic init */ 5519 5520/* 5521 * gzip service functions 5522 */ 5523 5524static int bnx2x_gunzip_init(struct bnx2x *bp) 5525{ 5526 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5527 &bp->gunzip_mapping, GFP_KERNEL); 5528 if (bp->gunzip_buf == NULL) 5529 goto gunzip_nomem1; 5530 5531 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5532 if (bp->strm == NULL) 5533 goto gunzip_nomem2; 5534 5535 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5536 if (bp->strm->workspace == NULL) 5537 goto gunzip_nomem3; 5538 5539 return 0; 5540 5541gunzip_nomem3: 5542 kfree(bp->strm); 5543 bp->strm = NULL; 5544 5545gunzip_nomem2: 5546 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5547 bp->gunzip_mapping); 5548 bp->gunzip_buf = NULL; 5549 5550gunzip_nomem1: 5551 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5552 " un-compression\n"); 5553 return -ENOMEM; 5554} 5555 5556static void bnx2x_gunzip_end(struct bnx2x *bp) 5557{ 5558 if (bp->strm) { 5559 vfree(bp->strm->workspace); 5560 kfree(bp->strm); 5561 bp->strm = NULL; 5562 } 5563 5564 if (bp->gunzip_buf) { 5565 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5566 bp->gunzip_mapping); 5567 bp->gunzip_buf = NULL; 5568 } 5569} 5570 5571static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5572{ 5573 int n, rc; 5574 5575 /* check gzip header */ 5576 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5577 BNX2X_ERR("Bad gzip header\n"); 5578 return -EINVAL; 5579 } 5580 5581 n = 10; 5582 5583#define FNAME 0x8 5584 5585 if (zbuf[3] & FNAME) 5586 while ((zbuf[n++] != 0) && (n < len)); 5587 5588 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5589 bp->strm->avail_in = len - n; 5590 bp->strm->next_out = bp->gunzip_buf; 5591 bp->strm->avail_out = FW_BUF_SIZE; 5592 5593 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5594 if (rc != Z_OK) 5595 return rc; 5596 5597 rc = zlib_inflate(bp->strm, Z_FINISH); 5598 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5599 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5600 bp->strm->msg); 5601 5602 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5603 if (bp->gunzip_outlen & 0x3) 5604 netdev_err(bp->dev, "Firmware decompression error:" 5605 " gunzip_outlen (%d) not aligned\n", 5606 bp->gunzip_outlen); 5607 bp->gunzip_outlen >>= 2; 5608 5609 zlib_inflateEnd(bp->strm); 5610 5611 if (rc == Z_STREAM_END) 5612 return 0; 5613 5614 return rc; 5615} 5616 5617/* nic load/unload */ 5618 5619/* 5620 * General service functions 5621 */ 5622 5623/* send a NIG loopback debug packet */ 5624static void bnx2x_lb_pckt(struct bnx2x *bp) 5625{ 5626 u32 wb_write[3]; 5627 5628 /* Ethernet source and destination addresses */ 5629 wb_write[0] = 0x55555555; 5630 wb_write[1] = 0x55555555; 5631 wb_write[2] = 0x20; /* SOP */ 5632 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5633 5634 /* NON-IP protocol */ 5635 wb_write[0] = 0x09000000; 5636 wb_write[1] = 0x55555555; 5637 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5638 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5639} 5640 5641/* some of the internal memories 5642 * are not directly readable from the driver 5643 * to test them we send debug packets 5644 */ 5645static int bnx2x_int_mem_test(struct bnx2x *bp) 5646{ 5647 int factor; 5648 int count, i; 5649 u32 val = 0; 5650 5651 if (CHIP_REV_IS_FPGA(bp)) 5652 factor = 120; 5653 else if (CHIP_REV_IS_EMUL(bp)) 5654 factor = 200; 5655 else 5656 factor = 1; 5657 5658 /* Disable inputs of parser neighbor blocks */ 5659 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5660 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5661 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5662 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5663 5664 /* Write 0 to parser credits for CFC search request */ 5665 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5666 5667 /* send Ethernet packet */ 5668 bnx2x_lb_pckt(bp); 5669 5670 /* TODO do i reset NIG statistic? */ 5671 /* Wait until NIG register shows 1 packet of size 0x10 */ 5672 count = 1000 * factor; 5673 while (count) { 5674 5675 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5676 val = *bnx2x_sp(bp, wb_data[0]); 5677 if (val == 0x10) 5678 break; 5679 5680 msleep(10); 5681 count--; 5682 } 5683 if (val != 0x10) { 5684 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5685 return -1; 5686 } 5687 5688 /* Wait until PRS register shows 1 packet */ 5689 count = 1000 * factor; 5690 while (count) { 5691 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5692 if (val == 1) 5693 break; 5694 5695 msleep(10); 5696 count--; 5697 } 5698 if (val != 0x1) { 5699 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5700 return -2; 5701 } 5702 5703 /* Reset and init BRB, PRS */ 5704 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5705 msleep(50); 5706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5707 msleep(50); 5708 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5709 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5710 5711 DP(NETIF_MSG_HW, "part2\n"); 5712 5713 /* Disable inputs of parser neighbor blocks */ 5714 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5715 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5716 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5717 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5718 5719 /* Write 0 to parser credits for CFC search request */ 5720 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5721 5722 /* send 10 Ethernet packets */ 5723 for (i = 0; i < 10; i++) 5724 bnx2x_lb_pckt(bp); 5725 5726 /* Wait until NIG register shows 10 + 1 5727 packets of size 11*0x10 = 0xb0 */ 5728 count = 1000 * factor; 5729 while (count) { 5730 5731 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5732 val = *bnx2x_sp(bp, wb_data[0]); 5733 if (val == 0xb0) 5734 break; 5735 5736 msleep(10); 5737 count--; 5738 } 5739 if (val != 0xb0) { 5740 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5741 return -3; 5742 } 5743 5744 /* Wait until PRS register shows 2 packets */ 5745 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5746 if (val != 2) 5747 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5748 5749 /* Write 1 to parser credits for CFC search request */ 5750 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5751 5752 /* Wait until PRS register shows 3 packets */ 5753 msleep(10 * factor); 5754 /* Wait until NIG register shows 1 packet of size 0x10 */ 5755 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5756 if (val != 3) 5757 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5758 5759 /* clear NIG EOP FIFO */ 5760 for (i = 0; i < 11; i++) 5761 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5762 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5763 if (val != 1) { 5764 BNX2X_ERR("clear of NIG failed\n"); 5765 return -4; 5766 } 5767 5768 /* Reset and init BRB, PRS, NIG */ 5769 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5770 msleep(50); 5771 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5772 msleep(50); 5773 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5774 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5775#ifndef BCM_CNIC 5776 /* set NIC mode */ 5777 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5778#endif 5779 5780 /* Enable inputs of parser neighbor blocks */ 5781 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5782 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5783 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5784 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5785 5786 DP(NETIF_MSG_HW, "done\n"); 5787 5788 return 0; /* OK */ 5789} 5790 5791static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5792{ 5793 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5794 if (!CHIP_IS_E1x(bp)) 5795 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5796 else 5797 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5798 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5799 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5800 /* 5801 * mask read length error interrupts in brb for parser 5802 * (parsing unit and 'checksum and crc' unit) 5803 * these errors are legal (PU reads fixed length and CAC can cause 5804 * read length error on truncated packets) 5805 */ 5806 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5807 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5808 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5809 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5810 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5811 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5812/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5813/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5814 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5815 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5816 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5817/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5818/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5819 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5820 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5821 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5822 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5823/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5824/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5825 5826 if (CHIP_REV_IS_FPGA(bp)) 5827 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5828 else if (!CHIP_IS_E1x(bp)) 5829 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5830 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5831 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5832 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5833 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5834 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5835 else 5836 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5837 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5838 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5839 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5840/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5841 5842 if (!CHIP_IS_E1x(bp)) 5843 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5844 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5845 5846 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5847 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5848/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5849 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5850} 5851 5852static void bnx2x_reset_common(struct bnx2x *bp) 5853{ 5854 u32 val = 0x1400; 5855 5856 /* reset_common */ 5857 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5858 0xd3ffff7f); 5859 5860 if (CHIP_IS_E3(bp)) { 5861 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5862 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5863 } 5864 5865 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5866} 5867 5868static void bnx2x_setup_dmae(struct bnx2x *bp) 5869{ 5870 bp->dmae_ready = 0; 5871 spin_lock_init(&bp->dmae_lock); 5872} 5873 5874static void bnx2x_init_pxp(struct bnx2x *bp) 5875{ 5876 u16 devctl; 5877 int r_order, w_order; 5878 5879 pci_read_config_word(bp->pdev, 5880 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5881 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5882 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5883 if (bp->mrrs == -1) 5884 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5885 else { 5886 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5887 r_order = bp->mrrs; 5888 } 5889 5890 bnx2x_init_pxp_arb(bp, r_order, w_order); 5891} 5892 5893static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5894{ 5895 int is_required; 5896 u32 val; 5897 int port; 5898 5899 if (BP_NOMCP(bp)) 5900 return; 5901 5902 is_required = 0; 5903 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5904 SHARED_HW_CFG_FAN_FAILURE_MASK; 5905 5906 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5907 is_required = 1; 5908 5909 /* 5910 * The fan failure mechanism is usually related to the PHY type since 5911 * the power consumption of the board is affected by the PHY. Currently, 5912 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5913 */ 5914 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5915 for (port = PORT_0; port < PORT_MAX; port++) { 5916 is_required |= 5917 bnx2x_fan_failure_det_req( 5918 bp, 5919 bp->common.shmem_base, 5920 bp->common.shmem2_base, 5921 port); 5922 } 5923 5924 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5925 5926 if (is_required == 0) 5927 return; 5928 5929 /* Fan failure is indicated by SPIO 5 */ 5930 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5931 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5932 5933 /* set to active low mode */ 5934 val = REG_RD(bp, MISC_REG_SPIO_INT); 5935 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5936 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5937 REG_WR(bp, MISC_REG_SPIO_INT, val); 5938 5939 /* enable interrupt to signal the IGU */ 5940 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5941 val |= (1 << MISC_REGISTERS_SPIO_5); 5942 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5943} 5944 5945static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5946{ 5947 u32 offset = 0; 5948 5949 if (CHIP_IS_E1(bp)) 5950 return; 5951 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5952 return; 5953 5954 switch (BP_ABS_FUNC(bp)) { 5955 case 0: 5956 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5957 break; 5958 case 1: 5959 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5960 break; 5961 case 2: 5962 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5963 break; 5964 case 3: 5965 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5966 break; 5967 case 4: 5968 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5969 break; 5970 case 5: 5971 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5972 break; 5973 case 6: 5974 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5975 break; 5976 case 7: 5977 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5978 break; 5979 default: 5980 return; 5981 } 5982 5983 REG_WR(bp, offset, pretend_func_num); 5984 REG_RD(bp, offset); 5985 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5986} 5987 5988void bnx2x_pf_disable(struct bnx2x *bp) 5989{ 5990 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5991 val &= ~IGU_PF_CONF_FUNC_EN; 5992 5993 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5994 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5995 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5996} 5997 5998static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5999{ 6000 u32 shmem_base[2], shmem2_base[2]; 6001 shmem_base[0] = bp->common.shmem_base; 6002 shmem2_base[0] = bp->common.shmem2_base; 6003 if (!CHIP_IS_E1x(bp)) { 6004 shmem_base[1] = 6005 SHMEM2_RD(bp, other_shmem_base_addr); 6006 shmem2_base[1] = 6007 SHMEM2_RD(bp, other_shmem2_base_addr); 6008 } 6009 bnx2x_acquire_phy_lock(bp); 6010 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 6011 bp->common.chip_id); 6012 bnx2x_release_phy_lock(bp); 6013} 6014 6015/** 6016 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 6017 * 6018 * @bp: driver handle 6019 */ 6020static int bnx2x_init_hw_common(struct bnx2x *bp) 6021{ 6022 u32 val; 6023 6024 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6025 6026 /* 6027 * take the UNDI lock to protect undi_unload flow from accessing 6028 * registers while we're resetting the chip 6029 */ 6030 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6031 6032 bnx2x_reset_common(bp); 6033 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6034 6035 val = 0xfffc; 6036 if (CHIP_IS_E3(bp)) { 6037 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6038 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6039 } 6040 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6041 6042 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6043 6044 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6045 6046 if (!CHIP_IS_E1x(bp)) { 6047 u8 abs_func_id; 6048 6049 /** 6050 * 4-port mode or 2-port mode we need to turn of master-enable 6051 * for everyone, after that, turn it back on for self. 6052 * so, we disregard multi-function or not, and always disable 6053 * for all functions on the given path, this means 0,2,4,6 for 6054 * path 0 and 1,3,5,7 for path 1 6055 */ 6056 for (abs_func_id = BP_PATH(bp); 6057 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6058 if (abs_func_id == BP_ABS_FUNC(bp)) { 6059 REG_WR(bp, 6060 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6061 1); 6062 continue; 6063 } 6064 6065 bnx2x_pretend_func(bp, abs_func_id); 6066 /* clear pf enable */ 6067 bnx2x_pf_disable(bp); 6068 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6069 } 6070 } 6071 6072 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6073 if (CHIP_IS_E1(bp)) { 6074 /* enable HW interrupt from PXP on USDM overflow 6075 bit 16 on INT_MASK_0 */ 6076 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6077 } 6078 6079 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6080 bnx2x_init_pxp(bp); 6081 6082#ifdef __BIG_ENDIAN 6083 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6084 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6085 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6086 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6087 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6088 /* make sure this value is 0 */ 6089 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6090 6091/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6092 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6093 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6094 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6095 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6096#endif 6097 6098 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6099 6100 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6101 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6102 6103 /* let the HW do it's magic ... */ 6104 msleep(100); 6105 /* finish PXP init */ 6106 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6107 if (val != 1) { 6108 BNX2X_ERR("PXP2 CFG failed\n"); 6109 return -EBUSY; 6110 } 6111 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6112 if (val != 1) { 6113 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6114 return -EBUSY; 6115 } 6116 6117 /* Timers bug workaround E2 only. We need to set the entire ILT to 6118 * have entries with value "0" and valid bit on. 6119 * This needs to be done by the first PF that is loaded in a path 6120 * (i.e. common phase) 6121 */ 6122 if (!CHIP_IS_E1x(bp)) { 6123/* In E2 there is a bug in the timers block that can cause function 6 / 7 6124 * (i.e. vnic3) to start even if it is marked as "scan-off". 6125 * This occurs when a different function (func2,3) is being marked 6126 * as "scan-off". Real-life scenario for example: if a driver is being 6127 * load-unloaded while func6,7 are down. This will cause the timer to access 6128 * the ilt, translate to a logical address and send a request to read/write. 6129 * Since the ilt for the function that is down is not valid, this will cause 6130 * a translation error which is unrecoverable. 6131 * The Workaround is intended to make sure that when this happens nothing fatal 6132 * will occur. The workaround: 6133 * 1. First PF driver which loads on a path will: 6134 * a. After taking the chip out of reset, by using pretend, 6135 * it will write "0" to the following registers of 6136 * the other vnics. 6137 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6138 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6139 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6140 * And for itself it will write '1' to 6141 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6142 * dmae-operations (writing to pram for example.) 6143 * note: can be done for only function 6,7 but cleaner this 6144 * way. 6145 * b. Write zero+valid to the entire ILT. 6146 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6147 * VNIC3 (of that port). The range allocated will be the 6148 * entire ILT. This is needed to prevent ILT range error. 6149 * 2. Any PF driver load flow: 6150 * a. ILT update with the physical addresses of the allocated 6151 * logical pages. 6152 * b. Wait 20msec. - note that this timeout is needed to make 6153 * sure there are no requests in one of the PXP internal 6154 * queues with "old" ILT addresses. 6155 * c. PF enable in the PGLC. 6156 * d. Clear the was_error of the PF in the PGLC. (could have 6157 * occured while driver was down) 6158 * e. PF enable in the CFC (WEAK + STRONG) 6159 * f. Timers scan enable 6160 * 3. PF driver unload flow: 6161 * a. Clear the Timers scan_en. 6162 * b. Polling for scan_on=0 for that PF. 6163 * c. Clear the PF enable bit in the PXP. 6164 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6165 * e. Write zero+valid to all ILT entries (The valid bit must 6166 * stay set) 6167 * f. If this is VNIC 3 of a port then also init 6168 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6169 * to the last enrty in the ILT. 6170 * 6171 * Notes: 6172 * Currently the PF error in the PGLC is non recoverable. 6173 * In the future the there will be a recovery routine for this error. 6174 * Currently attention is masked. 6175 * Having an MCP lock on the load/unload process does not guarantee that 6176 * there is no Timer disable during Func6/7 enable. This is because the 6177 * Timers scan is currently being cleared by the MCP on FLR. 6178 * Step 2.d can be done only for PF6/7 and the driver can also check if 6179 * there is error before clearing it. But the flow above is simpler and 6180 * more general. 6181 * All ILT entries are written by zero+valid and not just PF6/7 6182 * ILT entries since in the future the ILT entries allocation for 6183 * PF-s might be dynamic. 6184 */ 6185 struct ilt_client_info ilt_cli; 6186 struct bnx2x_ilt ilt; 6187 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6188 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6189 6190 /* initialize dummy TM client */ 6191 ilt_cli.start = 0; 6192 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6193 ilt_cli.client_num = ILT_CLIENT_TM; 6194 6195 /* Step 1: set zeroes to all ilt page entries with valid bit on 6196 * Step 2: set the timers first/last ilt entry to point 6197 * to the entire range to prevent ILT range error for 3rd/4th 6198 * vnic (this code assumes existance of the vnic) 6199 * 6200 * both steps performed by call to bnx2x_ilt_client_init_op() 6201 * with dummy TM client 6202 * 6203 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6204 * and his brother are split registers 6205 */ 6206 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6207 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6208 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6209 6210 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6211 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6212 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6213 } 6214 6215 6216 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6217 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6218 6219 if (!CHIP_IS_E1x(bp)) { 6220 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6221 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6222 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6223 6224 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6225 6226 /* let the HW do it's magic ... */ 6227 do { 6228 msleep(200); 6229 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6230 } while (factor-- && (val != 1)); 6231 6232 if (val != 1) { 6233 BNX2X_ERR("ATC_INIT failed\n"); 6234 return -EBUSY; 6235 } 6236 } 6237 6238 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6239 6240 /* clean the DMAE memory */ 6241 bp->dmae_ready = 1; 6242 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6243 6244 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6245 6246 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6247 6248 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6249 6250 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6251 6252 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6253 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6254 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6255 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6256 6257 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6258 6259 6260 /* QM queues pointers table */ 6261 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6262 6263 /* soft reset pulse */ 6264 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6265 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6266 6267#ifdef BCM_CNIC 6268 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6269#endif 6270 6271 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6272 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6273 if (!CHIP_REV_IS_SLOW(bp)) 6274 /* enable hw interrupt from doorbell Q */ 6275 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6276 6277 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6278 6279 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6280 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6281 6282 if (!CHIP_IS_E1(bp)) 6283 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6284 6285 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6286 /* Bit-map indicating which L2 hdrs may appear 6287 * after the basic Ethernet header 6288 */ 6289 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6290 bp->path_has_ovlan ? 7 : 6); 6291 6292 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6293 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6294 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6295 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6296 6297 if (!CHIP_IS_E1x(bp)) { 6298 /* reset VFC memories */ 6299 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6300 VFC_MEMORIES_RST_REG_CAM_RST | 6301 VFC_MEMORIES_RST_REG_RAM_RST); 6302 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6303 VFC_MEMORIES_RST_REG_CAM_RST | 6304 VFC_MEMORIES_RST_REG_RAM_RST); 6305 6306 msleep(20); 6307 } 6308 6309 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6310 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6311 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6312 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6313 6314 /* sync semi rtc */ 6315 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6316 0x80000000); 6317 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6318 0x80000000); 6319 6320 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6321 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6322 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6323 6324 if (!CHIP_IS_E1x(bp)) 6325 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6326 bp->path_has_ovlan ? 7 : 6); 6327 6328 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6329 6330 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6331 6332#ifdef BCM_CNIC 6333 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6334 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6335 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6336 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6337 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6338 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6339 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6340 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6341 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6342 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6343#endif 6344 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6345 6346 if (sizeof(union cdu_context) != 1024) 6347 /* we currently assume that a context is 1024 bytes */ 6348 dev_alert(&bp->pdev->dev, "please adjust the size " 6349 "of cdu_context(%ld)\n", 6350 (long)sizeof(union cdu_context)); 6351 6352 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6353 val = (4 << 24) + (0 << 12) + 1024; 6354 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6355 6356 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6357 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6358 /* enable context validation interrupt from CFC */ 6359 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6360 6361 /* set the thresholds to prevent CFC/CDU race */ 6362 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6363 6364 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6365 6366 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6367 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6368 6369 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6370 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6371 6372 /* Reset PCIE errors for debug */ 6373 REG_WR(bp, 0x2814, 0xffffffff); 6374 REG_WR(bp, 0x3820, 0xffffffff); 6375 6376 if (!CHIP_IS_E1x(bp)) { 6377 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6378 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6379 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6380 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6381 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6382 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6383 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6384 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6385 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6386 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6387 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6388 } 6389 6390 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6391 if (!CHIP_IS_E1(bp)) { 6392 /* in E3 this done in per-port section */ 6393 if (!CHIP_IS_E3(bp)) 6394 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6395 } 6396 if (CHIP_IS_E1H(bp)) 6397 /* not applicable for E2 (and above ...) */ 6398 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6399 6400 if (CHIP_REV_IS_SLOW(bp)) 6401 msleep(200); 6402 6403 /* finish CFC init */ 6404 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6405 if (val != 1) { 6406 BNX2X_ERR("CFC LL_INIT failed\n"); 6407 return -EBUSY; 6408 } 6409 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6410 if (val != 1) { 6411 BNX2X_ERR("CFC AC_INIT failed\n"); 6412 return -EBUSY; 6413 } 6414 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6415 if (val != 1) { 6416 BNX2X_ERR("CFC CAM_INIT failed\n"); 6417 return -EBUSY; 6418 } 6419 REG_WR(bp, CFC_REG_DEBUG0, 0); 6420 6421 if (CHIP_IS_E1(bp)) { 6422 /* read NIG statistic 6423 to see if this is our first up since powerup */ 6424 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6425 val = *bnx2x_sp(bp, wb_data[0]); 6426 6427 /* do internal memory self test */ 6428 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6429 BNX2X_ERR("internal mem self test failed\n"); 6430 return -EBUSY; 6431 } 6432 } 6433 6434 bnx2x_setup_fan_failure_detection(bp); 6435 6436 /* clear PXP2 attentions */ 6437 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6438 6439 bnx2x_enable_blocks_attention(bp); 6440 bnx2x_enable_blocks_parity(bp); 6441 6442 if (!BP_NOMCP(bp)) { 6443 if (CHIP_IS_E1x(bp)) 6444 bnx2x__common_init_phy(bp); 6445 } else 6446 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6447 6448 return 0; 6449} 6450 6451/** 6452 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6453 * 6454 * @bp: driver handle 6455 */ 6456static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6457{ 6458 int rc = bnx2x_init_hw_common(bp); 6459 6460 if (rc) 6461 return rc; 6462 6463 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6464 if (!BP_NOMCP(bp)) 6465 bnx2x__common_init_phy(bp); 6466 6467 return 0; 6468} 6469 6470static int bnx2x_init_hw_port(struct bnx2x *bp) 6471{ 6472 int port = BP_PORT(bp); 6473 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6474 u32 low, high; 6475 u32 val; 6476 6477 bnx2x__link_reset(bp); 6478 6479 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6480 6481 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6482 6483 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6484 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6485 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6486 6487 /* Timers bug workaround: disables the pf_master bit in pglue at 6488 * common phase, we need to enable it here before any dmae access are 6489 * attempted. Therefore we manually added the enable-master to the 6490 * port phase (it also happens in the function phase) 6491 */ 6492 if (!CHIP_IS_E1x(bp)) 6493 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6494 6495 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6496 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6497 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6498 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6499 6500 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6501 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6502 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6503 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6504 6505 /* QM cid (connection) count */ 6506 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6507 6508#ifdef BCM_CNIC 6509 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6510 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6511 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6512#endif 6513 6514 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6515 6516 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6517 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6518 6519 if (IS_MF(bp)) 6520 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6521 else if (bp->dev->mtu > 4096) { 6522 if (bp->flags & ONE_PORT_FLAG) 6523 low = 160; 6524 else { 6525 val = bp->dev->mtu; 6526 /* (24*1024 + val*4)/256 */ 6527 low = 96 + (val/64) + 6528 ((val % 64) ? 1 : 0); 6529 } 6530 } else 6531 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6532 high = low + 56; /* 14*1024/256 */ 6533 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6534 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6535 } 6536 6537 if (CHIP_MODE_IS_4_PORT(bp)) 6538 REG_WR(bp, (BP_PORT(bp) ? 6539 BRB1_REG_MAC_GUARANTIED_1 : 6540 BRB1_REG_MAC_GUARANTIED_0), 40); 6541 6542 6543 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6544 if (CHIP_IS_E3B0(bp)) 6545 /* Ovlan exists only if we are in multi-function + 6546 * switch-dependent mode, in switch-independent there 6547 * is no ovlan headers 6548 */ 6549 REG_WR(bp, BP_PORT(bp) ? 6550 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6551 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6552 (bp->path_has_ovlan ? 7 : 6)); 6553 6554 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6555 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6556 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6557 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6558 6559 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6560 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6561 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6562 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6563 6564 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6565 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6566 6567 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6568 6569 if (CHIP_IS_E1x(bp)) { 6570 /* configure PBF to work without PAUSE mtu 9000 */ 6571 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6572 6573 /* update threshold */ 6574 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6575 /* update init credit */ 6576 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6577 6578 /* probe changes */ 6579 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6580 udelay(50); 6581 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6582 } 6583 6584#ifdef BCM_CNIC 6585 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6586#endif 6587 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6588 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6589 6590 if (CHIP_IS_E1(bp)) { 6591 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6592 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6593 } 6594 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6595 6596 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6597 6598 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6599 /* init aeu_mask_attn_func_0/1: 6600 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6601 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6602 * bits 4-7 are used for "per vn group attention" */ 6603 val = IS_MF(bp) ? 0xF7 : 0x7; 6604 /* Enable DCBX attention for all but E1 */ 6605 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6606 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6607 6608 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6609 6610 if (!CHIP_IS_E1x(bp)) { 6611 /* Bit-map indicating which L2 hdrs may appear after the 6612 * basic Ethernet header 6613 */ 6614 REG_WR(bp, BP_PORT(bp) ? 6615 NIG_REG_P1_HDRS_AFTER_BASIC : 6616 NIG_REG_P0_HDRS_AFTER_BASIC, 6617 IS_MF_SD(bp) ? 7 : 6); 6618 6619 if (CHIP_IS_E3(bp)) 6620 REG_WR(bp, BP_PORT(bp) ? 6621 NIG_REG_LLH1_MF_MODE : 6622 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6623 } 6624 if (!CHIP_IS_E3(bp)) 6625 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6626 6627 if (!CHIP_IS_E1(bp)) { 6628 /* 0x2 disable mf_ov, 0x1 enable */ 6629 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6630 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6631 6632 if (!CHIP_IS_E1x(bp)) { 6633 val = 0; 6634 switch (bp->mf_mode) { 6635 case MULTI_FUNCTION_SD: 6636 val = 1; 6637 break; 6638 case MULTI_FUNCTION_SI: 6639 val = 2; 6640 break; 6641 } 6642 6643 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6644 NIG_REG_LLH0_CLS_TYPE), val); 6645 } 6646 { 6647 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6648 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6649 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6650 } 6651 } 6652 6653 6654 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6655 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6656 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6657 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6658 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6659 val = REG_RD(bp, reg_addr); 6660 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6661 REG_WR(bp, reg_addr, val); 6662 } 6663 6664 return 0; 6665} 6666 6667static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6668{ 6669 int reg; 6670 6671 if (CHIP_IS_E1(bp)) 6672 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6673 else 6674 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6675 6676 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6677} 6678 6679static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6680{ 6681 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6682} 6683 6684static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6685{ 6686 u32 i, base = FUNC_ILT_BASE(func); 6687 for (i = base; i < base + ILT_PER_FUNC; i++) 6688 bnx2x_ilt_wr(bp, i, 0); 6689} 6690 6691static int bnx2x_init_hw_func(struct bnx2x *bp) 6692{ 6693 int port = BP_PORT(bp); 6694 int func = BP_FUNC(bp); 6695 int init_phase = PHASE_PF0 + func; 6696 struct bnx2x_ilt *ilt = BP_ILT(bp); 6697 u16 cdu_ilt_start; 6698 u32 addr, val; 6699 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6700 int i, main_mem_width, rc; 6701 6702 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6703 6704 /* FLR cleanup - hmmm */ 6705 if (!CHIP_IS_E1x(bp)) { 6706 rc = bnx2x_pf_flr_clnup(bp); 6707 if (rc) 6708 return rc; 6709 } 6710 6711 /* set MSI reconfigure capability */ 6712 if (bp->common.int_block == INT_BLOCK_HC) { 6713 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6714 val = REG_RD(bp, addr); 6715 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6716 REG_WR(bp, addr, val); 6717 } 6718 6719 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6720 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6721 6722 ilt = BP_ILT(bp); 6723 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6724 6725 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6726 ilt->lines[cdu_ilt_start + i].page = 6727 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6728 ilt->lines[cdu_ilt_start + i].page_mapping = 6729 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6730 /* cdu ilt pages are allocated manually so there's no need to 6731 set the size */ 6732 } 6733 bnx2x_ilt_init_op(bp, INITOP_SET); 6734 6735#ifdef BCM_CNIC 6736 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6737 6738 /* T1 hash bits value determines the T1 number of entries */ 6739 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6740#endif 6741 6742#ifndef BCM_CNIC 6743 /* set NIC mode */ 6744 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6745#endif /* BCM_CNIC */ 6746 6747 if (!CHIP_IS_E1x(bp)) { 6748 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6749 6750 /* Turn on a single ISR mode in IGU if driver is going to use 6751 * INT#x or MSI 6752 */ 6753 if (!(bp->flags & USING_MSIX_FLAG)) 6754 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6755 /* 6756 * Timers workaround bug: function init part. 6757 * Need to wait 20msec after initializing ILT, 6758 * needed to make sure there are no requests in 6759 * one of the PXP internal queues with "old" ILT addresses 6760 */ 6761 msleep(20); 6762 /* 6763 * Master enable - Due to WB DMAE writes performed before this 6764 * register is re-initialized as part of the regular function 6765 * init 6766 */ 6767 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6768 /* Enable the function in IGU */ 6769 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6770 } 6771 6772 bp->dmae_ready = 1; 6773 6774 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6775 6776 if (!CHIP_IS_E1x(bp)) 6777 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6778 6779 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6780 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6781 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6782 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6783 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6784 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6785 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6786 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6787 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6788 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6789 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6790 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6791 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6792 6793 if (!CHIP_IS_E1x(bp)) 6794 REG_WR(bp, QM_REG_PF_EN, 1); 6795 6796 if (!CHIP_IS_E1x(bp)) { 6797 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6798 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6799 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6800 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6801 } 6802 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6803 6804 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6805 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6806 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6807 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6808 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6809 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6810 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6811 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6812 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6813 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6814 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6815 if (!CHIP_IS_E1x(bp)) 6816 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6817 6818 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6819 6820 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6821 6822 if (!CHIP_IS_E1x(bp)) 6823 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6824 6825 if (IS_MF(bp)) { 6826 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6827 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6828 } 6829 6830 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6831 6832 /* HC init per function */ 6833 if (bp->common.int_block == INT_BLOCK_HC) { 6834 if (CHIP_IS_E1H(bp)) { 6835 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6836 6837 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6838 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6839 } 6840 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6841 6842 } else { 6843 int num_segs, sb_idx, prod_offset; 6844 6845 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6846 6847 if (!CHIP_IS_E1x(bp)) { 6848 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6849 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6850 } 6851 6852 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6853 6854 if (!CHIP_IS_E1x(bp)) { 6855 int dsb_idx = 0; 6856 /** 6857 * Producer memory: 6858 * E2 mode: address 0-135 match to the mapping memory; 6859 * 136 - PF0 default prod; 137 - PF1 default prod; 6860 * 138 - PF2 default prod; 139 - PF3 default prod; 6861 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6862 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6863 * 144-147 reserved. 6864 * 6865 * E1.5 mode - In backward compatible mode; 6866 * for non default SB; each even line in the memory 6867 * holds the U producer and each odd line hold 6868 * the C producer. The first 128 producers are for 6869 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6870 * producers are for the DSB for each PF. 6871 * Each PF has five segments: (the order inside each 6872 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6873 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6874 * 144-147 attn prods; 6875 */ 6876 /* non-default-status-blocks */ 6877 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6878 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6879 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6880 prod_offset = (bp->igu_base_sb + sb_idx) * 6881 num_segs; 6882 6883 for (i = 0; i < num_segs; i++) { 6884 addr = IGU_REG_PROD_CONS_MEMORY + 6885 (prod_offset + i) * 4; 6886 REG_WR(bp, addr, 0); 6887 } 6888 /* send consumer update with value 0 */ 6889 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6890 USTORM_ID, 0, IGU_INT_NOP, 1); 6891 bnx2x_igu_clear_sb(bp, 6892 bp->igu_base_sb + sb_idx); 6893 } 6894 6895 /* default-status-blocks */ 6896 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6897 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6898 6899 if (CHIP_MODE_IS_4_PORT(bp)) 6900 dsb_idx = BP_FUNC(bp); 6901 else 6902 dsb_idx = BP_VN(bp); 6903 6904 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6905 IGU_BC_BASE_DSB_PROD + dsb_idx : 6906 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6907 6908 /* 6909 * igu prods come in chunks of E1HVN_MAX (4) - 6910 * does not matters what is the current chip mode 6911 */ 6912 for (i = 0; i < (num_segs * E1HVN_MAX); 6913 i += E1HVN_MAX) { 6914 addr = IGU_REG_PROD_CONS_MEMORY + 6915 (prod_offset + i)*4; 6916 REG_WR(bp, addr, 0); 6917 } 6918 /* send consumer update with 0 */ 6919 if (CHIP_INT_MODE_IS_BC(bp)) { 6920 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6921 USTORM_ID, 0, IGU_INT_NOP, 1); 6922 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6923 CSTORM_ID, 0, IGU_INT_NOP, 1); 6924 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6925 XSTORM_ID, 0, IGU_INT_NOP, 1); 6926 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6927 TSTORM_ID, 0, IGU_INT_NOP, 1); 6928 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6929 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6930 } else { 6931 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6932 USTORM_ID, 0, IGU_INT_NOP, 1); 6933 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6934 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6935 } 6936 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6937 6938 /* !!! these should become driver const once 6939 rf-tool supports split-68 const */ 6940 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6941 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6942 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6943 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6944 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6945 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6946 } 6947 } 6948 6949 /* Reset PCIE errors for debug */ 6950 REG_WR(bp, 0x2114, 0xffffffff); 6951 REG_WR(bp, 0x2120, 0xffffffff); 6952 6953 if (CHIP_IS_E1x(bp)) { 6954 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6955 main_mem_base = HC_REG_MAIN_MEMORY + 6956 BP_PORT(bp) * (main_mem_size * 4); 6957 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6958 main_mem_width = 8; 6959 6960 val = REG_RD(bp, main_mem_prty_clr); 6961 if (val) 6962 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6963 "block during " 6964 "function init (0x%x)!\n", val); 6965 6966 /* Clear "false" parity errors in MSI-X table */ 6967 for (i = main_mem_base; 6968 i < main_mem_base + main_mem_size * 4; 6969 i += main_mem_width) { 6970 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6971 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6972 i, main_mem_width / 4); 6973 } 6974 /* Clear HC parity attention */ 6975 REG_RD(bp, main_mem_prty_clr); 6976 } 6977 6978#ifdef BNX2X_STOP_ON_ERROR 6979 /* Enable STORMs SP logging */ 6980 REG_WR8(bp, BAR_USTRORM_INTMEM + 6981 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6982 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6983 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6984 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6985 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6986 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6987 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6988#endif 6989 6990 bnx2x_phy_probe(&bp->link_params); 6991 6992 return 0; 6993} 6994 6995 6996void bnx2x_free_mem(struct bnx2x *bp) 6997{ 6998 /* fastpath */ 6999 bnx2x_free_fp_mem(bp); 7000 /* end of fastpath */ 7001 7002 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 7003 sizeof(struct host_sp_status_block)); 7004 7005 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7006 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7007 7008 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 7009 sizeof(struct bnx2x_slowpath)); 7010 7011 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 7012 bp->context.size); 7013 7014 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 7015 7016 BNX2X_FREE(bp->ilt->lines); 7017 7018#ifdef BCM_CNIC 7019 if (!CHIP_IS_E1x(bp)) 7020 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 7021 sizeof(struct host_hc_status_block_e2)); 7022 else 7023 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 7024 sizeof(struct host_hc_status_block_e1x)); 7025 7026 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7027#endif 7028 7029 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7030 7031 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7032 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7033} 7034 7035static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7036{ 7037 int num_groups; 7038 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7039 7040 /* number of queues for statistics is number of eth queues + FCoE */ 7041 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7042 7043 /* Total number of FW statistics requests = 7044 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7045 * num of queues 7046 */ 7047 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7048 7049 7050 /* Request is built from stats_query_header and an array of 7051 * stats_query_cmd_group each of which contains 7052 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7053 * configured in the stats_query_header. 7054 */ 7055 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7056 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7057 7058 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7059 num_groups * sizeof(struct stats_query_cmd_group); 7060 7061 /* Data for statistics requests + stats_conter 7062 * 7063 * stats_counter holds per-STORM counters that are incremented 7064 * when STORM has finished with the current request. 7065 * 7066 * memory for FCoE offloaded statistics are counted anyway, 7067 * even if they will not be sent. 7068 */ 7069 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7070 sizeof(struct per_pf_stats) + 7071 sizeof(struct fcoe_statistics_params) + 7072 sizeof(struct per_queue_stats) * num_queue_stats + 7073 sizeof(struct stats_counter); 7074 7075 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7076 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7077 7078 /* Set shortcuts */ 7079 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7080 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7081 7082 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7083 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7084 7085 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7086 bp->fw_stats_req_sz; 7087 return 0; 7088 7089alloc_mem_err: 7090 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7091 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7092 return -ENOMEM; 7093} 7094 7095 7096int bnx2x_alloc_mem(struct bnx2x *bp) 7097{ 7098#ifdef BCM_CNIC 7099 if (!CHIP_IS_E1x(bp)) 7100 /* size = the status block + ramrod buffers */ 7101 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7102 sizeof(struct host_hc_status_block_e2)); 7103 else 7104 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7105 sizeof(struct host_hc_status_block_e1x)); 7106 7107 /* allocate searcher T2 table */ 7108 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7109#endif 7110 7111 7112 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7113 sizeof(struct host_sp_status_block)); 7114 7115 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7116 sizeof(struct bnx2x_slowpath)); 7117 7118#ifdef BCM_CNIC 7119 /* write address to which L5 should insert its values */ 7120 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp; 7121#endif 7122 7123 /* Allocated memory for FW statistics */ 7124 if (bnx2x_alloc_fw_stats_mem(bp)) 7125 goto alloc_mem_err; 7126 7127 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7128 7129 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7130 bp->context.size); 7131 7132 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7133 7134 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7135 goto alloc_mem_err; 7136 7137 /* Slow path ring */ 7138 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7139 7140 /* EQ */ 7141 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7142 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7143 7144 7145 /* fastpath */ 7146 /* need to be done at the end, since it's self adjusting to amount 7147 * of memory available for RSS queues 7148 */ 7149 if (bnx2x_alloc_fp_mem(bp)) 7150 goto alloc_mem_err; 7151 return 0; 7152 7153alloc_mem_err: 7154 bnx2x_free_mem(bp); 7155 return -ENOMEM; 7156} 7157 7158/* 7159 * Init service functions 7160 */ 7161 7162int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7163 struct bnx2x_vlan_mac_obj *obj, bool set, 7164 int mac_type, unsigned long *ramrod_flags) 7165{ 7166 int rc; 7167 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7168 7169 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7170 7171 /* Fill general parameters */ 7172 ramrod_param.vlan_mac_obj = obj; 7173 ramrod_param.ramrod_flags = *ramrod_flags; 7174 7175 /* Fill a user request section if needed */ 7176 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7177 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7178 7179 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7180 7181 /* Set the command: ADD or DEL */ 7182 if (set) 7183 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7184 else 7185 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7186 } 7187 7188 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7189 if (rc < 0) 7190 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7191 return rc; 7192} 7193 7194int bnx2x_del_all_macs(struct bnx2x *bp, 7195 struct bnx2x_vlan_mac_obj *mac_obj, 7196 int mac_type, bool wait_for_comp) 7197{ 7198 int rc; 7199 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7200 7201 /* Wait for completion of requested */ 7202 if (wait_for_comp) 7203 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7204 7205 /* Set the mac type of addresses we want to clear */ 7206 __set_bit(mac_type, &vlan_mac_flags); 7207 7208 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7209 if (rc < 0) 7210 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7211 7212 return rc; 7213} 7214 7215int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7216{ 7217 unsigned long ramrod_flags = 0; 7218 7219#ifdef BCM_CNIC 7220 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) { 7221 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n"); 7222 return 0; 7223 } 7224#endif 7225 7226 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7227 7228 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7229 /* Eth MAC is set on RSS leading client (fp[0]) */ 7230 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7231 BNX2X_ETH_MAC, &ramrod_flags); 7232} 7233 7234int bnx2x_setup_leading(struct bnx2x *bp) 7235{ 7236 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7237} 7238 7239/** 7240 * bnx2x_set_int_mode - configure interrupt mode 7241 * 7242 * @bp: driver handle 7243 * 7244 * In case of MSI-X it will also try to enable MSI-X. 7245 */ 7246static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7247{ 7248 switch (int_mode) { 7249 case INT_MODE_MSI: 7250 bnx2x_enable_msi(bp); 7251 /* falling through... */ 7252 case INT_MODE_INTx: 7253 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7254 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7255 break; 7256 default: 7257 /* Set number of queues according to bp->multi_mode value */ 7258 bnx2x_set_num_queues(bp); 7259 7260 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7261 bp->num_queues); 7262 7263 /* if we can't use MSI-X we only need one fp, 7264 * so try to enable MSI-X with the requested number of fp's 7265 * and fallback to MSI or legacy INTx with one fp 7266 */ 7267 if (bnx2x_enable_msix(bp)) { 7268 /* failed to enable MSI-X */ 7269 if (bp->multi_mode) 7270 DP(NETIF_MSG_IFUP, 7271 "Multi requested but failed to " 7272 "enable MSI-X (%d), " 7273 "set number of queues to %d\n", 7274 bp->num_queues, 7275 1 + NON_ETH_CONTEXT_USE); 7276 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7277 7278 /* Try to enable MSI */ 7279 if (!(bp->flags & DISABLE_MSI_FLAG)) 7280 bnx2x_enable_msi(bp); 7281 } 7282 break; 7283 } 7284} 7285 7286/* must be called prioir to any HW initializations */ 7287static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7288{ 7289 return L2_ILT_LINES(bp); 7290} 7291 7292void bnx2x_ilt_set_info(struct bnx2x *bp) 7293{ 7294 struct ilt_client_info *ilt_client; 7295 struct bnx2x_ilt *ilt = BP_ILT(bp); 7296 u16 line = 0; 7297 7298 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7299 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7300 7301 /* CDU */ 7302 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7303 ilt_client->client_num = ILT_CLIENT_CDU; 7304 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7305 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7306 ilt_client->start = line; 7307 line += bnx2x_cid_ilt_lines(bp); 7308#ifdef BCM_CNIC 7309 line += CNIC_ILT_LINES; 7310#endif 7311 ilt_client->end = line - 1; 7312 7313 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7314 "flags 0x%x, hw psz %d\n", 7315 ilt_client->start, 7316 ilt_client->end, 7317 ilt_client->page_size, 7318 ilt_client->flags, 7319 ilog2(ilt_client->page_size >> 12)); 7320 7321 /* QM */ 7322 if (QM_INIT(bp->qm_cid_count)) { 7323 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7324 ilt_client->client_num = ILT_CLIENT_QM; 7325 ilt_client->page_size = QM_ILT_PAGE_SZ; 7326 ilt_client->flags = 0; 7327 ilt_client->start = line; 7328 7329 /* 4 bytes for each cid */ 7330 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7331 QM_ILT_PAGE_SZ); 7332 7333 ilt_client->end = line - 1; 7334 7335 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7336 "flags 0x%x, hw psz %d\n", 7337 ilt_client->start, 7338 ilt_client->end, 7339 ilt_client->page_size, 7340 ilt_client->flags, 7341 ilog2(ilt_client->page_size >> 12)); 7342 7343 } 7344 /* SRC */ 7345 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7346#ifdef BCM_CNIC 7347 ilt_client->client_num = ILT_CLIENT_SRC; 7348 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7349 ilt_client->flags = 0; 7350 ilt_client->start = line; 7351 line += SRC_ILT_LINES; 7352 ilt_client->end = line - 1; 7353 7354 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7355 "flags 0x%x, hw psz %d\n", 7356 ilt_client->start, 7357 ilt_client->end, 7358 ilt_client->page_size, 7359 ilt_client->flags, 7360 ilog2(ilt_client->page_size >> 12)); 7361 7362#else 7363 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7364#endif 7365 7366 /* TM */ 7367 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7368#ifdef BCM_CNIC 7369 ilt_client->client_num = ILT_CLIENT_TM; 7370 ilt_client->page_size = TM_ILT_PAGE_SZ; 7371 ilt_client->flags = 0; 7372 ilt_client->start = line; 7373 line += TM_ILT_LINES; 7374 ilt_client->end = line - 1; 7375 7376 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7377 "flags 0x%x, hw psz %d\n", 7378 ilt_client->start, 7379 ilt_client->end, 7380 ilt_client->page_size, 7381 ilt_client->flags, 7382 ilog2(ilt_client->page_size >> 12)); 7383 7384#else 7385 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7386#endif 7387 BUG_ON(line > ILT_MAX_LINES); 7388} 7389 7390/** 7391 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7392 * 7393 * @bp: driver handle 7394 * @fp: pointer to fastpath 7395 * @init_params: pointer to parameters structure 7396 * 7397 * parameters configured: 7398 * - HC configuration 7399 * - Queue's CDU context 7400 */ 7401static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7402 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7403{ 7404 7405 u8 cos; 7406 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7407 if (!IS_FCOE_FP(fp)) { 7408 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7409 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7410 7411 /* If HC is supporterd, enable host coalescing in the transition 7412 * to INIT state. 7413 */ 7414 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7415 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7416 7417 /* HC rate */ 7418 init_params->rx.hc_rate = bp->rx_ticks ? 7419 (1000000 / bp->rx_ticks) : 0; 7420 init_params->tx.hc_rate = bp->tx_ticks ? 7421 (1000000 / bp->tx_ticks) : 0; 7422 7423 /* FW SB ID */ 7424 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7425 fp->fw_sb_id; 7426 7427 /* 7428 * CQ index among the SB indices: FCoE clients uses the default 7429 * SB, therefore it's different. 7430 */ 7431 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7432 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7433 } 7434 7435 /* set maximum number of COSs supported by this queue */ 7436 init_params->max_cos = fp->max_cos; 7437 7438 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7439 fp->index, init_params->max_cos); 7440 7441 /* set the context pointers queue object */ 7442 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7443 init_params->cxts[cos] = 7444 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7445} 7446 7447int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7448 struct bnx2x_queue_state_params *q_params, 7449 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7450 int tx_index, bool leading) 7451{ 7452 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7453 7454 /* Set the command */ 7455 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7456 7457 /* Set tx-only QUEUE flags: don't zero statistics */ 7458 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7459 7460 /* choose the index of the cid to send the slow path on */ 7461 tx_only_params->cid_index = tx_index; 7462 7463 /* Set general TX_ONLY_SETUP parameters */ 7464 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7465 7466 /* Set Tx TX_ONLY_SETUP parameters */ 7467 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7468 7469 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7470 "cos %d, primary cid %d, cid %d, " 7471 "client id %d, sp-client id %d, flags %lx\n", 7472 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7473 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7474 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7475 7476 /* send the ramrod */ 7477 return bnx2x_queue_state_change(bp, q_params); 7478} 7479 7480 7481/** 7482 * bnx2x_setup_queue - setup queue 7483 * 7484 * @bp: driver handle 7485 * @fp: pointer to fastpath 7486 * @leading: is leading 7487 * 7488 * This function performs 2 steps in a Queue state machine 7489 * actually: 1) RESET->INIT 2) INIT->SETUP 7490 */ 7491 7492int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7493 bool leading) 7494{ 7495 struct bnx2x_queue_state_params q_params = {0}; 7496 struct bnx2x_queue_setup_params *setup_params = 7497 &q_params.params.setup; 7498 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7499 &q_params.params.tx_only; 7500 int rc; 7501 u8 tx_index; 7502 7503 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7504 7505 /* reset IGU state skip FCoE L2 queue */ 7506 if (!IS_FCOE_FP(fp)) 7507 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7508 IGU_INT_ENABLE, 0); 7509 7510 q_params.q_obj = &fp->q_obj; 7511 /* We want to wait for completion in this context */ 7512 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7513 7514 /* Prepare the INIT parameters */ 7515 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7516 7517 /* Set the command */ 7518 q_params.cmd = BNX2X_Q_CMD_INIT; 7519 7520 /* Change the state to INIT */ 7521 rc = bnx2x_queue_state_change(bp, &q_params); 7522 if (rc) { 7523 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7524 return rc; 7525 } 7526 7527 DP(BNX2X_MSG_SP, "init complete\n"); 7528 7529 7530 /* Now move the Queue to the SETUP state... */ 7531 memset(setup_params, 0, sizeof(*setup_params)); 7532 7533 /* Set QUEUE flags */ 7534 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7535 7536 /* Set general SETUP parameters */ 7537 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7538 FIRST_TX_COS_INDEX); 7539 7540 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7541 &setup_params->rxq_params); 7542 7543 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7544 FIRST_TX_COS_INDEX); 7545 7546 /* Set the command */ 7547 q_params.cmd = BNX2X_Q_CMD_SETUP; 7548 7549 /* Change the state to SETUP */ 7550 rc = bnx2x_queue_state_change(bp, &q_params); 7551 if (rc) { 7552 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7553 return rc; 7554 } 7555 7556 /* loop through the relevant tx-only indices */ 7557 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7558 tx_index < fp->max_cos; 7559 tx_index++) { 7560 7561 /* prepare and send tx-only ramrod*/ 7562 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7563 tx_only_params, tx_index, leading); 7564 if (rc) { 7565 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7566 fp->index, tx_index); 7567 return rc; 7568 } 7569 } 7570 7571 return rc; 7572} 7573 7574static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7575{ 7576 struct bnx2x_fastpath *fp = &bp->fp[index]; 7577 struct bnx2x_fp_txdata *txdata; 7578 struct bnx2x_queue_state_params q_params = {0}; 7579 int rc, tx_index; 7580 7581 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7582 7583 q_params.q_obj = &fp->q_obj; 7584 /* We want to wait for completion in this context */ 7585 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7586 7587 7588 /* close tx-only connections */ 7589 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7590 tx_index < fp->max_cos; 7591 tx_index++){ 7592 7593 /* ascertain this is a normal queue*/ 7594 txdata = &fp->txdata[tx_index]; 7595 7596 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7597 txdata->txq_index); 7598 7599 /* send halt terminate on tx-only connection */ 7600 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7601 memset(&q_params.params.terminate, 0, 7602 sizeof(q_params.params.terminate)); 7603 q_params.params.terminate.cid_index = tx_index; 7604 7605 rc = bnx2x_queue_state_change(bp, &q_params); 7606 if (rc) 7607 return rc; 7608 7609 /* send halt terminate on tx-only connection */ 7610 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7611 memset(&q_params.params.cfc_del, 0, 7612 sizeof(q_params.params.cfc_del)); 7613 q_params.params.cfc_del.cid_index = tx_index; 7614 rc = bnx2x_queue_state_change(bp, &q_params); 7615 if (rc) 7616 return rc; 7617 } 7618 /* Stop the primary connection: */ 7619 /* ...halt the connection */ 7620 q_params.cmd = BNX2X_Q_CMD_HALT; 7621 rc = bnx2x_queue_state_change(bp, &q_params); 7622 if (rc) 7623 return rc; 7624 7625 /* ...terminate the connection */ 7626 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7627 memset(&q_params.params.terminate, 0, 7628 sizeof(q_params.params.terminate)); 7629 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7630 rc = bnx2x_queue_state_change(bp, &q_params); 7631 if (rc) 7632 return rc; 7633 /* ...delete cfc entry */ 7634 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7635 memset(&q_params.params.cfc_del, 0, 7636 sizeof(q_params.params.cfc_del)); 7637 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7638 return bnx2x_queue_state_change(bp, &q_params); 7639} 7640 7641 7642static void bnx2x_reset_func(struct bnx2x *bp) 7643{ 7644 int port = BP_PORT(bp); 7645 int func = BP_FUNC(bp); 7646 int i; 7647 7648 /* Disable the function in the FW */ 7649 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7650 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7651 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7652 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7653 7654 /* FP SBs */ 7655 for_each_eth_queue(bp, i) { 7656 struct bnx2x_fastpath *fp = &bp->fp[i]; 7657 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7658 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7659 SB_DISABLED); 7660 } 7661 7662#ifdef BCM_CNIC 7663 /* CNIC SB */ 7664 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7665 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7666 SB_DISABLED); 7667#endif 7668 /* SP SB */ 7669 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7670 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7671 SB_DISABLED); 7672 7673 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7674 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7675 0); 7676 7677 /* Configure IGU */ 7678 if (bp->common.int_block == INT_BLOCK_HC) { 7679 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7680 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7681 } else { 7682 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7683 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7684 } 7685 7686#ifdef BCM_CNIC 7687 /* Disable Timer scan */ 7688 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7689 /* 7690 * Wait for at least 10ms and up to 2 second for the timers scan to 7691 * complete 7692 */ 7693 for (i = 0; i < 200; i++) { 7694 msleep(10); 7695 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7696 break; 7697 } 7698#endif 7699 /* Clear ILT */ 7700 bnx2x_clear_func_ilt(bp, func); 7701 7702 /* Timers workaround bug for E2: if this is vnic-3, 7703 * we need to set the entire ilt range for this timers. 7704 */ 7705 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7706 struct ilt_client_info ilt_cli; 7707 /* use dummy TM client */ 7708 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7709 ilt_cli.start = 0; 7710 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7711 ilt_cli.client_num = ILT_CLIENT_TM; 7712 7713 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7714 } 7715 7716 /* this assumes that reset_port() called before reset_func()*/ 7717 if (!CHIP_IS_E1x(bp)) 7718 bnx2x_pf_disable(bp); 7719 7720 bp->dmae_ready = 0; 7721} 7722 7723static void bnx2x_reset_port(struct bnx2x *bp) 7724{ 7725 int port = BP_PORT(bp); 7726 u32 val; 7727 7728 /* Reset physical Link */ 7729 bnx2x__link_reset(bp); 7730 7731 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7732 7733 /* Do not rcv packets to BRB */ 7734 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7735 /* Do not direct rcv packets that are not for MCP to the BRB */ 7736 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7737 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7738 7739 /* Configure AEU */ 7740 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7741 7742 msleep(100); 7743 /* Check for BRB port occupancy */ 7744 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7745 if (val) 7746 DP(NETIF_MSG_IFDOWN, 7747 "BRB1 is not empty %d blocks are occupied\n", val); 7748 7749 /* TODO: Close Doorbell port? */ 7750} 7751 7752static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7753{ 7754 struct bnx2x_func_state_params func_params = {0}; 7755 7756 /* Prepare parameters for function state transitions */ 7757 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7758 7759 func_params.f_obj = &bp->func_obj; 7760 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7761 7762 func_params.params.hw_init.load_phase = load_code; 7763 7764 return bnx2x_func_state_change(bp, &func_params); 7765} 7766 7767static inline int bnx2x_func_stop(struct bnx2x *bp) 7768{ 7769 struct bnx2x_func_state_params func_params = {0}; 7770 int rc; 7771 7772 /* Prepare parameters for function state transitions */ 7773 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7774 func_params.f_obj = &bp->func_obj; 7775 func_params.cmd = BNX2X_F_CMD_STOP; 7776 7777 /* 7778 * Try to stop the function the 'good way'. If fails (in case 7779 * of a parity error during bnx2x_chip_cleanup()) and we are 7780 * not in a debug mode, perform a state transaction in order to 7781 * enable further HW_RESET transaction. 7782 */ 7783 rc = bnx2x_func_state_change(bp, &func_params); 7784 if (rc) { 7785#ifdef BNX2X_STOP_ON_ERROR 7786 return rc; 7787#else 7788 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7789 "transaction\n"); 7790 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7791 return bnx2x_func_state_change(bp, &func_params); 7792#endif 7793 } 7794 7795 return 0; 7796} 7797 7798/** 7799 * bnx2x_send_unload_req - request unload mode from the MCP. 7800 * 7801 * @bp: driver handle 7802 * @unload_mode: requested function's unload mode 7803 * 7804 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7805 */ 7806u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7807{ 7808 u32 reset_code = 0; 7809 int port = BP_PORT(bp); 7810 7811 /* Select the UNLOAD request mode */ 7812 if (unload_mode == UNLOAD_NORMAL) 7813 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7814 7815 else if (bp->flags & NO_WOL_FLAG) 7816 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7817 7818 else if (bp->wol) { 7819 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7820 u8 *mac_addr = bp->dev->dev_addr; 7821 u32 val; 7822 u16 pmc; 7823 7824 /* The mac address is written to entries 1-4 to 7825 * preserve entry 0 which is used by the PMF 7826 */ 7827 u8 entry = (BP_VN(bp) + 1)*8; 7828 7829 val = (mac_addr[0] << 8) | mac_addr[1]; 7830 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7831 7832 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7833 (mac_addr[4] << 8) | mac_addr[5]; 7834 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7835 7836 /* Enable the PME and clear the status */ 7837 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7838 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7839 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7840 7841 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7842 7843 } else 7844 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7845 7846 /* Send the request to the MCP */ 7847 if (!BP_NOMCP(bp)) 7848 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7849 else { 7850 int path = BP_PATH(bp); 7851 7852 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7853 "%d, %d, %d\n", 7854 path, load_count[path][0], load_count[path][1], 7855 load_count[path][2]); 7856 load_count[path][0]--; 7857 load_count[path][1 + port]--; 7858 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7859 "%d, %d, %d\n", 7860 path, load_count[path][0], load_count[path][1], 7861 load_count[path][2]); 7862 if (load_count[path][0] == 0) 7863 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7864 else if (load_count[path][1 + port] == 0) 7865 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7866 else 7867 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7868 } 7869 7870 return reset_code; 7871} 7872 7873/** 7874 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7875 * 7876 * @bp: driver handle 7877 */ 7878void bnx2x_send_unload_done(struct bnx2x *bp) 7879{ 7880 /* Report UNLOAD_DONE to MCP */ 7881 if (!BP_NOMCP(bp)) 7882 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7883} 7884 7885static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7886{ 7887 int tout = 50; 7888 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7889 7890 if (!bp->port.pmf) 7891 return 0; 7892 7893 /* 7894 * (assumption: No Attention from MCP at this stage) 7895 * PMF probably in the middle of TXdisable/enable transaction 7896 * 1. Sync IRS for default SB 7897 * 2. Sync SP queue - this guarantes us that attention handling started 7898 * 3. Wait, that TXdisable/enable transaction completes 7899 * 7900 * 1+2 guranty that if DCBx attention was scheduled it already changed 7901 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7902 * received complettion for the transaction the state is TX_STOPPED. 7903 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7904 * transaction. 7905 */ 7906 7907 /* make sure default SB ISR is done */ 7908 if (msix) 7909 synchronize_irq(bp->msix_table[0].vector); 7910 else 7911 synchronize_irq(bp->pdev->irq); 7912 7913 flush_workqueue(bnx2x_wq); 7914 7915 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7916 BNX2X_F_STATE_STARTED && tout--) 7917 msleep(20); 7918 7919 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7920 BNX2X_F_STATE_STARTED) { 7921#ifdef BNX2X_STOP_ON_ERROR 7922 return -EBUSY; 7923#else 7924 /* 7925 * Failed to complete the transaction in a "good way" 7926 * Force both transactions with CLR bit 7927 */ 7928 struct bnx2x_func_state_params func_params = {0}; 7929 7930 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7931 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7932 7933 func_params.f_obj = &bp->func_obj; 7934 __set_bit(RAMROD_DRV_CLR_ONLY, 7935 &func_params.ramrod_flags); 7936 7937 /* STARTED-->TX_ST0PPED */ 7938 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7939 bnx2x_func_state_change(bp, &func_params); 7940 7941 /* TX_ST0PPED-->STARTED */ 7942 func_params.cmd = BNX2X_F_CMD_TX_START; 7943 return bnx2x_func_state_change(bp, &func_params); 7944#endif 7945 } 7946 7947 return 0; 7948} 7949 7950void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7951{ 7952 int port = BP_PORT(bp); 7953 int i, rc = 0; 7954 u8 cos; 7955 struct bnx2x_mcast_ramrod_params rparam = {0}; 7956 u32 reset_code; 7957 7958 /* Wait until tx fastpath tasks complete */ 7959 for_each_tx_queue(bp, i) { 7960 struct bnx2x_fastpath *fp = &bp->fp[i]; 7961 7962 for_each_cos_in_tx_queue(fp, cos) 7963 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7964#ifdef BNX2X_STOP_ON_ERROR 7965 if (rc) 7966 return; 7967#endif 7968 } 7969 7970 /* Give HW time to discard old tx messages */ 7971 usleep_range(1000, 1000); 7972 7973 /* Clean all ETH MACs */ 7974 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7975 if (rc < 0) 7976 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7977 7978 /* Clean up UC list */ 7979 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7980 true); 7981 if (rc < 0) 7982 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7983 "%d\n", rc); 7984 7985 /* Disable LLH */ 7986 if (!CHIP_IS_E1(bp)) 7987 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7988 7989 /* Set "drop all" (stop Rx). 7990 * We need to take a netif_addr_lock() here in order to prevent 7991 * a race between the completion code and this code. 7992 */ 7993 netif_addr_lock_bh(bp->dev); 7994 /* Schedule the rx_mode command */ 7995 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7996 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7997 else 7998 bnx2x_set_storm_rx_mode(bp); 7999 8000 /* Cleanup multicast configuration */ 8001 rparam.mcast_obj = &bp->mcast_obj; 8002 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 8003 if (rc < 0) 8004 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 8005 8006 netif_addr_unlock_bh(bp->dev); 8007 8008 8009 8010 /* 8011 * Send the UNLOAD_REQUEST to the MCP. This will return if 8012 * this function should perform FUNC, PORT or COMMON HW 8013 * reset. 8014 */ 8015 reset_code = bnx2x_send_unload_req(bp, unload_mode); 8016 8017 /* 8018 * (assumption: No Attention from MCP at this stage) 8019 * PMF probably in the middle of TXdisable/enable transaction 8020 */ 8021 rc = bnx2x_func_wait_started(bp); 8022 if (rc) { 8023 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 8024#ifdef BNX2X_STOP_ON_ERROR 8025 return; 8026#endif 8027 } 8028 8029 /* Close multi and leading connections 8030 * Completions for ramrods are collected in a synchronous way 8031 */ 8032 for_each_queue(bp, i) 8033 if (bnx2x_stop_queue(bp, i)) 8034#ifdef BNX2X_STOP_ON_ERROR 8035 return; 8036#else 8037 goto unload_error; 8038#endif 8039 /* If SP settings didn't get completed so far - something 8040 * very wrong has happen. 8041 */ 8042 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8043 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8044 8045#ifndef BNX2X_STOP_ON_ERROR 8046unload_error: 8047#endif 8048 rc = bnx2x_func_stop(bp); 8049 if (rc) { 8050 BNX2X_ERR("Function stop failed!\n"); 8051#ifdef BNX2X_STOP_ON_ERROR 8052 return; 8053#endif 8054 } 8055 8056 /* Disable HW interrupts, NAPI */ 8057 bnx2x_netif_stop(bp, 1); 8058 8059 /* Release IRQs */ 8060 bnx2x_free_irq(bp); 8061 8062 /* Reset the chip */ 8063 rc = bnx2x_reset_hw(bp, reset_code); 8064 if (rc) 8065 BNX2X_ERR("HW_RESET failed\n"); 8066 8067 8068 /* Report UNLOAD_DONE to MCP */ 8069 bnx2x_send_unload_done(bp); 8070} 8071 8072void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8073{ 8074 u32 val; 8075 8076 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 8077 8078 if (CHIP_IS_E1(bp)) { 8079 int port = BP_PORT(bp); 8080 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8081 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8082 8083 val = REG_RD(bp, addr); 8084 val &= ~(0x300); 8085 REG_WR(bp, addr, val); 8086 } else { 8087 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8088 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8089 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8090 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8091 } 8092} 8093 8094/* Close gates #2, #3 and #4: */ 8095static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8096{ 8097 u32 val; 8098 8099 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8100 if (!CHIP_IS_E1(bp)) { 8101 /* #4 */ 8102 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8103 /* #2 */ 8104 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8105 } 8106 8107 /* #3 */ 8108 if (CHIP_IS_E1x(bp)) { 8109 /* Prevent interrupts from HC on both ports */ 8110 val = REG_RD(bp, HC_REG_CONFIG_1); 8111 REG_WR(bp, HC_REG_CONFIG_1, 8112 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8113 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8114 8115 val = REG_RD(bp, HC_REG_CONFIG_0); 8116 REG_WR(bp, HC_REG_CONFIG_0, 8117 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8118 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8119 } else { 8120 /* Prevent incomming interrupts in IGU */ 8121 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8122 8123 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8124 (!close) ? 8125 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8126 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8127 } 8128 8129 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 8130 close ? "closing" : "opening"); 8131 mmiowb(); 8132} 8133 8134#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8135 8136static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8137{ 8138 /* Do some magic... */ 8139 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8140 *magic_val = val & SHARED_MF_CLP_MAGIC; 8141 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8142} 8143 8144/** 8145 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8146 * 8147 * @bp: driver handle 8148 * @magic_val: old value of the `magic' bit. 8149 */ 8150static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8151{ 8152 /* Restore the `magic' bit value... */ 8153 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8154 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8155 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8156} 8157 8158/** 8159 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8160 * 8161 * @bp: driver handle 8162 * @magic_val: old value of 'magic' bit. 8163 * 8164 * Takes care of CLP configurations. 8165 */ 8166static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8167{ 8168 u32 shmem; 8169 u32 validity_offset; 8170 8171 DP(NETIF_MSG_HW, "Starting\n"); 8172 8173 /* Set `magic' bit in order to save MF config */ 8174 if (!CHIP_IS_E1(bp)) 8175 bnx2x_clp_reset_prep(bp, magic_val); 8176 8177 /* Get shmem offset */ 8178 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8179 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8180 8181 /* Clear validity map flags */ 8182 if (shmem > 0) 8183 REG_WR(bp, shmem + validity_offset, 0); 8184} 8185 8186#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8187#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8188 8189/** 8190 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8191 * 8192 * @bp: driver handle 8193 */ 8194static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8195{ 8196 /* special handling for emulation and FPGA, 8197 wait 10 times longer */ 8198 if (CHIP_REV_IS_SLOW(bp)) 8199 msleep(MCP_ONE_TIMEOUT*10); 8200 else 8201 msleep(MCP_ONE_TIMEOUT); 8202} 8203 8204/* 8205 * initializes bp->common.shmem_base and waits for validity signature to appear 8206 */ 8207static int bnx2x_init_shmem(struct bnx2x *bp) 8208{ 8209 int cnt = 0; 8210 u32 val = 0; 8211 8212 do { 8213 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8214 if (bp->common.shmem_base) { 8215 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8216 if (val & SHR_MEM_VALIDITY_MB) 8217 return 0; 8218 } 8219 8220 bnx2x_mcp_wait_one(bp); 8221 8222 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8223 8224 BNX2X_ERR("BAD MCP validity signature\n"); 8225 8226 return -ENODEV; 8227} 8228 8229static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8230{ 8231 int rc = bnx2x_init_shmem(bp); 8232 8233 /* Restore the `magic' bit value */ 8234 if (!CHIP_IS_E1(bp)) 8235 bnx2x_clp_reset_done(bp, magic_val); 8236 8237 return rc; 8238} 8239 8240static void bnx2x_pxp_prep(struct bnx2x *bp) 8241{ 8242 if (!CHIP_IS_E1(bp)) { 8243 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8244 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8245 mmiowb(); 8246 } 8247} 8248 8249/* 8250 * Reset the whole chip except for: 8251 * - PCIE core 8252 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8253 * one reset bit) 8254 * - IGU 8255 * - MISC (including AEU) 8256 * - GRC 8257 * - RBCN, RBCP 8258 */ 8259static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8260{ 8261 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8262 u32 global_bits2, stay_reset2; 8263 8264 /* 8265 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8266 * (per chip) blocks. 8267 */ 8268 global_bits2 = 8269 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8270 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8271 8272 /* Don't reset the following blocks */ 8273 not_reset_mask1 = 8274 MISC_REGISTERS_RESET_REG_1_RST_HC | 8275 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8276 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8277 8278 not_reset_mask2 = 8279 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8280 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8281 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8282 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8283 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8284 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8285 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8286 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8287 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8288 MISC_REGISTERS_RESET_REG_2_PGLC; 8289 8290 /* 8291 * Keep the following blocks in reset: 8292 * - all xxMACs are handled by the bnx2x_link code. 8293 */ 8294 stay_reset2 = 8295 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8296 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8297 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8298 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8299 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8300 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8301 MISC_REGISTERS_RESET_REG_2_XMAC | 8302 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8303 8304 /* Full reset masks according to the chip */ 8305 reset_mask1 = 0xffffffff; 8306 8307 if (CHIP_IS_E1(bp)) 8308 reset_mask2 = 0xffff; 8309 else if (CHIP_IS_E1H(bp)) 8310 reset_mask2 = 0x1ffff; 8311 else if (CHIP_IS_E2(bp)) 8312 reset_mask2 = 0xfffff; 8313 else /* CHIP_IS_E3 */ 8314 reset_mask2 = 0x3ffffff; 8315 8316 /* Don't reset global blocks unless we need to */ 8317 if (!global) 8318 reset_mask2 &= ~global_bits2; 8319 8320 /* 8321 * In case of attention in the QM, we need to reset PXP 8322 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8323 * because otherwise QM reset would release 'close the gates' shortly 8324 * before resetting the PXP, then the PSWRQ would send a write 8325 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8326 * read the payload data from PSWWR, but PSWWR would not 8327 * respond. The write queue in PGLUE would stuck, dmae commands 8328 * would not return. Therefore it's important to reset the second 8329 * reset register (containing the 8330 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8331 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8332 * bit). 8333 */ 8334 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8335 reset_mask2 & (~not_reset_mask2)); 8336 8337 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8338 reset_mask1 & (~not_reset_mask1)); 8339 8340 barrier(); 8341 mmiowb(); 8342 8343 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8344 reset_mask2 & (~stay_reset2)); 8345 8346 barrier(); 8347 mmiowb(); 8348 8349 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8350 mmiowb(); 8351} 8352 8353/** 8354 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8355 * It should get cleared in no more than 1s. 8356 * 8357 * @bp: driver handle 8358 * 8359 * It should get cleared in no more than 1s. Returns 0 if 8360 * pending writes bit gets cleared. 8361 */ 8362static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8363{ 8364 u32 cnt = 1000; 8365 u32 pend_bits = 0; 8366 8367 do { 8368 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8369 8370 if (pend_bits == 0) 8371 break; 8372 8373 usleep_range(1000, 1000); 8374 } while (cnt-- > 0); 8375 8376 if (cnt <= 0) { 8377 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8378 pend_bits); 8379 return -EBUSY; 8380 } 8381 8382 return 0; 8383} 8384 8385static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8386{ 8387 int cnt = 1000; 8388 u32 val = 0; 8389 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8390 8391 8392 /* Empty the Tetris buffer, wait for 1s */ 8393 do { 8394 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8395 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8396 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8397 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8398 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8399 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8400 ((port_is_idle_0 & 0x1) == 0x1) && 8401 ((port_is_idle_1 & 0x1) == 0x1) && 8402 (pgl_exp_rom2 == 0xffffffff)) 8403 break; 8404 usleep_range(1000, 1000); 8405 } while (cnt-- > 0); 8406 8407 if (cnt <= 0) { 8408 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8409 " are still" 8410 " outstanding read requests after 1s!\n"); 8411 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8412 " port_is_idle_0=0x%08x," 8413 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8414 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8415 pgl_exp_rom2); 8416 return -EAGAIN; 8417 } 8418 8419 barrier(); 8420 8421 /* Close gates #2, #3 and #4 */ 8422 bnx2x_set_234_gates(bp, true); 8423 8424 /* Poll for IGU VQs for 57712 and newer chips */ 8425 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8426 return -EAGAIN; 8427 8428 8429 /* TBD: Indicate that "process kill" is in progress to MCP */ 8430 8431 /* Clear "unprepared" bit */ 8432 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8433 barrier(); 8434 8435 /* Make sure all is written to the chip before the reset */ 8436 mmiowb(); 8437 8438 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8439 * PSWHST, GRC and PSWRD Tetris buffer. 8440 */ 8441 usleep_range(1000, 1000); 8442 8443 /* Prepare to chip reset: */ 8444 /* MCP */ 8445 if (global) 8446 bnx2x_reset_mcp_prep(bp, &val); 8447 8448 /* PXP */ 8449 bnx2x_pxp_prep(bp); 8450 barrier(); 8451 8452 /* reset the chip */ 8453 bnx2x_process_kill_chip_reset(bp, global); 8454 barrier(); 8455 8456 /* Recover after reset: */ 8457 /* MCP */ 8458 if (global && bnx2x_reset_mcp_comp(bp, val)) 8459 return -EAGAIN; 8460 8461 /* TBD: Add resetting the NO_MCP mode DB here */ 8462 8463 /* PXP */ 8464 bnx2x_pxp_prep(bp); 8465 8466 /* Open the gates #2, #3 and #4 */ 8467 bnx2x_set_234_gates(bp, false); 8468 8469 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8470 * reset state, re-enable attentions. */ 8471 8472 return 0; 8473} 8474 8475int bnx2x_leader_reset(struct bnx2x *bp) 8476{ 8477 int rc = 0; 8478 bool global = bnx2x_reset_is_global(bp); 8479 u32 load_code; 8480 8481 /* if not going to reset MCP - load "fake" driver to reset HW while 8482 * driver is owner of the HW 8483 */ 8484 if (!global && !BP_NOMCP(bp)) { 8485 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); 8486 if (!load_code) { 8487 BNX2X_ERR("MCP response failure, aborting\n"); 8488 rc = -EAGAIN; 8489 goto exit_leader_reset; 8490 } 8491 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 8492 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 8493 BNX2X_ERR("MCP unexpected resp, aborting\n"); 8494 rc = -EAGAIN; 8495 goto exit_leader_reset2; 8496 } 8497 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 8498 if (!load_code) { 8499 BNX2X_ERR("MCP response failure, aborting\n"); 8500 rc = -EAGAIN; 8501 goto exit_leader_reset2; 8502 } 8503 } 8504 8505 /* Try to recover after the failure */ 8506 if (bnx2x_process_kill(bp, global)) { 8507 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8508 "Aii!\n", BP_PATH(bp)); 8509 rc = -EAGAIN; 8510 goto exit_leader_reset2; 8511 } 8512 8513 /* 8514 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8515 * state. 8516 */ 8517 bnx2x_set_reset_done(bp); 8518 if (global) 8519 bnx2x_clear_reset_global(bp); 8520 8521exit_leader_reset2: 8522 /* unload "fake driver" if it was loaded */ 8523 if (!global && !BP_NOMCP(bp)) { 8524 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 8525 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8526 } 8527exit_leader_reset: 8528 bp->is_leader = 0; 8529 bnx2x_release_leader_lock(bp); 8530 smp_mb(); 8531 return rc; 8532} 8533 8534static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8535{ 8536 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8537 8538 /* Disconnect this device */ 8539 netif_device_detach(bp->dev); 8540 8541 /* 8542 * Block ifup for all function on this engine until "process kill" 8543 * or power cycle. 8544 */ 8545 bnx2x_set_reset_in_progress(bp); 8546 8547 /* Shut down the power */ 8548 bnx2x_set_power_state(bp, PCI_D3hot); 8549 8550 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8551 8552 smp_mb(); 8553} 8554 8555/* 8556 * Assumption: runs under rtnl lock. This together with the fact 8557 * that it's called only from bnx2x_sp_rtnl() ensure that it 8558 * will never be called when netif_running(bp->dev) is false. 8559 */ 8560static void bnx2x_parity_recover(struct bnx2x *bp) 8561{ 8562 bool global = false; 8563 u32 error_recovered, error_unrecovered; 8564 bool is_parity; 8565 8566 DP(NETIF_MSG_HW, "Handling parity\n"); 8567 while (1) { 8568 switch (bp->recovery_state) { 8569 case BNX2X_RECOVERY_INIT: 8570 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8571 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 8572 WARN_ON(!is_parity); 8573 8574 /* Try to get a LEADER_LOCK HW lock */ 8575 if (bnx2x_trylock_leader_lock(bp)) { 8576 bnx2x_set_reset_in_progress(bp); 8577 /* 8578 * Check if there is a global attention and if 8579 * there was a global attention, set the global 8580 * reset bit. 8581 */ 8582 8583 if (global) 8584 bnx2x_set_reset_global(bp); 8585 8586 bp->is_leader = 1; 8587 } 8588 8589 /* Stop the driver */ 8590 /* If interface has been removed - break */ 8591 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8592 return; 8593 8594 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8595 8596 /* Ensure "is_leader", MCP command sequence and 8597 * "recovery_state" update values are seen on other 8598 * CPUs. 8599 */ 8600 smp_mb(); 8601 break; 8602 8603 case BNX2X_RECOVERY_WAIT: 8604 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8605 if (bp->is_leader) { 8606 int other_engine = BP_PATH(bp) ? 0 : 1; 8607 bool other_load_status = 8608 bnx2x_get_load_status(bp, other_engine); 8609 bool load_status = 8610 bnx2x_get_load_status(bp, BP_PATH(bp)); 8611 global = bnx2x_reset_is_global(bp); 8612 8613 /* 8614 * In case of a parity in a global block, let 8615 * the first leader that performs a 8616 * leader_reset() reset the global blocks in 8617 * order to clear global attentions. Otherwise 8618 * the the gates will remain closed for that 8619 * engine. 8620 */ 8621 if (load_status || 8622 (global && other_load_status)) { 8623 /* Wait until all other functions get 8624 * down. 8625 */ 8626 schedule_delayed_work(&bp->sp_rtnl_task, 8627 HZ/10); 8628 return; 8629 } else { 8630 /* If all other functions got down - 8631 * try to bring the chip back to 8632 * normal. In any case it's an exit 8633 * point for a leader. 8634 */ 8635 if (bnx2x_leader_reset(bp)) { 8636 bnx2x_recovery_failed(bp); 8637 return; 8638 } 8639 8640 /* If we are here, means that the 8641 * leader has succeeded and doesn't 8642 * want to be a leader any more. Try 8643 * to continue as a none-leader. 8644 */ 8645 break; 8646 } 8647 } else { /* non-leader */ 8648 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8649 /* Try to get a LEADER_LOCK HW lock as 8650 * long as a former leader may have 8651 * been unloaded by the user or 8652 * released a leadership by another 8653 * reason. 8654 */ 8655 if (bnx2x_trylock_leader_lock(bp)) { 8656 /* I'm a leader now! Restart a 8657 * switch case. 8658 */ 8659 bp->is_leader = 1; 8660 break; 8661 } 8662 8663 schedule_delayed_work(&bp->sp_rtnl_task, 8664 HZ/10); 8665 return; 8666 8667 } else { 8668 /* 8669 * If there was a global attention, wait 8670 * for it to be cleared. 8671 */ 8672 if (bnx2x_reset_is_global(bp)) { 8673 schedule_delayed_work( 8674 &bp->sp_rtnl_task, 8675 HZ/10); 8676 return; 8677 } 8678 8679 error_recovered = 8680 bp->eth_stats.recoverable_error; 8681 error_unrecovered = 8682 bp->eth_stats.unrecoverable_error; 8683 bp->recovery_state = 8684 BNX2X_RECOVERY_NIC_LOADING; 8685 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 8686 error_unrecovered++; 8687 netdev_err(bp->dev, 8688 "Recovery failed. " 8689 "Power cycle " 8690 "needed\n"); 8691 /* Disconnect this device */ 8692 netif_device_detach(bp->dev); 8693 /* Shut down the power */ 8694 bnx2x_set_power_state( 8695 bp, PCI_D3hot); 8696 smp_mb(); 8697 } else { 8698 bp->recovery_state = 8699 BNX2X_RECOVERY_DONE; 8700 error_recovered++; 8701 smp_mb(); 8702 } 8703 bp->eth_stats.recoverable_error = 8704 error_recovered; 8705 bp->eth_stats.unrecoverable_error = 8706 error_unrecovered; 8707 8708 return; 8709 } 8710 } 8711 default: 8712 return; 8713 } 8714 } 8715} 8716 8717static int bnx2x_close(struct net_device *dev); 8718 8719/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8720 * scheduled on a general queue in order to prevent a dead lock. 8721 */ 8722static void bnx2x_sp_rtnl_task(struct work_struct *work) 8723{ 8724 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8725 8726 rtnl_lock(); 8727 8728 if (!netif_running(bp->dev)) 8729 goto sp_rtnl_exit; 8730 8731 /* if stop on error is defined no recovery flows should be executed */ 8732#ifdef BNX2X_STOP_ON_ERROR 8733 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8734 "so reset not done to allow debug dump,\n" 8735 "you will need to reboot when done\n"); 8736 goto sp_rtnl_not_reset; 8737#endif 8738 8739 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8740 /* 8741 * Clear all pending SP commands as we are going to reset the 8742 * function anyway. 8743 */ 8744 bp->sp_rtnl_state = 0; 8745 smp_mb(); 8746 8747 bnx2x_parity_recover(bp); 8748 8749 goto sp_rtnl_exit; 8750 } 8751 8752 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8753 /* 8754 * Clear all pending SP commands as we are going to reset the 8755 * function anyway. 8756 */ 8757 bp->sp_rtnl_state = 0; 8758 smp_mb(); 8759 8760 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8761 bnx2x_nic_load(bp, LOAD_NORMAL); 8762 8763 goto sp_rtnl_exit; 8764 } 8765#ifdef BNX2X_STOP_ON_ERROR 8766sp_rtnl_not_reset: 8767#endif 8768 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8769 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8770 8771 /* 8772 * in case of fan failure we need to reset id if the "stop on error" 8773 * debug flag is set, since we trying to prevent permanent overheating 8774 * damage 8775 */ 8776 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8777 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8778 netif_device_detach(bp->dev); 8779 bnx2x_close(bp->dev); 8780 } 8781 8782sp_rtnl_exit: 8783 rtnl_unlock(); 8784} 8785 8786/* end of nic load/unload */ 8787 8788static void bnx2x_period_task(struct work_struct *work) 8789{ 8790 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8791 8792 if (!netif_running(bp->dev)) 8793 goto period_task_exit; 8794 8795 if (CHIP_REV_IS_SLOW(bp)) { 8796 BNX2X_ERR("period task called on emulation, ignoring\n"); 8797 goto period_task_exit; 8798 } 8799 8800 bnx2x_acquire_phy_lock(bp); 8801 /* 8802 * The barrier is needed to ensure the ordering between the writing to 8803 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8804 * the reading here. 8805 */ 8806 smp_mb(); 8807 if (bp->port.pmf) { 8808 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8809 8810 /* Re-queue task in 1 sec */ 8811 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8812 } 8813 8814 bnx2x_release_phy_lock(bp); 8815period_task_exit: 8816 return; 8817} 8818 8819/* 8820 * Init service functions 8821 */ 8822 8823static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8824{ 8825 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8826 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8827 return base + (BP_ABS_FUNC(bp)) * stride; 8828} 8829 8830static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8831{ 8832 u32 reg = bnx2x_get_pretend_reg(bp); 8833 8834 /* Flush all outstanding writes */ 8835 mmiowb(); 8836 8837 /* Pretend to be function 0 */ 8838 REG_WR(bp, reg, 0); 8839 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8840 8841 /* From now we are in the "like-E1" mode */ 8842 bnx2x_int_disable(bp); 8843 8844 /* Flush all outstanding writes */ 8845 mmiowb(); 8846 8847 /* Restore the original function */ 8848 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8849 REG_RD(bp, reg); 8850} 8851 8852static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8853{ 8854 if (CHIP_IS_E1(bp)) 8855 bnx2x_int_disable(bp); 8856 else 8857 bnx2x_undi_int_disable_e1h(bp); 8858} 8859 8860static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8861{ 8862 u32 val; 8863 8864 /* possibly another driver is trying to reset the chip */ 8865 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8866 8867 /* check if doorbell queue is reset */ 8868 if (REG_RD(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET) 8869 & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 8870 8871 /* 8872 * Check if it is the UNDI driver 8873 * UNDI driver initializes CID offset for normal bell to 0x7 8874 */ 8875 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8876 if (val == 0x7) { 8877 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8878 /* save our pf_num */ 8879 int orig_pf_num = bp->pf_num; 8880 int port; 8881 u32 swap_en, swap_val, value; 8882 8883 /* clear the UNDI indication */ 8884 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8885 8886 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8887 8888 /* try unload UNDI on port 0 */ 8889 bp->pf_num = 0; 8890 bp->fw_seq = 8891 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8892 DRV_MSG_SEQ_NUMBER_MASK); 8893 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8894 8895 /* if UNDI is loaded on the other port */ 8896 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8897 8898 /* send "DONE" for previous unload */ 8899 bnx2x_fw_command(bp, 8900 DRV_MSG_CODE_UNLOAD_DONE, 0); 8901 8902 /* unload UNDI on port 1 */ 8903 bp->pf_num = 1; 8904 bp->fw_seq = 8905 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8906 DRV_MSG_SEQ_NUMBER_MASK); 8907 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8908 8909 bnx2x_fw_command(bp, reset_code, 0); 8910 } 8911 8912 bnx2x_undi_int_disable(bp); 8913 port = BP_PORT(bp); 8914 8915 /* close input traffic and wait for it */ 8916 /* Do not rcv packets to BRB */ 8917 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8918 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8919 /* Do not direct rcv packets that are not for MCP to 8920 * the BRB */ 8921 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8922 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8923 /* clear AEU */ 8924 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8925 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8926 msleep(10); 8927 8928 /* save NIG port swap info */ 8929 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8930 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8931 /* reset device */ 8932 REG_WR(bp, 8933 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8934 0xd3ffffff); 8935 8936 value = 0x1400; 8937 if (CHIP_IS_E3(bp)) { 8938 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8939 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8940 } 8941 8942 REG_WR(bp, 8943 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8944 value); 8945 8946 /* take the NIG out of reset and restore swap values */ 8947 REG_WR(bp, 8948 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8949 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8950 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8951 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8952 8953 /* send unload done to the MCP */ 8954 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8955 8956 /* restore our func and fw_seq */ 8957 bp->pf_num = orig_pf_num; 8958 } 8959 } 8960 8961 /* now it's safe to release the lock */ 8962 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8963} 8964 8965static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8966{ 8967 u32 val, val2, val3, val4, id, boot_mode; 8968 u16 pmc; 8969 8970 /* Get the chip revision id and number. */ 8971 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8972 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8973 id = ((val & 0xffff) << 16); 8974 val = REG_RD(bp, MISC_REG_CHIP_REV); 8975 id |= ((val & 0xf) << 12); 8976 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8977 id |= ((val & 0xff) << 4); 8978 val = REG_RD(bp, MISC_REG_BOND_ID); 8979 id |= (val & 0xf); 8980 bp->common.chip_id = id; 8981 8982 /* Set doorbell size */ 8983 bp->db_size = (1 << BNX2X_DB_SHIFT); 8984 8985 if (!CHIP_IS_E1x(bp)) { 8986 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8987 if ((val & 1) == 0) 8988 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8989 else 8990 val = (val >> 1) & 1; 8991 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8992 "2_PORT_MODE"); 8993 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8994 CHIP_2_PORT_MODE; 8995 8996 if (CHIP_MODE_IS_4_PORT(bp)) 8997 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8998 else 8999 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 9000 } else { 9001 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 9002 bp->pfid = bp->pf_num; /* 0..7 */ 9003 } 9004 9005 bp->link_params.chip_id = bp->common.chip_id; 9006 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 9007 9008 val = (REG_RD(bp, 0x2874) & 0x55); 9009 if ((bp->common.chip_id & 0x1) || 9010 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 9011 bp->flags |= ONE_PORT_FLAG; 9012 BNX2X_DEV_INFO("single port device\n"); 9013 } 9014 9015 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 9016 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 9017 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 9018 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 9019 bp->common.flash_size, bp->common.flash_size); 9020 9021 bnx2x_init_shmem(bp); 9022 9023 9024 9025 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 9026 MISC_REG_GENERIC_CR_1 : 9027 MISC_REG_GENERIC_CR_0)); 9028 9029 bp->link_params.shmem_base = bp->common.shmem_base; 9030 bp->link_params.shmem2_base = bp->common.shmem2_base; 9031 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 9032 bp->common.shmem_base, bp->common.shmem2_base); 9033 9034 if (!bp->common.shmem_base) { 9035 BNX2X_DEV_INFO("MCP not active\n"); 9036 bp->flags |= NO_MCP_FLAG; 9037 return; 9038 } 9039 9040 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 9041 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 9042 9043 bp->link_params.hw_led_mode = ((bp->common.hw_config & 9044 SHARED_HW_CFG_LED_MODE_MASK) >> 9045 SHARED_HW_CFG_LED_MODE_SHIFT); 9046 9047 bp->link_params.feature_config_flags = 0; 9048 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 9049 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 9050 bp->link_params.feature_config_flags |= 9051 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9052 else 9053 bp->link_params.feature_config_flags &= 9054 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9055 9056 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 9057 bp->common.bc_ver = val; 9058 BNX2X_DEV_INFO("bc_ver %X\n", val); 9059 if (val < BNX2X_BC_VER) { 9060 /* for now only warn 9061 * later we might need to enforce this */ 9062 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 9063 "please upgrade BC\n", BNX2X_BC_VER, val); 9064 } 9065 bp->link_params.feature_config_flags |= 9066 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9067 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 9068 9069 bp->link_params.feature_config_flags |= 9070 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 9071 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 9072 9073 bp->link_params.feature_config_flags |= 9074 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 9075 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 9076 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 9077 BC_SUPPORTS_PFC_STATS : 0; 9078 9079 boot_mode = SHMEM_RD(bp, 9080 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9081 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9082 switch (boot_mode) { 9083 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9084 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9085 break; 9086 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9087 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9088 break; 9089 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9090 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9091 break; 9092 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9093 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9094 break; 9095 } 9096 9097 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9098 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9099 9100 BNX2X_DEV_INFO("%sWoL capable\n", 9101 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9102 9103 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9104 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9105 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9106 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9107 9108 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9109 val, val2, val3, val4); 9110} 9111 9112#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9113#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9114 9115static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9116{ 9117 int pfid = BP_FUNC(bp); 9118 int igu_sb_id; 9119 u32 val; 9120 u8 fid, igu_sb_cnt = 0; 9121 9122 bp->igu_base_sb = 0xff; 9123 if (CHIP_INT_MODE_IS_BC(bp)) { 9124 int vn = BP_VN(bp); 9125 igu_sb_cnt = bp->igu_sb_cnt; 9126 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9127 FP_SB_MAX_E1x; 9128 9129 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9130 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9131 9132 return; 9133 } 9134 9135 /* IGU in normal mode - read CAM */ 9136 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9137 igu_sb_id++) { 9138 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9139 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9140 continue; 9141 fid = IGU_FID(val); 9142 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9143 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9144 continue; 9145 if (IGU_VEC(val) == 0) 9146 /* default status block */ 9147 bp->igu_dsb_id = igu_sb_id; 9148 else { 9149 if (bp->igu_base_sb == 0xff) 9150 bp->igu_base_sb = igu_sb_id; 9151 igu_sb_cnt++; 9152 } 9153 } 9154 } 9155 9156#ifdef CONFIG_PCI_MSI 9157 /* 9158 * It's expected that number of CAM entries for this functions is equal 9159 * to the number evaluated based on the MSI-X table size. We want a 9160 * harsh warning if these values are different! 9161 */ 9162 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9163#endif 9164 9165 if (igu_sb_cnt == 0) 9166 BNX2X_ERR("CAM configuration error\n"); 9167} 9168 9169static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9170 u32 switch_cfg) 9171{ 9172 int cfg_size = 0, idx, port = BP_PORT(bp); 9173 9174 /* Aggregation of supported attributes of all external phys */ 9175 bp->port.supported[0] = 0; 9176 bp->port.supported[1] = 0; 9177 switch (bp->link_params.num_phys) { 9178 case 1: 9179 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9180 cfg_size = 1; 9181 break; 9182 case 2: 9183 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9184 cfg_size = 1; 9185 break; 9186 case 3: 9187 if (bp->link_params.multi_phy_config & 9188 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9189 bp->port.supported[1] = 9190 bp->link_params.phy[EXT_PHY1].supported; 9191 bp->port.supported[0] = 9192 bp->link_params.phy[EXT_PHY2].supported; 9193 } else { 9194 bp->port.supported[0] = 9195 bp->link_params.phy[EXT_PHY1].supported; 9196 bp->port.supported[1] = 9197 bp->link_params.phy[EXT_PHY2].supported; 9198 } 9199 cfg_size = 2; 9200 break; 9201 } 9202 9203 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9204 BNX2X_ERR("NVRAM config error. BAD phy config." 9205 "PHY1 config 0x%x, PHY2 config 0x%x\n", 9206 SHMEM_RD(bp, 9207 dev_info.port_hw_config[port].external_phy_config), 9208 SHMEM_RD(bp, 9209 dev_info.port_hw_config[port].external_phy_config2)); 9210 return; 9211 } 9212 9213 if (CHIP_IS_E3(bp)) 9214 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9215 else { 9216 switch (switch_cfg) { 9217 case SWITCH_CFG_1G: 9218 bp->port.phy_addr = REG_RD( 9219 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9220 break; 9221 case SWITCH_CFG_10G: 9222 bp->port.phy_addr = REG_RD( 9223 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9224 break; 9225 default: 9226 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9227 bp->port.link_config[0]); 9228 return; 9229 } 9230 } 9231 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9232 /* mask what we support according to speed_cap_mask per configuration */ 9233 for (idx = 0; idx < cfg_size; idx++) { 9234 if (!(bp->link_params.speed_cap_mask[idx] & 9235 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9236 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9237 9238 if (!(bp->link_params.speed_cap_mask[idx] & 9239 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9240 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9241 9242 if (!(bp->link_params.speed_cap_mask[idx] & 9243 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9244 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9245 9246 if (!(bp->link_params.speed_cap_mask[idx] & 9247 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9248 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9249 9250 if (!(bp->link_params.speed_cap_mask[idx] & 9251 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9252 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9253 SUPPORTED_1000baseT_Full); 9254 9255 if (!(bp->link_params.speed_cap_mask[idx] & 9256 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9257 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9258 9259 if (!(bp->link_params.speed_cap_mask[idx] & 9260 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9261 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9262 9263 } 9264 9265 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9266 bp->port.supported[1]); 9267} 9268 9269static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9270{ 9271 u32 link_config, idx, cfg_size = 0; 9272 bp->port.advertising[0] = 0; 9273 bp->port.advertising[1] = 0; 9274 switch (bp->link_params.num_phys) { 9275 case 1: 9276 case 2: 9277 cfg_size = 1; 9278 break; 9279 case 3: 9280 cfg_size = 2; 9281 break; 9282 } 9283 for (idx = 0; idx < cfg_size; idx++) { 9284 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9285 link_config = bp->port.link_config[idx]; 9286 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9287 case PORT_FEATURE_LINK_SPEED_AUTO: 9288 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9289 bp->link_params.req_line_speed[idx] = 9290 SPEED_AUTO_NEG; 9291 bp->port.advertising[idx] |= 9292 bp->port.supported[idx]; 9293 if (bp->link_params.phy[EXT_PHY1].type == 9294 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 9295 bp->port.advertising[idx] |= 9296 (SUPPORTED_100baseT_Half | 9297 SUPPORTED_100baseT_Full); 9298 } else { 9299 /* force 10G, no AN */ 9300 bp->link_params.req_line_speed[idx] = 9301 SPEED_10000; 9302 bp->port.advertising[idx] |= 9303 (ADVERTISED_10000baseT_Full | 9304 ADVERTISED_FIBRE); 9305 continue; 9306 } 9307 break; 9308 9309 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9310 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9311 bp->link_params.req_line_speed[idx] = 9312 SPEED_10; 9313 bp->port.advertising[idx] |= 9314 (ADVERTISED_10baseT_Full | 9315 ADVERTISED_TP); 9316 } else { 9317 BNX2X_ERR("NVRAM config error. " 9318 "Invalid link_config 0x%x" 9319 " speed_cap_mask 0x%x\n", 9320 link_config, 9321 bp->link_params.speed_cap_mask[idx]); 9322 return; 9323 } 9324 break; 9325 9326 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9327 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9328 bp->link_params.req_line_speed[idx] = 9329 SPEED_10; 9330 bp->link_params.req_duplex[idx] = 9331 DUPLEX_HALF; 9332 bp->port.advertising[idx] |= 9333 (ADVERTISED_10baseT_Half | 9334 ADVERTISED_TP); 9335 } else { 9336 BNX2X_ERR("NVRAM config error. " 9337 "Invalid link_config 0x%x" 9338 " speed_cap_mask 0x%x\n", 9339 link_config, 9340 bp->link_params.speed_cap_mask[idx]); 9341 return; 9342 } 9343 break; 9344 9345 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9346 if (bp->port.supported[idx] & 9347 SUPPORTED_100baseT_Full) { 9348 bp->link_params.req_line_speed[idx] = 9349 SPEED_100; 9350 bp->port.advertising[idx] |= 9351 (ADVERTISED_100baseT_Full | 9352 ADVERTISED_TP); 9353 } else { 9354 BNX2X_ERR("NVRAM config error. " 9355 "Invalid link_config 0x%x" 9356 " speed_cap_mask 0x%x\n", 9357 link_config, 9358 bp->link_params.speed_cap_mask[idx]); 9359 return; 9360 } 9361 break; 9362 9363 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9364 if (bp->port.supported[idx] & 9365 SUPPORTED_100baseT_Half) { 9366 bp->link_params.req_line_speed[idx] = 9367 SPEED_100; 9368 bp->link_params.req_duplex[idx] = 9369 DUPLEX_HALF; 9370 bp->port.advertising[idx] |= 9371 (ADVERTISED_100baseT_Half | 9372 ADVERTISED_TP); 9373 } else { 9374 BNX2X_ERR("NVRAM config error. " 9375 "Invalid link_config 0x%x" 9376 " speed_cap_mask 0x%x\n", 9377 link_config, 9378 bp->link_params.speed_cap_mask[idx]); 9379 return; 9380 } 9381 break; 9382 9383 case PORT_FEATURE_LINK_SPEED_1G: 9384 if (bp->port.supported[idx] & 9385 SUPPORTED_1000baseT_Full) { 9386 bp->link_params.req_line_speed[idx] = 9387 SPEED_1000; 9388 bp->port.advertising[idx] |= 9389 (ADVERTISED_1000baseT_Full | 9390 ADVERTISED_TP); 9391 } else { 9392 BNX2X_ERR("NVRAM config error. " 9393 "Invalid link_config 0x%x" 9394 " speed_cap_mask 0x%x\n", 9395 link_config, 9396 bp->link_params.speed_cap_mask[idx]); 9397 return; 9398 } 9399 break; 9400 9401 case PORT_FEATURE_LINK_SPEED_2_5G: 9402 if (bp->port.supported[idx] & 9403 SUPPORTED_2500baseX_Full) { 9404 bp->link_params.req_line_speed[idx] = 9405 SPEED_2500; 9406 bp->port.advertising[idx] |= 9407 (ADVERTISED_2500baseX_Full | 9408 ADVERTISED_TP); 9409 } else { 9410 BNX2X_ERR("NVRAM config error. " 9411 "Invalid link_config 0x%x" 9412 " speed_cap_mask 0x%x\n", 9413 link_config, 9414 bp->link_params.speed_cap_mask[idx]); 9415 return; 9416 } 9417 break; 9418 9419 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9420 if (bp->port.supported[idx] & 9421 SUPPORTED_10000baseT_Full) { 9422 bp->link_params.req_line_speed[idx] = 9423 SPEED_10000; 9424 bp->port.advertising[idx] |= 9425 (ADVERTISED_10000baseT_Full | 9426 ADVERTISED_FIBRE); 9427 } else { 9428 BNX2X_ERR("NVRAM config error. " 9429 "Invalid link_config 0x%x" 9430 " speed_cap_mask 0x%x\n", 9431 link_config, 9432 bp->link_params.speed_cap_mask[idx]); 9433 return; 9434 } 9435 break; 9436 case PORT_FEATURE_LINK_SPEED_20G: 9437 bp->link_params.req_line_speed[idx] = SPEED_20000; 9438 9439 break; 9440 default: 9441 BNX2X_ERR("NVRAM config error. " 9442 "BAD link speed link_config 0x%x\n", 9443 link_config); 9444 bp->link_params.req_line_speed[idx] = 9445 SPEED_AUTO_NEG; 9446 bp->port.advertising[idx] = 9447 bp->port.supported[idx]; 9448 break; 9449 } 9450 9451 bp->link_params.req_flow_ctrl[idx] = (link_config & 9452 PORT_FEATURE_FLOW_CONTROL_MASK); 9453 if ((bp->link_params.req_flow_ctrl[idx] == 9454 BNX2X_FLOW_CTRL_AUTO) && 9455 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9456 bp->link_params.req_flow_ctrl[idx] = 9457 BNX2X_FLOW_CTRL_NONE; 9458 } 9459 9460 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9461 " 0x%x advertising 0x%x\n", 9462 bp->link_params.req_line_speed[idx], 9463 bp->link_params.req_duplex[idx], 9464 bp->link_params.req_flow_ctrl[idx], 9465 bp->port.advertising[idx]); 9466 } 9467} 9468 9469static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9470{ 9471 mac_hi = cpu_to_be16(mac_hi); 9472 mac_lo = cpu_to_be32(mac_lo); 9473 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9474 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9475} 9476 9477static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9478{ 9479 int port = BP_PORT(bp); 9480 u32 config; 9481 u32 ext_phy_type, ext_phy_config; 9482 9483 bp->link_params.bp = bp; 9484 bp->link_params.port = port; 9485 9486 bp->link_params.lane_config = 9487 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9488 9489 bp->link_params.speed_cap_mask[0] = 9490 SHMEM_RD(bp, 9491 dev_info.port_hw_config[port].speed_capability_mask); 9492 bp->link_params.speed_cap_mask[1] = 9493 SHMEM_RD(bp, 9494 dev_info.port_hw_config[port].speed_capability_mask2); 9495 bp->port.link_config[0] = 9496 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9497 9498 bp->port.link_config[1] = 9499 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9500 9501 bp->link_params.multi_phy_config = 9502 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9503 /* If the device is capable of WoL, set the default state according 9504 * to the HW 9505 */ 9506 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9507 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9508 (config & PORT_FEATURE_WOL_ENABLED)); 9509 9510 BNX2X_DEV_INFO("lane_config 0x%08x " 9511 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9512 bp->link_params.lane_config, 9513 bp->link_params.speed_cap_mask[0], 9514 bp->port.link_config[0]); 9515 9516 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9517 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9518 bnx2x_phy_probe(&bp->link_params); 9519 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9520 9521 bnx2x_link_settings_requested(bp); 9522 9523 /* 9524 * If connected directly, work with the internal PHY, otherwise, work 9525 * with the external PHY 9526 */ 9527 ext_phy_config = 9528 SHMEM_RD(bp, 9529 dev_info.port_hw_config[port].external_phy_config); 9530 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9531 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9532 bp->mdio.prtad = bp->port.phy_addr; 9533 9534 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9535 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9536 bp->mdio.prtad = 9537 XGXS_EXT_PHY_ADDR(ext_phy_config); 9538 9539 /* 9540 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9541 * In MF mode, it is set to cover self test cases 9542 */ 9543 if (IS_MF(bp)) 9544 bp->port.need_hw_lock = 1; 9545 else 9546 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9547 bp->common.shmem_base, 9548 bp->common.shmem2_base); 9549} 9550 9551void bnx2x_get_iscsi_info(struct bnx2x *bp) 9552{ 9553#ifdef BCM_CNIC 9554 int port = BP_PORT(bp); 9555 9556 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9557 drv_lic_key[port].max_iscsi_conn); 9558 9559 /* Get the number of maximum allowed iSCSI connections */ 9560 bp->cnic_eth_dev.max_iscsi_conn = 9561 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9562 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9563 9564 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9565 bp->cnic_eth_dev.max_iscsi_conn); 9566 9567 /* 9568 * If maximum allowed number of connections is zero - 9569 * disable the feature. 9570 */ 9571 if (!bp->cnic_eth_dev.max_iscsi_conn) 9572 bp->flags |= NO_ISCSI_FLAG; 9573#else 9574 bp->flags |= NO_ISCSI_FLAG; 9575#endif 9576} 9577 9578static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9579{ 9580#ifdef BCM_CNIC 9581 int port = BP_PORT(bp); 9582 int func = BP_ABS_FUNC(bp); 9583 9584 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9585 drv_lic_key[port].max_fcoe_conn); 9586 9587 /* Get the number of maximum allowed FCoE connections */ 9588 bp->cnic_eth_dev.max_fcoe_conn = 9589 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9590 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9591 9592 /* Read the WWN: */ 9593 if (!IS_MF(bp)) { 9594 /* Port info */ 9595 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9596 SHMEM_RD(bp, 9597 dev_info.port_hw_config[port]. 9598 fcoe_wwn_port_name_upper); 9599 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9600 SHMEM_RD(bp, 9601 dev_info.port_hw_config[port]. 9602 fcoe_wwn_port_name_lower); 9603 9604 /* Node info */ 9605 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9606 SHMEM_RD(bp, 9607 dev_info.port_hw_config[port]. 9608 fcoe_wwn_node_name_upper); 9609 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9610 SHMEM_RD(bp, 9611 dev_info.port_hw_config[port]. 9612 fcoe_wwn_node_name_lower); 9613 } else if (!IS_MF_SD(bp)) { 9614 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9615 9616 /* 9617 * Read the WWN info only if the FCoE feature is enabled for 9618 * this function. 9619 */ 9620 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9621 /* Port info */ 9622 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9623 MF_CFG_RD(bp, func_ext_config[func]. 9624 fcoe_wwn_port_name_upper); 9625 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9626 MF_CFG_RD(bp, func_ext_config[func]. 9627 fcoe_wwn_port_name_lower); 9628 9629 /* Node info */ 9630 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9631 MF_CFG_RD(bp, func_ext_config[func]. 9632 fcoe_wwn_node_name_upper); 9633 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9634 MF_CFG_RD(bp, func_ext_config[func]. 9635 fcoe_wwn_node_name_lower); 9636 } 9637 } 9638 9639 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9640 9641 /* 9642 * If maximum allowed number of connections is zero - 9643 * disable the feature. 9644 */ 9645 if (!bp->cnic_eth_dev.max_fcoe_conn) 9646 bp->flags |= NO_FCOE_FLAG; 9647#else 9648 bp->flags |= NO_FCOE_FLAG; 9649#endif 9650} 9651 9652static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9653{ 9654 /* 9655 * iSCSI may be dynamically disabled but reading 9656 * info here we will decrease memory usage by driver 9657 * if the feature is disabled for good 9658 */ 9659 bnx2x_get_iscsi_info(bp); 9660 bnx2x_get_fcoe_info(bp); 9661} 9662 9663static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9664{ 9665 u32 val, val2; 9666 int func = BP_ABS_FUNC(bp); 9667 int port = BP_PORT(bp); 9668#ifdef BCM_CNIC 9669 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9670 u8 *fip_mac = bp->fip_mac; 9671#endif 9672 9673 /* Zero primary MAC configuration */ 9674 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9675 9676 if (BP_NOMCP(bp)) { 9677 BNX2X_ERROR("warning: random MAC workaround active\n"); 9678 eth_hw_addr_random(bp->dev); 9679 } else if (IS_MF(bp)) { 9680 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9681 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9682 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9683 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9684 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9685 9686#ifdef BCM_CNIC 9687 /* 9688 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9689 * FCoE MAC then the appropriate feature should be disabled. 9690 */ 9691 if (IS_MF_SI(bp)) { 9692 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9693 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9694 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9695 iscsi_mac_addr_upper); 9696 val = MF_CFG_RD(bp, func_ext_config[func]. 9697 iscsi_mac_addr_lower); 9698 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9699 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9700 iscsi_mac); 9701 } else 9702 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9703 9704 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9705 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9706 fcoe_mac_addr_upper); 9707 val = MF_CFG_RD(bp, func_ext_config[func]. 9708 fcoe_mac_addr_lower); 9709 bnx2x_set_mac_buf(fip_mac, val, val2); 9710 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9711 fip_mac); 9712 9713 } else 9714 bp->flags |= NO_FCOE_FLAG; 9715 } else { /* SD mode */ 9716 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) { 9717 /* use primary mac as iscsi mac */ 9718 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 9719 /* Zero primary MAC configuration */ 9720 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9721 9722 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9723 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9724 iscsi_mac); 9725 } 9726 } 9727#endif 9728 } else { 9729 /* in SF read MACs from port configuration */ 9730 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9731 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9732 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9733 9734#ifdef BCM_CNIC 9735 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9736 iscsi_mac_upper); 9737 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9738 iscsi_mac_lower); 9739 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9740 9741 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9742 fcoe_fip_mac_upper); 9743 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9744 fcoe_fip_mac_lower); 9745 bnx2x_set_mac_buf(fip_mac, val, val2); 9746#endif 9747 } 9748 9749 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9750 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9751 9752#ifdef BCM_CNIC 9753 /* Set the FCoE MAC in MF_SD mode */ 9754 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9755 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9756 9757 /* Disable iSCSI if MAC configuration is 9758 * invalid. 9759 */ 9760 if (!is_valid_ether_addr(iscsi_mac)) { 9761 bp->flags |= NO_ISCSI_FLAG; 9762 memset(iscsi_mac, 0, ETH_ALEN); 9763 } 9764 9765 /* Disable FCoE if MAC configuration is 9766 * invalid. 9767 */ 9768 if (!is_valid_ether_addr(fip_mac)) { 9769 bp->flags |= NO_FCOE_FLAG; 9770 memset(bp->fip_mac, 0, ETH_ALEN); 9771 } 9772#endif 9773 9774 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9775 dev_err(&bp->pdev->dev, 9776 "bad Ethernet MAC address configuration: " 9777 "%pM, change it manually before bringing up " 9778 "the appropriate network interface\n", 9779 bp->dev->dev_addr); 9780} 9781 9782static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9783{ 9784 int /*abs*/func = BP_ABS_FUNC(bp); 9785 int vn; 9786 u32 val = 0; 9787 int rc = 0; 9788 9789 bnx2x_get_common_hwinfo(bp); 9790 9791 /* 9792 * initialize IGU parameters 9793 */ 9794 if (CHIP_IS_E1x(bp)) { 9795 bp->common.int_block = INT_BLOCK_HC; 9796 9797 bp->igu_dsb_id = DEF_SB_IGU_ID; 9798 bp->igu_base_sb = 0; 9799 } else { 9800 bp->common.int_block = INT_BLOCK_IGU; 9801 9802 /* do not allow device reset during IGU info preocessing */ 9803 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9804 9805 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9806 9807 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9808 int tout = 5000; 9809 9810 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9811 9812 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9813 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9814 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9815 9816 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9817 tout--; 9818 usleep_range(1000, 1000); 9819 } 9820 9821 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9822 dev_err(&bp->pdev->dev, 9823 "FORCING Normal Mode failed!!!\n"); 9824 return -EPERM; 9825 } 9826 } 9827 9828 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9829 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9830 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9831 } else 9832 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9833 9834 bnx2x_get_igu_cam_info(bp); 9835 9836 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9837 } 9838 9839 /* 9840 * set base FW non-default (fast path) status block id, this value is 9841 * used to initialize the fw_sb_id saved on the fp/queue structure to 9842 * determine the id used by the FW. 9843 */ 9844 if (CHIP_IS_E1x(bp)) 9845 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9846 else /* 9847 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9848 * the same queue are indicated on the same IGU SB). So we prefer 9849 * FW and IGU SBs to be the same value. 9850 */ 9851 bp->base_fw_ndsb = bp->igu_base_sb; 9852 9853 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9854 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9855 bp->igu_sb_cnt, bp->base_fw_ndsb); 9856 9857 /* 9858 * Initialize MF configuration 9859 */ 9860 9861 bp->mf_ov = 0; 9862 bp->mf_mode = 0; 9863 vn = BP_VN(bp); 9864 9865 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9866 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9867 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9868 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9869 9870 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9871 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9872 else 9873 bp->common.mf_cfg_base = bp->common.shmem_base + 9874 offsetof(struct shmem_region, func_mb) + 9875 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9876 /* 9877 * get mf configuration: 9878 * 1. existence of MF configuration 9879 * 2. MAC address must be legal (check only upper bytes) 9880 * for Switch-Independent mode; 9881 * OVLAN must be legal for Switch-Dependent mode 9882 * 3. SF_MODE configures specific MF mode 9883 */ 9884 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9885 /* get mf configuration */ 9886 val = SHMEM_RD(bp, 9887 dev_info.shared_feature_config.config); 9888 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9889 9890 switch (val) { 9891 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9892 val = MF_CFG_RD(bp, func_mf_config[func]. 9893 mac_upper); 9894 /* check for legal mac (upper bytes)*/ 9895 if (val != 0xffff) { 9896 bp->mf_mode = MULTI_FUNCTION_SI; 9897 bp->mf_config[vn] = MF_CFG_RD(bp, 9898 func_mf_config[func].config); 9899 } else 9900 BNX2X_DEV_INFO("illegal MAC address " 9901 "for SI\n"); 9902 break; 9903 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9904 /* get OV configuration */ 9905 val = MF_CFG_RD(bp, 9906 func_mf_config[FUNC_0].e1hov_tag); 9907 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9908 9909 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9910 bp->mf_mode = MULTI_FUNCTION_SD; 9911 bp->mf_config[vn] = MF_CFG_RD(bp, 9912 func_mf_config[func].config); 9913 } else 9914 BNX2X_DEV_INFO("illegal OV for SD\n"); 9915 break; 9916 default: 9917 /* Unknown configuration: reset mf_config */ 9918 bp->mf_config[vn] = 0; 9919 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9920 } 9921 } 9922 9923 BNX2X_DEV_INFO("%s function mode\n", 9924 IS_MF(bp) ? "multi" : "single"); 9925 9926 switch (bp->mf_mode) { 9927 case MULTI_FUNCTION_SD: 9928 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9929 FUNC_MF_CFG_E1HOV_TAG_MASK; 9930 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9931 bp->mf_ov = val; 9932 bp->path_has_ovlan = true; 9933 9934 BNX2X_DEV_INFO("MF OV for func %d is %d " 9935 "(0x%04x)\n", func, bp->mf_ov, 9936 bp->mf_ov); 9937 } else { 9938 dev_err(&bp->pdev->dev, 9939 "No valid MF OV for func %d, " 9940 "aborting\n", func); 9941 return -EPERM; 9942 } 9943 break; 9944 case MULTI_FUNCTION_SI: 9945 BNX2X_DEV_INFO("func %d is in MF " 9946 "switch-independent mode\n", func); 9947 break; 9948 default: 9949 if (vn) { 9950 dev_err(&bp->pdev->dev, 9951 "VN %d is in a single function mode, " 9952 "aborting\n", vn); 9953 return -EPERM; 9954 } 9955 break; 9956 } 9957 9958 /* check if other port on the path needs ovlan: 9959 * Since MF configuration is shared between ports 9960 * Possible mixed modes are only 9961 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9962 */ 9963 if (CHIP_MODE_IS_4_PORT(bp) && 9964 !bp->path_has_ovlan && 9965 !IS_MF(bp) && 9966 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9967 u8 other_port = !BP_PORT(bp); 9968 u8 other_func = BP_PATH(bp) + 2*other_port; 9969 val = MF_CFG_RD(bp, 9970 func_mf_config[other_func].e1hov_tag); 9971 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9972 bp->path_has_ovlan = true; 9973 } 9974 } 9975 9976 /* adjust igu_sb_cnt to MF for E1x */ 9977 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9978 bp->igu_sb_cnt /= E1HVN_MAX; 9979 9980 /* port info */ 9981 bnx2x_get_port_hwinfo(bp); 9982 9983 /* Get MAC addresses */ 9984 bnx2x_get_mac_hwinfo(bp); 9985 9986 bnx2x_get_cnic_info(bp); 9987 9988 return rc; 9989} 9990 9991static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9992{ 9993 int cnt, i, block_end, rodi; 9994 char vpd_start[BNX2X_VPD_LEN+1]; 9995 char str_id_reg[VENDOR_ID_LEN+1]; 9996 char str_id_cap[VENDOR_ID_LEN+1]; 9997 char *vpd_data; 9998 char *vpd_extended_data = NULL; 9999 u8 len; 10000 10001 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 10002 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 10003 10004 if (cnt < BNX2X_VPD_LEN) 10005 goto out_not_found; 10006 10007 /* VPD RO tag should be first tag after identifier string, hence 10008 * we should be able to find it in first BNX2X_VPD_LEN chars 10009 */ 10010 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 10011 PCI_VPD_LRDT_RO_DATA); 10012 if (i < 0) 10013 goto out_not_found; 10014 10015 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 10016 pci_vpd_lrdt_size(&vpd_start[i]); 10017 10018 i += PCI_VPD_LRDT_TAG_SIZE; 10019 10020 if (block_end > BNX2X_VPD_LEN) { 10021 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 10022 if (vpd_extended_data == NULL) 10023 goto out_not_found; 10024 10025 /* read rest of vpd image into vpd_extended_data */ 10026 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 10027 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 10028 block_end - BNX2X_VPD_LEN, 10029 vpd_extended_data + BNX2X_VPD_LEN); 10030 if (cnt < (block_end - BNX2X_VPD_LEN)) 10031 goto out_not_found; 10032 vpd_data = vpd_extended_data; 10033 } else 10034 vpd_data = vpd_start; 10035 10036 /* now vpd_data holds full vpd content in both cases */ 10037 10038 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10039 PCI_VPD_RO_KEYWORD_MFR_ID); 10040 if (rodi < 0) 10041 goto out_not_found; 10042 10043 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10044 10045 if (len != VENDOR_ID_LEN) 10046 goto out_not_found; 10047 10048 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10049 10050 /* vendor specific info */ 10051 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 10052 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 10053 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 10054 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 10055 10056 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10057 PCI_VPD_RO_KEYWORD_VENDOR0); 10058 if (rodi >= 0) { 10059 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10060 10061 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10062 10063 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 10064 memcpy(bp->fw_ver, &vpd_data[rodi], len); 10065 bp->fw_ver[len] = ' '; 10066 } 10067 } 10068 kfree(vpd_extended_data); 10069 return; 10070 } 10071out_not_found: 10072 kfree(vpd_extended_data); 10073 return; 10074} 10075 10076static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 10077{ 10078 u32 flags = 0; 10079 10080 if (CHIP_REV_IS_FPGA(bp)) 10081 SET_FLAGS(flags, MODE_FPGA); 10082 else if (CHIP_REV_IS_EMUL(bp)) 10083 SET_FLAGS(flags, MODE_EMUL); 10084 else 10085 SET_FLAGS(flags, MODE_ASIC); 10086 10087 if (CHIP_MODE_IS_4_PORT(bp)) 10088 SET_FLAGS(flags, MODE_PORT4); 10089 else 10090 SET_FLAGS(flags, MODE_PORT2); 10091 10092 if (CHIP_IS_E2(bp)) 10093 SET_FLAGS(flags, MODE_E2); 10094 else if (CHIP_IS_E3(bp)) { 10095 SET_FLAGS(flags, MODE_E3); 10096 if (CHIP_REV(bp) == CHIP_REV_Ax) 10097 SET_FLAGS(flags, MODE_E3_A0); 10098 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10099 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10100 } 10101 10102 if (IS_MF(bp)) { 10103 SET_FLAGS(flags, MODE_MF); 10104 switch (bp->mf_mode) { 10105 case MULTI_FUNCTION_SD: 10106 SET_FLAGS(flags, MODE_MF_SD); 10107 break; 10108 case MULTI_FUNCTION_SI: 10109 SET_FLAGS(flags, MODE_MF_SI); 10110 break; 10111 } 10112 } else 10113 SET_FLAGS(flags, MODE_SF); 10114 10115#if defined(__LITTLE_ENDIAN) 10116 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10117#else /*(__BIG_ENDIAN)*/ 10118 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10119#endif 10120 INIT_MODE_FLAGS(bp) = flags; 10121} 10122 10123static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10124{ 10125 int func; 10126 int rc; 10127 10128 mutex_init(&bp->port.phy_mutex); 10129 mutex_init(&bp->fw_mb_mutex); 10130 spin_lock_init(&bp->stats_lock); 10131#ifdef BCM_CNIC 10132 mutex_init(&bp->cnic_mutex); 10133#endif 10134 10135 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10136 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10137 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10138 rc = bnx2x_get_hwinfo(bp); 10139 if (rc) 10140 return rc; 10141 10142 bnx2x_set_modes_bitmap(bp); 10143 10144 rc = bnx2x_alloc_mem_bp(bp); 10145 if (rc) 10146 return rc; 10147 10148 bnx2x_read_fwinfo(bp); 10149 10150 func = BP_FUNC(bp); 10151 10152 /* need to reset chip if undi was active */ 10153 if (!BP_NOMCP(bp)) 10154 bnx2x_undi_unload(bp); 10155 10156 if (CHIP_REV_IS_FPGA(bp)) 10157 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10158 10159 if (BP_NOMCP(bp) && (func == 0)) 10160 dev_err(&bp->pdev->dev, "MCP disabled, " 10161 "must load devices in order!\n"); 10162 10163 bp->multi_mode = multi_mode; 10164 10165 bp->disable_tpa = disable_tpa; 10166 10167#ifdef BCM_CNIC 10168 bp->disable_tpa |= IS_MF_ISCSI_SD(bp); 10169#endif 10170 10171 /* Set TPA flags */ 10172 if (bp->disable_tpa) { 10173 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 10174 bp->dev->features &= ~NETIF_F_LRO; 10175 } else { 10176 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 10177 bp->dev->features |= NETIF_F_LRO; 10178 } 10179 10180 if (CHIP_IS_E1(bp)) 10181 bp->dropless_fc = 0; 10182 else 10183 bp->dropless_fc = dropless_fc; 10184 10185 bp->mrrs = mrrs; 10186 10187 bp->tx_ring_size = MAX_TX_AVAIL; 10188 10189 /* make sure that the numbers are in the right granularity */ 10190 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10191 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10192 10193 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 10194 10195 init_timer(&bp->timer); 10196 bp->timer.expires = jiffies + bp->current_interval; 10197 bp->timer.data = (unsigned long) bp; 10198 bp->timer.function = bnx2x_timer; 10199 10200 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10201 bnx2x_dcbx_init_params(bp); 10202 10203#ifdef BCM_CNIC 10204 if (CHIP_IS_E1x(bp)) 10205 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10206 else 10207 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10208#endif 10209 10210 /* multiple tx priority */ 10211 if (CHIP_IS_E1x(bp)) 10212 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10213 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10214 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10215 if (CHIP_IS_E3B0(bp)) 10216 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10217 10218 bp->gro_check = bnx2x_need_gro_check(bp->dev->mtu); 10219 10220 return rc; 10221} 10222 10223 10224/**************************************************************************** 10225* General service functions 10226****************************************************************************/ 10227 10228/* 10229 * net_device service functions 10230 */ 10231 10232/* called with rtnl_lock */ 10233static int bnx2x_open(struct net_device *dev) 10234{ 10235 struct bnx2x *bp = netdev_priv(dev); 10236 bool global = false; 10237 int other_engine = BP_PATH(bp) ? 0 : 1; 10238 bool other_load_status, load_status; 10239 10240 bp->stats_init = true; 10241 10242 netif_carrier_off(dev); 10243 10244 bnx2x_set_power_state(bp, PCI_D0); 10245 10246 other_load_status = bnx2x_get_load_status(bp, other_engine); 10247 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 10248 10249 /* 10250 * If parity had happen during the unload, then attentions 10251 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10252 * want the first function loaded on the current engine to 10253 * complete the recovery. 10254 */ 10255 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10256 bnx2x_chk_parity_attn(bp, &global, true)) 10257 do { 10258 /* 10259 * If there are attentions and they are in a global 10260 * blocks, set the GLOBAL_RESET bit regardless whether 10261 * it will be this function that will complete the 10262 * recovery or not. 10263 */ 10264 if (global) 10265 bnx2x_set_reset_global(bp); 10266 10267 /* 10268 * Only the first function on the current engine should 10269 * try to recover in open. In case of attentions in 10270 * global blocks only the first in the chip should try 10271 * to recover. 10272 */ 10273 if ((!load_status && 10274 (!global || !other_load_status)) && 10275 bnx2x_trylock_leader_lock(bp) && 10276 !bnx2x_leader_reset(bp)) { 10277 netdev_info(bp->dev, "Recovered in open\n"); 10278 break; 10279 } 10280 10281 /* recovery has failed... */ 10282 bnx2x_set_power_state(bp, PCI_D3hot); 10283 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10284 10285 netdev_err(bp->dev, "Recovery flow hasn't been properly" 10286 " completed yet. Try again later. If u still see this" 10287 " message after a few retries then power cycle is" 10288 " required.\n"); 10289 10290 return -EAGAIN; 10291 } while (0); 10292 10293 bp->recovery_state = BNX2X_RECOVERY_DONE; 10294 return bnx2x_nic_load(bp, LOAD_OPEN); 10295} 10296 10297/* called with rtnl_lock */ 10298static int bnx2x_close(struct net_device *dev) 10299{ 10300 struct bnx2x *bp = netdev_priv(dev); 10301 10302 /* Unload the driver, release IRQs */ 10303 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10304 10305 /* Power off */ 10306 bnx2x_set_power_state(bp, PCI_D3hot); 10307 10308 return 0; 10309} 10310 10311static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10312 struct bnx2x_mcast_ramrod_params *p) 10313{ 10314 int mc_count = netdev_mc_count(bp->dev); 10315 struct bnx2x_mcast_list_elem *mc_mac = 10316 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10317 struct netdev_hw_addr *ha; 10318 10319 if (!mc_mac) 10320 return -ENOMEM; 10321 10322 INIT_LIST_HEAD(&p->mcast_list); 10323 10324 netdev_for_each_mc_addr(ha, bp->dev) { 10325 mc_mac->mac = bnx2x_mc_addr(ha); 10326 list_add_tail(&mc_mac->link, &p->mcast_list); 10327 mc_mac++; 10328 } 10329 10330 p->mcast_list_len = mc_count; 10331 10332 return 0; 10333} 10334 10335static inline void bnx2x_free_mcast_macs_list( 10336 struct bnx2x_mcast_ramrod_params *p) 10337{ 10338 struct bnx2x_mcast_list_elem *mc_mac = 10339 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10340 link); 10341 10342 WARN_ON(!mc_mac); 10343 kfree(mc_mac); 10344} 10345 10346/** 10347 * bnx2x_set_uc_list - configure a new unicast MACs list. 10348 * 10349 * @bp: driver handle 10350 * 10351 * We will use zero (0) as a MAC type for these MACs. 10352 */ 10353static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10354{ 10355 int rc; 10356 struct net_device *dev = bp->dev; 10357 struct netdev_hw_addr *ha; 10358 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10359 unsigned long ramrod_flags = 0; 10360 10361 /* First schedule a cleanup up of old configuration */ 10362 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10363 if (rc < 0) { 10364 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10365 return rc; 10366 } 10367 10368 netdev_for_each_uc_addr(ha, dev) { 10369 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10370 BNX2X_UC_LIST_MAC, &ramrod_flags); 10371 if (rc < 0) { 10372 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10373 rc); 10374 return rc; 10375 } 10376 } 10377 10378 /* Execute the pending commands */ 10379 __set_bit(RAMROD_CONT, &ramrod_flags); 10380 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10381 BNX2X_UC_LIST_MAC, &ramrod_flags); 10382} 10383 10384static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10385{ 10386 struct net_device *dev = bp->dev; 10387 struct bnx2x_mcast_ramrod_params rparam = {0}; 10388 int rc = 0; 10389 10390 rparam.mcast_obj = &bp->mcast_obj; 10391 10392 /* first, clear all configured multicast MACs */ 10393 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10394 if (rc < 0) { 10395 BNX2X_ERR("Failed to clear multicast " 10396 "configuration: %d\n", rc); 10397 return rc; 10398 } 10399 10400 /* then, configure a new MACs list */ 10401 if (netdev_mc_count(dev)) { 10402 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10403 if (rc) { 10404 BNX2X_ERR("Failed to create multicast MACs " 10405 "list: %d\n", rc); 10406 return rc; 10407 } 10408 10409 /* Now add the new MACs */ 10410 rc = bnx2x_config_mcast(bp, &rparam, 10411 BNX2X_MCAST_CMD_ADD); 10412 if (rc < 0) 10413 BNX2X_ERR("Failed to set a new multicast " 10414 "configuration: %d\n", rc); 10415 10416 bnx2x_free_mcast_macs_list(&rparam); 10417 } 10418 10419 return rc; 10420} 10421 10422 10423/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10424void bnx2x_set_rx_mode(struct net_device *dev) 10425{ 10426 struct bnx2x *bp = netdev_priv(dev); 10427 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10428 10429 if (bp->state != BNX2X_STATE_OPEN) { 10430 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10431 return; 10432 } 10433 10434 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10435 10436 if (dev->flags & IFF_PROMISC) 10437 rx_mode = BNX2X_RX_MODE_PROMISC; 10438 else if ((dev->flags & IFF_ALLMULTI) || 10439 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10440 CHIP_IS_E1(bp))) 10441 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10442 else { 10443 /* some multicasts */ 10444 if (bnx2x_set_mc_list(bp) < 0) 10445 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10446 10447 if (bnx2x_set_uc_list(bp) < 0) 10448 rx_mode = BNX2X_RX_MODE_PROMISC; 10449 } 10450 10451 bp->rx_mode = rx_mode; 10452#ifdef BCM_CNIC 10453 /* handle ISCSI SD mode */ 10454 if (IS_MF_ISCSI_SD(bp)) 10455 bp->rx_mode = BNX2X_RX_MODE_NONE; 10456#endif 10457 10458 /* Schedule the rx_mode command */ 10459 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10460 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10461 return; 10462 } 10463 10464 bnx2x_set_storm_rx_mode(bp); 10465} 10466 10467/* called with rtnl_lock */ 10468static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10469 int devad, u16 addr) 10470{ 10471 struct bnx2x *bp = netdev_priv(netdev); 10472 u16 value; 10473 int rc; 10474 10475 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10476 prtad, devad, addr); 10477 10478 /* The HW expects different devad if CL22 is used */ 10479 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10480 10481 bnx2x_acquire_phy_lock(bp); 10482 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10483 bnx2x_release_phy_lock(bp); 10484 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10485 10486 if (!rc) 10487 rc = value; 10488 return rc; 10489} 10490 10491/* called with rtnl_lock */ 10492static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10493 u16 addr, u16 value) 10494{ 10495 struct bnx2x *bp = netdev_priv(netdev); 10496 int rc; 10497 10498 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10499 " value 0x%x\n", prtad, devad, addr, value); 10500 10501 /* The HW expects different devad if CL22 is used */ 10502 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10503 10504 bnx2x_acquire_phy_lock(bp); 10505 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10506 bnx2x_release_phy_lock(bp); 10507 return rc; 10508} 10509 10510/* called with rtnl_lock */ 10511static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10512{ 10513 struct bnx2x *bp = netdev_priv(dev); 10514 struct mii_ioctl_data *mdio = if_mii(ifr); 10515 10516 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10517 mdio->phy_id, mdio->reg_num, mdio->val_in); 10518 10519 if (!netif_running(dev)) 10520 return -EAGAIN; 10521 10522 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10523} 10524 10525#ifdef CONFIG_NET_POLL_CONTROLLER 10526static void poll_bnx2x(struct net_device *dev) 10527{ 10528 struct bnx2x *bp = netdev_priv(dev); 10529 10530 disable_irq(bp->pdev->irq); 10531 bnx2x_interrupt(bp->pdev->irq, dev); 10532 enable_irq(bp->pdev->irq); 10533} 10534#endif 10535 10536static int bnx2x_validate_addr(struct net_device *dev) 10537{ 10538 struct bnx2x *bp = netdev_priv(dev); 10539 10540 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) 10541 return -EADDRNOTAVAIL; 10542 return 0; 10543} 10544 10545static const struct net_device_ops bnx2x_netdev_ops = { 10546 .ndo_open = bnx2x_open, 10547 .ndo_stop = bnx2x_close, 10548 .ndo_start_xmit = bnx2x_start_xmit, 10549 .ndo_select_queue = bnx2x_select_queue, 10550 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10551 .ndo_set_mac_address = bnx2x_change_mac_addr, 10552 .ndo_validate_addr = bnx2x_validate_addr, 10553 .ndo_do_ioctl = bnx2x_ioctl, 10554 .ndo_change_mtu = bnx2x_change_mtu, 10555 .ndo_fix_features = bnx2x_fix_features, 10556 .ndo_set_features = bnx2x_set_features, 10557 .ndo_tx_timeout = bnx2x_tx_timeout, 10558#ifdef CONFIG_NET_POLL_CONTROLLER 10559 .ndo_poll_controller = poll_bnx2x, 10560#endif 10561 .ndo_setup_tc = bnx2x_setup_tc, 10562 10563#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10564 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10565#endif 10566}; 10567 10568static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10569{ 10570 struct device *dev = &bp->pdev->dev; 10571 10572 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10573 bp->flags |= USING_DAC_FLAG; 10574 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10575 dev_err(dev, "dma_set_coherent_mask failed, " 10576 "aborting\n"); 10577 return -EIO; 10578 } 10579 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10580 dev_err(dev, "System does not support DMA, aborting\n"); 10581 return -EIO; 10582 } 10583 10584 return 0; 10585} 10586 10587static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10588 struct net_device *dev, 10589 unsigned long board_type) 10590{ 10591 struct bnx2x *bp; 10592 int rc; 10593 u32 pci_cfg_dword; 10594 bool chip_is_e1x = (board_type == BCM57710 || 10595 board_type == BCM57711 || 10596 board_type == BCM57711E); 10597 10598 SET_NETDEV_DEV(dev, &pdev->dev); 10599 bp = netdev_priv(dev); 10600 10601 bp->dev = dev; 10602 bp->pdev = pdev; 10603 bp->flags = 0; 10604 10605 rc = pci_enable_device(pdev); 10606 if (rc) { 10607 dev_err(&bp->pdev->dev, 10608 "Cannot enable PCI device, aborting\n"); 10609 goto err_out; 10610 } 10611 10612 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10613 dev_err(&bp->pdev->dev, 10614 "Cannot find PCI device base address, aborting\n"); 10615 rc = -ENODEV; 10616 goto err_out_disable; 10617 } 10618 10619 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10620 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10621 " base address, aborting\n"); 10622 rc = -ENODEV; 10623 goto err_out_disable; 10624 } 10625 10626 if (atomic_read(&pdev->enable_cnt) == 1) { 10627 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10628 if (rc) { 10629 dev_err(&bp->pdev->dev, 10630 "Cannot obtain PCI resources, aborting\n"); 10631 goto err_out_disable; 10632 } 10633 10634 pci_set_master(pdev); 10635 pci_save_state(pdev); 10636 } 10637 10638 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10639 if (bp->pm_cap == 0) { 10640 dev_err(&bp->pdev->dev, 10641 "Cannot find power management capability, aborting\n"); 10642 rc = -EIO; 10643 goto err_out_release; 10644 } 10645 10646 if (!pci_is_pcie(pdev)) { 10647 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10648 rc = -EIO; 10649 goto err_out_release; 10650 } 10651 10652 rc = bnx2x_set_coherency_mask(bp); 10653 if (rc) 10654 goto err_out_release; 10655 10656 dev->mem_start = pci_resource_start(pdev, 0); 10657 dev->base_addr = dev->mem_start; 10658 dev->mem_end = pci_resource_end(pdev, 0); 10659 10660 dev->irq = pdev->irq; 10661 10662 bp->regview = pci_ioremap_bar(pdev, 0); 10663 if (!bp->regview) { 10664 dev_err(&bp->pdev->dev, 10665 "Cannot map register space, aborting\n"); 10666 rc = -ENOMEM; 10667 goto err_out_release; 10668 } 10669 10670 /* In E1/E1H use pci device function given by kernel. 10671 * In E2/E3 read physical function from ME register since these chips 10672 * support Physical Device Assignment where kernel BDF maybe arbitrary 10673 * (depending on hypervisor). 10674 */ 10675 if (chip_is_e1x) 10676 bp->pf_num = PCI_FUNC(pdev->devfn); 10677 else {/* chip is E2/3*/ 10678 pci_read_config_dword(bp->pdev, 10679 PCICFG_ME_REGISTER, &pci_cfg_dword); 10680 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 10681 ME_REG_ABS_PF_NUM_SHIFT); 10682 } 10683 DP(BNX2X_MSG_SP, "me reg PF num: %d\n", bp->pf_num); 10684 10685 bnx2x_set_power_state(bp, PCI_D0); 10686 10687 /* clean indirect addresses */ 10688 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10689 PCICFG_VENDOR_ID_OFFSET); 10690 /* 10691 * Clean the following indirect addresses for all functions since it 10692 * is not used by the driver. 10693 */ 10694 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10695 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10696 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10697 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10698 10699 if (chip_is_e1x) { 10700 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10701 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10702 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10703 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10704 } 10705 10706 /* 10707 * Enable internal target-read (in case we are probed after PF FLR). 10708 * Must be done prior to any BAR read access. Only for 57712 and up 10709 */ 10710 if (!chip_is_e1x) 10711 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10712 10713 /* Reset the load counter */ 10714 bnx2x_clear_load_status(bp); 10715 10716 dev->watchdog_timeo = TX_TIMEOUT; 10717 10718 dev->netdev_ops = &bnx2x_netdev_ops; 10719 bnx2x_set_ethtool_ops(dev); 10720 10721 dev->priv_flags |= IFF_UNICAST_FLT; 10722 10723 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10724 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 10725 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | 10726 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10727 10728 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10729 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10730 10731 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10732 if (bp->flags & USING_DAC_FLAG) 10733 dev->features |= NETIF_F_HIGHDMA; 10734 10735 /* Add Loopback capability to the device */ 10736 dev->hw_features |= NETIF_F_LOOPBACK; 10737 10738#ifdef BCM_DCBNL 10739 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10740#endif 10741 10742 /* get_port_hwinfo() will set prtad and mmds properly */ 10743 bp->mdio.prtad = MDIO_PRTAD_NONE; 10744 bp->mdio.mmds = 0; 10745 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10746 bp->mdio.dev = dev; 10747 bp->mdio.mdio_read = bnx2x_mdio_read; 10748 bp->mdio.mdio_write = bnx2x_mdio_write; 10749 10750 return 0; 10751 10752err_out_release: 10753 if (atomic_read(&pdev->enable_cnt) == 1) 10754 pci_release_regions(pdev); 10755 10756err_out_disable: 10757 pci_disable_device(pdev); 10758 pci_set_drvdata(pdev, NULL); 10759 10760err_out: 10761 return rc; 10762} 10763 10764static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10765 int *width, int *speed) 10766{ 10767 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10768 10769 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10770 10771 /* return value of 1=2.5GHz 2=5GHz */ 10772 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10773} 10774 10775static int bnx2x_check_firmware(struct bnx2x *bp) 10776{ 10777 const struct firmware *firmware = bp->firmware; 10778 struct bnx2x_fw_file_hdr *fw_hdr; 10779 struct bnx2x_fw_file_section *sections; 10780 u32 offset, len, num_ops; 10781 u16 *ops_offsets; 10782 int i; 10783 const u8 *fw_ver; 10784 10785 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10786 return -EINVAL; 10787 10788 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10789 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10790 10791 /* Make sure none of the offsets and sizes make us read beyond 10792 * the end of the firmware data */ 10793 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10794 offset = be32_to_cpu(sections[i].offset); 10795 len = be32_to_cpu(sections[i].len); 10796 if (offset + len > firmware->size) { 10797 dev_err(&bp->pdev->dev, 10798 "Section %d length is out of bounds\n", i); 10799 return -EINVAL; 10800 } 10801 } 10802 10803 /* Likewise for the init_ops offsets */ 10804 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10805 ops_offsets = (u16 *)(firmware->data + offset); 10806 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10807 10808 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10809 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10810 dev_err(&bp->pdev->dev, 10811 "Section offset %d is out of bounds\n", i); 10812 return -EINVAL; 10813 } 10814 } 10815 10816 /* Check FW version */ 10817 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10818 fw_ver = firmware->data + offset; 10819 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10820 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10821 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10822 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10823 dev_err(&bp->pdev->dev, 10824 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10825 fw_ver[0], fw_ver[1], fw_ver[2], 10826 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10827 BCM_5710_FW_MINOR_VERSION, 10828 BCM_5710_FW_REVISION_VERSION, 10829 BCM_5710_FW_ENGINEERING_VERSION); 10830 return -EINVAL; 10831 } 10832 10833 return 0; 10834} 10835 10836static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10837{ 10838 const __be32 *source = (const __be32 *)_source; 10839 u32 *target = (u32 *)_target; 10840 u32 i; 10841 10842 for (i = 0; i < n/4; i++) 10843 target[i] = be32_to_cpu(source[i]); 10844} 10845 10846/* 10847 Ops array is stored in the following format: 10848 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10849 */ 10850static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10851{ 10852 const __be32 *source = (const __be32 *)_source; 10853 struct raw_op *target = (struct raw_op *)_target; 10854 u32 i, j, tmp; 10855 10856 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10857 tmp = be32_to_cpu(source[j]); 10858 target[i].op = (tmp >> 24) & 0xff; 10859 target[i].offset = tmp & 0xffffff; 10860 target[i].raw_data = be32_to_cpu(source[j + 1]); 10861 } 10862} 10863 10864/** 10865 * IRO array is stored in the following format: 10866 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10867 */ 10868static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10869{ 10870 const __be32 *source = (const __be32 *)_source; 10871 struct iro *target = (struct iro *)_target; 10872 u32 i, j, tmp; 10873 10874 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10875 target[i].base = be32_to_cpu(source[j]); 10876 j++; 10877 tmp = be32_to_cpu(source[j]); 10878 target[i].m1 = (tmp >> 16) & 0xffff; 10879 target[i].m2 = tmp & 0xffff; 10880 j++; 10881 tmp = be32_to_cpu(source[j]); 10882 target[i].m3 = (tmp >> 16) & 0xffff; 10883 target[i].size = tmp & 0xffff; 10884 j++; 10885 } 10886} 10887 10888static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10889{ 10890 const __be16 *source = (const __be16 *)_source; 10891 u16 *target = (u16 *)_target; 10892 u32 i; 10893 10894 for (i = 0; i < n/2; i++) 10895 target[i] = be16_to_cpu(source[i]); 10896} 10897 10898#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10899do { \ 10900 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10901 bp->arr = kmalloc(len, GFP_KERNEL); \ 10902 if (!bp->arr) \ 10903 goto lbl; \ 10904 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10905 (u8 *)bp->arr, len); \ 10906} while (0) 10907 10908int bnx2x_init_firmware(struct bnx2x *bp) 10909{ 10910 struct bnx2x_fw_file_hdr *fw_hdr; 10911 int rc; 10912 10913 10914 if (!bp->firmware) { 10915 const char *fw_file_name; 10916 10917 if (CHIP_IS_E1(bp)) 10918 fw_file_name = FW_FILE_NAME_E1; 10919 else if (CHIP_IS_E1H(bp)) 10920 fw_file_name = FW_FILE_NAME_E1H; 10921 else if (!CHIP_IS_E1x(bp)) 10922 fw_file_name = FW_FILE_NAME_E2; 10923 else { 10924 BNX2X_ERR("Unsupported chip revision\n"); 10925 return -EINVAL; 10926 } 10927 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10928 10929 rc = request_firmware(&bp->firmware, fw_file_name, 10930 &bp->pdev->dev); 10931 if (rc) { 10932 BNX2X_ERR("Can't load firmware file %s\n", 10933 fw_file_name); 10934 goto request_firmware_exit; 10935 } 10936 10937 rc = bnx2x_check_firmware(bp); 10938 if (rc) { 10939 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10940 goto request_firmware_exit; 10941 } 10942 } 10943 10944 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10945 10946 /* Initialize the pointers to the init arrays */ 10947 /* Blob */ 10948 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10949 10950 /* Opcodes */ 10951 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10952 10953 /* Offsets */ 10954 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10955 be16_to_cpu_n); 10956 10957 /* STORMs firmware */ 10958 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10959 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10960 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10961 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10962 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10963 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10964 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10965 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10966 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10967 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10968 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10969 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10970 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10971 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10972 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10973 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10974 /* IRO */ 10975 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10976 10977 return 0; 10978 10979iro_alloc_err: 10980 kfree(bp->init_ops_offsets); 10981init_offsets_alloc_err: 10982 kfree(bp->init_ops); 10983init_ops_alloc_err: 10984 kfree(bp->init_data); 10985request_firmware_exit: 10986 release_firmware(bp->firmware); 10987 10988 return rc; 10989} 10990 10991static void bnx2x_release_firmware(struct bnx2x *bp) 10992{ 10993 kfree(bp->init_ops_offsets); 10994 kfree(bp->init_ops); 10995 kfree(bp->init_data); 10996 release_firmware(bp->firmware); 10997 bp->firmware = NULL; 10998} 10999 11000 11001static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 11002 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 11003 .init_hw_cmn = bnx2x_init_hw_common, 11004 .init_hw_port = bnx2x_init_hw_port, 11005 .init_hw_func = bnx2x_init_hw_func, 11006 11007 .reset_hw_cmn = bnx2x_reset_common, 11008 .reset_hw_port = bnx2x_reset_port, 11009 .reset_hw_func = bnx2x_reset_func, 11010 11011 .gunzip_init = bnx2x_gunzip_init, 11012 .gunzip_end = bnx2x_gunzip_end, 11013 11014 .init_fw = bnx2x_init_firmware, 11015 .release_fw = bnx2x_release_firmware, 11016}; 11017 11018void bnx2x__init_func_obj(struct bnx2x *bp) 11019{ 11020 /* Prepare DMAE related driver resources */ 11021 bnx2x_setup_dmae(bp); 11022 11023 bnx2x_init_func_obj(bp, &bp->func_obj, 11024 bnx2x_sp(bp, func_rdata), 11025 bnx2x_sp_mapping(bp, func_rdata), 11026 &bnx2x_func_sp_drv); 11027} 11028 11029/* must be called after sriov-enable */ 11030static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 11031{ 11032 int cid_count = BNX2X_L2_CID_COUNT(bp); 11033 11034#ifdef BCM_CNIC 11035 cid_count += CNIC_CID_MAX; 11036#endif 11037 return roundup(cid_count, QM_CID_ROUND); 11038} 11039 11040/** 11041 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 11042 * 11043 * @dev: pci device 11044 * 11045 */ 11046static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 11047{ 11048 int pos; 11049 u16 control; 11050 11051 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 11052 11053 /* 11054 * If MSI-X is not supported - return number of SBs needed to support 11055 * one fast path queue: one FP queue + SB for CNIC 11056 */ 11057 if (!pos) 11058 return 1 + CNIC_PRESENT; 11059 11060 /* 11061 * The value in the PCI configuration space is the index of the last 11062 * entry, namely one less than the actual size of the table, which is 11063 * exactly what we want to return from this function: number of all SBs 11064 * without the default SB. 11065 */ 11066 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 11067 return control & PCI_MSIX_FLAGS_QSIZE; 11068} 11069 11070static int __devinit bnx2x_init_one(struct pci_dev *pdev, 11071 const struct pci_device_id *ent) 11072{ 11073 struct net_device *dev = NULL; 11074 struct bnx2x *bp; 11075 int pcie_width, pcie_speed; 11076 int rc, max_non_def_sbs; 11077 int rx_count, tx_count, rss_count; 11078 /* 11079 * An estimated maximum supported CoS number according to the chip 11080 * version. 11081 * We will try to roughly estimate the maximum number of CoSes this chip 11082 * may support in order to minimize the memory allocated for Tx 11083 * netdev_queue's. This number will be accurately calculated during the 11084 * initialization of bp->max_cos based on the chip versions AND chip 11085 * revision in the bnx2x_init_bp(). 11086 */ 11087 u8 max_cos_est = 0; 11088 11089 switch (ent->driver_data) { 11090 case BCM57710: 11091 case BCM57711: 11092 case BCM57711E: 11093 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 11094 break; 11095 11096 case BCM57712: 11097 case BCM57712_MF: 11098 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11099 break; 11100 11101 case BCM57800: 11102 case BCM57800_MF: 11103 case BCM57810: 11104 case BCM57810_MF: 11105 case BCM57840: 11106 case BCM57840_MF: 11107 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11108 break; 11109 11110 default: 11111 pr_err("Unknown board_type (%ld), aborting\n", 11112 ent->driver_data); 11113 return -ENODEV; 11114 } 11115 11116 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11117 11118 /* !!! FIXME !!! 11119 * Do not allow the maximum SB count to grow above 16 11120 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11121 * We will use the FP_SB_MAX_E1x macro for this matter. 11122 */ 11123 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11124 11125 WARN_ON(!max_non_def_sbs); 11126 11127 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11128 rss_count = max_non_def_sbs - CNIC_PRESENT; 11129 11130 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11131 rx_count = rss_count + FCOE_PRESENT; 11132 11133 /* 11134 * Maximum number of netdev Tx queues: 11135 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11136 */ 11137 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11138 11139 /* dev zeroed in init_etherdev */ 11140 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11141 if (!dev) 11142 return -ENOMEM; 11143 11144 bp = netdev_priv(dev); 11145 11146 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 11147 tx_count, rx_count); 11148 11149 bp->igu_sb_cnt = max_non_def_sbs; 11150 bp->msg_enable = debug; 11151 pci_set_drvdata(pdev, dev); 11152 11153 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11154 if (rc < 0) { 11155 free_netdev(dev); 11156 return rc; 11157 } 11158 11159 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 11160 11161 rc = bnx2x_init_bp(bp); 11162 if (rc) 11163 goto init_one_exit; 11164 11165 /* 11166 * Map doorbels here as we need the real value of bp->max_cos which 11167 * is initialized in bnx2x_init_bp(). 11168 */ 11169 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11170 min_t(u64, BNX2X_DB_SIZE(bp), 11171 pci_resource_len(pdev, 2))); 11172 if (!bp->doorbells) { 11173 dev_err(&bp->pdev->dev, 11174 "Cannot map doorbell space, aborting\n"); 11175 rc = -ENOMEM; 11176 goto init_one_exit; 11177 } 11178 11179 /* calc qm_cid_count */ 11180 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11181 11182#ifdef BCM_CNIC 11183 /* disable FCOE L2 queue for E1x */ 11184 if (CHIP_IS_E1x(bp)) 11185 bp->flags |= NO_FCOE_FLAG; 11186 11187#endif 11188 11189 /* Configure interrupt mode: try to enable MSI-X/MSI if 11190 * needed, set bp->num_queues appropriately. 11191 */ 11192 bnx2x_set_int_mode(bp); 11193 11194 /* Add all NAPI objects */ 11195 bnx2x_add_all_napi(bp); 11196 11197 rc = register_netdev(dev); 11198 if (rc) { 11199 dev_err(&pdev->dev, "Cannot register net device\n"); 11200 goto init_one_exit; 11201 } 11202 11203#ifdef BCM_CNIC 11204 if (!NO_FCOE(bp)) { 11205 /* Add storage MAC address */ 11206 rtnl_lock(); 11207 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11208 rtnl_unlock(); 11209 } 11210#endif 11211 11212 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11213 11214 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11215 board_info[ent->driver_data].name, 11216 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11217 pcie_width, 11218 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11219 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11220 "5GHz (Gen2)" : "2.5GHz", 11221 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11222 11223 return 0; 11224 11225init_one_exit: 11226 if (bp->regview) 11227 iounmap(bp->regview); 11228 11229 if (bp->doorbells) 11230 iounmap(bp->doorbells); 11231 11232 free_netdev(dev); 11233 11234 if (atomic_read(&pdev->enable_cnt) == 1) 11235 pci_release_regions(pdev); 11236 11237 pci_disable_device(pdev); 11238 pci_set_drvdata(pdev, NULL); 11239 11240 return rc; 11241} 11242 11243static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11244{ 11245 struct net_device *dev = pci_get_drvdata(pdev); 11246 struct bnx2x *bp; 11247 11248 if (!dev) { 11249 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11250 return; 11251 } 11252 bp = netdev_priv(dev); 11253 11254#ifdef BCM_CNIC 11255 /* Delete storage MAC address */ 11256 if (!NO_FCOE(bp)) { 11257 rtnl_lock(); 11258 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11259 rtnl_unlock(); 11260 } 11261#endif 11262 11263#ifdef BCM_DCBNL 11264 /* Delete app tlvs from dcbnl */ 11265 bnx2x_dcbnl_update_applist(bp, true); 11266#endif 11267 11268 unregister_netdev(dev); 11269 11270 /* Delete all NAPI objects */ 11271 bnx2x_del_all_napi(bp); 11272 11273 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11274 bnx2x_set_power_state(bp, PCI_D0); 11275 11276 /* Disable MSI/MSI-X */ 11277 bnx2x_disable_msi(bp); 11278 11279 /* Power off */ 11280 bnx2x_set_power_state(bp, PCI_D3hot); 11281 11282 /* Make sure RESET task is not scheduled before continuing */ 11283 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11284 11285 if (bp->regview) 11286 iounmap(bp->regview); 11287 11288 if (bp->doorbells) 11289 iounmap(bp->doorbells); 11290 11291 bnx2x_release_firmware(bp); 11292 11293 bnx2x_free_mem_bp(bp); 11294 11295 free_netdev(dev); 11296 11297 if (atomic_read(&pdev->enable_cnt) == 1) 11298 pci_release_regions(pdev); 11299 11300 pci_disable_device(pdev); 11301 pci_set_drvdata(pdev, NULL); 11302} 11303 11304static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11305{ 11306 int i; 11307 11308 bp->state = BNX2X_STATE_ERROR; 11309 11310 bp->rx_mode = BNX2X_RX_MODE_NONE; 11311 11312#ifdef BCM_CNIC 11313 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11314#endif 11315 /* Stop Tx */ 11316 bnx2x_tx_disable(bp); 11317 11318 bnx2x_netif_stop(bp, 0); 11319 11320 del_timer_sync(&bp->timer); 11321 11322 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11323 11324 /* Release IRQs */ 11325 bnx2x_free_irq(bp); 11326 11327 /* Free SKBs, SGEs, TPA pool and driver internals */ 11328 bnx2x_free_skbs(bp); 11329 11330 for_each_rx_queue(bp, i) 11331 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11332 11333 bnx2x_free_mem(bp); 11334 11335 bp->state = BNX2X_STATE_CLOSED; 11336 11337 netif_carrier_off(bp->dev); 11338 11339 return 0; 11340} 11341 11342static void bnx2x_eeh_recover(struct bnx2x *bp) 11343{ 11344 u32 val; 11345 11346 mutex_init(&bp->port.phy_mutex); 11347 11348 11349 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11350 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11351 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11352 BNX2X_ERR("BAD MCP validity signature\n"); 11353} 11354 11355/** 11356 * bnx2x_io_error_detected - called when PCI error is detected 11357 * @pdev: Pointer to PCI device 11358 * @state: The current pci connection state 11359 * 11360 * This function is called after a PCI bus error affecting 11361 * this device has been detected. 11362 */ 11363static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11364 pci_channel_state_t state) 11365{ 11366 struct net_device *dev = pci_get_drvdata(pdev); 11367 struct bnx2x *bp = netdev_priv(dev); 11368 11369 rtnl_lock(); 11370 11371 netif_device_detach(dev); 11372 11373 if (state == pci_channel_io_perm_failure) { 11374 rtnl_unlock(); 11375 return PCI_ERS_RESULT_DISCONNECT; 11376 } 11377 11378 if (netif_running(dev)) 11379 bnx2x_eeh_nic_unload(bp); 11380 11381 pci_disable_device(pdev); 11382 11383 rtnl_unlock(); 11384 11385 /* Request a slot reset */ 11386 return PCI_ERS_RESULT_NEED_RESET; 11387} 11388 11389/** 11390 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11391 * @pdev: Pointer to PCI device 11392 * 11393 * Restart the card from scratch, as if from a cold-boot. 11394 */ 11395static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11396{ 11397 struct net_device *dev = pci_get_drvdata(pdev); 11398 struct bnx2x *bp = netdev_priv(dev); 11399 11400 rtnl_lock(); 11401 11402 if (pci_enable_device(pdev)) { 11403 dev_err(&pdev->dev, 11404 "Cannot re-enable PCI device after reset\n"); 11405 rtnl_unlock(); 11406 return PCI_ERS_RESULT_DISCONNECT; 11407 } 11408 11409 pci_set_master(pdev); 11410 pci_restore_state(pdev); 11411 11412 if (netif_running(dev)) 11413 bnx2x_set_power_state(bp, PCI_D0); 11414 11415 rtnl_unlock(); 11416 11417 return PCI_ERS_RESULT_RECOVERED; 11418} 11419 11420/** 11421 * bnx2x_io_resume - called when traffic can start flowing again 11422 * @pdev: Pointer to PCI device 11423 * 11424 * This callback is called when the error recovery driver tells us that 11425 * its OK to resume normal operation. 11426 */ 11427static void bnx2x_io_resume(struct pci_dev *pdev) 11428{ 11429 struct net_device *dev = pci_get_drvdata(pdev); 11430 struct bnx2x *bp = netdev_priv(dev); 11431 11432 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11433 netdev_err(bp->dev, "Handling parity error recovery. " 11434 "Try again later\n"); 11435 return; 11436 } 11437 11438 rtnl_lock(); 11439 11440 bnx2x_eeh_recover(bp); 11441 11442 if (netif_running(dev)) 11443 bnx2x_nic_load(bp, LOAD_NORMAL); 11444 11445 netif_device_attach(dev); 11446 11447 rtnl_unlock(); 11448} 11449 11450static struct pci_error_handlers bnx2x_err_handler = { 11451 .error_detected = bnx2x_io_error_detected, 11452 .slot_reset = bnx2x_io_slot_reset, 11453 .resume = bnx2x_io_resume, 11454}; 11455 11456static struct pci_driver bnx2x_pci_driver = { 11457 .name = DRV_MODULE_NAME, 11458 .id_table = bnx2x_pci_tbl, 11459 .probe = bnx2x_init_one, 11460 .remove = __devexit_p(bnx2x_remove_one), 11461 .suspend = bnx2x_suspend, 11462 .resume = bnx2x_resume, 11463 .err_handler = &bnx2x_err_handler, 11464}; 11465 11466static int __init bnx2x_init(void) 11467{ 11468 int ret; 11469 11470 pr_info("%s", version); 11471 11472 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11473 if (bnx2x_wq == NULL) { 11474 pr_err("Cannot create workqueue\n"); 11475 return -ENOMEM; 11476 } 11477 11478 ret = pci_register_driver(&bnx2x_pci_driver); 11479 if (ret) { 11480 pr_err("Cannot register driver\n"); 11481 destroy_workqueue(bnx2x_wq); 11482 } 11483 return ret; 11484} 11485 11486static void __exit bnx2x_cleanup(void) 11487{ 11488 pci_unregister_driver(&bnx2x_pci_driver); 11489 11490 destroy_workqueue(bnx2x_wq); 11491} 11492 11493void bnx2x_notify_link_changed(struct bnx2x *bp) 11494{ 11495 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11496} 11497 11498module_init(bnx2x_init); 11499module_exit(bnx2x_cleanup); 11500 11501#ifdef BCM_CNIC 11502/** 11503 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11504 * 11505 * @bp: driver handle 11506 * @set: set or clear the CAM entry 11507 * 11508 * This function will wait until the ramdord completion returns. 11509 * Return 0 if success, -ENODEV if ramrod doesn't return. 11510 */ 11511static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11512{ 11513 unsigned long ramrod_flags = 0; 11514 11515 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11516 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11517 &bp->iscsi_l2_mac_obj, true, 11518 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11519} 11520 11521/* count denotes the number of new completions we have seen */ 11522static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11523{ 11524 struct eth_spe *spe; 11525 11526#ifdef BNX2X_STOP_ON_ERROR 11527 if (unlikely(bp->panic)) 11528 return; 11529#endif 11530 11531 spin_lock_bh(&bp->spq_lock); 11532 BUG_ON(bp->cnic_spq_pending < count); 11533 bp->cnic_spq_pending -= count; 11534 11535 11536 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11537 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11538 & SPE_HDR_CONN_TYPE) >> 11539 SPE_HDR_CONN_TYPE_SHIFT; 11540 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11541 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11542 11543 /* Set validation for iSCSI L2 client before sending SETUP 11544 * ramrod 11545 */ 11546 if (type == ETH_CONNECTION_TYPE) { 11547 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11548 bnx2x_set_ctx_validation(bp, &bp->context. 11549 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11550 BNX2X_ISCSI_ETH_CID); 11551 } 11552 11553 /* 11554 * There may be not more than 8 L2, not more than 8 L5 SPEs 11555 * and in the air. We also check that number of outstanding 11556 * COMMON ramrods is not more than the EQ and SPQ can 11557 * accommodate. 11558 */ 11559 if (type == ETH_CONNECTION_TYPE) { 11560 if (!atomic_read(&bp->cq_spq_left)) 11561 break; 11562 else 11563 atomic_dec(&bp->cq_spq_left); 11564 } else if (type == NONE_CONNECTION_TYPE) { 11565 if (!atomic_read(&bp->eq_spq_left)) 11566 break; 11567 else 11568 atomic_dec(&bp->eq_spq_left); 11569 } else if ((type == ISCSI_CONNECTION_TYPE) || 11570 (type == FCOE_CONNECTION_TYPE)) { 11571 if (bp->cnic_spq_pending >= 11572 bp->cnic_eth_dev.max_kwqe_pending) 11573 break; 11574 else 11575 bp->cnic_spq_pending++; 11576 } else { 11577 BNX2X_ERR("Unknown SPE type: %d\n", type); 11578 bnx2x_panic(); 11579 break; 11580 } 11581 11582 spe = bnx2x_sp_get_next(bp); 11583 *spe = *bp->cnic_kwq_cons; 11584 11585 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11586 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11587 11588 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11589 bp->cnic_kwq_cons = bp->cnic_kwq; 11590 else 11591 bp->cnic_kwq_cons++; 11592 } 11593 bnx2x_sp_prod_update(bp); 11594 spin_unlock_bh(&bp->spq_lock); 11595} 11596 11597static int bnx2x_cnic_sp_queue(struct net_device *dev, 11598 struct kwqe_16 *kwqes[], u32 count) 11599{ 11600 struct bnx2x *bp = netdev_priv(dev); 11601 int i; 11602 11603#ifdef BNX2X_STOP_ON_ERROR 11604 if (unlikely(bp->panic)) 11605 return -EIO; 11606#endif 11607 11608 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 11609 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 11610 netdev_err(dev, "Handling parity error recovery. Try again " 11611 "later\n"); 11612 return -EAGAIN; 11613 } 11614 11615 spin_lock_bh(&bp->spq_lock); 11616 11617 for (i = 0; i < count; i++) { 11618 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11619 11620 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11621 break; 11622 11623 *bp->cnic_kwq_prod = *spe; 11624 11625 bp->cnic_kwq_pending++; 11626 11627 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11628 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11629 spe->data.update_data_addr.hi, 11630 spe->data.update_data_addr.lo, 11631 bp->cnic_kwq_pending); 11632 11633 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11634 bp->cnic_kwq_prod = bp->cnic_kwq; 11635 else 11636 bp->cnic_kwq_prod++; 11637 } 11638 11639 spin_unlock_bh(&bp->spq_lock); 11640 11641 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11642 bnx2x_cnic_sp_post(bp, 0); 11643 11644 return i; 11645} 11646 11647static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11648{ 11649 struct cnic_ops *c_ops; 11650 int rc = 0; 11651 11652 mutex_lock(&bp->cnic_mutex); 11653 c_ops = rcu_dereference_protected(bp->cnic_ops, 11654 lockdep_is_held(&bp->cnic_mutex)); 11655 if (c_ops) 11656 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11657 mutex_unlock(&bp->cnic_mutex); 11658 11659 return rc; 11660} 11661 11662static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11663{ 11664 struct cnic_ops *c_ops; 11665 int rc = 0; 11666 11667 rcu_read_lock(); 11668 c_ops = rcu_dereference(bp->cnic_ops); 11669 if (c_ops) 11670 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11671 rcu_read_unlock(); 11672 11673 return rc; 11674} 11675 11676/* 11677 * for commands that have no data 11678 */ 11679int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11680{ 11681 struct cnic_ctl_info ctl = {0}; 11682 11683 ctl.cmd = cmd; 11684 11685 return bnx2x_cnic_ctl_send(bp, &ctl); 11686} 11687 11688static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11689{ 11690 struct cnic_ctl_info ctl = {0}; 11691 11692 /* first we tell CNIC and only then we count this as a completion */ 11693 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11694 ctl.data.comp.cid = cid; 11695 ctl.data.comp.error = err; 11696 11697 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11698 bnx2x_cnic_sp_post(bp, 0); 11699} 11700 11701 11702/* Called with netif_addr_lock_bh() taken. 11703 * Sets an rx_mode config for an iSCSI ETH client. 11704 * Doesn't block. 11705 * Completion should be checked outside. 11706 */ 11707static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11708{ 11709 unsigned long accept_flags = 0, ramrod_flags = 0; 11710 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11711 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11712 11713 if (start) { 11714 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11715 * because it's the only way for UIO Queue to accept 11716 * multicasts (in non-promiscuous mode only one Queue per 11717 * function will receive multicast packets (leading in our 11718 * case). 11719 */ 11720 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11721 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11722 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11723 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11724 11725 /* Clear STOP_PENDING bit if START is requested */ 11726 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11727 11728 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11729 } else 11730 /* Clear START_PENDING bit if STOP is requested */ 11731 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11732 11733 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11734 set_bit(sched_state, &bp->sp_state); 11735 else { 11736 __set_bit(RAMROD_RX, &ramrod_flags); 11737 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11738 ramrod_flags); 11739 } 11740} 11741 11742 11743static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11744{ 11745 struct bnx2x *bp = netdev_priv(dev); 11746 int rc = 0; 11747 11748 switch (ctl->cmd) { 11749 case DRV_CTL_CTXTBL_WR_CMD: { 11750 u32 index = ctl->data.io.offset; 11751 dma_addr_t addr = ctl->data.io.dma_addr; 11752 11753 bnx2x_ilt_wr(bp, index, addr); 11754 break; 11755 } 11756 11757 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11758 int count = ctl->data.credit.credit_count; 11759 11760 bnx2x_cnic_sp_post(bp, count); 11761 break; 11762 } 11763 11764 /* rtnl_lock is held. */ 11765 case DRV_CTL_START_L2_CMD: { 11766 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11767 unsigned long sp_bits = 0; 11768 11769 /* Configure the iSCSI classification object */ 11770 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11771 cp->iscsi_l2_client_id, 11772 cp->iscsi_l2_cid, BP_FUNC(bp), 11773 bnx2x_sp(bp, mac_rdata), 11774 bnx2x_sp_mapping(bp, mac_rdata), 11775 BNX2X_FILTER_MAC_PENDING, 11776 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11777 &bp->macs_pool); 11778 11779 /* Set iSCSI MAC address */ 11780 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11781 if (rc) 11782 break; 11783 11784 mmiowb(); 11785 barrier(); 11786 11787 /* Start accepting on iSCSI L2 ring */ 11788 11789 netif_addr_lock_bh(dev); 11790 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11791 netif_addr_unlock_bh(dev); 11792 11793 /* bits to wait on */ 11794 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11795 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11796 11797 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11798 BNX2X_ERR("rx_mode completion timed out!\n"); 11799 11800 break; 11801 } 11802 11803 /* rtnl_lock is held. */ 11804 case DRV_CTL_STOP_L2_CMD: { 11805 unsigned long sp_bits = 0; 11806 11807 /* Stop accepting on iSCSI L2 ring */ 11808 netif_addr_lock_bh(dev); 11809 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11810 netif_addr_unlock_bh(dev); 11811 11812 /* bits to wait on */ 11813 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11814 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11815 11816 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11817 BNX2X_ERR("rx_mode completion timed out!\n"); 11818 11819 mmiowb(); 11820 barrier(); 11821 11822 /* Unset iSCSI L2 MAC */ 11823 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11824 BNX2X_ISCSI_ETH_MAC, true); 11825 break; 11826 } 11827 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11828 int count = ctl->data.credit.credit_count; 11829 11830 smp_mb__before_atomic_inc(); 11831 atomic_add(count, &bp->cq_spq_left); 11832 smp_mb__after_atomic_inc(); 11833 break; 11834 } 11835 case DRV_CTL_ULP_REGISTER_CMD: { 11836 int ulp_type = ctl->data.ulp_type; 11837 11838 if (CHIP_IS_E3(bp)) { 11839 int idx = BP_FW_MB_IDX(bp); 11840 u32 cap; 11841 11842 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11843 if (ulp_type == CNIC_ULP_ISCSI) 11844 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11845 else if (ulp_type == CNIC_ULP_FCOE) 11846 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11847 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11848 } 11849 break; 11850 } 11851 case DRV_CTL_ULP_UNREGISTER_CMD: { 11852 int ulp_type = ctl->data.ulp_type; 11853 11854 if (CHIP_IS_E3(bp)) { 11855 int idx = BP_FW_MB_IDX(bp); 11856 u32 cap; 11857 11858 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11859 if (ulp_type == CNIC_ULP_ISCSI) 11860 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11861 else if (ulp_type == CNIC_ULP_FCOE) 11862 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11863 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11864 } 11865 break; 11866 } 11867 11868 default: 11869 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11870 rc = -EINVAL; 11871 } 11872 11873 return rc; 11874} 11875 11876void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11877{ 11878 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11879 11880 if (bp->flags & USING_MSIX_FLAG) { 11881 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11882 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11883 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11884 } else { 11885 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11886 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11887 } 11888 if (!CHIP_IS_E1x(bp)) 11889 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11890 else 11891 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11892 11893 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11894 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11895 cp->irq_arr[1].status_blk = bp->def_status_blk; 11896 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11897 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11898 11899 cp->num_irq = 2; 11900} 11901 11902static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11903 void *data) 11904{ 11905 struct bnx2x *bp = netdev_priv(dev); 11906 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11907 11908 if (ops == NULL) 11909 return -EINVAL; 11910 11911 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11912 if (!bp->cnic_kwq) 11913 return -ENOMEM; 11914 11915 bp->cnic_kwq_cons = bp->cnic_kwq; 11916 bp->cnic_kwq_prod = bp->cnic_kwq; 11917 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11918 11919 bp->cnic_spq_pending = 0; 11920 bp->cnic_kwq_pending = 0; 11921 11922 bp->cnic_data = data; 11923 11924 cp->num_irq = 0; 11925 cp->drv_state |= CNIC_DRV_STATE_REGD; 11926 cp->iro_arr = bp->iro_arr; 11927 11928 bnx2x_setup_cnic_irq_info(bp); 11929 11930 rcu_assign_pointer(bp->cnic_ops, ops); 11931 11932 return 0; 11933} 11934 11935static int bnx2x_unregister_cnic(struct net_device *dev) 11936{ 11937 struct bnx2x *bp = netdev_priv(dev); 11938 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11939 11940 mutex_lock(&bp->cnic_mutex); 11941 cp->drv_state = 0; 11942 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11943 mutex_unlock(&bp->cnic_mutex); 11944 synchronize_rcu(); 11945 kfree(bp->cnic_kwq); 11946 bp->cnic_kwq = NULL; 11947 11948 return 0; 11949} 11950 11951struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11952{ 11953 struct bnx2x *bp = netdev_priv(dev); 11954 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11955 11956 /* If both iSCSI and FCoE are disabled - return NULL in 11957 * order to indicate CNIC that it should not try to work 11958 * with this device. 11959 */ 11960 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11961 return NULL; 11962 11963 cp->drv_owner = THIS_MODULE; 11964 cp->chip_id = CHIP_ID(bp); 11965 cp->pdev = bp->pdev; 11966 cp->io_base = bp->regview; 11967 cp->io_base2 = bp->doorbells; 11968 cp->max_kwqe_pending = 8; 11969 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11970 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11971 bnx2x_cid_ilt_lines(bp); 11972 cp->ctx_tbl_len = CNIC_ILT_LINES; 11973 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11974 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11975 cp->drv_ctl = bnx2x_drv_ctl; 11976 cp->drv_register_cnic = bnx2x_register_cnic; 11977 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11978 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11979 cp->iscsi_l2_client_id = 11980 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11981 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11982 11983 if (NO_ISCSI_OOO(bp)) 11984 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11985 11986 if (NO_ISCSI(bp)) 11987 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11988 11989 if (NO_FCOE(bp)) 11990 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11991 11992 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11993 "starting cid %d\n", 11994 cp->ctx_blk_size, 11995 cp->ctx_tbl_offset, 11996 cp->ctx_tbl_len, 11997 cp->starting_cid); 11998 return cp; 11999} 12000EXPORT_SYMBOL(bnx2x_cnic_probe); 12001 12002#endif /* BCM_CNIC */ 12003 12004