bnx2x_main.c revision aaeb6cdfa5c07533c2cd6d2c381374c69f7db9dc
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if_vlan.h> 43#include <net/ip.h> 44#include <net/ipv6.h> 45#include <net/tcp.h> 46#include <net/checksum.h> 47#include <net/ip6_checksum.h> 48#include <linux/workqueue.h> 49#include <linux/crc32.h> 50#include <linux/crc32c.h> 51#include <linux/prefetch.h> 52#include <linux/zlib.h> 53#include <linux/io.h> 54#include <linux/semaphore.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_vfpf.h" 63#include "bnx2x_dcb.h" 64#include "bnx2x_sp.h" 65 66#include <linux/firmware.h> 67#include "bnx2x_fw_file_hdr.h" 68/* FW files */ 69#define FW_FILE_VERSION \ 70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 73 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 74#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 76#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 77 78#define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) 79 80/* Time in jiffies before concluding the transmitter is hung */ 81#define TX_TIMEOUT (5*HZ) 82 83static char version[] = 84 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 85 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 86 87MODULE_AUTHOR("Eliezer Tamir"); 88MODULE_DESCRIPTION("Broadcom NetXtreme II " 89 "BCM57710/57711/57711E/" 90 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 91 "57840/57840_MF Driver"); 92MODULE_LICENSE("GPL"); 93MODULE_VERSION(DRV_MODULE_VERSION); 94MODULE_FIRMWARE(FW_FILE_NAME_E1); 95MODULE_FIRMWARE(FW_FILE_NAME_E1H); 96MODULE_FIRMWARE(FW_FILE_NAME_E2); 97 98 99int num_queues; 100module_param(num_queues, int, 0); 101MODULE_PARM_DESC(num_queues, 102 " Set number of queues (default is as a number of CPUs)"); 103 104static int disable_tpa; 105module_param(disable_tpa, int, 0); 106MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 107 108#define INT_MODE_INTx 1 109#define INT_MODE_MSI 2 110int int_mode; 111module_param(int_mode, int, 0); 112MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 113 "(1 INT#x; 2 MSI)"); 114 115static int dropless_fc; 116module_param(dropless_fc, int, 0); 117MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 118 119static int mrrs = -1; 120module_param(mrrs, int, 0); 121MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 122 123static int debug; 124module_param(debug, int, 0); 125MODULE_PARM_DESC(debug, " Default debug msglevel"); 126 127 128 129struct workqueue_struct *bnx2x_wq; 130 131enum bnx2x_board_type { 132 BCM57710 = 0, 133 BCM57711, 134 BCM57711E, 135 BCM57712, 136 BCM57712_MF, 137 BCM57712_VF, 138 BCM57800, 139 BCM57800_MF, 140 BCM57800_VF, 141 BCM57810, 142 BCM57810_MF, 143 BCM57810_VF, 144 BCM57840_4_10, 145 BCM57840_2_20, 146 BCM57840_MF, 147 BCM57840_VF, 148 BCM57811, 149 BCM57811_MF, 150 BCM57840_O, 151 BCM57840_MFO, 152 BCM57811_VF 153}; 154 155/* indexed by board_type, above */ 156static struct { 157 char *name; 158} board_info[] = { 159 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 160 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 161 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 162 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 163 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 164 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, 165 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 166 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 167 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, 168 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 169 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 170 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, 171 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, 172 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, 173 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, 174 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, 175 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, 176 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, 177 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 178 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, 179 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } 180}; 181 182#ifndef PCI_DEVICE_ID_NX2_57710 183#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 184#endif 185#ifndef PCI_DEVICE_ID_NX2_57711 186#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 187#endif 188#ifndef PCI_DEVICE_ID_NX2_57711E 189#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 190#endif 191#ifndef PCI_DEVICE_ID_NX2_57712 192#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 193#endif 194#ifndef PCI_DEVICE_ID_NX2_57712_MF 195#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 196#endif 197#ifndef PCI_DEVICE_ID_NX2_57712_VF 198#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF 199#endif 200#ifndef PCI_DEVICE_ID_NX2_57800 201#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 202#endif 203#ifndef PCI_DEVICE_ID_NX2_57800_MF 204#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 205#endif 206#ifndef PCI_DEVICE_ID_NX2_57800_VF 207#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF 208#endif 209#ifndef PCI_DEVICE_ID_NX2_57810 210#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 211#endif 212#ifndef PCI_DEVICE_ID_NX2_57810_MF 213#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 214#endif 215#ifndef PCI_DEVICE_ID_NX2_57840_O 216#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE 217#endif 218#ifndef PCI_DEVICE_ID_NX2_57810_VF 219#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF 220#endif 221#ifndef PCI_DEVICE_ID_NX2_57840_4_10 222#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 223#endif 224#ifndef PCI_DEVICE_ID_NX2_57840_2_20 225#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 226#endif 227#ifndef PCI_DEVICE_ID_NX2_57840_MFO 228#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE 229#endif 230#ifndef PCI_DEVICE_ID_NX2_57840_MF 231#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 232#endif 233#ifndef PCI_DEVICE_ID_NX2_57840_VF 234#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF 235#endif 236#ifndef PCI_DEVICE_ID_NX2_57811 237#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 238#endif 239#ifndef PCI_DEVICE_ID_NX2_57811_MF 240#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF 241#endif 242#ifndef PCI_DEVICE_ID_NX2_57811_VF 243#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF 244#endif 245 246static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 247 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 248 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 249 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 250 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 251 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, 253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, 259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, 268 { 0 } 269}; 270 271MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 272 273/* Global resources for unloading a previously loaded device */ 274#define BNX2X_PREV_WAIT_NEEDED 1 275static DEFINE_SEMAPHORE(bnx2x_prev_sem); 276static LIST_HEAD(bnx2x_prev_list); 277/**************************************************************************** 278* General service functions 279****************************************************************************/ 280 281static void __storm_memset_dma_mapping(struct bnx2x *bp, 282 u32 addr, dma_addr_t mapping) 283{ 284 REG_WR(bp, addr, U64_LO(mapping)); 285 REG_WR(bp, addr + 4, U64_HI(mapping)); 286} 287 288static void storm_memset_spq_addr(struct bnx2x *bp, 289 dma_addr_t mapping, u16 abs_fid) 290{ 291 u32 addr = XSEM_REG_FAST_MEMORY + 292 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 293 294 __storm_memset_dma_mapping(bp, addr, mapping); 295} 296 297static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 298 u16 pf_id) 299{ 300 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 301 pf_id); 302 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 303 pf_id); 304 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 305 pf_id); 306 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 307 pf_id); 308} 309 310static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 311 u8 enable) 312{ 313 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 314 enable); 315 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 316 enable); 317 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 318 enable); 319 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 320 enable); 321} 322 323static void storm_memset_eq_data(struct bnx2x *bp, 324 struct event_ring_data *eq_data, 325 u16 pfid) 326{ 327 size_t size = sizeof(struct event_ring_data); 328 329 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 330 331 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 332} 333 334static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 335 u16 pfid) 336{ 337 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 338 REG_WR16(bp, addr, eq_prod); 339} 340 341/* used only at init 342 * locking is done by mcp 343 */ 344static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 345{ 346 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 347 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 348 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 349 PCICFG_VENDOR_ID_OFFSET); 350} 351 352static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 353{ 354 u32 val; 355 356 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 357 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 358 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 359 PCICFG_VENDOR_ID_OFFSET); 360 361 return val; 362} 363 364#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 365#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 366#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 367#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 368#define DMAE_DP_DST_NONE "dst_addr [none]" 369 370void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl) 371{ 372 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 373 374 switch (dmae->opcode & DMAE_COMMAND_DST) { 375 case DMAE_CMD_DST_PCI: 376 if (src_type == DMAE_CMD_SRC_PCI) 377 DP(msglvl, "DMAE: opcode 0x%08x\n" 378 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 379 "comp_addr [%x:%08x], comp_val 0x%08x\n", 380 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 381 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 382 dmae->comp_addr_hi, dmae->comp_addr_lo, 383 dmae->comp_val); 384 else 385 DP(msglvl, "DMAE: opcode 0x%08x\n" 386 "src [%08x], len [%d*4], dst [%x:%08x]\n" 387 "comp_addr [%x:%08x], comp_val 0x%08x\n", 388 dmae->opcode, dmae->src_addr_lo >> 2, 389 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 390 dmae->comp_addr_hi, dmae->comp_addr_lo, 391 dmae->comp_val); 392 break; 393 case DMAE_CMD_DST_GRC: 394 if (src_type == DMAE_CMD_SRC_PCI) 395 DP(msglvl, "DMAE: opcode 0x%08x\n" 396 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 397 "comp_addr [%x:%08x], comp_val 0x%08x\n", 398 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 399 dmae->len, dmae->dst_addr_lo >> 2, 400 dmae->comp_addr_hi, dmae->comp_addr_lo, 401 dmae->comp_val); 402 else 403 DP(msglvl, "DMAE: opcode 0x%08x\n" 404 "src [%08x], len [%d*4], dst [%08x]\n" 405 "comp_addr [%x:%08x], comp_val 0x%08x\n", 406 dmae->opcode, dmae->src_addr_lo >> 2, 407 dmae->len, dmae->dst_addr_lo >> 2, 408 dmae->comp_addr_hi, dmae->comp_addr_lo, 409 dmae->comp_val); 410 break; 411 default: 412 if (src_type == DMAE_CMD_SRC_PCI) 413 DP(msglvl, "DMAE: opcode 0x%08x\n" 414 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 415 "comp_addr [%x:%08x] comp_val 0x%08x\n", 416 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 417 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 418 dmae->comp_val); 419 else 420 DP(msglvl, "DMAE: opcode 0x%08x\n" 421 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 422 "comp_addr [%x:%08x] comp_val 0x%08x\n", 423 dmae->opcode, dmae->src_addr_lo >> 2, 424 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 425 dmae->comp_val); 426 break; 427 } 428} 429 430/* copy command into DMAE command memory and set DMAE command go */ 431void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 432{ 433 u32 cmd_offset; 434 int i; 435 436 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 437 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 438 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 439 } 440 REG_WR(bp, dmae_reg_go_c[idx], 1); 441} 442 443u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 444{ 445 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 446 DMAE_CMD_C_ENABLE); 447} 448 449u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 450{ 451 return opcode & ~DMAE_CMD_SRC_RESET; 452} 453 454u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 455 bool with_comp, u8 comp_type) 456{ 457 u32 opcode = 0; 458 459 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 460 (dst_type << DMAE_COMMAND_DST_SHIFT)); 461 462 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 463 464 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 465 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 466 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 467 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 468 469#ifdef __BIG_ENDIAN 470 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 471#else 472 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 473#endif 474 if (with_comp) 475 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 476 return opcode; 477} 478 479void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 480 struct dmae_command *dmae, 481 u8 src_type, u8 dst_type) 482{ 483 memset(dmae, 0, sizeof(struct dmae_command)); 484 485 /* set the opcode */ 486 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 487 true, DMAE_COMP_PCI); 488 489 /* fill in the completion parameters */ 490 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 491 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 492 dmae->comp_val = DMAE_COMP_VAL; 493} 494 495/* issue a dmae command over the init-channel and wait for completion */ 496int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae) 497{ 498 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 499 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 500 int rc = 0; 501 502 /* 503 * Lock the dmae channel. Disable BHs to prevent a dead-lock 504 * as long as this code is called both from syscall context and 505 * from ndo_set_rx_mode() flow that may be called from BH. 506 */ 507 spin_lock_bh(&bp->dmae_lock); 508 509 /* reset completion */ 510 *wb_comp = 0; 511 512 /* post the command on the channel used for initializations */ 513 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 514 515 /* wait for completion */ 516 udelay(5); 517 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 518 519 if (!cnt || 520 (bp->recovery_state != BNX2X_RECOVERY_DONE && 521 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 522 BNX2X_ERR("DMAE timeout!\n"); 523 rc = DMAE_TIMEOUT; 524 goto unlock; 525 } 526 cnt--; 527 udelay(50); 528 } 529 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 530 BNX2X_ERR("DMAE PCI error!\n"); 531 rc = DMAE_PCI_ERROR; 532 } 533 534unlock: 535 spin_unlock_bh(&bp->dmae_lock); 536 return rc; 537} 538 539void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 540 u32 len32) 541{ 542 struct dmae_command dmae; 543 544 if (!bp->dmae_ready) { 545 u32 *data = bnx2x_sp(bp, wb_data[0]); 546 547 if (CHIP_IS_E1(bp)) 548 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 549 else 550 bnx2x_init_str_wr(bp, dst_addr, data, len32); 551 return; 552 } 553 554 /* set opcode and fixed command fields */ 555 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 556 557 /* fill in addresses and len */ 558 dmae.src_addr_lo = U64_LO(dma_addr); 559 dmae.src_addr_hi = U64_HI(dma_addr); 560 dmae.dst_addr_lo = dst_addr >> 2; 561 dmae.dst_addr_hi = 0; 562 dmae.len = len32; 563 564 /* issue the command and wait for completion */ 565 bnx2x_issue_dmae_with_comp(bp, &dmae); 566} 567 568void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 569{ 570 struct dmae_command dmae; 571 572 if (!bp->dmae_ready) { 573 u32 *data = bnx2x_sp(bp, wb_data[0]); 574 int i; 575 576 if (CHIP_IS_E1(bp)) 577 for (i = 0; i < len32; i++) 578 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 579 else 580 for (i = 0; i < len32; i++) 581 data[i] = REG_RD(bp, src_addr + i*4); 582 583 return; 584 } 585 586 /* set opcode and fixed command fields */ 587 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 588 589 /* fill in addresses and len */ 590 dmae.src_addr_lo = src_addr >> 2; 591 dmae.src_addr_hi = 0; 592 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 593 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 594 dmae.len = len32; 595 596 /* issue the command and wait for completion */ 597 bnx2x_issue_dmae_with_comp(bp, &dmae); 598} 599 600static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 601 u32 addr, u32 len) 602{ 603 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 604 int offset = 0; 605 606 while (len > dmae_wr_max) { 607 bnx2x_write_dmae(bp, phys_addr + offset, 608 addr + offset, dmae_wr_max); 609 offset += dmae_wr_max * 4; 610 len -= dmae_wr_max; 611 } 612 613 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 614} 615 616static int bnx2x_mc_assert(struct bnx2x *bp) 617{ 618 char last_idx; 619 int i, rc = 0; 620 u32 row0, row1, row2, row3; 621 622 /* XSTORM */ 623 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 624 XSTORM_ASSERT_LIST_INDEX_OFFSET); 625 if (last_idx) 626 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 627 628 /* print the asserts */ 629 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 630 631 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 632 XSTORM_ASSERT_LIST_OFFSET(i)); 633 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 634 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 635 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 636 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 637 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 638 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 639 640 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 641 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 642 i, row3, row2, row1, row0); 643 rc++; 644 } else { 645 break; 646 } 647 } 648 649 /* TSTORM */ 650 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 651 TSTORM_ASSERT_LIST_INDEX_OFFSET); 652 if (last_idx) 653 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 654 655 /* print the asserts */ 656 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 657 658 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 659 TSTORM_ASSERT_LIST_OFFSET(i)); 660 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 661 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 662 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 663 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 664 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 665 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 666 667 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 668 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 669 i, row3, row2, row1, row0); 670 rc++; 671 } else { 672 break; 673 } 674 } 675 676 /* CSTORM */ 677 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 678 CSTORM_ASSERT_LIST_INDEX_OFFSET); 679 if (last_idx) 680 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 681 682 /* print the asserts */ 683 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 684 685 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 686 CSTORM_ASSERT_LIST_OFFSET(i)); 687 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 688 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 689 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 690 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 691 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 692 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 693 694 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 695 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 696 i, row3, row2, row1, row0); 697 rc++; 698 } else { 699 break; 700 } 701 } 702 703 /* USTORM */ 704 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 705 USTORM_ASSERT_LIST_INDEX_OFFSET); 706 if (last_idx) 707 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 708 709 /* print the asserts */ 710 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 711 712 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 713 USTORM_ASSERT_LIST_OFFSET(i)); 714 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 715 USTORM_ASSERT_LIST_OFFSET(i) + 4); 716 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 717 USTORM_ASSERT_LIST_OFFSET(i) + 8); 718 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 719 USTORM_ASSERT_LIST_OFFSET(i) + 12); 720 721 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 722 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 723 i, row3, row2, row1, row0); 724 rc++; 725 } else { 726 break; 727 } 728 } 729 730 return rc; 731} 732 733void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 734{ 735 u32 addr, val; 736 u32 mark, offset; 737 __be32 data[9]; 738 int word; 739 u32 trace_shmem_base; 740 if (BP_NOMCP(bp)) { 741 BNX2X_ERR("NO MCP - can not dump\n"); 742 return; 743 } 744 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 745 (bp->common.bc_ver & 0xff0000) >> 16, 746 (bp->common.bc_ver & 0xff00) >> 8, 747 (bp->common.bc_ver & 0xff)); 748 749 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 750 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 751 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); 752 753 if (BP_PATH(bp) == 0) 754 trace_shmem_base = bp->common.shmem_base; 755 else 756 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 757 addr = trace_shmem_base - 0x800; 758 759 /* validate TRCB signature */ 760 mark = REG_RD(bp, addr); 761 if (mark != MFW_TRACE_SIGNATURE) { 762 BNX2X_ERR("Trace buffer signature is missing."); 763 return ; 764 } 765 766 /* read cyclic buffer pointer */ 767 addr += 4; 768 mark = REG_RD(bp, addr); 769 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 770 + ((mark + 0x3) & ~0x3) - 0x08000000; 771 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 772 773 printk("%s", lvl); 774 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 775 for (word = 0; word < 8; word++) 776 data[word] = htonl(REG_RD(bp, offset + 4*word)); 777 data[8] = 0x0; 778 pr_cont("%s", (char *)data); 779 } 780 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 781 for (word = 0; word < 8; word++) 782 data[word] = htonl(REG_RD(bp, offset + 4*word)); 783 data[8] = 0x0; 784 pr_cont("%s", (char *)data); 785 } 786 printk("%s" "end of fw dump\n", lvl); 787} 788 789static void bnx2x_fw_dump(struct bnx2x *bp) 790{ 791 bnx2x_fw_dump_lvl(bp, KERN_ERR); 792} 793 794void bnx2x_panic_dump(struct bnx2x *bp) 795{ 796 int i; 797 u16 j; 798 struct hc_sp_status_block_data sp_sb_data; 799 int func = BP_FUNC(bp); 800#ifdef BNX2X_STOP_ON_ERROR 801 u16 start = 0, end = 0; 802 u8 cos; 803#endif 804 805 bp->stats_state = STATS_STATE_DISABLED; 806 bp->eth_stats.unrecoverable_error++; 807 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 808 809 BNX2X_ERR("begin crash dump -----------------\n"); 810 811 /* Indices */ 812 /* Common */ 813 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 814 bp->def_idx, bp->def_att_idx, bp->attn_state, 815 bp->spq_prod_idx, bp->stats_counter); 816 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 817 bp->def_status_blk->atten_status_block.attn_bits, 818 bp->def_status_blk->atten_status_block.attn_bits_ack, 819 bp->def_status_blk->atten_status_block.status_block_id, 820 bp->def_status_blk->atten_status_block.attn_bits_index); 821 BNX2X_ERR(" def ("); 822 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 823 pr_cont("0x%x%s", 824 bp->def_status_blk->sp_sb.index_values[i], 825 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 826 827 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 828 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 829 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 830 i*sizeof(u32)); 831 832 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 833 sp_sb_data.igu_sb_id, 834 sp_sb_data.igu_seg_id, 835 sp_sb_data.p_func.pf_id, 836 sp_sb_data.p_func.vnic_id, 837 sp_sb_data.p_func.vf_id, 838 sp_sb_data.p_func.vf_valid, 839 sp_sb_data.state); 840 841 842 for_each_eth_queue(bp, i) { 843 struct bnx2x_fastpath *fp = &bp->fp[i]; 844 int loop; 845 struct hc_status_block_data_e2 sb_data_e2; 846 struct hc_status_block_data_e1x sb_data_e1x; 847 struct hc_status_block_sm *hc_sm_p = 848 CHIP_IS_E1x(bp) ? 849 sb_data_e1x.common.state_machine : 850 sb_data_e2.common.state_machine; 851 struct hc_index_data *hc_index_p = 852 CHIP_IS_E1x(bp) ? 853 sb_data_e1x.index_data : 854 sb_data_e2.index_data; 855 u8 data_size, cos; 856 u32 *sb_data_p; 857 struct bnx2x_fp_txdata txdata; 858 859 /* Rx */ 860 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 861 i, fp->rx_bd_prod, fp->rx_bd_cons, 862 fp->rx_comp_prod, 863 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 864 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", 865 fp->rx_sge_prod, fp->last_max_sge, 866 le16_to_cpu(fp->fp_hc_idx)); 867 868 /* Tx */ 869 for_each_cos_in_tx_queue(fp, cos) 870 { 871 txdata = *fp->txdata_ptr[cos]; 872 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", 873 i, txdata.tx_pkt_prod, 874 txdata.tx_pkt_cons, txdata.tx_bd_prod, 875 txdata.tx_bd_cons, 876 le16_to_cpu(*txdata.tx_cons_sb)); 877 } 878 879 loop = CHIP_IS_E1x(bp) ? 880 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 881 882 /* host sb data */ 883 884 if (IS_FCOE_FP(fp)) 885 continue; 886 887 BNX2X_ERR(" run indexes ("); 888 for (j = 0; j < HC_SB_MAX_SM; j++) 889 pr_cont("0x%x%s", 890 fp->sb_running_index[j], 891 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 892 893 BNX2X_ERR(" indexes ("); 894 for (j = 0; j < loop; j++) 895 pr_cont("0x%x%s", 896 fp->sb_index_values[j], 897 (j == loop - 1) ? ")" : " "); 898 /* fw sb data */ 899 data_size = CHIP_IS_E1x(bp) ? 900 sizeof(struct hc_status_block_data_e1x) : 901 sizeof(struct hc_status_block_data_e2); 902 data_size /= sizeof(u32); 903 sb_data_p = CHIP_IS_E1x(bp) ? 904 (u32 *)&sb_data_e1x : 905 (u32 *)&sb_data_e2; 906 /* copy sb data in here */ 907 for (j = 0; j < data_size; j++) 908 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 909 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 910 j * sizeof(u32)); 911 912 if (!CHIP_IS_E1x(bp)) { 913 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 914 sb_data_e2.common.p_func.pf_id, 915 sb_data_e2.common.p_func.vf_id, 916 sb_data_e2.common.p_func.vf_valid, 917 sb_data_e2.common.p_func.vnic_id, 918 sb_data_e2.common.same_igu_sb_1b, 919 sb_data_e2.common.state); 920 } else { 921 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 922 sb_data_e1x.common.p_func.pf_id, 923 sb_data_e1x.common.p_func.vf_id, 924 sb_data_e1x.common.p_func.vf_valid, 925 sb_data_e1x.common.p_func.vnic_id, 926 sb_data_e1x.common.same_igu_sb_1b, 927 sb_data_e1x.common.state); 928 } 929 930 /* SB_SMs data */ 931 for (j = 0; j < HC_SB_MAX_SM; j++) { 932 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", 933 j, hc_sm_p[j].__flags, 934 hc_sm_p[j].igu_sb_id, 935 hc_sm_p[j].igu_seg_id, 936 hc_sm_p[j].time_to_expire, 937 hc_sm_p[j].timer_value); 938 } 939 940 /* Indecies data */ 941 for (j = 0; j < loop; j++) { 942 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, 943 hc_index_p[j].flags, 944 hc_index_p[j].timeout); 945 } 946 } 947 948#ifdef BNX2X_STOP_ON_ERROR 949 /* Rings */ 950 /* Rx */ 951 for_each_valid_rx_queue(bp, i) { 952 struct bnx2x_fastpath *fp = &bp->fp[i]; 953 954 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 955 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 956 for (j = start; j != end; j = RX_BD(j + 1)) { 957 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 958 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 959 960 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 961 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 962 } 963 964 start = RX_SGE(fp->rx_sge_prod); 965 end = RX_SGE(fp->last_max_sge); 966 for (j = start; j != end; j = RX_SGE(j + 1)) { 967 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 968 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 969 970 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 971 i, j, rx_sge[1], rx_sge[0], sw_page->page); 972 } 973 974 start = RCQ_BD(fp->rx_comp_cons - 10); 975 end = RCQ_BD(fp->rx_comp_cons + 503); 976 for (j = start; j != end; j = RCQ_BD(j + 1)) { 977 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 978 979 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 980 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 981 } 982 } 983 984 /* Tx */ 985 for_each_valid_tx_queue(bp, i) { 986 struct bnx2x_fastpath *fp = &bp->fp[i]; 987 for_each_cos_in_tx_queue(fp, cos) { 988 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; 989 990 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 991 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 992 for (j = start; j != end; j = TX_BD(j + 1)) { 993 struct sw_tx_bd *sw_bd = 994 &txdata->tx_buf_ring[j]; 995 996 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", 997 i, cos, j, sw_bd->skb, 998 sw_bd->first_bd); 999 } 1000 1001 start = TX_BD(txdata->tx_bd_cons - 10); 1002 end = TX_BD(txdata->tx_bd_cons + 254); 1003 for (j = start; j != end; j = TX_BD(j + 1)) { 1004 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 1005 1006 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", 1007 i, cos, j, tx_bd[0], tx_bd[1], 1008 tx_bd[2], tx_bd[3]); 1009 } 1010 } 1011 } 1012#endif 1013 bnx2x_fw_dump(bp); 1014 bnx2x_mc_assert(bp); 1015 BNX2X_ERR("end crash dump -----------------\n"); 1016} 1017 1018/* 1019 * FLR Support for E2 1020 * 1021 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1022 * initialization. 1023 */ 1024#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1025#define FLR_WAIT_INTERVAL 50 /* usec */ 1026#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1027 1028struct pbf_pN_buf_regs { 1029 int pN; 1030 u32 init_crd; 1031 u32 crd; 1032 u32 crd_freed; 1033}; 1034 1035struct pbf_pN_cmd_regs { 1036 int pN; 1037 u32 lines_occup; 1038 u32 lines_freed; 1039}; 1040 1041static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1042 struct pbf_pN_buf_regs *regs, 1043 u32 poll_count) 1044{ 1045 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1046 u32 cur_cnt = poll_count; 1047 1048 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1049 crd = crd_start = REG_RD(bp, regs->crd); 1050 init_crd = REG_RD(bp, regs->init_crd); 1051 1052 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1053 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1055 1056 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1057 (init_crd - crd_start))) { 1058 if (cur_cnt--) { 1059 udelay(FLR_WAIT_INTERVAL); 1060 crd = REG_RD(bp, regs->crd); 1061 crd_freed = REG_RD(bp, regs->crd_freed); 1062 } else { 1063 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1064 regs->pN); 1065 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1066 regs->pN, crd); 1067 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1068 regs->pN, crd_freed); 1069 break; 1070 } 1071 } 1072 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1073 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1074} 1075 1076static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1077 struct pbf_pN_cmd_regs *regs, 1078 u32 poll_count) 1079{ 1080 u32 occup, to_free, freed, freed_start; 1081 u32 cur_cnt = poll_count; 1082 1083 occup = to_free = REG_RD(bp, regs->lines_occup); 1084 freed = freed_start = REG_RD(bp, regs->lines_freed); 1085 1086 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1087 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1088 1089 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1090 if (cur_cnt--) { 1091 udelay(FLR_WAIT_INTERVAL); 1092 occup = REG_RD(bp, regs->lines_occup); 1093 freed = REG_RD(bp, regs->lines_freed); 1094 } else { 1095 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1096 regs->pN); 1097 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1098 regs->pN, occup); 1099 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1100 regs->pN, freed); 1101 break; 1102 } 1103 } 1104 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1105 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1106} 1107 1108static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1109 u32 expected, u32 poll_count) 1110{ 1111 u32 cur_cnt = poll_count; 1112 u32 val; 1113 1114 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1115 udelay(FLR_WAIT_INTERVAL); 1116 1117 return val; 1118} 1119 1120int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1121 char *msg, u32 poll_cnt) 1122{ 1123 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1124 if (val != 0) { 1125 BNX2X_ERR("%s usage count=%d\n", msg, val); 1126 return 1; 1127 } 1128 return 0; 1129} 1130 1131/* Common routines with VF FLR cleanup */ 1132u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1133{ 1134 /* adjust polling timeout */ 1135 if (CHIP_REV_IS_EMUL(bp)) 1136 return FLR_POLL_CNT * 2000; 1137 1138 if (CHIP_REV_IS_FPGA(bp)) 1139 return FLR_POLL_CNT * 120; 1140 1141 return FLR_POLL_CNT; 1142} 1143 1144void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1145{ 1146 struct pbf_pN_cmd_regs cmd_regs[] = { 1147 {0, (CHIP_IS_E3B0(bp)) ? 1148 PBF_REG_TQ_OCCUPANCY_Q0 : 1149 PBF_REG_P0_TQ_OCCUPANCY, 1150 (CHIP_IS_E3B0(bp)) ? 1151 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1152 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1153 {1, (CHIP_IS_E3B0(bp)) ? 1154 PBF_REG_TQ_OCCUPANCY_Q1 : 1155 PBF_REG_P1_TQ_OCCUPANCY, 1156 (CHIP_IS_E3B0(bp)) ? 1157 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1158 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1159 {4, (CHIP_IS_E3B0(bp)) ? 1160 PBF_REG_TQ_OCCUPANCY_LB_Q : 1161 PBF_REG_P4_TQ_OCCUPANCY, 1162 (CHIP_IS_E3B0(bp)) ? 1163 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1164 PBF_REG_P4_TQ_LINES_FREED_CNT} 1165 }; 1166 1167 struct pbf_pN_buf_regs buf_regs[] = { 1168 {0, (CHIP_IS_E3B0(bp)) ? 1169 PBF_REG_INIT_CRD_Q0 : 1170 PBF_REG_P0_INIT_CRD , 1171 (CHIP_IS_E3B0(bp)) ? 1172 PBF_REG_CREDIT_Q0 : 1173 PBF_REG_P0_CREDIT, 1174 (CHIP_IS_E3B0(bp)) ? 1175 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1176 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1177 {1, (CHIP_IS_E3B0(bp)) ? 1178 PBF_REG_INIT_CRD_Q1 : 1179 PBF_REG_P1_INIT_CRD, 1180 (CHIP_IS_E3B0(bp)) ? 1181 PBF_REG_CREDIT_Q1 : 1182 PBF_REG_P1_CREDIT, 1183 (CHIP_IS_E3B0(bp)) ? 1184 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1185 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1186 {4, (CHIP_IS_E3B0(bp)) ? 1187 PBF_REG_INIT_CRD_LB_Q : 1188 PBF_REG_P4_INIT_CRD, 1189 (CHIP_IS_E3B0(bp)) ? 1190 PBF_REG_CREDIT_LB_Q : 1191 PBF_REG_P4_CREDIT, 1192 (CHIP_IS_E3B0(bp)) ? 1193 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1194 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1195 }; 1196 1197 int i; 1198 1199 /* Verify the command queues are flushed P0, P1, P4 */ 1200 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1201 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1202 1203 1204 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1205 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1206 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1207} 1208 1209#define OP_GEN_PARAM(param) \ 1210 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1211 1212#define OP_GEN_TYPE(type) \ 1213 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1214 1215#define OP_GEN_AGG_VECT(index) \ 1216 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1217 1218 1219int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) 1220{ 1221 struct sdm_op_gen op_gen = {0}; 1222 1223 u32 comp_addr = BAR_CSTRORM_INTMEM + 1224 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1225 int ret = 0; 1226 1227 if (REG_RD(bp, comp_addr)) { 1228 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1229 return 1; 1230 } 1231 1232 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1233 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1234 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1235 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1236 1237 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1238 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1239 1240 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1241 BNX2X_ERR("FW final cleanup did not succeed\n"); 1242 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", 1243 (REG_RD(bp, comp_addr))); 1244 bnx2x_panic(); 1245 return 1; 1246 } 1247 /* Zero completion for nxt FLR */ 1248 REG_WR(bp, comp_addr, 0); 1249 1250 return ret; 1251} 1252 1253u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1254{ 1255 u16 status; 1256 1257 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 1258 return status & PCI_EXP_DEVSTA_TRPND; 1259} 1260 1261/* PF FLR specific routines 1262*/ 1263static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1264{ 1265 1266 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1267 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1268 CFC_REG_NUM_LCIDS_INSIDE_PF, 1269 "CFC PF usage counter timed out", 1270 poll_cnt)) 1271 return 1; 1272 1273 1274 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1275 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1276 DORQ_REG_PF_USAGE_CNT, 1277 "DQ PF usage counter timed out", 1278 poll_cnt)) 1279 return 1; 1280 1281 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1282 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1283 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1284 "QM PF usage counter timed out", 1285 poll_cnt)) 1286 return 1; 1287 1288 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1289 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1290 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1291 "Timers VNIC usage counter timed out", 1292 poll_cnt)) 1293 return 1; 1294 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1295 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1296 "Timers NUM_SCANS usage counter timed out", 1297 poll_cnt)) 1298 return 1; 1299 1300 /* Wait DMAE PF usage counter to zero */ 1301 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1302 dmae_reg_go_c[INIT_DMAE_C(bp)], 1303 "DMAE dommand register timed out", 1304 poll_cnt)) 1305 return 1; 1306 1307 return 0; 1308} 1309 1310static void bnx2x_hw_enable_status(struct bnx2x *bp) 1311{ 1312 u32 val; 1313 1314 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1315 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1316 1317 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1318 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1319 1320 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1321 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1322 1323 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1324 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1325 1326 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1327 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1328 1329 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1330 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1331 1332 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1333 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1334 1335 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1336 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1337 val); 1338} 1339 1340static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1341{ 1342 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1343 1344 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1345 1346 /* Re-enable PF target read access */ 1347 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1348 1349 /* Poll HW usage counters */ 1350 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1351 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1352 return -EBUSY; 1353 1354 /* Zero the igu 'trailing edge' and 'leading edge' */ 1355 1356 /* Send the FW cleanup command */ 1357 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1358 return -EBUSY; 1359 1360 /* ATC cleanup */ 1361 1362 /* Verify TX hw is flushed */ 1363 bnx2x_tx_hw_flushed(bp, poll_cnt); 1364 1365 /* Wait 100ms (not adjusted according to platform) */ 1366 msleep(100); 1367 1368 /* Verify no pending pci transactions */ 1369 if (bnx2x_is_pcie_pending(bp->pdev)) 1370 BNX2X_ERR("PCIE Transactions still pending\n"); 1371 1372 /* Debug */ 1373 bnx2x_hw_enable_status(bp); 1374 1375 /* 1376 * Master enable - Due to WB DMAE writes performed before this 1377 * register is re-initialized as part of the regular function init 1378 */ 1379 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1380 1381 return 0; 1382} 1383 1384static void bnx2x_hc_int_enable(struct bnx2x *bp) 1385{ 1386 int port = BP_PORT(bp); 1387 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1388 u32 val = REG_RD(bp, addr); 1389 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1390 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1391 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1392 1393 if (msix) { 1394 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1395 HC_CONFIG_0_REG_INT_LINE_EN_0); 1396 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1397 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1398 if (single_msix) 1399 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 1400 } else if (msi) { 1401 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1402 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1403 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1404 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1405 } else { 1406 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1407 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1408 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1409 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1410 1411 if (!CHIP_IS_E1(bp)) { 1412 DP(NETIF_MSG_IFUP, 1413 "write %x to HC %d (addr 0x%x)\n", val, port, addr); 1414 1415 REG_WR(bp, addr, val); 1416 1417 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1418 } 1419 } 1420 1421 if (CHIP_IS_E1(bp)) 1422 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1423 1424 DP(NETIF_MSG_IFUP, 1425 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, 1426 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1427 1428 REG_WR(bp, addr, val); 1429 /* 1430 * Ensure that HC_CONFIG is written before leading/trailing edge config 1431 */ 1432 mmiowb(); 1433 barrier(); 1434 1435 if (!CHIP_IS_E1(bp)) { 1436 /* init leading/trailing edge */ 1437 if (IS_MF(bp)) { 1438 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1439 if (bp->port.pmf) 1440 /* enable nig and gpio3 attention */ 1441 val |= 0x1100; 1442 } else 1443 val = 0xffff; 1444 1445 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1446 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1447 } 1448 1449 /* Make sure that interrupts are indeed enabled from here on */ 1450 mmiowb(); 1451} 1452 1453static void bnx2x_igu_int_enable(struct bnx2x *bp) 1454{ 1455 u32 val; 1456 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1457 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1458 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1459 1460 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1461 1462 if (msix) { 1463 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1464 IGU_PF_CONF_SINGLE_ISR_EN); 1465 val |= (IGU_PF_CONF_FUNC_EN | 1466 IGU_PF_CONF_MSI_MSIX_EN | 1467 IGU_PF_CONF_ATTN_BIT_EN); 1468 1469 if (single_msix) 1470 val |= IGU_PF_CONF_SINGLE_ISR_EN; 1471 } else if (msi) { 1472 val &= ~IGU_PF_CONF_INT_LINE_EN; 1473 val |= (IGU_PF_CONF_FUNC_EN | 1474 IGU_PF_CONF_MSI_MSIX_EN | 1475 IGU_PF_CONF_ATTN_BIT_EN | 1476 IGU_PF_CONF_SINGLE_ISR_EN); 1477 } else { 1478 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1479 val |= (IGU_PF_CONF_FUNC_EN | 1480 IGU_PF_CONF_INT_LINE_EN | 1481 IGU_PF_CONF_ATTN_BIT_EN | 1482 IGU_PF_CONF_SINGLE_ISR_EN); 1483 } 1484 1485 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", 1486 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1487 1488 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1489 1490 if (val & IGU_PF_CONF_INT_LINE_EN) 1491 pci_intx(bp->pdev, true); 1492 1493 barrier(); 1494 1495 /* init leading/trailing edge */ 1496 if (IS_MF(bp)) { 1497 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1498 if (bp->port.pmf) 1499 /* enable nig and gpio3 attention */ 1500 val |= 0x1100; 1501 } else 1502 val = 0xffff; 1503 1504 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1505 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1506 1507 /* Make sure that interrupts are indeed enabled from here on */ 1508 mmiowb(); 1509} 1510 1511void bnx2x_int_enable(struct bnx2x *bp) 1512{ 1513 if (bp->common.int_block == INT_BLOCK_HC) 1514 bnx2x_hc_int_enable(bp); 1515 else 1516 bnx2x_igu_int_enable(bp); 1517} 1518 1519static void bnx2x_hc_int_disable(struct bnx2x *bp) 1520{ 1521 int port = BP_PORT(bp); 1522 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1523 u32 val = REG_RD(bp, addr); 1524 1525 /* 1526 * in E1 we must use only PCI configuration space to disable 1527 * MSI/MSIX capablility 1528 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1529 */ 1530 if (CHIP_IS_E1(bp)) { 1531 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1532 * Use mask register to prevent from HC sending interrupts 1533 * after we exit the function 1534 */ 1535 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1536 1537 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1538 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1539 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1540 } else 1541 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1542 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1543 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1544 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1545 1546 DP(NETIF_MSG_IFDOWN, 1547 "write %x to HC %d (addr 0x%x)\n", 1548 val, port, addr); 1549 1550 /* flush all outstanding writes */ 1551 mmiowb(); 1552 1553 REG_WR(bp, addr, val); 1554 if (REG_RD(bp, addr) != val) 1555 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1556} 1557 1558static void bnx2x_igu_int_disable(struct bnx2x *bp) 1559{ 1560 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1561 1562 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1563 IGU_PF_CONF_INT_LINE_EN | 1564 IGU_PF_CONF_ATTN_BIT_EN); 1565 1566 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); 1567 1568 /* flush all outstanding writes */ 1569 mmiowb(); 1570 1571 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1572 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1573 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1574} 1575 1576static void bnx2x_int_disable(struct bnx2x *bp) 1577{ 1578 if (bp->common.int_block == INT_BLOCK_HC) 1579 bnx2x_hc_int_disable(bp); 1580 else 1581 bnx2x_igu_int_disable(bp); 1582} 1583 1584void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1585{ 1586 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1587 int i, offset; 1588 1589 if (disable_hw) 1590 /* prevent the HW from sending interrupts */ 1591 bnx2x_int_disable(bp); 1592 1593 /* make sure all ISRs are done */ 1594 if (msix) { 1595 synchronize_irq(bp->msix_table[0].vector); 1596 offset = 1; 1597 if (CNIC_SUPPORT(bp)) 1598 offset++; 1599 for_each_eth_queue(bp, i) 1600 synchronize_irq(bp->msix_table[offset++].vector); 1601 } else 1602 synchronize_irq(bp->pdev->irq); 1603 1604 /* make sure sp_task is not running */ 1605 cancel_delayed_work(&bp->sp_task); 1606 cancel_delayed_work(&bp->period_task); 1607 flush_workqueue(bnx2x_wq); 1608} 1609 1610/* fast path */ 1611 1612/* 1613 * General service functions 1614 */ 1615 1616/* Return true if succeeded to acquire the lock */ 1617static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1618{ 1619 u32 lock_status; 1620 u32 resource_bit = (1 << resource); 1621 int func = BP_FUNC(bp); 1622 u32 hw_lock_control_reg; 1623 1624 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1625 "Trying to take a lock on resource %d\n", resource); 1626 1627 /* Validating that the resource is within range */ 1628 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1629 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1630 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1631 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1632 return false; 1633 } 1634 1635 if (func <= 5) 1636 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1637 else 1638 hw_lock_control_reg = 1639 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1640 1641 /* Try to acquire the lock */ 1642 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1643 lock_status = REG_RD(bp, hw_lock_control_reg); 1644 if (lock_status & resource_bit) 1645 return true; 1646 1647 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1648 "Failed to get a lock on resource %d\n", resource); 1649 return false; 1650} 1651 1652/** 1653 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1654 * 1655 * @bp: driver handle 1656 * 1657 * Returns the recovery leader resource id according to the engine this function 1658 * belongs to. Currently only only 2 engines is supported. 1659 */ 1660static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1661{ 1662 if (BP_PATH(bp)) 1663 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1664 else 1665 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1666} 1667 1668/** 1669 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1670 * 1671 * @bp: driver handle 1672 * 1673 * Tries to aquire a leader lock for current engine. 1674 */ 1675static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1676{ 1677 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1678} 1679 1680static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1681 1682/* schedule the sp task and mark that interrupt occurred (runs from ISR) */ 1683static int bnx2x_schedule_sp_task(struct bnx2x *bp) 1684{ 1685 /* Set the interrupt occurred bit for the sp-task to recognize it 1686 * must ack the interrupt and transition according to the IGU 1687 * state machine. 1688 */ 1689 atomic_set(&bp->interrupt_occurred, 1); 1690 1691 /* The sp_task must execute only after this bit 1692 * is set, otherwise we will get out of sync and miss all 1693 * further interrupts. Hence, the barrier. 1694 */ 1695 smp_wmb(); 1696 1697 /* schedule sp_task to workqueue */ 1698 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1699} 1700 1701void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1702{ 1703 struct bnx2x *bp = fp->bp; 1704 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1705 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1706 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1707 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 1708 1709 DP(BNX2X_MSG_SP, 1710 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1711 fp->index, cid, command, bp->state, 1712 rr_cqe->ramrod_cqe.ramrod_type); 1713 1714 /* If cid is within VF range, replace the slowpath object with the 1715 * one corresponding to this VF 1716 */ 1717 if (cid >= BNX2X_FIRST_VF_CID && 1718 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) 1719 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); 1720 1721 switch (command) { 1722 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1723 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1724 drv_cmd = BNX2X_Q_CMD_UPDATE; 1725 break; 1726 1727 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1728 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1729 drv_cmd = BNX2X_Q_CMD_SETUP; 1730 break; 1731 1732 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1733 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1734 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1735 break; 1736 1737 case (RAMROD_CMD_ID_ETH_HALT): 1738 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1739 drv_cmd = BNX2X_Q_CMD_HALT; 1740 break; 1741 1742 case (RAMROD_CMD_ID_ETH_TERMINATE): 1743 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1744 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1745 break; 1746 1747 case (RAMROD_CMD_ID_ETH_EMPTY): 1748 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1749 drv_cmd = BNX2X_Q_CMD_EMPTY; 1750 break; 1751 1752 default: 1753 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1754 command, fp->index); 1755 return; 1756 } 1757 1758 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1759 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1760 /* q_obj->complete_cmd() failure means that this was 1761 * an unexpected completion. 1762 * 1763 * In this case we don't want to increase the bp->spq_left 1764 * because apparently we haven't sent this command the first 1765 * place. 1766 */ 1767#ifdef BNX2X_STOP_ON_ERROR 1768 bnx2x_panic(); 1769#else 1770 return; 1771#endif 1772 /* SRIOV: reschedule any 'in_progress' operations */ 1773 bnx2x_iov_sp_event(bp, cid, true); 1774 1775 smp_mb__before_atomic_inc(); 1776 atomic_inc(&bp->cq_spq_left); 1777 /* push the change in bp->spq_left and towards the memory */ 1778 smp_mb__after_atomic_inc(); 1779 1780 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1781 1782 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && 1783 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { 1784 /* if Q update ramrod is completed for last Q in AFEX vif set 1785 * flow, then ACK MCP at the end 1786 * 1787 * mark pending ACK to MCP bit. 1788 * prevent case that both bits are cleared. 1789 * At the end of load/unload driver checks that 1790 * sp_state is cleaerd, and this order prevents 1791 * races 1792 */ 1793 smp_mb__before_clear_bit(); 1794 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); 1795 wmb(); 1796 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 1797 smp_mb__after_clear_bit(); 1798 1799 /* schedule the sp task as mcp ack is required */ 1800 bnx2x_schedule_sp_task(bp); 1801 } 1802 1803 return; 1804} 1805 1806irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1807{ 1808 struct bnx2x *bp = netdev_priv(dev_instance); 1809 u16 status = bnx2x_ack_int(bp); 1810 u16 mask; 1811 int i; 1812 u8 cos; 1813 1814 /* Return here if interrupt is shared and it's not for us */ 1815 if (unlikely(status == 0)) { 1816 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1817 return IRQ_NONE; 1818 } 1819 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1820 1821#ifdef BNX2X_STOP_ON_ERROR 1822 if (unlikely(bp->panic)) 1823 return IRQ_HANDLED; 1824#endif 1825 1826 for_each_eth_queue(bp, i) { 1827 struct bnx2x_fastpath *fp = &bp->fp[i]; 1828 1829 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); 1830 if (status & mask) { 1831 /* Handle Rx or Tx according to SB id */ 1832 prefetch(fp->rx_cons_sb); 1833 for_each_cos_in_tx_queue(fp, cos) 1834 prefetch(fp->txdata_ptr[cos]->tx_cons_sb); 1835 prefetch(&fp->sb_running_index[SM_RX_ID]); 1836 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1837 status &= ~mask; 1838 } 1839 } 1840 1841 if (CNIC_SUPPORT(bp)) { 1842 mask = 0x2; 1843 if (status & (mask | 0x1)) { 1844 struct cnic_ops *c_ops = NULL; 1845 1846 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1847 rcu_read_lock(); 1848 c_ops = rcu_dereference(bp->cnic_ops); 1849 if (c_ops) 1850 c_ops->cnic_handler(bp->cnic_data, 1851 NULL); 1852 rcu_read_unlock(); 1853 } 1854 1855 status &= ~mask; 1856 } 1857 } 1858 1859 if (unlikely(status & 0x1)) { 1860 1861 /* schedule sp task to perform default status block work, ack 1862 * attentions and enable interrupts. 1863 */ 1864 bnx2x_schedule_sp_task(bp); 1865 1866 status &= ~0x1; 1867 if (!status) 1868 return IRQ_HANDLED; 1869 } 1870 1871 if (unlikely(status)) 1872 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1873 status); 1874 1875 return IRQ_HANDLED; 1876} 1877 1878/* Link */ 1879 1880/* 1881 * General service functions 1882 */ 1883 1884int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1885{ 1886 u32 lock_status; 1887 u32 resource_bit = (1 << resource); 1888 int func = BP_FUNC(bp); 1889 u32 hw_lock_control_reg; 1890 int cnt; 1891 1892 /* Validating that the resource is within range */ 1893 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1894 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1895 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1896 return -EINVAL; 1897 } 1898 1899 if (func <= 5) { 1900 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1901 } else { 1902 hw_lock_control_reg = 1903 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1904 } 1905 1906 /* Validating that the resource is not already taken */ 1907 lock_status = REG_RD(bp, hw_lock_control_reg); 1908 if (lock_status & resource_bit) { 1909 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", 1910 lock_status, resource_bit); 1911 return -EEXIST; 1912 } 1913 1914 /* Try for 5 second every 5ms */ 1915 for (cnt = 0; cnt < 1000; cnt++) { 1916 /* Try to acquire the lock */ 1917 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1918 lock_status = REG_RD(bp, hw_lock_control_reg); 1919 if (lock_status & resource_bit) 1920 return 0; 1921 1922 msleep(5); 1923 } 1924 BNX2X_ERR("Timeout\n"); 1925 return -EAGAIN; 1926} 1927 1928int bnx2x_release_leader_lock(struct bnx2x *bp) 1929{ 1930 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1931} 1932 1933int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1934{ 1935 u32 lock_status; 1936 u32 resource_bit = (1 << resource); 1937 int func = BP_FUNC(bp); 1938 u32 hw_lock_control_reg; 1939 1940 /* Validating that the resource is within range */ 1941 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1942 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1943 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1944 return -EINVAL; 1945 } 1946 1947 if (func <= 5) { 1948 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1949 } else { 1950 hw_lock_control_reg = 1951 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1952 } 1953 1954 /* Validating that the resource is currently taken */ 1955 lock_status = REG_RD(bp, hw_lock_control_reg); 1956 if (!(lock_status & resource_bit)) { 1957 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", 1958 lock_status, resource_bit); 1959 return -EFAULT; 1960 } 1961 1962 REG_WR(bp, hw_lock_control_reg, resource_bit); 1963 return 0; 1964} 1965 1966 1967int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1968{ 1969 /* The GPIO should be swapped if swap register is set and active */ 1970 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1971 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1972 int gpio_shift = gpio_num + 1973 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1974 u32 gpio_mask = (1 << gpio_shift); 1975 u32 gpio_reg; 1976 int value; 1977 1978 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1979 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1980 return -EINVAL; 1981 } 1982 1983 /* read GPIO value */ 1984 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1985 1986 /* get the requested pin value */ 1987 if ((gpio_reg & gpio_mask) == gpio_mask) 1988 value = 1; 1989 else 1990 value = 0; 1991 1992 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1993 1994 return value; 1995} 1996 1997int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1998{ 1999 /* The GPIO should be swapped if swap register is set and active */ 2000 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2001 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2002 int gpio_shift = gpio_num + 2003 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2004 u32 gpio_mask = (1 << gpio_shift); 2005 u32 gpio_reg; 2006 2007 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2008 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2009 return -EINVAL; 2010 } 2011 2012 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2013 /* read GPIO and mask except the float bits */ 2014 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 2015 2016 switch (mode) { 2017 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2018 DP(NETIF_MSG_LINK, 2019 "Set GPIO %d (shift %d) -> output low\n", 2020 gpio_num, gpio_shift); 2021 /* clear FLOAT and set CLR */ 2022 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2023 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 2024 break; 2025 2026 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2027 DP(NETIF_MSG_LINK, 2028 "Set GPIO %d (shift %d) -> output high\n", 2029 gpio_num, gpio_shift); 2030 /* clear FLOAT and set SET */ 2031 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2032 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 2033 break; 2034 2035 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2036 DP(NETIF_MSG_LINK, 2037 "Set GPIO %d (shift %d) -> input\n", 2038 gpio_num, gpio_shift); 2039 /* set FLOAT */ 2040 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2041 break; 2042 2043 default: 2044 break; 2045 } 2046 2047 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2048 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2049 2050 return 0; 2051} 2052 2053int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 2054{ 2055 u32 gpio_reg = 0; 2056 int rc = 0; 2057 2058 /* Any port swapping should be handled by caller. */ 2059 2060 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2061 /* read GPIO and mask except the float bits */ 2062 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2063 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2064 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2065 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2066 2067 switch (mode) { 2068 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2069 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2070 /* set CLR */ 2071 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2072 break; 2073 2074 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2075 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2076 /* set SET */ 2077 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2078 break; 2079 2080 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2081 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2082 /* set FLOAT */ 2083 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2084 break; 2085 2086 default: 2087 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2088 rc = -EINVAL; 2089 break; 2090 } 2091 2092 if (rc == 0) 2093 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2094 2095 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2096 2097 return rc; 2098} 2099 2100int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2101{ 2102 /* The GPIO should be swapped if swap register is set and active */ 2103 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2104 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2105 int gpio_shift = gpio_num + 2106 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2107 u32 gpio_mask = (1 << gpio_shift); 2108 u32 gpio_reg; 2109 2110 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2111 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2112 return -EINVAL; 2113 } 2114 2115 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2116 /* read GPIO int */ 2117 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2118 2119 switch (mode) { 2120 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2121 DP(NETIF_MSG_LINK, 2122 "Clear GPIO INT %d (shift %d) -> output low\n", 2123 gpio_num, gpio_shift); 2124 /* clear SET and set CLR */ 2125 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2126 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2127 break; 2128 2129 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2130 DP(NETIF_MSG_LINK, 2131 "Set GPIO INT %d (shift %d) -> output high\n", 2132 gpio_num, gpio_shift); 2133 /* clear CLR and set SET */ 2134 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2135 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2136 break; 2137 2138 default: 2139 break; 2140 } 2141 2142 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2143 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2144 2145 return 0; 2146} 2147 2148static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) 2149{ 2150 u32 spio_reg; 2151 2152 /* Only 2 SPIOs are configurable */ 2153 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 2154 BNX2X_ERR("Invalid SPIO 0x%x\n", spio); 2155 return -EINVAL; 2156 } 2157 2158 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2159 /* read SPIO and mask except the float bits */ 2160 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 2161 2162 switch (mode) { 2163 case MISC_SPIO_OUTPUT_LOW: 2164 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); 2165 /* clear FLOAT and set CLR */ 2166 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2167 spio_reg |= (spio << MISC_SPIO_CLR_POS); 2168 break; 2169 2170 case MISC_SPIO_OUTPUT_HIGH: 2171 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); 2172 /* clear FLOAT and set SET */ 2173 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2174 spio_reg |= (spio << MISC_SPIO_SET_POS); 2175 break; 2176 2177 case MISC_SPIO_INPUT_HI_Z: 2178 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); 2179 /* set FLOAT */ 2180 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 2181 break; 2182 2183 default: 2184 break; 2185 } 2186 2187 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2188 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2189 2190 return 0; 2191} 2192 2193void bnx2x_calc_fc_adv(struct bnx2x *bp) 2194{ 2195 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2196 switch (bp->link_vars.ieee_fc & 2197 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2198 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2199 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2200 ADVERTISED_Pause); 2201 break; 2202 2203 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2204 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2205 ADVERTISED_Pause); 2206 break; 2207 2208 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2209 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2210 break; 2211 2212 default: 2213 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2214 ADVERTISED_Pause); 2215 break; 2216 } 2217} 2218 2219static void bnx2x_set_requested_fc(struct bnx2x *bp) 2220{ 2221 /* Initialize link parameters structure variables 2222 * It is recommended to turn off RX FC for jumbo frames 2223 * for better performance 2224 */ 2225 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2226 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2227 else 2228 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2229} 2230 2231int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2232{ 2233 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); 2234 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2235 2236 if (!BP_NOMCP(bp)) { 2237 bnx2x_set_requested_fc(bp); 2238 bnx2x_acquire_phy_lock(bp); 2239 2240 if (load_mode == LOAD_DIAG) { 2241 struct link_params *lp = &bp->link_params; 2242 lp->loopback_mode = LOOPBACK_XGXS; 2243 /* do PHY loopback at 10G speed, if possible */ 2244 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2245 if (lp->speed_cap_mask[cfx_idx] & 2246 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2247 lp->req_line_speed[cfx_idx] = 2248 SPEED_10000; 2249 else 2250 lp->req_line_speed[cfx_idx] = 2251 SPEED_1000; 2252 } 2253 } 2254 2255 if (load_mode == LOAD_LOOPBACK_EXT) { 2256 struct link_params *lp = &bp->link_params; 2257 lp->loopback_mode = LOOPBACK_EXT; 2258 } 2259 2260 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2261 2262 bnx2x_release_phy_lock(bp); 2263 2264 bnx2x_calc_fc_adv(bp); 2265 2266 if (bp->link_vars.link_up) { 2267 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2268 bnx2x_link_report(bp); 2269 } 2270 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2271 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2272 return rc; 2273 } 2274 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2275 return -EINVAL; 2276} 2277 2278void bnx2x_link_set(struct bnx2x *bp) 2279{ 2280 if (!BP_NOMCP(bp)) { 2281 bnx2x_acquire_phy_lock(bp); 2282 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2283 bnx2x_release_phy_lock(bp); 2284 2285 bnx2x_calc_fc_adv(bp); 2286 } else 2287 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2288} 2289 2290static void bnx2x__link_reset(struct bnx2x *bp) 2291{ 2292 if (!BP_NOMCP(bp)) { 2293 bnx2x_acquire_phy_lock(bp); 2294 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); 2295 bnx2x_release_phy_lock(bp); 2296 } else 2297 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2298} 2299 2300void bnx2x_force_link_reset(struct bnx2x *bp) 2301{ 2302 bnx2x_acquire_phy_lock(bp); 2303 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2304 bnx2x_release_phy_lock(bp); 2305} 2306 2307u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2308{ 2309 u8 rc = 0; 2310 2311 if (!BP_NOMCP(bp)) { 2312 bnx2x_acquire_phy_lock(bp); 2313 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2314 is_serdes); 2315 bnx2x_release_phy_lock(bp); 2316 } else 2317 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2318 2319 return rc; 2320} 2321 2322 2323/* Calculates the sum of vn_min_rates. 2324 It's needed for further normalizing of the min_rates. 2325 Returns: 2326 sum of vn_min_rates. 2327 or 2328 0 - if all the min_rates are 0. 2329 In the later case fainess algorithm should be deactivated. 2330 If not all min_rates are zero then those that are zeroes will be set to 1. 2331 */ 2332static void bnx2x_calc_vn_min(struct bnx2x *bp, 2333 struct cmng_init_input *input) 2334{ 2335 int all_zero = 1; 2336 int vn; 2337 2338 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2339 u32 vn_cfg = bp->mf_config[vn]; 2340 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2341 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2342 2343 /* Skip hidden vns */ 2344 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2345 vn_min_rate = 0; 2346 /* If min rate is zero - set it to 1 */ 2347 else if (!vn_min_rate) 2348 vn_min_rate = DEF_MIN_RATE; 2349 else 2350 all_zero = 0; 2351 2352 input->vnic_min_rate[vn] = vn_min_rate; 2353 } 2354 2355 /* if ETS or all min rates are zeros - disable fairness */ 2356 if (BNX2X_IS_ETS_ENABLED(bp)) { 2357 input->flags.cmng_enables &= 2358 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2359 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2360 } else if (all_zero) { 2361 input->flags.cmng_enables &= 2362 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2363 DP(NETIF_MSG_IFUP, 2364 "All MIN values are zeroes fairness will be disabled\n"); 2365 } else 2366 input->flags.cmng_enables |= 2367 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2368} 2369 2370static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, 2371 struct cmng_init_input *input) 2372{ 2373 u16 vn_max_rate; 2374 u32 vn_cfg = bp->mf_config[vn]; 2375 2376 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2377 vn_max_rate = 0; 2378 else { 2379 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2380 2381 if (IS_MF_SI(bp)) { 2382 /* maxCfg in percents of linkspeed */ 2383 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2384 } else /* SD modes */ 2385 /* maxCfg is absolute in 100Mb units */ 2386 vn_max_rate = maxCfg * 100; 2387 } 2388 2389 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 2390 2391 input->vnic_max_rate[vn] = vn_max_rate; 2392} 2393 2394 2395static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2396{ 2397 if (CHIP_REV_IS_SLOW(bp)) 2398 return CMNG_FNS_NONE; 2399 if (IS_MF(bp)) 2400 return CMNG_FNS_MINMAX; 2401 2402 return CMNG_FNS_NONE; 2403} 2404 2405void bnx2x_read_mf_cfg(struct bnx2x *bp) 2406{ 2407 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2408 2409 if (BP_NOMCP(bp)) 2410 return; /* what should be the default bvalue in this case */ 2411 2412 /* For 2 port configuration the absolute function number formula 2413 * is: 2414 * abs_func = 2 * vn + BP_PORT + BP_PATH 2415 * 2416 * and there are 4 functions per port 2417 * 2418 * For 4 port configuration it is 2419 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2420 * 2421 * and there are 2 functions per port 2422 */ 2423 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2424 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2425 2426 if (func >= E1H_FUNC_MAX) 2427 break; 2428 2429 bp->mf_config[vn] = 2430 MF_CFG_RD(bp, func_mf_config[func].config); 2431 } 2432 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2433 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); 2434 bp->flags |= MF_FUNC_DIS; 2435 } else { 2436 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2437 bp->flags &= ~MF_FUNC_DIS; 2438 } 2439} 2440 2441static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2442{ 2443 struct cmng_init_input input; 2444 memset(&input, 0, sizeof(struct cmng_init_input)); 2445 2446 input.port_rate = bp->link_vars.line_speed; 2447 2448 if (cmng_type == CMNG_FNS_MINMAX) { 2449 int vn; 2450 2451 /* read mf conf from shmem */ 2452 if (read_cfg) 2453 bnx2x_read_mf_cfg(bp); 2454 2455 /* vn_weight_sum and enable fairness if not 0 */ 2456 bnx2x_calc_vn_min(bp, &input); 2457 2458 /* calculate and set min-max rate for each vn */ 2459 if (bp->port.pmf) 2460 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2461 bnx2x_calc_vn_max(bp, vn, &input); 2462 2463 /* always enable rate shaping and fairness */ 2464 input.flags.cmng_enables |= 2465 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2466 2467 bnx2x_init_cmng(&input, &bp->cmng); 2468 return; 2469 } 2470 2471 /* rate shaping and fairness are disabled */ 2472 DP(NETIF_MSG_IFUP, 2473 "rate shaping and fairness are disabled\n"); 2474} 2475 2476static void storm_memset_cmng(struct bnx2x *bp, 2477 struct cmng_init *cmng, 2478 u8 port) 2479{ 2480 int vn; 2481 size_t size = sizeof(struct cmng_struct_per_port); 2482 2483 u32 addr = BAR_XSTRORM_INTMEM + 2484 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); 2485 2486 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); 2487 2488 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2489 int func = func_by_vn(bp, vn); 2490 2491 addr = BAR_XSTRORM_INTMEM + 2492 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); 2493 size = sizeof(struct rate_shaping_vars_per_vn); 2494 __storm_memset_struct(bp, addr, size, 2495 (u32 *)&cmng->vnic.vnic_max_rate[vn]); 2496 2497 addr = BAR_XSTRORM_INTMEM + 2498 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); 2499 size = sizeof(struct fairness_vars_per_vn); 2500 __storm_memset_struct(bp, addr, size, 2501 (u32 *)&cmng->vnic.vnic_min_rate[vn]); 2502 } 2503} 2504 2505/* This function is called upon link interrupt */ 2506static void bnx2x_link_attn(struct bnx2x *bp) 2507{ 2508 /* Make sure that we are synced with the current statistics */ 2509 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2510 2511 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2512 2513 if (bp->link_vars.link_up) { 2514 2515 /* dropless flow control */ 2516 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2517 int port = BP_PORT(bp); 2518 u32 pause_enabled = 0; 2519 2520 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2521 pause_enabled = 1; 2522 2523 REG_WR(bp, BAR_USTRORM_INTMEM + 2524 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2525 pause_enabled); 2526 } 2527 2528 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2529 struct host_port_stats *pstats; 2530 2531 pstats = bnx2x_sp(bp, port_stats); 2532 /* reset old mac stats */ 2533 memset(&(pstats->mac_stx[0]), 0, 2534 sizeof(struct mac_stx)); 2535 } 2536 if (bp->state == BNX2X_STATE_OPEN) 2537 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2538 } 2539 2540 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2541 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2542 2543 if (cmng_fns != CMNG_FNS_NONE) { 2544 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2545 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2546 } else 2547 /* rate shaping and fairness are disabled */ 2548 DP(NETIF_MSG_IFUP, 2549 "single function mode without fairness\n"); 2550 } 2551 2552 __bnx2x_link_report(bp); 2553 2554 if (IS_MF(bp)) 2555 bnx2x_link_sync_notify(bp); 2556} 2557 2558void bnx2x__link_status_update(struct bnx2x *bp) 2559{ 2560 if (bp->state != BNX2X_STATE_OPEN) 2561 return; 2562 2563 /* read updated dcb configuration */ 2564 if (IS_PF(bp)) { 2565 bnx2x_dcbx_pmf_update(bp); 2566 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2567 if (bp->link_vars.link_up) 2568 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2569 else 2570 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2571 /* indicate link status */ 2572 bnx2x_link_report(bp); 2573 2574 } else { /* VF */ 2575 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | 2576 SUPPORTED_10baseT_Full | 2577 SUPPORTED_100baseT_Half | 2578 SUPPORTED_100baseT_Full | 2579 SUPPORTED_1000baseT_Full | 2580 SUPPORTED_2500baseX_Full | 2581 SUPPORTED_10000baseT_Full | 2582 SUPPORTED_TP | 2583 SUPPORTED_FIBRE | 2584 SUPPORTED_Autoneg | 2585 SUPPORTED_Pause | 2586 SUPPORTED_Asym_Pause); 2587 bp->port.advertising[0] = bp->port.supported[0]; 2588 2589 bp->link_params.bp = bp; 2590 bp->link_params.port = BP_PORT(bp); 2591 bp->link_params.req_duplex[0] = DUPLEX_FULL; 2592 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; 2593 bp->link_params.req_line_speed[0] = SPEED_10000; 2594 bp->link_params.speed_cap_mask[0] = 0x7f0000; 2595 bp->link_params.switch_cfg = SWITCH_CFG_10G; 2596 bp->link_vars.mac_type = MAC_TYPE_BMAC; 2597 bp->link_vars.line_speed = SPEED_10000; 2598 bp->link_vars.link_status = 2599 (LINK_STATUS_LINK_UP | 2600 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 2601 bp->link_vars.link_up = 1; 2602 bp->link_vars.duplex = DUPLEX_FULL; 2603 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; 2604 __bnx2x_link_report(bp); 2605 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2606 } 2607} 2608 2609static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, 2610 u16 vlan_val, u8 allowed_prio) 2611{ 2612 struct bnx2x_func_state_params func_params = {0}; 2613 struct bnx2x_func_afex_update_params *f_update_params = 2614 &func_params.params.afex_update; 2615 2616 func_params.f_obj = &bp->func_obj; 2617 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; 2618 2619 /* no need to wait for RAMROD completion, so don't 2620 * set RAMROD_COMP_WAIT flag 2621 */ 2622 2623 f_update_params->vif_id = vifid; 2624 f_update_params->afex_default_vlan = vlan_val; 2625 f_update_params->allowed_priorities = allowed_prio; 2626 2627 /* if ramrod can not be sent, response to MCP immediately */ 2628 if (bnx2x_func_state_change(bp, &func_params) < 0) 2629 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 2630 2631 return 0; 2632} 2633 2634static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, 2635 u16 vif_index, u8 func_bit_map) 2636{ 2637 struct bnx2x_func_state_params func_params = {0}; 2638 struct bnx2x_func_afex_viflists_params *update_params = 2639 &func_params.params.afex_viflists; 2640 int rc; 2641 u32 drv_msg_code; 2642 2643 /* validate only LIST_SET and LIST_GET are received from switch */ 2644 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) 2645 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", 2646 cmd_type); 2647 2648 func_params.f_obj = &bp->func_obj; 2649 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; 2650 2651 /* set parameters according to cmd_type */ 2652 update_params->afex_vif_list_command = cmd_type; 2653 update_params->vif_list_index = cpu_to_le16(vif_index); 2654 update_params->func_bit_map = 2655 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; 2656 update_params->func_to_clear = 0; 2657 drv_msg_code = 2658 (cmd_type == VIF_LIST_RULE_GET) ? 2659 DRV_MSG_CODE_AFEX_LISTGET_ACK : 2660 DRV_MSG_CODE_AFEX_LISTSET_ACK; 2661 2662 /* if ramrod can not be sent, respond to MCP immediately for 2663 * SET and GET requests (other are not triggered from MCP) 2664 */ 2665 rc = bnx2x_func_state_change(bp, &func_params); 2666 if (rc < 0) 2667 bnx2x_fw_command(bp, drv_msg_code, 0); 2668 2669 return 0; 2670} 2671 2672static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) 2673{ 2674 struct afex_stats afex_stats; 2675 u32 func = BP_ABS_FUNC(bp); 2676 u32 mf_config; 2677 u16 vlan_val; 2678 u32 vlan_prio; 2679 u16 vif_id; 2680 u8 allowed_prio; 2681 u8 vlan_mode; 2682 u32 addr_to_write, vifid, addrs, stats_type, i; 2683 2684 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { 2685 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2686 DP(BNX2X_MSG_MCP, 2687 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); 2688 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); 2689 } 2690 2691 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { 2692 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2693 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); 2694 DP(BNX2X_MSG_MCP, 2695 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", 2696 vifid, addrs); 2697 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, 2698 addrs); 2699 } 2700 2701 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { 2702 addr_to_write = SHMEM2_RD(bp, 2703 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); 2704 stats_type = SHMEM2_RD(bp, 2705 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2706 2707 DP(BNX2X_MSG_MCP, 2708 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", 2709 addr_to_write); 2710 2711 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); 2712 2713 /* write response to scratchpad, for MCP */ 2714 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) 2715 REG_WR(bp, addr_to_write + i*sizeof(u32), 2716 *(((u32 *)(&afex_stats))+i)); 2717 2718 /* send ack message to MCP */ 2719 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); 2720 } 2721 2722 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { 2723 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); 2724 bp->mf_config[BP_VN(bp)] = mf_config; 2725 DP(BNX2X_MSG_MCP, 2726 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", 2727 mf_config); 2728 2729 /* if VIF_SET is "enabled" */ 2730 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { 2731 /* set rate limit directly to internal RAM */ 2732 struct cmng_init_input cmng_input; 2733 struct rate_shaping_vars_per_vn m_rs_vn; 2734 size_t size = sizeof(struct rate_shaping_vars_per_vn); 2735 u32 addr = BAR_XSTRORM_INTMEM + 2736 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); 2737 2738 bp->mf_config[BP_VN(bp)] = mf_config; 2739 2740 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); 2741 m_rs_vn.vn_counter.rate = 2742 cmng_input.vnic_max_rate[BP_VN(bp)]; 2743 m_rs_vn.vn_counter.quota = 2744 (m_rs_vn.vn_counter.rate * 2745 RS_PERIODIC_TIMEOUT_USEC) / 8; 2746 2747 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); 2748 2749 /* read relevant values from mf_cfg struct in shmem */ 2750 vif_id = 2751 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2752 FUNC_MF_CFG_E1HOV_TAG_MASK) >> 2753 FUNC_MF_CFG_E1HOV_TAG_SHIFT; 2754 vlan_val = 2755 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2756 FUNC_MF_CFG_AFEX_VLAN_MASK) >> 2757 FUNC_MF_CFG_AFEX_VLAN_SHIFT; 2758 vlan_prio = (mf_config & 2759 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 2760 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; 2761 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); 2762 vlan_mode = 2763 (MF_CFG_RD(bp, 2764 func_mf_config[func].afex_config) & 2765 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 2766 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; 2767 allowed_prio = 2768 (MF_CFG_RD(bp, 2769 func_mf_config[func].afex_config) & 2770 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 2771 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; 2772 2773 /* send ramrod to FW, return in case of failure */ 2774 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, 2775 allowed_prio)) 2776 return; 2777 2778 bp->afex_def_vlan_tag = vlan_val; 2779 bp->afex_vlan_mode = vlan_mode; 2780 } else { 2781 /* notify link down because BP->flags is disabled */ 2782 bnx2x_link_report(bp); 2783 2784 /* send INVALID VIF ramrod to FW */ 2785 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); 2786 2787 /* Reset the default afex VLAN */ 2788 bp->afex_def_vlan_tag = -1; 2789 } 2790 } 2791} 2792 2793static void bnx2x_pmf_update(struct bnx2x *bp) 2794{ 2795 int port = BP_PORT(bp); 2796 u32 val; 2797 2798 bp->port.pmf = 1; 2799 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); 2800 2801 /* 2802 * We need the mb() to ensure the ordering between the writing to 2803 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2804 */ 2805 smp_mb(); 2806 2807 /* queue a periodic task */ 2808 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2809 2810 bnx2x_dcbx_pmf_update(bp); 2811 2812 /* enable nig attention */ 2813 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2814 if (bp->common.int_block == INT_BLOCK_HC) { 2815 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2816 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2817 } else if (!CHIP_IS_E1x(bp)) { 2818 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2819 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2820 } 2821 2822 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2823} 2824 2825/* end of Link */ 2826 2827/* slow path */ 2828 2829/* 2830 * General service functions 2831 */ 2832 2833/* send the MCP a request, block until there is a reply */ 2834u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2835{ 2836 int mb_idx = BP_FW_MB_IDX(bp); 2837 u32 seq; 2838 u32 rc = 0; 2839 u32 cnt = 1; 2840 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2841 2842 mutex_lock(&bp->fw_mb_mutex); 2843 seq = ++bp->fw_seq; 2844 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2845 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2846 2847 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2848 (command | seq), param); 2849 2850 do { 2851 /* let the FW do it's magic ... */ 2852 msleep(delay); 2853 2854 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2855 2856 /* Give the FW up to 5 second (500*10ms) */ 2857 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2858 2859 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2860 cnt*delay, rc, seq); 2861 2862 /* is this a reply to our command? */ 2863 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2864 rc &= FW_MSG_CODE_MASK; 2865 else { 2866 /* FW BUG! */ 2867 BNX2X_ERR("FW failed to respond!\n"); 2868 bnx2x_fw_dump(bp); 2869 rc = 0; 2870 } 2871 mutex_unlock(&bp->fw_mb_mutex); 2872 2873 return rc; 2874} 2875 2876 2877static void storm_memset_func_cfg(struct bnx2x *bp, 2878 struct tstorm_eth_function_common_config *tcfg, 2879 u16 abs_fid) 2880{ 2881 size_t size = sizeof(struct tstorm_eth_function_common_config); 2882 2883 u32 addr = BAR_TSTRORM_INTMEM + 2884 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); 2885 2886 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); 2887} 2888 2889void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2890{ 2891 if (CHIP_IS_E1x(bp)) { 2892 struct tstorm_eth_function_common_config tcfg = {0}; 2893 2894 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2895 } 2896 2897 /* Enable the function in the FW */ 2898 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2899 storm_memset_func_en(bp, p->func_id, 1); 2900 2901 /* spq */ 2902 if (p->func_flgs & FUNC_FLG_SPQ) { 2903 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2904 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2905 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2906 } 2907} 2908 2909/** 2910 * bnx2x_get_tx_only_flags - Return common flags 2911 * 2912 * @bp device handle 2913 * @fp queue handle 2914 * @zero_stats TRUE if statistics zeroing is needed 2915 * 2916 * Return the flags that are common for the Tx-only and not normal connections. 2917 */ 2918static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2919 struct bnx2x_fastpath *fp, 2920 bool zero_stats) 2921{ 2922 unsigned long flags = 0; 2923 2924 /* PF driver will always initialize the Queue to an ACTIVE state */ 2925 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2926 2927 /* tx only connections collect statistics (on the same index as the 2928 * parent connection). The statistics are zeroed when the parent 2929 * connection is initialized. 2930 */ 2931 2932 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2933 if (zero_stats) 2934 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2935 2936 2937 return flags; 2938} 2939 2940static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2941 struct bnx2x_fastpath *fp, 2942 bool leading) 2943{ 2944 unsigned long flags = 0; 2945 2946 /* calculate other queue flags */ 2947 if (IS_MF_SD(bp)) 2948 __set_bit(BNX2X_Q_FLG_OV, &flags); 2949 2950 if (IS_FCOE_FP(fp)) { 2951 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2952 /* For FCoE - force usage of default priority (for afex) */ 2953 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); 2954 } 2955 2956 if (!fp->disable_tpa) { 2957 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2958 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2959 if (fp->mode == TPA_MODE_GRO) 2960 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 2961 } 2962 2963 if (leading) { 2964 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2965 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2966 } 2967 2968 /* Always set HW VLAN stripping */ 2969 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2970 2971 /* configure silent vlan removal */ 2972 if (IS_MF_AFEX(bp)) 2973 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); 2974 2975 2976 return flags | bnx2x_get_common_flags(bp, fp, true); 2977} 2978 2979static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2980 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2981 u8 cos) 2982{ 2983 gen_init->stat_id = bnx2x_stats_id(fp); 2984 gen_init->spcl_id = fp->cl_id; 2985 2986 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2987 if (IS_FCOE_FP(fp)) 2988 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2989 else 2990 gen_init->mtu = bp->dev->mtu; 2991 2992 gen_init->cos = cos; 2993} 2994 2995static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2996 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2997 struct bnx2x_rxq_setup_params *rxq_init) 2998{ 2999 u8 max_sge = 0; 3000 u16 sge_sz = 0; 3001 u16 tpa_agg_size = 0; 3002 3003 if (!fp->disable_tpa) { 3004 pause->sge_th_lo = SGE_TH_LO(bp); 3005 pause->sge_th_hi = SGE_TH_HI(bp); 3006 3007 /* validate SGE ring has enough to cross high threshold */ 3008 WARN_ON(bp->dropless_fc && 3009 pause->sge_th_hi + FW_PREFETCH_CNT > 3010 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 3011 3012 tpa_agg_size = min_t(u32, 3013 (min_t(u32, 8, MAX_SKB_FRAGS) * 3014 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 3015 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 3016 SGE_PAGE_SHIFT; 3017 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 3018 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 3019 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 3020 0xffff); 3021 } 3022 3023 /* pause - not for e1 */ 3024 if (!CHIP_IS_E1(bp)) { 3025 pause->bd_th_lo = BD_TH_LO(bp); 3026 pause->bd_th_hi = BD_TH_HI(bp); 3027 3028 pause->rcq_th_lo = RCQ_TH_LO(bp); 3029 pause->rcq_th_hi = RCQ_TH_HI(bp); 3030 /* 3031 * validate that rings have enough entries to cross 3032 * high thresholds 3033 */ 3034 WARN_ON(bp->dropless_fc && 3035 pause->bd_th_hi + FW_PREFETCH_CNT > 3036 bp->rx_ring_size); 3037 WARN_ON(bp->dropless_fc && 3038 pause->rcq_th_hi + FW_PREFETCH_CNT > 3039 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 3040 3041 pause->pri_map = 1; 3042 } 3043 3044 /* rxq setup */ 3045 rxq_init->dscr_map = fp->rx_desc_mapping; 3046 rxq_init->sge_map = fp->rx_sge_mapping; 3047 rxq_init->rcq_map = fp->rx_comp_mapping; 3048 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 3049 3050 /* This should be a maximum number of data bytes that may be 3051 * placed on the BD (not including paddings). 3052 */ 3053 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 3054 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 3055 3056 rxq_init->cl_qzone_id = fp->cl_qzone_id; 3057 rxq_init->tpa_agg_sz = tpa_agg_size; 3058 rxq_init->sge_buf_sz = sge_sz; 3059 rxq_init->max_sges_pkt = max_sge; 3060 rxq_init->rss_engine_id = BP_FUNC(bp); 3061 rxq_init->mcast_engine_id = BP_FUNC(bp); 3062 3063 /* Maximum number or simultaneous TPA aggregation for this Queue. 3064 * 3065 * For PF Clients it should be the maximum avaliable number. 3066 * VF driver(s) may want to define it to a smaller value. 3067 */ 3068 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 3069 3070 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 3071 rxq_init->fw_sb_id = fp->fw_sb_id; 3072 3073 if (IS_FCOE_FP(fp)) 3074 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 3075 else 3076 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 3077 /* configure silent vlan removal 3078 * if multi function mode is afex, then mask default vlan 3079 */ 3080 if (IS_MF_AFEX(bp)) { 3081 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; 3082 rxq_init->silent_removal_mask = VLAN_VID_MASK; 3083 } 3084} 3085 3086static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 3087 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 3088 u8 cos) 3089{ 3090 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; 3091 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 3092 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 3093 txq_init->fw_sb_id = fp->fw_sb_id; 3094 3095 /* 3096 * set the tss leading client id for TX classfication == 3097 * leading RSS client id 3098 */ 3099 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 3100 3101 if (IS_FCOE_FP(fp)) { 3102 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 3103 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 3104 } 3105} 3106 3107static void bnx2x_pf_init(struct bnx2x *bp) 3108{ 3109 struct bnx2x_func_init_params func_init = {0}; 3110 struct event_ring_data eq_data = { {0} }; 3111 u16 flags; 3112 3113 if (!CHIP_IS_E1x(bp)) { 3114 /* reset IGU PF statistics: MSIX + ATTN */ 3115 /* PF */ 3116 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3117 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3118 (CHIP_MODE_IS_4_PORT(bp) ? 3119 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3120 /* ATTN */ 3121 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3122 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3123 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 3124 (CHIP_MODE_IS_4_PORT(bp) ? 3125 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3126 } 3127 3128 /* function setup flags */ 3129 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 3130 3131 /* This flag is relevant for E1x only. 3132 * E2 doesn't have a TPA configuration in a function level. 3133 */ 3134 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 3135 3136 func_init.func_flgs = flags; 3137 func_init.pf_id = BP_FUNC(bp); 3138 func_init.func_id = BP_FUNC(bp); 3139 func_init.spq_map = bp->spq_mapping; 3140 func_init.spq_prod = bp->spq_prod_idx; 3141 3142 bnx2x_func_init(bp, &func_init); 3143 3144 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 3145 3146 /* 3147 * Congestion management values depend on the link rate 3148 * There is no active link so initial link rate is set to 10 Gbps. 3149 * When the link comes up The congestion management values are 3150 * re-calculated according to the actual link rate. 3151 */ 3152 bp->link_vars.line_speed = SPEED_10000; 3153 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 3154 3155 /* Only the PMF sets the HW */ 3156 if (bp->port.pmf) 3157 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3158 3159 /* init Event Queue */ 3160 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 3161 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 3162 eq_data.producer = bp->eq_prod; 3163 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 3164 eq_data.sb_id = DEF_SB_ID; 3165 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 3166} 3167 3168 3169static void bnx2x_e1h_disable(struct bnx2x *bp) 3170{ 3171 int port = BP_PORT(bp); 3172 3173 bnx2x_tx_disable(bp); 3174 3175 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 3176} 3177 3178static void bnx2x_e1h_enable(struct bnx2x *bp) 3179{ 3180 int port = BP_PORT(bp); 3181 3182 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 3183 3184 /* Tx queue should be only reenabled */ 3185 netif_tx_wake_all_queues(bp->dev); 3186 3187 /* 3188 * Should not call netif_carrier_on since it will be called if the link 3189 * is up when checking for link state 3190 */ 3191} 3192 3193#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 3194 3195static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 3196{ 3197 struct eth_stats_info *ether_stat = 3198 &bp->slowpath->drv_info_to_mcp.ether_stat; 3199 3200 strlcpy(ether_stat->version, DRV_MODULE_VERSION, 3201 ETH_STAT_INFO_VERSION_LEN); 3202 3203 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj, 3204 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 3205 ether_stat->mac_local); 3206 3207 ether_stat->mtu_size = bp->dev->mtu; 3208 3209 if (bp->dev->features & NETIF_F_RXCSUM) 3210 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 3211 if (bp->dev->features & NETIF_F_TSO) 3212 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 3213 ether_stat->feature_flags |= bp->common.boot_mode; 3214 3215 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 3216 3217 ether_stat->txq_size = bp->tx_ring_size; 3218 ether_stat->rxq_size = bp->rx_ring_size; 3219} 3220 3221static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 3222{ 3223 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3224 struct fcoe_stats_info *fcoe_stat = 3225 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 3226 3227 if (!CNIC_LOADED(bp)) 3228 return; 3229 3230 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT, 3231 bp->fip_mac, ETH_ALEN); 3232 3233 fcoe_stat->qos_priority = 3234 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 3235 3236 /* insert FCoE stats from ramrod response */ 3237 if (!NO_FCOE(bp)) { 3238 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 3239 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3240 tstorm_queue_statistics; 3241 3242 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 3243 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3244 xstorm_queue_statistics; 3245 3246 struct fcoe_statistics_params *fw_fcoe_stat = 3247 &bp->fw_stats_data->fcoe; 3248 3249 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 3250 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 3251 3252 ADD_64(fcoe_stat->rx_bytes_hi, 3253 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 3254 fcoe_stat->rx_bytes_lo, 3255 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 3256 3257 ADD_64(fcoe_stat->rx_bytes_hi, 3258 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 3259 fcoe_stat->rx_bytes_lo, 3260 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 3261 3262 ADD_64(fcoe_stat->rx_bytes_hi, 3263 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 3264 fcoe_stat->rx_bytes_lo, 3265 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 3266 3267 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3268 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3269 3270 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3271 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3272 3273 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3274 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3275 3276 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3277 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3278 3279 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 3280 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3281 3282 ADD_64(fcoe_stat->tx_bytes_hi, 3283 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3284 fcoe_stat->tx_bytes_lo, 3285 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3286 3287 ADD_64(fcoe_stat->tx_bytes_hi, 3288 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3289 fcoe_stat->tx_bytes_lo, 3290 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3291 3292 ADD_64(fcoe_stat->tx_bytes_hi, 3293 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3294 fcoe_stat->tx_bytes_lo, 3295 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3296 3297 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3298 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3299 3300 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3301 fcoe_q_xstorm_stats->ucast_pkts_sent); 3302 3303 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3304 fcoe_q_xstorm_stats->bcast_pkts_sent); 3305 3306 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3307 fcoe_q_xstorm_stats->mcast_pkts_sent); 3308 } 3309 3310 /* ask L5 driver to add data to the struct */ 3311 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3312} 3313 3314static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3315{ 3316 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3317 struct iscsi_stats_info *iscsi_stat = 3318 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3319 3320 if (!CNIC_LOADED(bp)) 3321 return; 3322 3323 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT, 3324 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3325 3326 iscsi_stat->qos_priority = 3327 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3328 3329 /* ask L5 driver to add data to the struct */ 3330 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3331} 3332 3333/* called due to MCP event (on pmf): 3334 * reread new bandwidth configuration 3335 * configure FW 3336 * notify others function about the change 3337 */ 3338static void bnx2x_config_mf_bw(struct bnx2x *bp) 3339{ 3340 if (bp->link_vars.link_up) { 3341 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3342 bnx2x_link_sync_notify(bp); 3343 } 3344 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3345} 3346 3347static void bnx2x_set_mf_bw(struct bnx2x *bp) 3348{ 3349 bnx2x_config_mf_bw(bp); 3350 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3351} 3352 3353static void bnx2x_handle_eee_event(struct bnx2x *bp) 3354{ 3355 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); 3356 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 3357} 3358 3359static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3360{ 3361 enum drv_info_opcode op_code; 3362 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3363 3364 /* if drv_info version supported by MFW doesn't match - send NACK */ 3365 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3366 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3367 return; 3368 } 3369 3370 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3371 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3372 3373 memset(&bp->slowpath->drv_info_to_mcp, 0, 3374 sizeof(union drv_info_to_mcp)); 3375 3376 switch (op_code) { 3377 case ETH_STATS_OPCODE: 3378 bnx2x_drv_info_ether_stat(bp); 3379 break; 3380 case FCOE_STATS_OPCODE: 3381 bnx2x_drv_info_fcoe_stat(bp); 3382 break; 3383 case ISCSI_STATS_OPCODE: 3384 bnx2x_drv_info_iscsi_stat(bp); 3385 break; 3386 default: 3387 /* if op code isn't supported - send NACK */ 3388 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3389 return; 3390 } 3391 3392 /* if we got drv_info attn from MFW then these fields are defined in 3393 * shmem2 for sure 3394 */ 3395 SHMEM2_WR(bp, drv_info_host_addr_lo, 3396 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3397 SHMEM2_WR(bp, drv_info_host_addr_hi, 3398 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3399 3400 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3401} 3402 3403static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3404{ 3405 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3406 3407 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3408 3409 /* 3410 * This is the only place besides the function initialization 3411 * where the bp->flags can change so it is done without any 3412 * locks 3413 */ 3414 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3415 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); 3416 bp->flags |= MF_FUNC_DIS; 3417 3418 bnx2x_e1h_disable(bp); 3419 } else { 3420 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); 3421 bp->flags &= ~MF_FUNC_DIS; 3422 3423 bnx2x_e1h_enable(bp); 3424 } 3425 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3426 } 3427 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3428 bnx2x_config_mf_bw(bp); 3429 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3430 } 3431 3432 /* Report results to MCP */ 3433 if (dcc_event) 3434 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3435 else 3436 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3437} 3438 3439/* must be called under the spq lock */ 3440static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3441{ 3442 struct eth_spe *next_spe = bp->spq_prod_bd; 3443 3444 if (bp->spq_prod_bd == bp->spq_last_bd) { 3445 bp->spq_prod_bd = bp->spq; 3446 bp->spq_prod_idx = 0; 3447 DP(BNX2X_MSG_SP, "end of spq\n"); 3448 } else { 3449 bp->spq_prod_bd++; 3450 bp->spq_prod_idx++; 3451 } 3452 return next_spe; 3453} 3454 3455/* must be called under the spq lock */ 3456static void bnx2x_sp_prod_update(struct bnx2x *bp) 3457{ 3458 int func = BP_FUNC(bp); 3459 3460 /* 3461 * Make sure that BD data is updated before writing the producer: 3462 * BD data is written to the memory, the producer is read from the 3463 * memory, thus we need a full memory barrier to ensure the ordering. 3464 */ 3465 mb(); 3466 3467 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3468 bp->spq_prod_idx); 3469 mmiowb(); 3470} 3471 3472/** 3473 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3474 * 3475 * @cmd: command to check 3476 * @cmd_type: command type 3477 */ 3478static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3479{ 3480 if ((cmd_type == NONE_CONNECTION_TYPE) || 3481 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3482 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3483 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3484 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3485 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3486 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3487 return true; 3488 else 3489 return false; 3490 3491} 3492 3493 3494/** 3495 * bnx2x_sp_post - place a single command on an SP ring 3496 * 3497 * @bp: driver handle 3498 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3499 * @cid: SW CID the command is related to 3500 * @data_hi: command private data address (high 32 bits) 3501 * @data_lo: command private data address (low 32 bits) 3502 * @cmd_type: command type (e.g. NONE, ETH) 3503 * 3504 * SP data is handled as if it's always an address pair, thus data fields are 3505 * not swapped to little endian in upper functions. Instead this function swaps 3506 * data as if it's two u32 fields. 3507 */ 3508int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3509 u32 data_hi, u32 data_lo, int cmd_type) 3510{ 3511 struct eth_spe *spe; 3512 u16 type; 3513 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3514 3515#ifdef BNX2X_STOP_ON_ERROR 3516 if (unlikely(bp->panic)) { 3517 BNX2X_ERR("Can't post SP when there is panic\n"); 3518 return -EIO; 3519 } 3520#endif 3521 3522 spin_lock_bh(&bp->spq_lock); 3523 3524 if (common) { 3525 if (!atomic_read(&bp->eq_spq_left)) { 3526 BNX2X_ERR("BUG! EQ ring full!\n"); 3527 spin_unlock_bh(&bp->spq_lock); 3528 bnx2x_panic(); 3529 return -EBUSY; 3530 } 3531 } else if (!atomic_read(&bp->cq_spq_left)) { 3532 BNX2X_ERR("BUG! SPQ ring full!\n"); 3533 spin_unlock_bh(&bp->spq_lock); 3534 bnx2x_panic(); 3535 return -EBUSY; 3536 } 3537 3538 spe = bnx2x_sp_get_next(bp); 3539 3540 /* CID needs port number to be encoded int it */ 3541 spe->hdr.conn_and_cmd_data = 3542 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3543 HW_CID(bp, cid)); 3544 3545 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3546 3547 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3548 SPE_HDR_FUNCTION_ID); 3549 3550 spe->hdr.type = cpu_to_le16(type); 3551 3552 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3553 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3554 3555 /* 3556 * It's ok if the actual decrement is issued towards the memory 3557 * somewhere between the spin_lock and spin_unlock. Thus no 3558 * more explict memory barrier is needed. 3559 */ 3560 if (common) 3561 atomic_dec(&bp->eq_spq_left); 3562 else 3563 atomic_dec(&bp->cq_spq_left); 3564 3565 3566 DP(BNX2X_MSG_SP, 3567 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", 3568 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3569 (u32)(U64_LO(bp->spq_mapping) + 3570 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3571 HW_CID(bp, cid), data_hi, data_lo, type, 3572 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3573 3574 bnx2x_sp_prod_update(bp); 3575 spin_unlock_bh(&bp->spq_lock); 3576 return 0; 3577} 3578 3579/* acquire split MCP access lock register */ 3580static int bnx2x_acquire_alr(struct bnx2x *bp) 3581{ 3582 u32 j, val; 3583 int rc = 0; 3584 3585 might_sleep(); 3586 for (j = 0; j < 1000; j++) { 3587 val = (1UL << 31); 3588 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3589 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3590 if (val & (1L << 31)) 3591 break; 3592 3593 msleep(5); 3594 } 3595 if (!(val & (1L << 31))) { 3596 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3597 rc = -EBUSY; 3598 } 3599 3600 return rc; 3601} 3602 3603/* release split MCP access lock register */ 3604static void bnx2x_release_alr(struct bnx2x *bp) 3605{ 3606 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3607} 3608 3609#define BNX2X_DEF_SB_ATT_IDX 0x0001 3610#define BNX2X_DEF_SB_IDX 0x0002 3611 3612static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3613{ 3614 struct host_sp_status_block *def_sb = bp->def_status_blk; 3615 u16 rc = 0; 3616 3617 barrier(); /* status block is written to by the chip */ 3618 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3619 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3620 rc |= BNX2X_DEF_SB_ATT_IDX; 3621 } 3622 3623 if (bp->def_idx != def_sb->sp_sb.running_index) { 3624 bp->def_idx = def_sb->sp_sb.running_index; 3625 rc |= BNX2X_DEF_SB_IDX; 3626 } 3627 3628 /* Do not reorder: indecies reading should complete before handling */ 3629 barrier(); 3630 return rc; 3631} 3632 3633/* 3634 * slow path service functions 3635 */ 3636 3637static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3638{ 3639 int port = BP_PORT(bp); 3640 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3641 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3642 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3643 NIG_REG_MASK_INTERRUPT_PORT0; 3644 u32 aeu_mask; 3645 u32 nig_mask = 0; 3646 u32 reg_addr; 3647 3648 if (bp->attn_state & asserted) 3649 BNX2X_ERR("IGU ERROR\n"); 3650 3651 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3652 aeu_mask = REG_RD(bp, aeu_addr); 3653 3654 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3655 aeu_mask, asserted); 3656 aeu_mask &= ~(asserted & 0x3ff); 3657 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3658 3659 REG_WR(bp, aeu_addr, aeu_mask); 3660 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3661 3662 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3663 bp->attn_state |= asserted; 3664 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3665 3666 if (asserted & ATTN_HARD_WIRED_MASK) { 3667 if (asserted & ATTN_NIG_FOR_FUNC) { 3668 3669 bnx2x_acquire_phy_lock(bp); 3670 3671 /* save nig interrupt mask */ 3672 nig_mask = REG_RD(bp, nig_int_mask_addr); 3673 3674 /* If nig_mask is not set, no need to call the update 3675 * function. 3676 */ 3677 if (nig_mask) { 3678 REG_WR(bp, nig_int_mask_addr, 0); 3679 3680 bnx2x_link_attn(bp); 3681 } 3682 3683 /* handle unicore attn? */ 3684 } 3685 if (asserted & ATTN_SW_TIMER_4_FUNC) 3686 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3687 3688 if (asserted & GPIO_2_FUNC) 3689 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3690 3691 if (asserted & GPIO_3_FUNC) 3692 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3693 3694 if (asserted & GPIO_4_FUNC) 3695 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3696 3697 if (port == 0) { 3698 if (asserted & ATTN_GENERAL_ATTN_1) { 3699 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3700 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3701 } 3702 if (asserted & ATTN_GENERAL_ATTN_2) { 3703 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3704 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3705 } 3706 if (asserted & ATTN_GENERAL_ATTN_3) { 3707 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3708 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3709 } 3710 } else { 3711 if (asserted & ATTN_GENERAL_ATTN_4) { 3712 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3713 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3714 } 3715 if (asserted & ATTN_GENERAL_ATTN_5) { 3716 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3717 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3718 } 3719 if (asserted & ATTN_GENERAL_ATTN_6) { 3720 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3721 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3722 } 3723 } 3724 3725 } /* if hardwired */ 3726 3727 if (bp->common.int_block == INT_BLOCK_HC) 3728 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3729 COMMAND_REG_ATTN_BITS_SET); 3730 else 3731 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3732 3733 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3734 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3735 REG_WR(bp, reg_addr, asserted); 3736 3737 /* now set back the mask */ 3738 if (asserted & ATTN_NIG_FOR_FUNC) { 3739 /* Verify that IGU ack through BAR was written before restoring 3740 * NIG mask. This loop should exit after 2-3 iterations max. 3741 */ 3742 if (bp->common.int_block != INT_BLOCK_HC) { 3743 u32 cnt = 0, igu_acked; 3744 do { 3745 igu_acked = REG_RD(bp, 3746 IGU_REG_ATTENTION_ACK_BITS); 3747 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 3748 (++cnt < MAX_IGU_ATTN_ACK_TO)); 3749 if (!igu_acked) 3750 DP(NETIF_MSG_HW, 3751 "Failed to verify IGU ack on time\n"); 3752 barrier(); 3753 } 3754 REG_WR(bp, nig_int_mask_addr, nig_mask); 3755 bnx2x_release_phy_lock(bp); 3756 } 3757} 3758 3759static void bnx2x_fan_failure(struct bnx2x *bp) 3760{ 3761 int port = BP_PORT(bp); 3762 u32 ext_phy_config; 3763 /* mark the failure */ 3764 ext_phy_config = 3765 SHMEM_RD(bp, 3766 dev_info.port_hw_config[port].external_phy_config); 3767 3768 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3769 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3770 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3771 ext_phy_config); 3772 3773 /* log the failure */ 3774 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" 3775 "Please contact OEM Support for assistance\n"); 3776 3777 /* 3778 * Scheudle device reset (unload) 3779 * This is due to some boards consuming sufficient power when driver is 3780 * up to overheat if fan fails. 3781 */ 3782 smp_mb__before_clear_bit(); 3783 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3784 smp_mb__after_clear_bit(); 3785 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3786 3787} 3788 3789static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3790{ 3791 int port = BP_PORT(bp); 3792 int reg_offset; 3793 u32 val; 3794 3795 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3796 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3797 3798 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3799 3800 val = REG_RD(bp, reg_offset); 3801 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3802 REG_WR(bp, reg_offset, val); 3803 3804 BNX2X_ERR("SPIO5 hw attention\n"); 3805 3806 /* Fan failure attention */ 3807 bnx2x_hw_reset_phy(&bp->link_params); 3808 bnx2x_fan_failure(bp); 3809 } 3810 3811 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3812 bnx2x_acquire_phy_lock(bp); 3813 bnx2x_handle_module_detect_int(&bp->link_params); 3814 bnx2x_release_phy_lock(bp); 3815 } 3816 3817 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3818 3819 val = REG_RD(bp, reg_offset); 3820 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3821 REG_WR(bp, reg_offset, val); 3822 3823 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3824 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3825 bnx2x_panic(); 3826 } 3827} 3828 3829static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3830{ 3831 u32 val; 3832 3833 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3834 3835 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3836 BNX2X_ERR("DB hw attention 0x%x\n", val); 3837 /* DORQ discard attention */ 3838 if (val & 0x2) 3839 BNX2X_ERR("FATAL error from DORQ\n"); 3840 } 3841 3842 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3843 3844 int port = BP_PORT(bp); 3845 int reg_offset; 3846 3847 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3848 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3849 3850 val = REG_RD(bp, reg_offset); 3851 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3852 REG_WR(bp, reg_offset, val); 3853 3854 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3855 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3856 bnx2x_panic(); 3857 } 3858} 3859 3860static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3861{ 3862 u32 val; 3863 3864 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3865 3866 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3867 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3868 /* CFC error attention */ 3869 if (val & 0x2) 3870 BNX2X_ERR("FATAL error from CFC\n"); 3871 } 3872 3873 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3874 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3875 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3876 /* RQ_USDMDP_FIFO_OVERFLOW */ 3877 if (val & 0x18000) 3878 BNX2X_ERR("FATAL error from PXP\n"); 3879 3880 if (!CHIP_IS_E1x(bp)) { 3881 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3882 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3883 } 3884 } 3885 3886 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3887 3888 int port = BP_PORT(bp); 3889 int reg_offset; 3890 3891 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3892 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3893 3894 val = REG_RD(bp, reg_offset); 3895 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3896 REG_WR(bp, reg_offset, val); 3897 3898 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3899 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3900 bnx2x_panic(); 3901 } 3902} 3903 3904static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3905{ 3906 u32 val; 3907 3908 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3909 3910 if (attn & BNX2X_PMF_LINK_ASSERT) { 3911 int func = BP_FUNC(bp); 3912 3913 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3914 bnx2x_read_mf_cfg(bp); 3915 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3916 func_mf_config[BP_ABS_FUNC(bp)].config); 3917 val = SHMEM_RD(bp, 3918 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3919 if (val & DRV_STATUS_DCC_EVENT_MASK) 3920 bnx2x_dcc_event(bp, 3921 (val & DRV_STATUS_DCC_EVENT_MASK)); 3922 3923 if (val & DRV_STATUS_SET_MF_BW) 3924 bnx2x_set_mf_bw(bp); 3925 3926 if (val & DRV_STATUS_DRV_INFO_REQ) 3927 bnx2x_handle_drv_info_req(bp); 3928 3929 if (val & DRV_STATUS_VF_DISABLED) 3930 bnx2x_vf_handle_flr_event(bp); 3931 3932 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3933 bnx2x_pmf_update(bp); 3934 3935 if (bp->port.pmf && 3936 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3937 bp->dcbx_enabled > 0) 3938 /* start dcbx state machine */ 3939 bnx2x_dcbx_set_params(bp, 3940 BNX2X_DCBX_STATE_NEG_RECEIVED); 3941 if (val & DRV_STATUS_AFEX_EVENT_MASK) 3942 bnx2x_handle_afex_cmd(bp, 3943 val & DRV_STATUS_AFEX_EVENT_MASK); 3944 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 3945 bnx2x_handle_eee_event(bp); 3946 if (bp->link_vars.periodic_flags & 3947 PERIODIC_FLAGS_LINK_EVENT) { 3948 /* sync with link */ 3949 bnx2x_acquire_phy_lock(bp); 3950 bp->link_vars.periodic_flags &= 3951 ~PERIODIC_FLAGS_LINK_EVENT; 3952 bnx2x_release_phy_lock(bp); 3953 if (IS_MF(bp)) 3954 bnx2x_link_sync_notify(bp); 3955 bnx2x_link_report(bp); 3956 } 3957 /* Always call it here: bnx2x_link_report() will 3958 * prevent the link indication duplication. 3959 */ 3960 bnx2x__link_status_update(bp); 3961 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3962 3963 BNX2X_ERR("MC assert!\n"); 3964 bnx2x_mc_assert(bp); 3965 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3966 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3967 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3968 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3969 bnx2x_panic(); 3970 3971 } else if (attn & BNX2X_MCP_ASSERT) { 3972 3973 BNX2X_ERR("MCP assert!\n"); 3974 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3975 bnx2x_fw_dump(bp); 3976 3977 } else 3978 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3979 } 3980 3981 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3982 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3983 if (attn & BNX2X_GRC_TIMEOUT) { 3984 val = CHIP_IS_E1(bp) ? 0 : 3985 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3986 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3987 } 3988 if (attn & BNX2X_GRC_RSV) { 3989 val = CHIP_IS_E1(bp) ? 0 : 3990 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3991 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3992 } 3993 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3994 } 3995} 3996 3997/* 3998 * Bits map: 3999 * 0-7 - Engine0 load counter. 4000 * 8-15 - Engine1 load counter. 4001 * 16 - Engine0 RESET_IN_PROGRESS bit. 4002 * 17 - Engine1 RESET_IN_PROGRESS bit. 4003 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 4004 * on the engine 4005 * 19 - Engine1 ONE_IS_LOADED. 4006 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 4007 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 4008 * just the one belonging to its engine). 4009 * 4010 */ 4011#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 4012 4013#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 4014#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 4015#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 4016#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 4017#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 4018#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 4019#define BNX2X_GLOBAL_RESET_BIT 0x00040000 4020 4021/* 4022 * Set the GLOBAL_RESET bit. 4023 * 4024 * Should be run under rtnl lock 4025 */ 4026void bnx2x_set_reset_global(struct bnx2x *bp) 4027{ 4028 u32 val; 4029 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4030 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4031 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 4032 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4033} 4034 4035/* 4036 * Clear the GLOBAL_RESET bit. 4037 * 4038 * Should be run under rtnl lock 4039 */ 4040static void bnx2x_clear_reset_global(struct bnx2x *bp) 4041{ 4042 u32 val; 4043 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4044 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4045 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 4046 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4047} 4048 4049/* 4050 * Checks the GLOBAL_RESET bit. 4051 * 4052 * should be run under rtnl lock 4053 */ 4054static bool bnx2x_reset_is_global(struct bnx2x *bp) 4055{ 4056 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4057 4058 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 4059 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 4060} 4061 4062/* 4063 * Clear RESET_IN_PROGRESS bit for the current engine. 4064 * 4065 * Should be run under rtnl lock 4066 */ 4067static void bnx2x_set_reset_done(struct bnx2x *bp) 4068{ 4069 u32 val; 4070 u32 bit = BP_PATH(bp) ? 4071 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4072 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4073 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4074 4075 /* Clear the bit */ 4076 val &= ~bit; 4077 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4078 4079 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4080} 4081 4082/* 4083 * Set RESET_IN_PROGRESS for the current engine. 4084 * 4085 * should be run under rtnl lock 4086 */ 4087void bnx2x_set_reset_in_progress(struct bnx2x *bp) 4088{ 4089 u32 val; 4090 u32 bit = BP_PATH(bp) ? 4091 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4092 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4093 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4094 4095 /* Set the bit */ 4096 val |= bit; 4097 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4098 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4099} 4100 4101/* 4102 * Checks the RESET_IN_PROGRESS bit for the given engine. 4103 * should be run under rtnl lock 4104 */ 4105bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 4106{ 4107 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4108 u32 bit = engine ? 4109 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4110 4111 /* return false if bit is set */ 4112 return (val & bit) ? false : true; 4113} 4114 4115/* 4116 * set pf load for the current pf. 4117 * 4118 * should be run under rtnl lock 4119 */ 4120void bnx2x_set_pf_load(struct bnx2x *bp) 4121{ 4122 u32 val1, val; 4123 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4124 BNX2X_PATH0_LOAD_CNT_MASK; 4125 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4126 BNX2X_PATH0_LOAD_CNT_SHIFT; 4127 4128 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4129 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4130 4131 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); 4132 4133 /* get the current counter value */ 4134 val1 = (val & mask) >> shift; 4135 4136 /* set bit of that PF */ 4137 val1 |= (1 << bp->pf_num); 4138 4139 /* clear the old value */ 4140 val &= ~mask; 4141 4142 /* set the new one */ 4143 val |= ((val1 << shift) & mask); 4144 4145 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4146 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4147} 4148 4149/** 4150 * bnx2x_clear_pf_load - clear pf load mark 4151 * 4152 * @bp: driver handle 4153 * 4154 * Should be run under rtnl lock. 4155 * Decrements the load counter for the current engine. Returns 4156 * whether other functions are still loaded 4157 */ 4158bool bnx2x_clear_pf_load(struct bnx2x *bp) 4159{ 4160 u32 val1, val; 4161 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4162 BNX2X_PATH0_LOAD_CNT_MASK; 4163 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4164 BNX2X_PATH0_LOAD_CNT_SHIFT; 4165 4166 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4167 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4168 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); 4169 4170 /* get the current counter value */ 4171 val1 = (val & mask) >> shift; 4172 4173 /* clear bit of that PF */ 4174 val1 &= ~(1 << bp->pf_num); 4175 4176 /* clear the old value */ 4177 val &= ~mask; 4178 4179 /* set the new one */ 4180 val |= ((val1 << shift) & mask); 4181 4182 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4183 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4184 return val1 != 0; 4185} 4186 4187/* 4188 * Read the load status for the current engine. 4189 * 4190 * should be run under rtnl lock 4191 */ 4192static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 4193{ 4194 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 4195 BNX2X_PATH0_LOAD_CNT_MASK); 4196 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4197 BNX2X_PATH0_LOAD_CNT_SHIFT); 4198 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4199 4200 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); 4201 4202 val = (val & mask) >> shift; 4203 4204 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", 4205 engine, val); 4206 4207 return val != 0; 4208} 4209 4210static void _print_next_block(int idx, const char *blk) 4211{ 4212 pr_cont("%s%s", idx ? ", " : "", blk); 4213} 4214 4215static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 4216 bool print) 4217{ 4218 int i = 0; 4219 u32 cur_bit = 0; 4220 for (i = 0; sig; i++) { 4221 cur_bit = ((u32)0x1 << i); 4222 if (sig & cur_bit) { 4223 switch (cur_bit) { 4224 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 4225 if (print) 4226 _print_next_block(par_num++, "BRB"); 4227 break; 4228 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 4229 if (print) 4230 _print_next_block(par_num++, "PARSER"); 4231 break; 4232 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 4233 if (print) 4234 _print_next_block(par_num++, "TSDM"); 4235 break; 4236 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 4237 if (print) 4238 _print_next_block(par_num++, 4239 "SEARCHER"); 4240 break; 4241 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 4242 if (print) 4243 _print_next_block(par_num++, "TCM"); 4244 break; 4245 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 4246 if (print) 4247 _print_next_block(par_num++, "TSEMI"); 4248 break; 4249 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 4250 if (print) 4251 _print_next_block(par_num++, "XPB"); 4252 break; 4253 } 4254 4255 /* Clear the bit */ 4256 sig &= ~cur_bit; 4257 } 4258 } 4259 4260 return par_num; 4261} 4262 4263static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 4264 bool *global, bool print) 4265{ 4266 int i = 0; 4267 u32 cur_bit = 0; 4268 for (i = 0; sig; i++) { 4269 cur_bit = ((u32)0x1 << i); 4270 if (sig & cur_bit) { 4271 switch (cur_bit) { 4272 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 4273 if (print) 4274 _print_next_block(par_num++, "PBF"); 4275 break; 4276 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 4277 if (print) 4278 _print_next_block(par_num++, "QM"); 4279 break; 4280 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 4281 if (print) 4282 _print_next_block(par_num++, "TM"); 4283 break; 4284 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4285 if (print) 4286 _print_next_block(par_num++, "XSDM"); 4287 break; 4288 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4289 if (print) 4290 _print_next_block(par_num++, "XCM"); 4291 break; 4292 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4293 if (print) 4294 _print_next_block(par_num++, "XSEMI"); 4295 break; 4296 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4297 if (print) 4298 _print_next_block(par_num++, 4299 "DOORBELLQ"); 4300 break; 4301 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4302 if (print) 4303 _print_next_block(par_num++, "NIG"); 4304 break; 4305 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4306 if (print) 4307 _print_next_block(par_num++, 4308 "VAUX PCI CORE"); 4309 *global = true; 4310 break; 4311 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4312 if (print) 4313 _print_next_block(par_num++, "DEBUG"); 4314 break; 4315 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4316 if (print) 4317 _print_next_block(par_num++, "USDM"); 4318 break; 4319 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4320 if (print) 4321 _print_next_block(par_num++, "UCM"); 4322 break; 4323 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4324 if (print) 4325 _print_next_block(par_num++, "USEMI"); 4326 break; 4327 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4328 if (print) 4329 _print_next_block(par_num++, "UPB"); 4330 break; 4331 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4332 if (print) 4333 _print_next_block(par_num++, "CSDM"); 4334 break; 4335 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4336 if (print) 4337 _print_next_block(par_num++, "CCM"); 4338 break; 4339 } 4340 4341 /* Clear the bit */ 4342 sig &= ~cur_bit; 4343 } 4344 } 4345 4346 return par_num; 4347} 4348 4349static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4350 bool print) 4351{ 4352 int i = 0; 4353 u32 cur_bit = 0; 4354 for (i = 0; sig; i++) { 4355 cur_bit = ((u32)0x1 << i); 4356 if (sig & cur_bit) { 4357 switch (cur_bit) { 4358 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4359 if (print) 4360 _print_next_block(par_num++, "CSEMI"); 4361 break; 4362 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4363 if (print) 4364 _print_next_block(par_num++, "PXP"); 4365 break; 4366 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4367 if (print) 4368 _print_next_block(par_num++, 4369 "PXPPCICLOCKCLIENT"); 4370 break; 4371 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4372 if (print) 4373 _print_next_block(par_num++, "CFC"); 4374 break; 4375 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4376 if (print) 4377 _print_next_block(par_num++, "CDU"); 4378 break; 4379 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4380 if (print) 4381 _print_next_block(par_num++, "DMAE"); 4382 break; 4383 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4384 if (print) 4385 _print_next_block(par_num++, "IGU"); 4386 break; 4387 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4388 if (print) 4389 _print_next_block(par_num++, "MISC"); 4390 break; 4391 } 4392 4393 /* Clear the bit */ 4394 sig &= ~cur_bit; 4395 } 4396 } 4397 4398 return par_num; 4399} 4400 4401static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4402 bool *global, bool print) 4403{ 4404 int i = 0; 4405 u32 cur_bit = 0; 4406 for (i = 0; sig; i++) { 4407 cur_bit = ((u32)0x1 << i); 4408 if (sig & cur_bit) { 4409 switch (cur_bit) { 4410 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4411 if (print) 4412 _print_next_block(par_num++, "MCP ROM"); 4413 *global = true; 4414 break; 4415 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4416 if (print) 4417 _print_next_block(par_num++, 4418 "MCP UMP RX"); 4419 *global = true; 4420 break; 4421 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4422 if (print) 4423 _print_next_block(par_num++, 4424 "MCP UMP TX"); 4425 *global = true; 4426 break; 4427 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4428 if (print) 4429 _print_next_block(par_num++, 4430 "MCP SCPAD"); 4431 *global = true; 4432 break; 4433 } 4434 4435 /* Clear the bit */ 4436 sig &= ~cur_bit; 4437 } 4438 } 4439 4440 return par_num; 4441} 4442 4443static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4444 bool print) 4445{ 4446 int i = 0; 4447 u32 cur_bit = 0; 4448 for (i = 0; sig; i++) { 4449 cur_bit = ((u32)0x1 << i); 4450 if (sig & cur_bit) { 4451 switch (cur_bit) { 4452 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4453 if (print) 4454 _print_next_block(par_num++, "PGLUE_B"); 4455 break; 4456 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4457 if (print) 4458 _print_next_block(par_num++, "ATC"); 4459 break; 4460 } 4461 4462 /* Clear the bit */ 4463 sig &= ~cur_bit; 4464 } 4465 } 4466 4467 return par_num; 4468} 4469 4470static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4471 u32 *sig) 4472{ 4473 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4474 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4475 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4476 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4477 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4478 int par_num = 0; 4479 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" 4480 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 4481 sig[0] & HW_PRTY_ASSERT_SET_0, 4482 sig[1] & HW_PRTY_ASSERT_SET_1, 4483 sig[2] & HW_PRTY_ASSERT_SET_2, 4484 sig[3] & HW_PRTY_ASSERT_SET_3, 4485 sig[4] & HW_PRTY_ASSERT_SET_4); 4486 if (print) 4487 netdev_err(bp->dev, 4488 "Parity errors detected in blocks: "); 4489 par_num = bnx2x_check_blocks_with_parity0( 4490 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4491 par_num = bnx2x_check_blocks_with_parity1( 4492 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4493 par_num = bnx2x_check_blocks_with_parity2( 4494 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4495 par_num = bnx2x_check_blocks_with_parity3( 4496 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4497 par_num = bnx2x_check_blocks_with_parity4( 4498 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4499 4500 if (print) 4501 pr_cont("\n"); 4502 4503 return true; 4504 } else 4505 return false; 4506} 4507 4508/** 4509 * bnx2x_chk_parity_attn - checks for parity attentions. 4510 * 4511 * @bp: driver handle 4512 * @global: true if there was a global attention 4513 * @print: show parity attention in syslog 4514 */ 4515bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4516{ 4517 struct attn_route attn = { {0} }; 4518 int port = BP_PORT(bp); 4519 4520 attn.sig[0] = REG_RD(bp, 4521 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4522 port*4); 4523 attn.sig[1] = REG_RD(bp, 4524 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4525 port*4); 4526 attn.sig[2] = REG_RD(bp, 4527 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4528 port*4); 4529 attn.sig[3] = REG_RD(bp, 4530 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4531 port*4); 4532 4533 if (!CHIP_IS_E1x(bp)) 4534 attn.sig[4] = REG_RD(bp, 4535 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4536 port*4); 4537 4538 return bnx2x_parity_attn(bp, global, print, attn.sig); 4539} 4540 4541 4542static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4543{ 4544 u32 val; 4545 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4546 4547 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4548 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4549 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4550 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 4551 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4552 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 4553 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4554 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 4555 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4556 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 4557 if (val & 4558 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4559 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 4560 if (val & 4561 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4562 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 4563 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4564 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 4565 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4566 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 4567 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4568 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 4569 } 4570 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4571 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4572 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4573 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4574 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4575 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4576 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 4577 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4578 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 4579 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4580 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 4581 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4582 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4583 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4584 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 4585 } 4586 4587 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4588 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4589 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4590 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4591 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4592 } 4593 4594} 4595 4596static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4597{ 4598 struct attn_route attn, *group_mask; 4599 int port = BP_PORT(bp); 4600 int index; 4601 u32 reg_addr; 4602 u32 val; 4603 u32 aeu_mask; 4604 bool global = false; 4605 4606 /* need to take HW lock because MCP or other port might also 4607 try to handle this event */ 4608 bnx2x_acquire_alr(bp); 4609 4610 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4611#ifndef BNX2X_STOP_ON_ERROR 4612 bp->recovery_state = BNX2X_RECOVERY_INIT; 4613 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4614 /* Disable HW interrupts */ 4615 bnx2x_int_disable(bp); 4616 /* In case of parity errors don't handle attentions so that 4617 * other function would "see" parity errors. 4618 */ 4619#else 4620 bnx2x_panic(); 4621#endif 4622 bnx2x_release_alr(bp); 4623 return; 4624 } 4625 4626 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4627 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4628 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4629 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4630 if (!CHIP_IS_E1x(bp)) 4631 attn.sig[4] = 4632 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4633 else 4634 attn.sig[4] = 0; 4635 4636 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4637 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4638 4639 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4640 if (deasserted & (1 << index)) { 4641 group_mask = &bp->attn_group[index]; 4642 4643 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", 4644 index, 4645 group_mask->sig[0], group_mask->sig[1], 4646 group_mask->sig[2], group_mask->sig[3], 4647 group_mask->sig[4]); 4648 4649 bnx2x_attn_int_deasserted4(bp, 4650 attn.sig[4] & group_mask->sig[4]); 4651 bnx2x_attn_int_deasserted3(bp, 4652 attn.sig[3] & group_mask->sig[3]); 4653 bnx2x_attn_int_deasserted1(bp, 4654 attn.sig[1] & group_mask->sig[1]); 4655 bnx2x_attn_int_deasserted2(bp, 4656 attn.sig[2] & group_mask->sig[2]); 4657 bnx2x_attn_int_deasserted0(bp, 4658 attn.sig[0] & group_mask->sig[0]); 4659 } 4660 } 4661 4662 bnx2x_release_alr(bp); 4663 4664 if (bp->common.int_block == INT_BLOCK_HC) 4665 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4666 COMMAND_REG_ATTN_BITS_CLR); 4667 else 4668 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4669 4670 val = ~deasserted; 4671 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4672 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4673 REG_WR(bp, reg_addr, val); 4674 4675 if (~bp->attn_state & deasserted) 4676 BNX2X_ERR("IGU ERROR\n"); 4677 4678 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4679 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4680 4681 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4682 aeu_mask = REG_RD(bp, reg_addr); 4683 4684 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4685 aeu_mask, deasserted); 4686 aeu_mask |= (deasserted & 0x3ff); 4687 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4688 4689 REG_WR(bp, reg_addr, aeu_mask); 4690 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4691 4692 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4693 bp->attn_state &= ~deasserted; 4694 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4695} 4696 4697static void bnx2x_attn_int(struct bnx2x *bp) 4698{ 4699 /* read local copy of bits */ 4700 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4701 attn_bits); 4702 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4703 attn_bits_ack); 4704 u32 attn_state = bp->attn_state; 4705 4706 /* look for changed bits */ 4707 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4708 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4709 4710 DP(NETIF_MSG_HW, 4711 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4712 attn_bits, attn_ack, asserted, deasserted); 4713 4714 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4715 BNX2X_ERR("BAD attention state\n"); 4716 4717 /* handle bits that were raised */ 4718 if (asserted) 4719 bnx2x_attn_int_asserted(bp, asserted); 4720 4721 if (deasserted) 4722 bnx2x_attn_int_deasserted(bp, deasserted); 4723} 4724 4725void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4726 u16 index, u8 op, u8 update) 4727{ 4728 u32 igu_addr = bp->igu_base_addr; 4729 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4730 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4731 igu_addr); 4732} 4733 4734static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4735{ 4736 /* No memory barriers */ 4737 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4738 mmiowb(); /* keep prod updates ordered */ 4739} 4740 4741static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4742 union event_ring_elem *elem) 4743{ 4744 u8 err = elem->message.error; 4745 4746 if (!bp->cnic_eth_dev.starting_cid || 4747 (cid < bp->cnic_eth_dev.starting_cid && 4748 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4749 return 1; 4750 4751 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4752 4753 if (unlikely(err)) { 4754 4755 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4756 cid); 4757 bnx2x_panic_dump(bp); 4758 } 4759 bnx2x_cnic_cfc_comp(bp, cid, err); 4760 return 0; 4761} 4762 4763static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4764{ 4765 struct bnx2x_mcast_ramrod_params rparam; 4766 int rc; 4767 4768 memset(&rparam, 0, sizeof(rparam)); 4769 4770 rparam.mcast_obj = &bp->mcast_obj; 4771 4772 netif_addr_lock_bh(bp->dev); 4773 4774 /* Clear pending state for the last command */ 4775 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4776 4777 /* If there are pending mcast commands - send them */ 4778 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4779 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4780 if (rc < 0) 4781 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4782 rc); 4783 } 4784 4785 netif_addr_unlock_bh(bp->dev); 4786} 4787 4788static void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4789 union event_ring_elem *elem) 4790{ 4791 unsigned long ramrod_flags = 0; 4792 int rc = 0; 4793 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4794 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4795 4796 /* Always push next commands out, don't wait here */ 4797 __set_bit(RAMROD_CONT, &ramrod_flags); 4798 4799 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4800 case BNX2X_FILTER_MAC_PENDING: 4801 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); 4802 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) 4803 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4804 else 4805 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; 4806 4807 break; 4808 case BNX2X_FILTER_MCAST_PENDING: 4809 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); 4810 /* This is only relevant for 57710 where multicast MACs are 4811 * configured as unicast MACs using the same ramrod. 4812 */ 4813 bnx2x_handle_mcast_eqe(bp); 4814 return; 4815 default: 4816 BNX2X_ERR("Unsupported classification command: %d\n", 4817 elem->message.data.eth_event.echo); 4818 return; 4819 } 4820 4821 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4822 4823 if (rc < 0) 4824 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4825 else if (rc > 0) 4826 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4827 4828} 4829 4830static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4831 4832static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4833{ 4834 netif_addr_lock_bh(bp->dev); 4835 4836 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4837 4838 /* Send rx_mode command again if was requested */ 4839 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4840 bnx2x_set_storm_rx_mode(bp); 4841 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4842 &bp->sp_state)) 4843 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4844 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4845 &bp->sp_state)) 4846 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4847 4848 netif_addr_unlock_bh(bp->dev); 4849} 4850 4851static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, 4852 union event_ring_elem *elem) 4853{ 4854 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { 4855 DP(BNX2X_MSG_SP, 4856 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", 4857 elem->message.data.vif_list_event.func_bit_map); 4858 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, 4859 elem->message.data.vif_list_event.func_bit_map); 4860 } else if (elem->message.data.vif_list_event.echo == 4861 VIF_LIST_RULE_SET) { 4862 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); 4863 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); 4864 } 4865} 4866 4867/* called with rtnl_lock */ 4868static void bnx2x_after_function_update(struct bnx2x *bp) 4869{ 4870 int q, rc; 4871 struct bnx2x_fastpath *fp; 4872 struct bnx2x_queue_state_params queue_params = {NULL}; 4873 struct bnx2x_queue_update_params *q_update_params = 4874 &queue_params.params.update; 4875 4876 /* Send Q update command with afex vlan removal values for all Qs */ 4877 queue_params.cmd = BNX2X_Q_CMD_UPDATE; 4878 4879 /* set silent vlan removal values according to vlan mode */ 4880 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 4881 &q_update_params->update_flags); 4882 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 4883 &q_update_params->update_flags); 4884 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 4885 4886 /* in access mode mark mask and value are 0 to strip all vlans */ 4887 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { 4888 q_update_params->silent_removal_value = 0; 4889 q_update_params->silent_removal_mask = 0; 4890 } else { 4891 q_update_params->silent_removal_value = 4892 (bp->afex_def_vlan_tag & VLAN_VID_MASK); 4893 q_update_params->silent_removal_mask = VLAN_VID_MASK; 4894 } 4895 4896 for_each_eth_queue(bp, q) { 4897 /* Set the appropriate Queue object */ 4898 fp = &bp->fp[q]; 4899 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 4900 4901 /* send the ramrod */ 4902 rc = bnx2x_queue_state_change(bp, &queue_params); 4903 if (rc < 0) 4904 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 4905 q); 4906 } 4907 4908 if (!NO_FCOE(bp)) { 4909 fp = &bp->fp[FCOE_IDX(bp)]; 4910 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 4911 4912 /* clear pending completion bit */ 4913 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 4914 4915 /* mark latest Q bit */ 4916 smp_mb__before_clear_bit(); 4917 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 4918 smp_mb__after_clear_bit(); 4919 4920 /* send Q update ramrod for FCoE Q */ 4921 rc = bnx2x_queue_state_change(bp, &queue_params); 4922 if (rc < 0) 4923 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 4924 q); 4925 } else { 4926 /* If no FCoE ring - ACK MCP now */ 4927 bnx2x_link_report(bp); 4928 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 4929 } 4930} 4931 4932static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4933 struct bnx2x *bp, u32 cid) 4934{ 4935 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4936 4937 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) 4938 return &bnx2x_fcoe_sp_obj(bp, q_obj); 4939 else 4940 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; 4941} 4942 4943static void bnx2x_eq_int(struct bnx2x *bp) 4944{ 4945 u16 hw_cons, sw_cons, sw_prod; 4946 union event_ring_elem *elem; 4947 u8 echo; 4948 u32 cid; 4949 u8 opcode; 4950 int rc, spqe_cnt = 0; 4951 struct bnx2x_queue_sp_obj *q_obj; 4952 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4953 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4954 4955 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4956 4957 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4958 * when we get the the next-page we nned to adjust so the loop 4959 * condition below will be met. The next element is the size of a 4960 * regular element and hence incrementing by 1 4961 */ 4962 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4963 hw_cons++; 4964 4965 /* This function may never run in parallel with itself for a 4966 * specific bp, thus there is no need in "paired" read memory 4967 * barrier here. 4968 */ 4969 sw_cons = bp->eq_cons; 4970 sw_prod = bp->eq_prod; 4971 4972 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4973 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4974 4975 for (; sw_cons != hw_cons; 4976 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4977 4978 4979 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4980 4981 rc = bnx2x_iov_eq_sp_event(bp, elem); 4982 if (!rc) { 4983 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", 4984 rc); 4985 goto next_spqe; 4986 } 4987 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4988 opcode = elem->message.opcode; 4989 4990 4991 /* handle eq element */ 4992 switch (opcode) { 4993 case EVENT_RING_OPCODE_VF_PF_CHANNEL: 4994 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n"); 4995 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event); 4996 continue; 4997 4998 case EVENT_RING_OPCODE_STAT_QUERY: 4999 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, 5000 "got statistics comp event %d\n", 5001 bp->stats_comp++); 5002 /* nothing to do with stats comp */ 5003 goto next_spqe; 5004 5005 case EVENT_RING_OPCODE_CFC_DEL: 5006 /* handle according to cid range */ 5007 /* 5008 * we may want to verify here that the bp state is 5009 * HALTING 5010 */ 5011 DP(BNX2X_MSG_SP, 5012 "got delete ramrod for MULTI[%d]\n", cid); 5013 5014 if (CNIC_LOADED(bp) && 5015 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 5016 goto next_spqe; 5017 5018 q_obj = bnx2x_cid_to_q_obj(bp, cid); 5019 5020 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 5021 break; 5022 5023 5024 5025 goto next_spqe; 5026 5027 case EVENT_RING_OPCODE_STOP_TRAFFIC: 5028 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); 5029 if (f_obj->complete_cmd(bp, f_obj, 5030 BNX2X_F_CMD_TX_STOP)) 5031 break; 5032 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 5033 goto next_spqe; 5034 5035 case EVENT_RING_OPCODE_START_TRAFFIC: 5036 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); 5037 if (f_obj->complete_cmd(bp, f_obj, 5038 BNX2X_F_CMD_TX_START)) 5039 break; 5040 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 5041 goto next_spqe; 5042 5043 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 5044 echo = elem->message.data.function_update_event.echo; 5045 if (echo == SWITCH_UPDATE) { 5046 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5047 "got FUNC_SWITCH_UPDATE ramrod\n"); 5048 if (f_obj->complete_cmd( 5049 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) 5050 break; 5051 5052 } else { 5053 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, 5054 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 5055 f_obj->complete_cmd(bp, f_obj, 5056 BNX2X_F_CMD_AFEX_UPDATE); 5057 5058 /* We will perform the Queues update from 5059 * sp_rtnl task as all Queue SP operations 5060 * should run under rtnl_lock. 5061 */ 5062 smp_mb__before_clear_bit(); 5063 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, 5064 &bp->sp_rtnl_state); 5065 smp_mb__after_clear_bit(); 5066 5067 schedule_delayed_work(&bp->sp_rtnl_task, 0); 5068 } 5069 5070 goto next_spqe; 5071 5072 case EVENT_RING_OPCODE_AFEX_VIF_LISTS: 5073 f_obj->complete_cmd(bp, f_obj, 5074 BNX2X_F_CMD_AFEX_VIFLISTS); 5075 bnx2x_after_afex_vif_lists(bp, elem); 5076 goto next_spqe; 5077 case EVENT_RING_OPCODE_FUNCTION_START: 5078 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5079 "got FUNC_START ramrod\n"); 5080 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 5081 break; 5082 5083 goto next_spqe; 5084 5085 case EVENT_RING_OPCODE_FUNCTION_STOP: 5086 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5087 "got FUNC_STOP ramrod\n"); 5088 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 5089 break; 5090 5091 goto next_spqe; 5092 } 5093 5094 switch (opcode | bp->state) { 5095 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5096 BNX2X_STATE_OPEN): 5097 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5098 BNX2X_STATE_OPENING_WAIT4_PORT): 5099 cid = elem->message.data.eth_event.echo & 5100 BNX2X_SWCID_MASK; 5101 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 5102 cid); 5103 rss_raw->clear_pending(rss_raw); 5104 break; 5105 5106 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 5107 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 5108 case (EVENT_RING_OPCODE_SET_MAC | 5109 BNX2X_STATE_CLOSING_WAIT4_HALT): 5110 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5111 BNX2X_STATE_OPEN): 5112 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5113 BNX2X_STATE_DIAG): 5114 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5115 BNX2X_STATE_CLOSING_WAIT4_HALT): 5116 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 5117 bnx2x_handle_classification_eqe(bp, elem); 5118 break; 5119 5120 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5121 BNX2X_STATE_OPEN): 5122 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5123 BNX2X_STATE_DIAG): 5124 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5125 BNX2X_STATE_CLOSING_WAIT4_HALT): 5126 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 5127 bnx2x_handle_mcast_eqe(bp); 5128 break; 5129 5130 case (EVENT_RING_OPCODE_FILTERS_RULES | 5131 BNX2X_STATE_OPEN): 5132 case (EVENT_RING_OPCODE_FILTERS_RULES | 5133 BNX2X_STATE_DIAG): 5134 case (EVENT_RING_OPCODE_FILTERS_RULES | 5135 BNX2X_STATE_CLOSING_WAIT4_HALT): 5136 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 5137 bnx2x_handle_rx_mode_eqe(bp); 5138 break; 5139 default: 5140 /* unknown event log error and continue */ 5141 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 5142 elem->message.opcode, bp->state); 5143 } 5144next_spqe: 5145 spqe_cnt++; 5146 } /* for */ 5147 5148 smp_mb__before_atomic_inc(); 5149 atomic_add(spqe_cnt, &bp->eq_spq_left); 5150 5151 bp->eq_cons = sw_cons; 5152 bp->eq_prod = sw_prod; 5153 /* Make sure that above mem writes were issued towards the memory */ 5154 smp_wmb(); 5155 5156 /* update producer */ 5157 bnx2x_update_eq_prod(bp, bp->eq_prod); 5158} 5159 5160static void bnx2x_sp_task(struct work_struct *work) 5161{ 5162 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 5163 5164 DP(BNX2X_MSG_SP, "sp task invoked\n"); 5165 5166 /* make sure the atomic interupt_occurred has been written */ 5167 smp_rmb(); 5168 if (atomic_read(&bp->interrupt_occurred)) { 5169 5170 /* what work needs to be performed? */ 5171 u16 status = bnx2x_update_dsb_idx(bp); 5172 5173 DP(BNX2X_MSG_SP, "status %x\n", status); 5174 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); 5175 atomic_set(&bp->interrupt_occurred, 0); 5176 5177 /* HW attentions */ 5178 if (status & BNX2X_DEF_SB_ATT_IDX) { 5179 bnx2x_attn_int(bp); 5180 status &= ~BNX2X_DEF_SB_ATT_IDX; 5181 } 5182 5183 /* SP events: STAT_QUERY and others */ 5184 if (status & BNX2X_DEF_SB_IDX) { 5185 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 5186 5187 if (FCOE_INIT(bp) && 5188 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 5189 /* Prevent local bottom-halves from running as 5190 * we are going to change the local NAPI list. 5191 */ 5192 local_bh_disable(); 5193 napi_schedule(&bnx2x_fcoe(bp, napi)); 5194 local_bh_enable(); 5195 } 5196 5197 /* Handle EQ completions */ 5198 bnx2x_eq_int(bp); 5199 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 5200 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 5201 5202 status &= ~BNX2X_DEF_SB_IDX; 5203 } 5204 5205 /* if status is non zero then perhaps something went wrong */ 5206 if (unlikely(status)) 5207 DP(BNX2X_MSG_SP, 5208 "got an unknown interrupt! (status 0x%x)\n", status); 5209 5210 /* ack status block only if something was actually handled */ 5211 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 5212 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 5213 5214 } 5215 5216 /* must be called after the EQ processing (since eq leads to sriov 5217 * ramrod completion flows). 5218 * This flow may have been scheduled by the arrival of a ramrod 5219 * completion, or by the sriov code rescheduling itself. 5220 */ 5221 bnx2x_iov_sp_task(bp); 5222 5223 /* afex - poll to check if VIFSET_ACK should be sent to MFW */ 5224 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, 5225 &bp->sp_state)) { 5226 bnx2x_link_report(bp); 5227 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5228 } 5229} 5230 5231irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 5232{ 5233 struct net_device *dev = dev_instance; 5234 struct bnx2x *bp = netdev_priv(dev); 5235 5236 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 5237 IGU_INT_DISABLE, 0); 5238 5239#ifdef BNX2X_STOP_ON_ERROR 5240 if (unlikely(bp->panic)) 5241 return IRQ_HANDLED; 5242#endif 5243 5244 if (CNIC_LOADED(bp)) { 5245 struct cnic_ops *c_ops; 5246 5247 rcu_read_lock(); 5248 c_ops = rcu_dereference(bp->cnic_ops); 5249 if (c_ops) 5250 c_ops->cnic_handler(bp->cnic_data, NULL); 5251 rcu_read_unlock(); 5252 } 5253 5254 /* schedule sp task to perform default status block work, ack 5255 * attentions and enable interrupts. 5256 */ 5257 bnx2x_schedule_sp_task(bp); 5258 5259 return IRQ_HANDLED; 5260} 5261 5262/* end of slow path */ 5263 5264 5265void bnx2x_drv_pulse(struct bnx2x *bp) 5266{ 5267 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 5268 bp->fw_drv_pulse_wr_seq); 5269} 5270 5271static void bnx2x_timer(unsigned long data) 5272{ 5273 struct bnx2x *bp = (struct bnx2x *) data; 5274 5275 if (!netif_running(bp->dev)) 5276 return; 5277 5278 if (IS_PF(bp) && 5279 !BP_NOMCP(bp)) { 5280 int mb_idx = BP_FW_MB_IDX(bp); 5281 u32 drv_pulse; 5282 u32 mcp_pulse; 5283 5284 ++bp->fw_drv_pulse_wr_seq; 5285 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 5286 /* TBD - add SYSTEM_TIME */ 5287 drv_pulse = bp->fw_drv_pulse_wr_seq; 5288 bnx2x_drv_pulse(bp); 5289 5290 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 5291 MCP_PULSE_SEQ_MASK); 5292 /* The delta between driver pulse and mcp response 5293 * should be 1 (before mcp response) or 0 (after mcp response) 5294 */ 5295 if ((drv_pulse != mcp_pulse) && 5296 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 5297 /* someone lost a heartbeat... */ 5298 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 5299 drv_pulse, mcp_pulse); 5300 } 5301 } 5302 5303 if (bp->state == BNX2X_STATE_OPEN) 5304 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 5305 5306 /* sample pf vf bulletin board for new posts from pf */ 5307 if (IS_VF(bp)) 5308 bnx2x_sample_bulletin(bp); 5309 5310 mod_timer(&bp->timer, jiffies + bp->current_interval); 5311} 5312 5313/* end of Statistics */ 5314 5315/* nic init */ 5316 5317/* 5318 * nic init service functions 5319 */ 5320 5321static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 5322{ 5323 u32 i; 5324 if (!(len%4) && !(addr%4)) 5325 for (i = 0; i < len; i += 4) 5326 REG_WR(bp, addr + i, fill); 5327 else 5328 for (i = 0; i < len; i++) 5329 REG_WR8(bp, addr + i, fill); 5330 5331} 5332 5333/* helper: writes FP SP data to FW - data_size in dwords */ 5334static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 5335 int fw_sb_id, 5336 u32 *sb_data_p, 5337 u32 data_size) 5338{ 5339 int index; 5340 for (index = 0; index < data_size; index++) 5341 REG_WR(bp, BAR_CSTRORM_INTMEM + 5342 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 5343 sizeof(u32)*index, 5344 *(sb_data_p + index)); 5345} 5346 5347static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 5348{ 5349 u32 *sb_data_p; 5350 u32 data_size = 0; 5351 struct hc_status_block_data_e2 sb_data_e2; 5352 struct hc_status_block_data_e1x sb_data_e1x; 5353 5354 /* disable the function first */ 5355 if (!CHIP_IS_E1x(bp)) { 5356 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5357 sb_data_e2.common.state = SB_DISABLED; 5358 sb_data_e2.common.p_func.vf_valid = false; 5359 sb_data_p = (u32 *)&sb_data_e2; 5360 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5361 } else { 5362 memset(&sb_data_e1x, 0, 5363 sizeof(struct hc_status_block_data_e1x)); 5364 sb_data_e1x.common.state = SB_DISABLED; 5365 sb_data_e1x.common.p_func.vf_valid = false; 5366 sb_data_p = (u32 *)&sb_data_e1x; 5367 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5368 } 5369 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5370 5371 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5372 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 5373 CSTORM_STATUS_BLOCK_SIZE); 5374 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5375 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 5376 CSTORM_SYNC_BLOCK_SIZE); 5377} 5378 5379/* helper: writes SP SB data to FW */ 5380static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 5381 struct hc_sp_status_block_data *sp_sb_data) 5382{ 5383 int func = BP_FUNC(bp); 5384 int i; 5385 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 5386 REG_WR(bp, BAR_CSTRORM_INTMEM + 5387 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 5388 i*sizeof(u32), 5389 *((u32 *)sp_sb_data + i)); 5390} 5391 5392static void bnx2x_zero_sp_sb(struct bnx2x *bp) 5393{ 5394 int func = BP_FUNC(bp); 5395 struct hc_sp_status_block_data sp_sb_data; 5396 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5397 5398 sp_sb_data.state = SB_DISABLED; 5399 sp_sb_data.p_func.vf_valid = false; 5400 5401 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5402 5403 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5404 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 5405 CSTORM_SP_STATUS_BLOCK_SIZE); 5406 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5407 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 5408 CSTORM_SP_SYNC_BLOCK_SIZE); 5409 5410} 5411 5412 5413static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 5414 int igu_sb_id, int igu_seg_id) 5415{ 5416 hc_sm->igu_sb_id = igu_sb_id; 5417 hc_sm->igu_seg_id = igu_seg_id; 5418 hc_sm->timer_value = 0xFF; 5419 hc_sm->time_to_expire = 0xFFFFFFFF; 5420} 5421 5422 5423/* allocates state machine ids. */ 5424static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5425{ 5426 /* zero out state machine indices */ 5427 /* rx indices */ 5428 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5429 5430 /* tx indices */ 5431 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5432 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5433 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5434 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5435 5436 /* map indices */ 5437 /* rx indices */ 5438 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5439 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5440 5441 /* tx indices */ 5442 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5443 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5444 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5445 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5446 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5447 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5448 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5449 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5450} 5451 5452void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5453 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5454{ 5455 int igu_seg_id; 5456 5457 struct hc_status_block_data_e2 sb_data_e2; 5458 struct hc_status_block_data_e1x sb_data_e1x; 5459 struct hc_status_block_sm *hc_sm_p; 5460 int data_size; 5461 u32 *sb_data_p; 5462 5463 if (CHIP_INT_MODE_IS_BC(bp)) 5464 igu_seg_id = HC_SEG_ACCESS_NORM; 5465 else 5466 igu_seg_id = IGU_SEG_ACCESS_NORM; 5467 5468 bnx2x_zero_fp_sb(bp, fw_sb_id); 5469 5470 if (!CHIP_IS_E1x(bp)) { 5471 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5472 sb_data_e2.common.state = SB_ENABLED; 5473 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5474 sb_data_e2.common.p_func.vf_id = vfid; 5475 sb_data_e2.common.p_func.vf_valid = vf_valid; 5476 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5477 sb_data_e2.common.same_igu_sb_1b = true; 5478 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5479 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5480 hc_sm_p = sb_data_e2.common.state_machine; 5481 sb_data_p = (u32 *)&sb_data_e2; 5482 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5483 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5484 } else { 5485 memset(&sb_data_e1x, 0, 5486 sizeof(struct hc_status_block_data_e1x)); 5487 sb_data_e1x.common.state = SB_ENABLED; 5488 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5489 sb_data_e1x.common.p_func.vf_id = 0xff; 5490 sb_data_e1x.common.p_func.vf_valid = false; 5491 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5492 sb_data_e1x.common.same_igu_sb_1b = true; 5493 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5494 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5495 hc_sm_p = sb_data_e1x.common.state_machine; 5496 sb_data_p = (u32 *)&sb_data_e1x; 5497 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5498 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5499 } 5500 5501 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5502 igu_sb_id, igu_seg_id); 5503 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5504 igu_sb_id, igu_seg_id); 5505 5506 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); 5507 5508 /* write indecies to HW */ 5509 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5510} 5511 5512static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5513 u16 tx_usec, u16 rx_usec) 5514{ 5515 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5516 false, rx_usec); 5517 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5518 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5519 tx_usec); 5520 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5521 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5522 tx_usec); 5523 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5524 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5525 tx_usec); 5526} 5527 5528static void bnx2x_init_def_sb(struct bnx2x *bp) 5529{ 5530 struct host_sp_status_block *def_sb = bp->def_status_blk; 5531 dma_addr_t mapping = bp->def_status_blk_mapping; 5532 int igu_sp_sb_index; 5533 int igu_seg_id; 5534 int port = BP_PORT(bp); 5535 int func = BP_FUNC(bp); 5536 int reg_offset, reg_offset_en5; 5537 u64 section; 5538 int index; 5539 struct hc_sp_status_block_data sp_sb_data; 5540 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5541 5542 if (CHIP_INT_MODE_IS_BC(bp)) { 5543 igu_sp_sb_index = DEF_SB_IGU_ID; 5544 igu_seg_id = HC_SEG_ACCESS_DEF; 5545 } else { 5546 igu_sp_sb_index = bp->igu_dsb_id; 5547 igu_seg_id = IGU_SEG_ACCESS_DEF; 5548 } 5549 5550 /* ATTN */ 5551 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5552 atten_status_block); 5553 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5554 5555 bp->attn_state = 0; 5556 5557 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5558 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5559 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5560 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5561 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5562 int sindex; 5563 /* take care of sig[0]..sig[4] */ 5564 for (sindex = 0; sindex < 4; sindex++) 5565 bp->attn_group[index].sig[sindex] = 5566 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5567 5568 if (!CHIP_IS_E1x(bp)) 5569 /* 5570 * enable5 is separate from the rest of the registers, 5571 * and therefore the address skip is 4 5572 * and not 16 between the different groups 5573 */ 5574 bp->attn_group[index].sig[4] = REG_RD(bp, 5575 reg_offset_en5 + 0x4*index); 5576 else 5577 bp->attn_group[index].sig[4] = 0; 5578 } 5579 5580 if (bp->common.int_block == INT_BLOCK_HC) { 5581 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5582 HC_REG_ATTN_MSG0_ADDR_L); 5583 5584 REG_WR(bp, reg_offset, U64_LO(section)); 5585 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5586 } else if (!CHIP_IS_E1x(bp)) { 5587 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5588 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5589 } 5590 5591 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5592 sp_sb); 5593 5594 bnx2x_zero_sp_sb(bp); 5595 5596 sp_sb_data.state = SB_ENABLED; 5597 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5598 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5599 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5600 sp_sb_data.igu_seg_id = igu_seg_id; 5601 sp_sb_data.p_func.pf_id = func; 5602 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5603 sp_sb_data.p_func.vf_id = 0xff; 5604 5605 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5606 5607 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5608} 5609 5610void bnx2x_update_coalesce(struct bnx2x *bp) 5611{ 5612 int i; 5613 5614 for_each_eth_queue(bp, i) 5615 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5616 bp->tx_ticks, bp->rx_ticks); 5617} 5618 5619static void bnx2x_init_sp_ring(struct bnx2x *bp) 5620{ 5621 spin_lock_init(&bp->spq_lock); 5622 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5623 5624 bp->spq_prod_idx = 0; 5625 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5626 bp->spq_prod_bd = bp->spq; 5627 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5628} 5629 5630static void bnx2x_init_eq_ring(struct bnx2x *bp) 5631{ 5632 int i; 5633 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5634 union event_ring_elem *elem = 5635 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5636 5637 elem->next_page.addr.hi = 5638 cpu_to_le32(U64_HI(bp->eq_mapping + 5639 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5640 elem->next_page.addr.lo = 5641 cpu_to_le32(U64_LO(bp->eq_mapping + 5642 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5643 } 5644 bp->eq_cons = 0; 5645 bp->eq_prod = NUM_EQ_DESC; 5646 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5647 /* we want a warning message before it gets rought... */ 5648 atomic_set(&bp->eq_spq_left, 5649 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5650} 5651 5652 5653/* called with netif_addr_lock_bh() */ 5654void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5655 unsigned long rx_mode_flags, 5656 unsigned long rx_accept_flags, 5657 unsigned long tx_accept_flags, 5658 unsigned long ramrod_flags) 5659{ 5660 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5661 int rc; 5662 5663 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5664 5665 /* Prepare ramrod parameters */ 5666 ramrod_param.cid = 0; 5667 ramrod_param.cl_id = cl_id; 5668 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5669 ramrod_param.func_id = BP_FUNC(bp); 5670 5671 ramrod_param.pstate = &bp->sp_state; 5672 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5673 5674 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5675 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5676 5677 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5678 5679 ramrod_param.ramrod_flags = ramrod_flags; 5680 ramrod_param.rx_mode_flags = rx_mode_flags; 5681 5682 ramrod_param.rx_accept_flags = rx_accept_flags; 5683 ramrod_param.tx_accept_flags = tx_accept_flags; 5684 5685 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5686 if (rc < 0) { 5687 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5688 return; 5689 } 5690} 5691 5692/* called with netif_addr_lock_bh() */ 5693void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5694{ 5695 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5696 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5697 5698 if (!NO_FCOE(bp)) 5699 5700 /* Configure rx_mode of FCoE Queue */ 5701 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5702 5703 switch (bp->rx_mode) { 5704 case BNX2X_RX_MODE_NONE: 5705 /* 5706 * 'drop all' supersedes any accept flags that may have been 5707 * passed to the function. 5708 */ 5709 break; 5710 case BNX2X_RX_MODE_NORMAL: 5711 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5712 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5713 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5714 5715 /* internal switching mode */ 5716 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5717 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5718 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5719 5720 break; 5721 case BNX2X_RX_MODE_ALLMULTI: 5722 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5723 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5724 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5725 5726 /* internal switching mode */ 5727 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5728 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5729 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5730 5731 break; 5732 case BNX2X_RX_MODE_PROMISC: 5733 /* According to deffinition of SI mode, iface in promisc mode 5734 * should receive matched and unmatched (in resolution of port) 5735 * unicast packets. 5736 */ 5737 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5738 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5739 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5740 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5741 5742 /* internal switching mode */ 5743 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5744 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5745 5746 if (IS_MF_SI(bp)) 5747 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5748 else 5749 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5750 5751 break; 5752 default: 5753 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5754 return; 5755 } 5756 5757 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5758 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5759 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5760 } 5761 5762 __set_bit(RAMROD_RX, &ramrod_flags); 5763 __set_bit(RAMROD_TX, &ramrod_flags); 5764 5765 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5766 tx_accept_flags, ramrod_flags); 5767} 5768 5769static void bnx2x_init_internal_common(struct bnx2x *bp) 5770{ 5771 int i; 5772 5773 if (IS_MF_SI(bp)) 5774 /* 5775 * In switch independent mode, the TSTORM needs to accept 5776 * packets that failed classification, since approximate match 5777 * mac addresses aren't written to NIG LLH 5778 */ 5779 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5780 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5781 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5782 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5783 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5784 5785 /* Zero this manually as its initialization is 5786 currently missing in the initTool */ 5787 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5788 REG_WR(bp, BAR_USTRORM_INTMEM + 5789 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5790 if (!CHIP_IS_E1x(bp)) { 5791 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5792 CHIP_INT_MODE_IS_BC(bp) ? 5793 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5794 } 5795} 5796 5797static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5798{ 5799 switch (load_code) { 5800 case FW_MSG_CODE_DRV_LOAD_COMMON: 5801 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5802 bnx2x_init_internal_common(bp); 5803 /* no break */ 5804 5805 case FW_MSG_CODE_DRV_LOAD_PORT: 5806 /* nothing to do */ 5807 /* no break */ 5808 5809 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5810 /* internal memory per function is 5811 initialized inside bnx2x_pf_init */ 5812 break; 5813 5814 default: 5815 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5816 break; 5817 } 5818} 5819 5820static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5821{ 5822 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); 5823} 5824 5825static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5826{ 5827 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); 5828} 5829 5830static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5831{ 5832 if (CHIP_IS_E1x(fp->bp)) 5833 return BP_L_ID(fp->bp) + fp->index; 5834 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5835 return bnx2x_fp_igu_sb_id(fp); 5836} 5837 5838static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5839{ 5840 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5841 u8 cos; 5842 unsigned long q_type = 0; 5843 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5844 fp->rx_queue = fp_idx; 5845 fp->cid = fp_idx; 5846 fp->cl_id = bnx2x_fp_cl_id(fp); 5847 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5848 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5849 /* qZone id equals to FW (per path) client id */ 5850 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5851 5852 /* init shortcut */ 5853 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5854 5855 /* Setup SB indicies */ 5856 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5857 5858 /* Configure Queue State object */ 5859 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5860 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5861 5862 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5863 5864 /* init tx data */ 5865 for_each_cos_in_tx_queue(fp, cos) { 5866 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], 5867 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), 5868 FP_COS_TO_TXQ(fp, cos, bp), 5869 BNX2X_TX_SB_INDEX_BASE + cos, fp); 5870 cids[cos] = fp->txdata_ptr[cos]->cid; 5871 } 5872 5873 /* nothing more for vf to do here */ 5874 if (IS_VF(bp)) 5875 return; 5876 5877 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5878 fp->fw_sb_id, fp->igu_sb_id); 5879 bnx2x_update_fpsb_idx(fp); 5880 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, 5881 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5882 bnx2x_sp_mapping(bp, q_rdata), q_type); 5883 5884 /** 5885 * Configure classification DBs: Always enable Tx switching 5886 */ 5887 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5888 5889 DP(NETIF_MSG_IFUP, 5890 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 5891 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5892 fp->igu_sb_id); 5893} 5894 5895static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) 5896{ 5897 int i; 5898 5899 for (i = 1; i <= NUM_TX_RINGS; i++) { 5900 struct eth_tx_next_bd *tx_next_bd = 5901 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 5902 5903 tx_next_bd->addr_hi = 5904 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + 5905 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 5906 tx_next_bd->addr_lo = 5907 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + 5908 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 5909 } 5910 5911 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 5912 txdata->tx_db.data.zero_fill1 = 0; 5913 txdata->tx_db.data.prod = 0; 5914 5915 txdata->tx_pkt_prod = 0; 5916 txdata->tx_pkt_cons = 0; 5917 txdata->tx_bd_prod = 0; 5918 txdata->tx_bd_cons = 0; 5919 txdata->tx_pkt = 0; 5920} 5921 5922static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) 5923{ 5924 int i; 5925 5926 for_each_tx_queue_cnic(bp, i) 5927 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); 5928} 5929static void bnx2x_init_tx_rings(struct bnx2x *bp) 5930{ 5931 int i; 5932 u8 cos; 5933 5934 for_each_eth_queue(bp, i) 5935 for_each_cos_in_tx_queue(&bp->fp[i], cos) 5936 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); 5937} 5938 5939void bnx2x_nic_init_cnic(struct bnx2x *bp) 5940{ 5941 if (!NO_FCOE(bp)) 5942 bnx2x_init_fcoe_fp(bp); 5943 5944 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5945 BNX2X_VF_ID_INVALID, false, 5946 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5947 5948 /* ensure status block indices were read */ 5949 rmb(); 5950 bnx2x_init_rx_rings_cnic(bp); 5951 bnx2x_init_tx_rings_cnic(bp); 5952 5953 /* flush all */ 5954 mb(); 5955 mmiowb(); 5956} 5957 5958void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5959{ 5960 int i; 5961 5962 for_each_eth_queue(bp, i) 5963 bnx2x_init_eth_fp(bp, i); 5964 5965 /* ensure status block indices were read */ 5966 rmb(); 5967 bnx2x_init_rx_rings(bp); 5968 bnx2x_init_tx_rings(bp); 5969 5970 if (IS_VF(bp)) 5971 return; 5972 5973 /* Initialize MOD_ABS interrupts */ 5974 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5975 bp->common.shmem_base, bp->common.shmem2_base, 5976 BP_PORT(bp)); 5977 5978 bnx2x_init_def_sb(bp); 5979 bnx2x_update_dsb_idx(bp); 5980 bnx2x_init_sp_ring(bp); 5981 bnx2x_init_eq_ring(bp); 5982 bnx2x_init_internal(bp, load_code); 5983 bnx2x_pf_init(bp); 5984 bnx2x_stats_init(bp); 5985 5986 /* flush all before enabling interrupts */ 5987 mb(); 5988 mmiowb(); 5989 5990 bnx2x_int_enable(bp); 5991 5992 /* Check for SPIO5 */ 5993 bnx2x_attn_int_deasserted0(bp, 5994 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5995 AEU_INPUTS_ATTN_BITS_SPIO5); 5996} 5997 5998/* end of nic init */ 5999 6000/* 6001 * gzip service functions 6002 */ 6003 6004static int bnx2x_gunzip_init(struct bnx2x *bp) 6005{ 6006 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 6007 &bp->gunzip_mapping, GFP_KERNEL); 6008 if (bp->gunzip_buf == NULL) 6009 goto gunzip_nomem1; 6010 6011 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 6012 if (bp->strm == NULL) 6013 goto gunzip_nomem2; 6014 6015 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 6016 if (bp->strm->workspace == NULL) 6017 goto gunzip_nomem3; 6018 6019 return 0; 6020 6021gunzip_nomem3: 6022 kfree(bp->strm); 6023 bp->strm = NULL; 6024 6025gunzip_nomem2: 6026 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6027 bp->gunzip_mapping); 6028 bp->gunzip_buf = NULL; 6029 6030gunzip_nomem1: 6031 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); 6032 return -ENOMEM; 6033} 6034 6035static void bnx2x_gunzip_end(struct bnx2x *bp) 6036{ 6037 if (bp->strm) { 6038 vfree(bp->strm->workspace); 6039 kfree(bp->strm); 6040 bp->strm = NULL; 6041 } 6042 6043 if (bp->gunzip_buf) { 6044 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6045 bp->gunzip_mapping); 6046 bp->gunzip_buf = NULL; 6047 } 6048} 6049 6050static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 6051{ 6052 int n, rc; 6053 6054 /* check gzip header */ 6055 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 6056 BNX2X_ERR("Bad gzip header\n"); 6057 return -EINVAL; 6058 } 6059 6060 n = 10; 6061 6062#define FNAME 0x8 6063 6064 if (zbuf[3] & FNAME) 6065 while ((zbuf[n++] != 0) && (n < len)); 6066 6067 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 6068 bp->strm->avail_in = len - n; 6069 bp->strm->next_out = bp->gunzip_buf; 6070 bp->strm->avail_out = FW_BUF_SIZE; 6071 6072 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 6073 if (rc != Z_OK) 6074 return rc; 6075 6076 rc = zlib_inflate(bp->strm, Z_FINISH); 6077 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 6078 netdev_err(bp->dev, "Firmware decompression error: %s\n", 6079 bp->strm->msg); 6080 6081 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 6082 if (bp->gunzip_outlen & 0x3) 6083 netdev_err(bp->dev, 6084 "Firmware decompression error: gunzip_outlen (%d) not aligned\n", 6085 bp->gunzip_outlen); 6086 bp->gunzip_outlen >>= 2; 6087 6088 zlib_inflateEnd(bp->strm); 6089 6090 if (rc == Z_STREAM_END) 6091 return 0; 6092 6093 return rc; 6094} 6095 6096/* nic load/unload */ 6097 6098/* 6099 * General service functions 6100 */ 6101 6102/* send a NIG loopback debug packet */ 6103static void bnx2x_lb_pckt(struct bnx2x *bp) 6104{ 6105 u32 wb_write[3]; 6106 6107 /* Ethernet source and destination addresses */ 6108 wb_write[0] = 0x55555555; 6109 wb_write[1] = 0x55555555; 6110 wb_write[2] = 0x20; /* SOP */ 6111 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6112 6113 /* NON-IP protocol */ 6114 wb_write[0] = 0x09000000; 6115 wb_write[1] = 0x55555555; 6116 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 6117 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6118} 6119 6120/* some of the internal memories 6121 * are not directly readable from the driver 6122 * to test them we send debug packets 6123 */ 6124static int bnx2x_int_mem_test(struct bnx2x *bp) 6125{ 6126 int factor; 6127 int count, i; 6128 u32 val = 0; 6129 6130 if (CHIP_REV_IS_FPGA(bp)) 6131 factor = 120; 6132 else if (CHIP_REV_IS_EMUL(bp)) 6133 factor = 200; 6134 else 6135 factor = 1; 6136 6137 /* Disable inputs of parser neighbor blocks */ 6138 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6139 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6140 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6141 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6142 6143 /* Write 0 to parser credits for CFC search request */ 6144 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6145 6146 /* send Ethernet packet */ 6147 bnx2x_lb_pckt(bp); 6148 6149 /* TODO do i reset NIG statistic? */ 6150 /* Wait until NIG register shows 1 packet of size 0x10 */ 6151 count = 1000 * factor; 6152 while (count) { 6153 6154 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6155 val = *bnx2x_sp(bp, wb_data[0]); 6156 if (val == 0x10) 6157 break; 6158 6159 msleep(10); 6160 count--; 6161 } 6162 if (val != 0x10) { 6163 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6164 return -1; 6165 } 6166 6167 /* Wait until PRS register shows 1 packet */ 6168 count = 1000 * factor; 6169 while (count) { 6170 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6171 if (val == 1) 6172 break; 6173 6174 msleep(10); 6175 count--; 6176 } 6177 if (val != 0x1) { 6178 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6179 return -2; 6180 } 6181 6182 /* Reset and init BRB, PRS */ 6183 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6184 msleep(50); 6185 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6186 msleep(50); 6187 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6188 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6189 6190 DP(NETIF_MSG_HW, "part2\n"); 6191 6192 /* Disable inputs of parser neighbor blocks */ 6193 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6194 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6195 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6196 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6197 6198 /* Write 0 to parser credits for CFC search request */ 6199 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6200 6201 /* send 10 Ethernet packets */ 6202 for (i = 0; i < 10; i++) 6203 bnx2x_lb_pckt(bp); 6204 6205 /* Wait until NIG register shows 10 + 1 6206 packets of size 11*0x10 = 0xb0 */ 6207 count = 1000 * factor; 6208 while (count) { 6209 6210 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6211 val = *bnx2x_sp(bp, wb_data[0]); 6212 if (val == 0xb0) 6213 break; 6214 6215 msleep(10); 6216 count--; 6217 } 6218 if (val != 0xb0) { 6219 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6220 return -3; 6221 } 6222 6223 /* Wait until PRS register shows 2 packets */ 6224 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6225 if (val != 2) 6226 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6227 6228 /* Write 1 to parser credits for CFC search request */ 6229 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 6230 6231 /* Wait until PRS register shows 3 packets */ 6232 msleep(10 * factor); 6233 /* Wait until NIG register shows 1 packet of size 0x10 */ 6234 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6235 if (val != 3) 6236 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6237 6238 /* clear NIG EOP FIFO */ 6239 for (i = 0; i < 11; i++) 6240 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 6241 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 6242 if (val != 1) { 6243 BNX2X_ERR("clear of NIG failed\n"); 6244 return -4; 6245 } 6246 6247 /* Reset and init BRB, PRS, NIG */ 6248 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6249 msleep(50); 6250 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6251 msleep(50); 6252 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6253 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6254 if (!CNIC_SUPPORT(bp)) 6255 /* set NIC mode */ 6256 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6257 6258 /* Enable inputs of parser neighbor blocks */ 6259 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 6260 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 6261 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 6262 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 6263 6264 DP(NETIF_MSG_HW, "done\n"); 6265 6266 return 0; /* OK */ 6267} 6268 6269static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 6270{ 6271 u32 val; 6272 6273 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6274 if (!CHIP_IS_E1x(bp)) 6275 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 6276 else 6277 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 6278 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6279 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6280 /* 6281 * mask read length error interrupts in brb for parser 6282 * (parsing unit and 'checksum and crc' unit) 6283 * these errors are legal (PU reads fixed length and CAC can cause 6284 * read length error on truncated packets) 6285 */ 6286 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 6287 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 6288 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 6289 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 6290 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 6291 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 6292/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 6293/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 6294 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 6295 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 6296 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 6297/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 6298/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 6299 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 6300 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 6301 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 6302 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 6303/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 6304/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 6305 6306 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 6307 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 6308 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; 6309 if (!CHIP_IS_E1x(bp)) 6310 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 6311 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; 6312 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); 6313 6314 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 6315 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 6316 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 6317/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 6318 6319 if (!CHIP_IS_E1x(bp)) 6320 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 6321 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 6322 6323 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 6324 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 6325/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 6326 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 6327} 6328 6329static void bnx2x_reset_common(struct bnx2x *bp) 6330{ 6331 u32 val = 0x1400; 6332 6333 /* reset_common */ 6334 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6335 0xd3ffff7f); 6336 6337 if (CHIP_IS_E3(bp)) { 6338 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6339 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6340 } 6341 6342 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 6343} 6344 6345static void bnx2x_setup_dmae(struct bnx2x *bp) 6346{ 6347 bp->dmae_ready = 0; 6348 spin_lock_init(&bp->dmae_lock); 6349} 6350 6351static void bnx2x_init_pxp(struct bnx2x *bp) 6352{ 6353 u16 devctl; 6354 int r_order, w_order; 6355 6356 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); 6357 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 6358 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 6359 if (bp->mrrs == -1) 6360 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 6361 else { 6362 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 6363 r_order = bp->mrrs; 6364 } 6365 6366 bnx2x_init_pxp_arb(bp, r_order, w_order); 6367} 6368 6369static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 6370{ 6371 int is_required; 6372 u32 val; 6373 int port; 6374 6375 if (BP_NOMCP(bp)) 6376 return; 6377 6378 is_required = 0; 6379 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 6380 SHARED_HW_CFG_FAN_FAILURE_MASK; 6381 6382 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 6383 is_required = 1; 6384 6385 /* 6386 * The fan failure mechanism is usually related to the PHY type since 6387 * the power consumption of the board is affected by the PHY. Currently, 6388 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 6389 */ 6390 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 6391 for (port = PORT_0; port < PORT_MAX; port++) { 6392 is_required |= 6393 bnx2x_fan_failure_det_req( 6394 bp, 6395 bp->common.shmem_base, 6396 bp->common.shmem2_base, 6397 port); 6398 } 6399 6400 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 6401 6402 if (is_required == 0) 6403 return; 6404 6405 /* Fan failure is indicated by SPIO 5 */ 6406 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); 6407 6408 /* set to active low mode */ 6409 val = REG_RD(bp, MISC_REG_SPIO_INT); 6410 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); 6411 REG_WR(bp, MISC_REG_SPIO_INT, val); 6412 6413 /* enable interrupt to signal the IGU */ 6414 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6415 val |= MISC_SPIO_SPIO5; 6416 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 6417} 6418 6419void bnx2x_pf_disable(struct bnx2x *bp) 6420{ 6421 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 6422 val &= ~IGU_PF_CONF_FUNC_EN; 6423 6424 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 6425 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6426 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 6427} 6428 6429static void bnx2x__common_init_phy(struct bnx2x *bp) 6430{ 6431 u32 shmem_base[2], shmem2_base[2]; 6432 /* Avoid common init in case MFW supports LFA */ 6433 if (SHMEM2_RD(bp, size) > 6434 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 6435 return; 6436 shmem_base[0] = bp->common.shmem_base; 6437 shmem2_base[0] = bp->common.shmem2_base; 6438 if (!CHIP_IS_E1x(bp)) { 6439 shmem_base[1] = 6440 SHMEM2_RD(bp, other_shmem_base_addr); 6441 shmem2_base[1] = 6442 SHMEM2_RD(bp, other_shmem2_base_addr); 6443 } 6444 bnx2x_acquire_phy_lock(bp); 6445 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 6446 bp->common.chip_id); 6447 bnx2x_release_phy_lock(bp); 6448} 6449 6450/** 6451 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 6452 * 6453 * @bp: driver handle 6454 */ 6455static int bnx2x_init_hw_common(struct bnx2x *bp) 6456{ 6457 u32 val; 6458 6459 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6460 6461 /* 6462 * take the UNDI lock to protect undi_unload flow from accessing 6463 * registers while we're resetting the chip 6464 */ 6465 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6466 6467 bnx2x_reset_common(bp); 6468 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6469 6470 val = 0xfffc; 6471 if (CHIP_IS_E3(bp)) { 6472 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6473 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6474 } 6475 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6476 6477 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6478 6479 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6480 6481 if (!CHIP_IS_E1x(bp)) { 6482 u8 abs_func_id; 6483 6484 /** 6485 * 4-port mode or 2-port mode we need to turn of master-enable 6486 * for everyone, after that, turn it back on for self. 6487 * so, we disregard multi-function or not, and always disable 6488 * for all functions on the given path, this means 0,2,4,6 for 6489 * path 0 and 1,3,5,7 for path 1 6490 */ 6491 for (abs_func_id = BP_PATH(bp); 6492 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6493 if (abs_func_id == BP_ABS_FUNC(bp)) { 6494 REG_WR(bp, 6495 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6496 1); 6497 continue; 6498 } 6499 6500 bnx2x_pretend_func(bp, abs_func_id); 6501 /* clear pf enable */ 6502 bnx2x_pf_disable(bp); 6503 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6504 } 6505 } 6506 6507 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6508 if (CHIP_IS_E1(bp)) { 6509 /* enable HW interrupt from PXP on USDM overflow 6510 bit 16 on INT_MASK_0 */ 6511 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6512 } 6513 6514 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6515 bnx2x_init_pxp(bp); 6516 6517#ifdef __BIG_ENDIAN 6518 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6519 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6520 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6521 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6522 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6523 /* make sure this value is 0 */ 6524 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6525 6526/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6527 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6528 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6529 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6530 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6531#endif 6532 6533 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6534 6535 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6536 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6537 6538 /* let the HW do it's magic ... */ 6539 msleep(100); 6540 /* finish PXP init */ 6541 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6542 if (val != 1) { 6543 BNX2X_ERR("PXP2 CFG failed\n"); 6544 return -EBUSY; 6545 } 6546 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6547 if (val != 1) { 6548 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6549 return -EBUSY; 6550 } 6551 6552 /* Timers bug workaround E2 only. We need to set the entire ILT to 6553 * have entries with value "0" and valid bit on. 6554 * This needs to be done by the first PF that is loaded in a path 6555 * (i.e. common phase) 6556 */ 6557 if (!CHIP_IS_E1x(bp)) { 6558/* In E2 there is a bug in the timers block that can cause function 6 / 7 6559 * (i.e. vnic3) to start even if it is marked as "scan-off". 6560 * This occurs when a different function (func2,3) is being marked 6561 * as "scan-off". Real-life scenario for example: if a driver is being 6562 * load-unloaded while func6,7 are down. This will cause the timer to access 6563 * the ilt, translate to a logical address and send a request to read/write. 6564 * Since the ilt for the function that is down is not valid, this will cause 6565 * a translation error which is unrecoverable. 6566 * The Workaround is intended to make sure that when this happens nothing fatal 6567 * will occur. The workaround: 6568 * 1. First PF driver which loads on a path will: 6569 * a. After taking the chip out of reset, by using pretend, 6570 * it will write "0" to the following registers of 6571 * the other vnics. 6572 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6573 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6574 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6575 * And for itself it will write '1' to 6576 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6577 * dmae-operations (writing to pram for example.) 6578 * note: can be done for only function 6,7 but cleaner this 6579 * way. 6580 * b. Write zero+valid to the entire ILT. 6581 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6582 * VNIC3 (of that port). The range allocated will be the 6583 * entire ILT. This is needed to prevent ILT range error. 6584 * 2. Any PF driver load flow: 6585 * a. ILT update with the physical addresses of the allocated 6586 * logical pages. 6587 * b. Wait 20msec. - note that this timeout is needed to make 6588 * sure there are no requests in one of the PXP internal 6589 * queues with "old" ILT addresses. 6590 * c. PF enable in the PGLC. 6591 * d. Clear the was_error of the PF in the PGLC. (could have 6592 * occured while driver was down) 6593 * e. PF enable in the CFC (WEAK + STRONG) 6594 * f. Timers scan enable 6595 * 3. PF driver unload flow: 6596 * a. Clear the Timers scan_en. 6597 * b. Polling for scan_on=0 for that PF. 6598 * c. Clear the PF enable bit in the PXP. 6599 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6600 * e. Write zero+valid to all ILT entries (The valid bit must 6601 * stay set) 6602 * f. If this is VNIC 3 of a port then also init 6603 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6604 * to the last enrty in the ILT. 6605 * 6606 * Notes: 6607 * Currently the PF error in the PGLC is non recoverable. 6608 * In the future the there will be a recovery routine for this error. 6609 * Currently attention is masked. 6610 * Having an MCP lock on the load/unload process does not guarantee that 6611 * there is no Timer disable during Func6/7 enable. This is because the 6612 * Timers scan is currently being cleared by the MCP on FLR. 6613 * Step 2.d can be done only for PF6/7 and the driver can also check if 6614 * there is error before clearing it. But the flow above is simpler and 6615 * more general. 6616 * All ILT entries are written by zero+valid and not just PF6/7 6617 * ILT entries since in the future the ILT entries allocation for 6618 * PF-s might be dynamic. 6619 */ 6620 struct ilt_client_info ilt_cli; 6621 struct bnx2x_ilt ilt; 6622 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6623 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6624 6625 /* initialize dummy TM client */ 6626 ilt_cli.start = 0; 6627 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6628 ilt_cli.client_num = ILT_CLIENT_TM; 6629 6630 /* Step 1: set zeroes to all ilt page entries with valid bit on 6631 * Step 2: set the timers first/last ilt entry to point 6632 * to the entire range to prevent ILT range error for 3rd/4th 6633 * vnic (this code assumes existance of the vnic) 6634 * 6635 * both steps performed by call to bnx2x_ilt_client_init_op() 6636 * with dummy TM client 6637 * 6638 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6639 * and his brother are split registers 6640 */ 6641 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6642 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6643 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6644 6645 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6646 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6647 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6648 } 6649 6650 6651 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6652 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6653 6654 if (!CHIP_IS_E1x(bp)) { 6655 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6656 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6657 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6658 6659 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6660 6661 /* let the HW do it's magic ... */ 6662 do { 6663 msleep(200); 6664 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6665 } while (factor-- && (val != 1)); 6666 6667 if (val != 1) { 6668 BNX2X_ERR("ATC_INIT failed\n"); 6669 return -EBUSY; 6670 } 6671 } 6672 6673 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6674 6675 bnx2x_iov_init_dmae(bp); 6676 6677 /* clean the DMAE memory */ 6678 bp->dmae_ready = 1; 6679 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6680 6681 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6682 6683 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6684 6685 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6686 6687 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6688 6689 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6690 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6691 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6692 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6693 6694 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6695 6696 6697 /* QM queues pointers table */ 6698 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6699 6700 /* soft reset pulse */ 6701 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6702 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6703 6704 if (CNIC_SUPPORT(bp)) 6705 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6706 6707 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6708 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6709 if (!CHIP_REV_IS_SLOW(bp)) 6710 /* enable hw interrupt from doorbell Q */ 6711 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6712 6713 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6714 6715 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6716 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6717 6718 if (!CHIP_IS_E1(bp)) 6719 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6720 6721 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { 6722 if (IS_MF_AFEX(bp)) { 6723 /* configure that VNTag and VLAN headers must be 6724 * received in afex mode 6725 */ 6726 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); 6727 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); 6728 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); 6729 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); 6730 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); 6731 } else { 6732 /* Bit-map indicating which L2 hdrs may appear 6733 * after the basic Ethernet header 6734 */ 6735 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6736 bp->path_has_ovlan ? 7 : 6); 6737 } 6738 } 6739 6740 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6741 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6742 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6743 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6744 6745 if (!CHIP_IS_E1x(bp)) { 6746 /* reset VFC memories */ 6747 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6748 VFC_MEMORIES_RST_REG_CAM_RST | 6749 VFC_MEMORIES_RST_REG_RAM_RST); 6750 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6751 VFC_MEMORIES_RST_REG_CAM_RST | 6752 VFC_MEMORIES_RST_REG_RAM_RST); 6753 6754 msleep(20); 6755 } 6756 6757 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6758 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6759 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6760 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6761 6762 /* sync semi rtc */ 6763 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6764 0x80000000); 6765 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6766 0x80000000); 6767 6768 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6769 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6770 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6771 6772 if (!CHIP_IS_E1x(bp)) { 6773 if (IS_MF_AFEX(bp)) { 6774 /* configure that VNTag and VLAN headers must be 6775 * sent in afex mode 6776 */ 6777 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); 6778 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); 6779 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); 6780 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); 6781 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); 6782 } else { 6783 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6784 bp->path_has_ovlan ? 7 : 6); 6785 } 6786 } 6787 6788 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6789 6790 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6791 6792 if (CNIC_SUPPORT(bp)) { 6793 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6794 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6795 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6796 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6797 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6798 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6799 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6800 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6801 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6802 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6803 } 6804 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6805 6806 if (sizeof(union cdu_context) != 1024) 6807 /* we currently assume that a context is 1024 bytes */ 6808 dev_alert(&bp->pdev->dev, 6809 "please adjust the size of cdu_context(%ld)\n", 6810 (long)sizeof(union cdu_context)); 6811 6812 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6813 val = (4 << 24) + (0 << 12) + 1024; 6814 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6815 6816 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6817 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6818 /* enable context validation interrupt from CFC */ 6819 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6820 6821 /* set the thresholds to prevent CFC/CDU race */ 6822 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6823 6824 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6825 6826 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6827 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6828 6829 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6830 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6831 6832 /* Reset PCIE errors for debug */ 6833 REG_WR(bp, 0x2814, 0xffffffff); 6834 REG_WR(bp, 0x3820, 0xffffffff); 6835 6836 if (!CHIP_IS_E1x(bp)) { 6837 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6838 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6839 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6840 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6841 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6842 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6843 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6844 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6845 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6846 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6847 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6848 } 6849 6850 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6851 if (!CHIP_IS_E1(bp)) { 6852 /* in E3 this done in per-port section */ 6853 if (!CHIP_IS_E3(bp)) 6854 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6855 } 6856 if (CHIP_IS_E1H(bp)) 6857 /* not applicable for E2 (and above ...) */ 6858 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6859 6860 if (CHIP_REV_IS_SLOW(bp)) 6861 msleep(200); 6862 6863 /* finish CFC init */ 6864 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6865 if (val != 1) { 6866 BNX2X_ERR("CFC LL_INIT failed\n"); 6867 return -EBUSY; 6868 } 6869 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6870 if (val != 1) { 6871 BNX2X_ERR("CFC AC_INIT failed\n"); 6872 return -EBUSY; 6873 } 6874 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6875 if (val != 1) { 6876 BNX2X_ERR("CFC CAM_INIT failed\n"); 6877 return -EBUSY; 6878 } 6879 REG_WR(bp, CFC_REG_DEBUG0, 0); 6880 6881 if (CHIP_IS_E1(bp)) { 6882 /* read NIG statistic 6883 to see if this is our first up since powerup */ 6884 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6885 val = *bnx2x_sp(bp, wb_data[0]); 6886 6887 /* do internal memory self test */ 6888 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6889 BNX2X_ERR("internal mem self test failed\n"); 6890 return -EBUSY; 6891 } 6892 } 6893 6894 bnx2x_setup_fan_failure_detection(bp); 6895 6896 /* clear PXP2 attentions */ 6897 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6898 6899 bnx2x_enable_blocks_attention(bp); 6900 bnx2x_enable_blocks_parity(bp); 6901 6902 if (!BP_NOMCP(bp)) { 6903 if (CHIP_IS_E1x(bp)) 6904 bnx2x__common_init_phy(bp); 6905 } else 6906 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6907 6908 return 0; 6909} 6910 6911/** 6912 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6913 * 6914 * @bp: driver handle 6915 */ 6916static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6917{ 6918 int rc = bnx2x_init_hw_common(bp); 6919 6920 if (rc) 6921 return rc; 6922 6923 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6924 if (!BP_NOMCP(bp)) 6925 bnx2x__common_init_phy(bp); 6926 6927 return 0; 6928} 6929 6930static int bnx2x_init_hw_port(struct bnx2x *bp) 6931{ 6932 int port = BP_PORT(bp); 6933 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6934 u32 low, high; 6935 u32 val; 6936 6937 6938 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 6939 6940 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6941 6942 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6943 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6944 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6945 6946 /* Timers bug workaround: disables the pf_master bit in pglue at 6947 * common phase, we need to enable it here before any dmae access are 6948 * attempted. Therefore we manually added the enable-master to the 6949 * port phase (it also happens in the function phase) 6950 */ 6951 if (!CHIP_IS_E1x(bp)) 6952 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6953 6954 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6955 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6956 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6957 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6958 6959 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6960 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6961 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6962 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6963 6964 /* QM cid (connection) count */ 6965 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6966 6967 if (CNIC_SUPPORT(bp)) { 6968 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6969 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6970 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6971 } 6972 6973 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6974 6975 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6976 6977 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6978 6979 if (IS_MF(bp)) 6980 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6981 else if (bp->dev->mtu > 4096) { 6982 if (bp->flags & ONE_PORT_FLAG) 6983 low = 160; 6984 else { 6985 val = bp->dev->mtu; 6986 /* (24*1024 + val*4)/256 */ 6987 low = 96 + (val/64) + 6988 ((val % 64) ? 1 : 0); 6989 } 6990 } else 6991 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6992 high = low + 56; /* 14*1024/256 */ 6993 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6994 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6995 } 6996 6997 if (CHIP_MODE_IS_4_PORT(bp)) 6998 REG_WR(bp, (BP_PORT(bp) ? 6999 BRB1_REG_MAC_GUARANTIED_1 : 7000 BRB1_REG_MAC_GUARANTIED_0), 40); 7001 7002 7003 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 7004 if (CHIP_IS_E3B0(bp)) { 7005 if (IS_MF_AFEX(bp)) { 7006 /* configure headers for AFEX mode */ 7007 REG_WR(bp, BP_PORT(bp) ? 7008 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7009 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); 7010 REG_WR(bp, BP_PORT(bp) ? 7011 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : 7012 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); 7013 REG_WR(bp, BP_PORT(bp) ? 7014 PRS_REG_MUST_HAVE_HDRS_PORT_1 : 7015 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); 7016 } else { 7017 /* Ovlan exists only if we are in multi-function + 7018 * switch-dependent mode, in switch-independent there 7019 * is no ovlan headers 7020 */ 7021 REG_WR(bp, BP_PORT(bp) ? 7022 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7023 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 7024 (bp->path_has_ovlan ? 7 : 6)); 7025 } 7026 } 7027 7028 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 7029 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 7030 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 7031 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 7032 7033 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 7034 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 7035 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 7036 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 7037 7038 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 7039 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 7040 7041 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 7042 7043 if (CHIP_IS_E1x(bp)) { 7044 /* configure PBF to work without PAUSE mtu 9000 */ 7045 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 7046 7047 /* update threshold */ 7048 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 7049 /* update init credit */ 7050 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 7051 7052 /* probe changes */ 7053 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 7054 udelay(50); 7055 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 7056 } 7057 7058 if (CNIC_SUPPORT(bp)) 7059 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 7060 7061 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 7062 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 7063 7064 if (CHIP_IS_E1(bp)) { 7065 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7066 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7067 } 7068 bnx2x_init_block(bp, BLOCK_HC, init_phase); 7069 7070 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 7071 7072 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 7073 /* init aeu_mask_attn_func_0/1: 7074 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 7075 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 7076 * bits 4-7 are used for "per vn group attention" */ 7077 val = IS_MF(bp) ? 0xF7 : 0x7; 7078 /* Enable DCBX attention for all but E1 */ 7079 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 7080 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 7081 7082 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7083 7084 if (!CHIP_IS_E1x(bp)) { 7085 /* Bit-map indicating which L2 hdrs may appear after the 7086 * basic Ethernet header 7087 */ 7088 if (IS_MF_AFEX(bp)) 7089 REG_WR(bp, BP_PORT(bp) ? 7090 NIG_REG_P1_HDRS_AFTER_BASIC : 7091 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); 7092 else 7093 REG_WR(bp, BP_PORT(bp) ? 7094 NIG_REG_P1_HDRS_AFTER_BASIC : 7095 NIG_REG_P0_HDRS_AFTER_BASIC, 7096 IS_MF_SD(bp) ? 7 : 6); 7097 7098 if (CHIP_IS_E3(bp)) 7099 REG_WR(bp, BP_PORT(bp) ? 7100 NIG_REG_LLH1_MF_MODE : 7101 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7102 } 7103 if (!CHIP_IS_E3(bp)) 7104 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 7105 7106 if (!CHIP_IS_E1(bp)) { 7107 /* 0x2 disable mf_ov, 0x1 enable */ 7108 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 7109 (IS_MF_SD(bp) ? 0x1 : 0x2)); 7110 7111 if (!CHIP_IS_E1x(bp)) { 7112 val = 0; 7113 switch (bp->mf_mode) { 7114 case MULTI_FUNCTION_SD: 7115 val = 1; 7116 break; 7117 case MULTI_FUNCTION_SI: 7118 case MULTI_FUNCTION_AFEX: 7119 val = 2; 7120 break; 7121 } 7122 7123 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 7124 NIG_REG_LLH0_CLS_TYPE), val); 7125 } 7126 { 7127 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 7128 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 7129 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 7130 } 7131 } 7132 7133 7134 /* If SPIO5 is set to generate interrupts, enable it for this port */ 7135 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 7136 if (val & MISC_SPIO_SPIO5) { 7137 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 7138 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 7139 val = REG_RD(bp, reg_addr); 7140 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 7141 REG_WR(bp, reg_addr, val); 7142 } 7143 7144 return 0; 7145} 7146 7147static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 7148{ 7149 int reg; 7150 u32 wb_write[2]; 7151 7152 if (CHIP_IS_E1(bp)) 7153 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 7154 else 7155 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 7156 7157 wb_write[0] = ONCHIP_ADDR1(addr); 7158 wb_write[1] = ONCHIP_ADDR2(addr); 7159 REG_WR_DMAE(bp, reg, wb_write, 2); 7160} 7161 7162void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) 7163{ 7164 u32 data, ctl, cnt = 100; 7165 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 7166 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 7167 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 7168 u32 sb_bit = 1 << (idu_sb_id%32); 7169 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; 7170 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 7171 7172 /* Not supported in BC mode */ 7173 if (CHIP_INT_MODE_IS_BC(bp)) 7174 return; 7175 7176 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 7177 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 7178 IGU_REGULAR_CLEANUP_SET | 7179 IGU_REGULAR_BCLEANUP; 7180 7181 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 7182 func_encode << IGU_CTRL_REG_FID_SHIFT | 7183 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 7184 7185 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7186 data, igu_addr_data); 7187 REG_WR(bp, igu_addr_data, data); 7188 mmiowb(); 7189 barrier(); 7190 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7191 ctl, igu_addr_ctl); 7192 REG_WR(bp, igu_addr_ctl, ctl); 7193 mmiowb(); 7194 barrier(); 7195 7196 /* wait for clean up to finish */ 7197 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) 7198 msleep(20); 7199 7200 7201 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { 7202 DP(NETIF_MSG_HW, 7203 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", 7204 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 7205 } 7206} 7207 7208static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 7209{ 7210 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 7211} 7212 7213static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 7214{ 7215 u32 i, base = FUNC_ILT_BASE(func); 7216 for (i = base; i < base + ILT_PER_FUNC; i++) 7217 bnx2x_ilt_wr(bp, i, 0); 7218} 7219 7220 7221static void bnx2x_init_searcher(struct bnx2x *bp) 7222{ 7223 int port = BP_PORT(bp); 7224 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 7225 /* T1 hash bits value determines the T1 number of entries */ 7226 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 7227} 7228 7229static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) 7230{ 7231 int rc; 7232 struct bnx2x_func_state_params func_params = {NULL}; 7233 struct bnx2x_func_switch_update_params *switch_update_params = 7234 &func_params.params.switch_update; 7235 7236 /* Prepare parameters for function state transitions */ 7237 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7238 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 7239 7240 func_params.f_obj = &bp->func_obj; 7241 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 7242 7243 /* Function parameters */ 7244 switch_update_params->suspend = suspend; 7245 7246 rc = bnx2x_func_state_change(bp, &func_params); 7247 7248 return rc; 7249} 7250 7251static int bnx2x_reset_nic_mode(struct bnx2x *bp) 7252{ 7253 int rc, i, port = BP_PORT(bp); 7254 int vlan_en = 0, mac_en[NUM_MACS]; 7255 7256 7257 /* Close input from network */ 7258 if (bp->mf_mode == SINGLE_FUNCTION) { 7259 bnx2x_set_rx_filter(&bp->link_params, 0); 7260 } else { 7261 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : 7262 NIG_REG_LLH0_FUNC_EN); 7263 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7264 NIG_REG_LLH0_FUNC_EN, 0); 7265 for (i = 0; i < NUM_MACS; i++) { 7266 mac_en[i] = REG_RD(bp, port ? 7267 (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7268 4 * i) : 7269 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 7270 4 * i)); 7271 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7272 4 * i) : 7273 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); 7274 } 7275 } 7276 7277 /* Close BMC to host */ 7278 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7279 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); 7280 7281 /* Suspend Tx switching to the PF. Completion of this ramrod 7282 * further guarantees that all the packets of that PF / child 7283 * VFs in BRB were processed by the Parser, so it is safe to 7284 * change the NIC_MODE register. 7285 */ 7286 rc = bnx2x_func_switch_update(bp, 1); 7287 if (rc) { 7288 BNX2X_ERR("Can't suspend tx-switching!\n"); 7289 return rc; 7290 } 7291 7292 /* Change NIC_MODE register */ 7293 REG_WR(bp, PRS_REG_NIC_MODE, 0); 7294 7295 /* Open input from network */ 7296 if (bp->mf_mode == SINGLE_FUNCTION) { 7297 bnx2x_set_rx_filter(&bp->link_params, 1); 7298 } else { 7299 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7300 NIG_REG_LLH0_FUNC_EN, vlan_en); 7301 for (i = 0; i < NUM_MACS; i++) { 7302 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7303 4 * i) : 7304 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 7305 mac_en[i]); 7306 } 7307 } 7308 7309 /* Enable BMC to host */ 7310 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7311 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); 7312 7313 /* Resume Tx switching to the PF */ 7314 rc = bnx2x_func_switch_update(bp, 0); 7315 if (rc) { 7316 BNX2X_ERR("Can't resume tx-switching!\n"); 7317 return rc; 7318 } 7319 7320 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 7321 return 0; 7322} 7323 7324int bnx2x_init_hw_func_cnic(struct bnx2x *bp) 7325{ 7326 int rc; 7327 7328 bnx2x_ilt_init_op_cnic(bp, INITOP_SET); 7329 7330 if (CONFIGURE_NIC_MODE(bp)) { 7331 /* Configrue searcher as part of function hw init */ 7332 bnx2x_init_searcher(bp); 7333 7334 /* Reset NIC mode */ 7335 rc = bnx2x_reset_nic_mode(bp); 7336 if (rc) 7337 BNX2X_ERR("Can't change NIC mode!\n"); 7338 return rc; 7339 } 7340 7341 return 0; 7342} 7343 7344static int bnx2x_init_hw_func(struct bnx2x *bp) 7345{ 7346 int port = BP_PORT(bp); 7347 int func = BP_FUNC(bp); 7348 int init_phase = PHASE_PF0 + func; 7349 struct bnx2x_ilt *ilt = BP_ILT(bp); 7350 u16 cdu_ilt_start; 7351 u32 addr, val; 7352 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 7353 int i, main_mem_width, rc; 7354 7355 DP(NETIF_MSG_HW, "starting func init func %d\n", func); 7356 7357 /* FLR cleanup - hmmm */ 7358 if (!CHIP_IS_E1x(bp)) { 7359 rc = bnx2x_pf_flr_clnup(bp); 7360 if (rc) 7361 return rc; 7362 } 7363 7364 /* set MSI reconfigure capability */ 7365 if (bp->common.int_block == INT_BLOCK_HC) { 7366 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 7367 val = REG_RD(bp, addr); 7368 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 7369 REG_WR(bp, addr, val); 7370 } 7371 7372 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7373 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7374 7375 ilt = BP_ILT(bp); 7376 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7377 7378 if (IS_SRIOV(bp)) 7379 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; 7380 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); 7381 7382 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes 7383 * those of the VFs, so start line should be reset 7384 */ 7385 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7386 for (i = 0; i < L2_ILT_LINES(bp); i++) { 7387 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; 7388 ilt->lines[cdu_ilt_start + i].page_mapping = 7389 bp->context[i].cxt_mapping; 7390 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; 7391 } 7392 7393 bnx2x_ilt_init_op(bp, INITOP_SET); 7394 7395 if (!CONFIGURE_NIC_MODE(bp)) { 7396 bnx2x_init_searcher(bp); 7397 REG_WR(bp, PRS_REG_NIC_MODE, 0); 7398 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 7399 } else { 7400 /* Set NIC mode */ 7401 REG_WR(bp, PRS_REG_NIC_MODE, 1); 7402 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n"); 7403 7404 } 7405 7406 if (!CHIP_IS_E1x(bp)) { 7407 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 7408 7409 /* Turn on a single ISR mode in IGU if driver is going to use 7410 * INT#x or MSI 7411 */ 7412 if (!(bp->flags & USING_MSIX_FLAG)) 7413 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 7414 /* 7415 * Timers workaround bug: function init part. 7416 * Need to wait 20msec after initializing ILT, 7417 * needed to make sure there are no requests in 7418 * one of the PXP internal queues with "old" ILT addresses 7419 */ 7420 msleep(20); 7421 /* 7422 * Master enable - Due to WB DMAE writes performed before this 7423 * register is re-initialized as part of the regular function 7424 * init 7425 */ 7426 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 7427 /* Enable the function in IGU */ 7428 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 7429 } 7430 7431 bp->dmae_ready = 1; 7432 7433 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 7434 7435 if (!CHIP_IS_E1x(bp)) 7436 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 7437 7438 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 7439 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 7440 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7441 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 7442 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 7443 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 7444 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 7445 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 7446 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 7447 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 7448 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 7449 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 7450 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 7451 7452 if (!CHIP_IS_E1x(bp)) 7453 REG_WR(bp, QM_REG_PF_EN, 1); 7454 7455 if (!CHIP_IS_E1x(bp)) { 7456 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 7457 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 7458 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 7459 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 7460 } 7461 bnx2x_init_block(bp, BLOCK_QM, init_phase); 7462 7463 bnx2x_init_block(bp, BLOCK_TM, init_phase); 7464 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 7465 7466 bnx2x_iov_init_dq(bp); 7467 7468 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 7469 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 7470 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 7471 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 7472 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 7473 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 7474 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 7475 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 7476 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 7477 if (!CHIP_IS_E1x(bp)) 7478 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 7479 7480 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 7481 7482 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 7483 7484 if (!CHIP_IS_E1x(bp)) 7485 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 7486 7487 if (IS_MF(bp)) { 7488 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 7489 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 7490 } 7491 7492 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 7493 7494 /* HC init per function */ 7495 if (bp->common.int_block == INT_BLOCK_HC) { 7496 if (CHIP_IS_E1H(bp)) { 7497 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 7498 7499 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7500 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7501 } 7502 bnx2x_init_block(bp, BLOCK_HC, init_phase); 7503 7504 } else { 7505 int num_segs, sb_idx, prod_offset; 7506 7507 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 7508 7509 if (!CHIP_IS_E1x(bp)) { 7510 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7511 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7512 } 7513 7514 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 7515 7516 if (!CHIP_IS_E1x(bp)) { 7517 int dsb_idx = 0; 7518 /** 7519 * Producer memory: 7520 * E2 mode: address 0-135 match to the mapping memory; 7521 * 136 - PF0 default prod; 137 - PF1 default prod; 7522 * 138 - PF2 default prod; 139 - PF3 default prod; 7523 * 140 - PF0 attn prod; 141 - PF1 attn prod; 7524 * 142 - PF2 attn prod; 143 - PF3 attn prod; 7525 * 144-147 reserved. 7526 * 7527 * E1.5 mode - In backward compatible mode; 7528 * for non default SB; each even line in the memory 7529 * holds the U producer and each odd line hold 7530 * the C producer. The first 128 producers are for 7531 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 7532 * producers are for the DSB for each PF. 7533 * Each PF has five segments: (the order inside each 7534 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 7535 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 7536 * 144-147 attn prods; 7537 */ 7538 /* non-default-status-blocks */ 7539 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 7540 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 7541 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 7542 prod_offset = (bp->igu_base_sb + sb_idx) * 7543 num_segs; 7544 7545 for (i = 0; i < num_segs; i++) { 7546 addr = IGU_REG_PROD_CONS_MEMORY + 7547 (prod_offset + i) * 4; 7548 REG_WR(bp, addr, 0); 7549 } 7550 /* send consumer update with value 0 */ 7551 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 7552 USTORM_ID, 0, IGU_INT_NOP, 1); 7553 bnx2x_igu_clear_sb(bp, 7554 bp->igu_base_sb + sb_idx); 7555 } 7556 7557 /* default-status-blocks */ 7558 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 7559 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 7560 7561 if (CHIP_MODE_IS_4_PORT(bp)) 7562 dsb_idx = BP_FUNC(bp); 7563 else 7564 dsb_idx = BP_VN(bp); 7565 7566 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 7567 IGU_BC_BASE_DSB_PROD + dsb_idx : 7568 IGU_NORM_BASE_DSB_PROD + dsb_idx); 7569 7570 /* 7571 * igu prods come in chunks of E1HVN_MAX (4) - 7572 * does not matters what is the current chip mode 7573 */ 7574 for (i = 0; i < (num_segs * E1HVN_MAX); 7575 i += E1HVN_MAX) { 7576 addr = IGU_REG_PROD_CONS_MEMORY + 7577 (prod_offset + i)*4; 7578 REG_WR(bp, addr, 0); 7579 } 7580 /* send consumer update with 0 */ 7581 if (CHIP_INT_MODE_IS_BC(bp)) { 7582 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7583 USTORM_ID, 0, IGU_INT_NOP, 1); 7584 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7585 CSTORM_ID, 0, IGU_INT_NOP, 1); 7586 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7587 XSTORM_ID, 0, IGU_INT_NOP, 1); 7588 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7589 TSTORM_ID, 0, IGU_INT_NOP, 1); 7590 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7591 ATTENTION_ID, 0, IGU_INT_NOP, 1); 7592 } else { 7593 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7594 USTORM_ID, 0, IGU_INT_NOP, 1); 7595 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7596 ATTENTION_ID, 0, IGU_INT_NOP, 1); 7597 } 7598 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 7599 7600 /* !!! these should become driver const once 7601 rf-tool supports split-68 const */ 7602 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 7603 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 7604 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 7605 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 7606 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 7607 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 7608 } 7609 } 7610 7611 /* Reset PCIE errors for debug */ 7612 REG_WR(bp, 0x2114, 0xffffffff); 7613 REG_WR(bp, 0x2120, 0xffffffff); 7614 7615 if (CHIP_IS_E1x(bp)) { 7616 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 7617 main_mem_base = HC_REG_MAIN_MEMORY + 7618 BP_PORT(bp) * (main_mem_size * 4); 7619 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 7620 main_mem_width = 8; 7621 7622 val = REG_RD(bp, main_mem_prty_clr); 7623 if (val) 7624 DP(NETIF_MSG_HW, 7625 "Hmmm... Parity errors in HC block during function init (0x%x)!\n", 7626 val); 7627 7628 /* Clear "false" parity errors in MSI-X table */ 7629 for (i = main_mem_base; 7630 i < main_mem_base + main_mem_size * 4; 7631 i += main_mem_width) { 7632 bnx2x_read_dmae(bp, i, main_mem_width / 4); 7633 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 7634 i, main_mem_width / 4); 7635 } 7636 /* Clear HC parity attention */ 7637 REG_RD(bp, main_mem_prty_clr); 7638 } 7639 7640#ifdef BNX2X_STOP_ON_ERROR 7641 /* Enable STORMs SP logging */ 7642 REG_WR8(bp, BAR_USTRORM_INTMEM + 7643 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 7644 REG_WR8(bp, BAR_TSTRORM_INTMEM + 7645 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 7646 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7647 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 7648 REG_WR8(bp, BAR_XSTRORM_INTMEM + 7649 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 7650#endif 7651 7652 bnx2x_phy_probe(&bp->link_params); 7653 7654 return 0; 7655} 7656 7657 7658void bnx2x_free_mem_cnic(struct bnx2x *bp) 7659{ 7660 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); 7661 7662 if (!CHIP_IS_E1x(bp)) 7663 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 7664 sizeof(struct host_hc_status_block_e2)); 7665 else 7666 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 7667 sizeof(struct host_hc_status_block_e1x)); 7668 7669 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7670} 7671 7672void bnx2x_free_mem(struct bnx2x *bp) 7673{ 7674 int i; 7675 7676 /* fastpath */ 7677 bnx2x_free_fp_mem(bp); 7678 /* end of fastpath */ 7679 7680 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 7681 sizeof(struct host_sp_status_block)); 7682 7683 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7684 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7685 7686 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 7687 sizeof(struct bnx2x_slowpath)); 7688 7689 for (i = 0; i < L2_ILT_LINES(bp); i++) 7690 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, 7691 bp->context[i].size); 7692 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 7693 7694 BNX2X_FREE(bp->ilt->lines); 7695 7696 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7697 7698 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7699 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7700} 7701 7702 7703int bnx2x_alloc_mem_cnic(struct bnx2x *bp) 7704{ 7705 if (!CHIP_IS_E1x(bp)) 7706 /* size = the status block + ramrod buffers */ 7707 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7708 sizeof(struct host_hc_status_block_e2)); 7709 else 7710 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, 7711 &bp->cnic_sb_mapping, 7712 sizeof(struct 7713 host_hc_status_block_e1x)); 7714 7715 if (CONFIGURE_NIC_MODE(bp)) 7716 /* allocate searcher T2 table, as it wan't allocated before */ 7717 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7718 7719 /* write address to which L5 should insert its values */ 7720 bp->cnic_eth_dev.addr_drv_info_to_mcp = 7721 &bp->slowpath->drv_info_to_mcp; 7722 7723 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) 7724 goto alloc_mem_err; 7725 7726 return 0; 7727 7728alloc_mem_err: 7729 bnx2x_free_mem_cnic(bp); 7730 BNX2X_ERR("Can't allocate memory\n"); 7731 return -ENOMEM; 7732} 7733 7734int bnx2x_alloc_mem(struct bnx2x *bp) 7735{ 7736 int i, allocated, context_size; 7737 7738 if (!CONFIGURE_NIC_MODE(bp)) 7739 /* allocate searcher T2 table */ 7740 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7741 7742 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7743 sizeof(struct host_sp_status_block)); 7744 7745 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7746 sizeof(struct bnx2x_slowpath)); 7747 7748 /* Allocate memory for CDU context: 7749 * This memory is allocated separately and not in the generic ILT 7750 * functions because CDU differs in few aspects: 7751 * 1. There are multiple entities allocating memory for context - 7752 * 'regular' driver, CNIC and SRIOV driver. Each separately controls 7753 * its own ILT lines. 7754 * 2. Since CDU page-size is not a single 4KB page (which is the case 7755 * for the other ILT clients), to be efficient we want to support 7756 * allocation of sub-page-size in the last entry. 7757 * 3. Context pointers are used by the driver to pass to FW / update 7758 * the context (for the other ILT clients the pointers are used just to 7759 * free the memory during unload). 7760 */ 7761 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7762 7763 for (i = 0, allocated = 0; allocated < context_size; i++) { 7764 bp->context[i].size = min(CDU_ILT_PAGE_SZ, 7765 (context_size - allocated)); 7766 BNX2X_PCI_ALLOC(bp->context[i].vcxt, 7767 &bp->context[i].cxt_mapping, 7768 bp->context[i].size); 7769 allocated += bp->context[i].size; 7770 } 7771 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7772 7773 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7774 goto alloc_mem_err; 7775 7776 if (bnx2x_iov_alloc_mem(bp)) 7777 goto alloc_mem_err; 7778 7779 /* Slow path ring */ 7780 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7781 7782 /* EQ */ 7783 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7784 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7785 7786 return 0; 7787 7788alloc_mem_err: 7789 bnx2x_free_mem(bp); 7790 BNX2X_ERR("Can't allocate memory\n"); 7791 return -ENOMEM; 7792} 7793 7794/* 7795 * Init service functions 7796 */ 7797 7798int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7799 struct bnx2x_vlan_mac_obj *obj, bool set, 7800 int mac_type, unsigned long *ramrod_flags) 7801{ 7802 int rc; 7803 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7804 7805 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7806 7807 /* Fill general parameters */ 7808 ramrod_param.vlan_mac_obj = obj; 7809 ramrod_param.ramrod_flags = *ramrod_flags; 7810 7811 /* Fill a user request section if needed */ 7812 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7813 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7814 7815 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7816 7817 /* Set the command: ADD or DEL */ 7818 if (set) 7819 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7820 else 7821 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7822 } 7823 7824 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7825 7826 if (rc == -EEXIST) { 7827 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); 7828 /* do not treat adding same MAC as error */ 7829 rc = 0; 7830 } else if (rc < 0) 7831 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7832 7833 return rc; 7834} 7835 7836int bnx2x_del_all_macs(struct bnx2x *bp, 7837 struct bnx2x_vlan_mac_obj *mac_obj, 7838 int mac_type, bool wait_for_comp) 7839{ 7840 int rc; 7841 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7842 7843 /* Wait for completion of requested */ 7844 if (wait_for_comp) 7845 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7846 7847 /* Set the mac type of addresses we want to clear */ 7848 __set_bit(mac_type, &vlan_mac_flags); 7849 7850 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7851 if (rc < 0) 7852 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7853 7854 return rc; 7855} 7856 7857int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7858{ 7859 unsigned long ramrod_flags = 0; 7860 7861 if (is_zero_ether_addr(bp->dev->dev_addr) && 7862 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { 7863 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, 7864 "Ignoring Zero MAC for STORAGE SD mode\n"); 7865 return 0; 7866 } 7867 7868 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7869 7870 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7871 /* Eth MAC is set on RSS leading client (fp[0]) */ 7872 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj, 7873 set, BNX2X_ETH_MAC, &ramrod_flags); 7874} 7875 7876int bnx2x_setup_leading(struct bnx2x *bp) 7877{ 7878 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7879} 7880 7881/** 7882 * bnx2x_set_int_mode - configure interrupt mode 7883 * 7884 * @bp: driver handle 7885 * 7886 * In case of MSI-X it will also try to enable MSI-X. 7887 */ 7888int bnx2x_set_int_mode(struct bnx2x *bp) 7889{ 7890 int rc = 0; 7891 7892 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) 7893 return -EINVAL; 7894 7895 switch (int_mode) { 7896 case BNX2X_INT_MODE_MSIX: 7897 /* attempt to enable msix */ 7898 rc = bnx2x_enable_msix(bp); 7899 7900 /* msix attained */ 7901 if (!rc) 7902 return 0; 7903 7904 /* vfs use only msix */ 7905 if (rc && IS_VF(bp)) 7906 return rc; 7907 7908 /* failed to enable multiple MSI-X */ 7909 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", 7910 bp->num_queues, 7911 1 + bp->num_cnic_queues); 7912 7913 /* falling through... */ 7914 case BNX2X_INT_MODE_MSI: 7915 bnx2x_enable_msi(bp); 7916 7917 /* falling through... */ 7918 case BNX2X_INT_MODE_INTX: 7919 bp->num_ethernet_queues = 1; 7920 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 7921 BNX2X_DEV_INFO("set number of queues to 1\n"); 7922 break; 7923 default: 7924 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); 7925 return -EINVAL; 7926 } 7927 return 0; 7928} 7929 7930/* must be called prior to any HW initializations */ 7931static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7932{ 7933 if (IS_SRIOV(bp)) 7934 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; 7935 return L2_ILT_LINES(bp); 7936} 7937 7938void bnx2x_ilt_set_info(struct bnx2x *bp) 7939{ 7940 struct ilt_client_info *ilt_client; 7941 struct bnx2x_ilt *ilt = BP_ILT(bp); 7942 u16 line = 0; 7943 7944 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7945 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7946 7947 /* CDU */ 7948 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7949 ilt_client->client_num = ILT_CLIENT_CDU; 7950 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7951 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7952 ilt_client->start = line; 7953 line += bnx2x_cid_ilt_lines(bp); 7954 7955 if (CNIC_SUPPORT(bp)) 7956 line += CNIC_ILT_LINES; 7957 ilt_client->end = line - 1; 7958 7959 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7960 ilt_client->start, 7961 ilt_client->end, 7962 ilt_client->page_size, 7963 ilt_client->flags, 7964 ilog2(ilt_client->page_size >> 12)); 7965 7966 /* QM */ 7967 if (QM_INIT(bp->qm_cid_count)) { 7968 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7969 ilt_client->client_num = ILT_CLIENT_QM; 7970 ilt_client->page_size = QM_ILT_PAGE_SZ; 7971 ilt_client->flags = 0; 7972 ilt_client->start = line; 7973 7974 /* 4 bytes for each cid */ 7975 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7976 QM_ILT_PAGE_SZ); 7977 7978 ilt_client->end = line - 1; 7979 7980 DP(NETIF_MSG_IFUP, 7981 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7982 ilt_client->start, 7983 ilt_client->end, 7984 ilt_client->page_size, 7985 ilt_client->flags, 7986 ilog2(ilt_client->page_size >> 12)); 7987 7988 } 7989 7990 if (CNIC_SUPPORT(bp)) { 7991 /* SRC */ 7992 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7993 ilt_client->client_num = ILT_CLIENT_SRC; 7994 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7995 ilt_client->flags = 0; 7996 ilt_client->start = line; 7997 line += SRC_ILT_LINES; 7998 ilt_client->end = line - 1; 7999 8000 DP(NETIF_MSG_IFUP, 8001 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8002 ilt_client->start, 8003 ilt_client->end, 8004 ilt_client->page_size, 8005 ilt_client->flags, 8006 ilog2(ilt_client->page_size >> 12)); 8007 8008 /* TM */ 8009 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 8010 ilt_client->client_num = ILT_CLIENT_TM; 8011 ilt_client->page_size = TM_ILT_PAGE_SZ; 8012 ilt_client->flags = 0; 8013 ilt_client->start = line; 8014 line += TM_ILT_LINES; 8015 ilt_client->end = line - 1; 8016 8017 DP(NETIF_MSG_IFUP, 8018 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8019 ilt_client->start, 8020 ilt_client->end, 8021 ilt_client->page_size, 8022 ilt_client->flags, 8023 ilog2(ilt_client->page_size >> 12)); 8024 } 8025 8026 BUG_ON(line > ILT_MAX_LINES); 8027} 8028 8029/** 8030 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 8031 * 8032 * @bp: driver handle 8033 * @fp: pointer to fastpath 8034 * @init_params: pointer to parameters structure 8035 * 8036 * parameters configured: 8037 * - HC configuration 8038 * - Queue's CDU context 8039 */ 8040static void bnx2x_pf_q_prep_init(struct bnx2x *bp, 8041 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 8042{ 8043 8044 u8 cos; 8045 int cxt_index, cxt_offset; 8046 8047 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 8048 if (!IS_FCOE_FP(fp)) { 8049 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 8050 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 8051 8052 /* If HC is supporterd, enable host coalescing in the transition 8053 * to INIT state. 8054 */ 8055 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 8056 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 8057 8058 /* HC rate */ 8059 init_params->rx.hc_rate = bp->rx_ticks ? 8060 (1000000 / bp->rx_ticks) : 0; 8061 init_params->tx.hc_rate = bp->tx_ticks ? 8062 (1000000 / bp->tx_ticks) : 0; 8063 8064 /* FW SB ID */ 8065 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 8066 fp->fw_sb_id; 8067 8068 /* 8069 * CQ index among the SB indices: FCoE clients uses the default 8070 * SB, therefore it's different. 8071 */ 8072 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 8073 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 8074 } 8075 8076 /* set maximum number of COSs supported by this queue */ 8077 init_params->max_cos = fp->max_cos; 8078 8079 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", 8080 fp->index, init_params->max_cos); 8081 8082 /* set the context pointers queue object */ 8083 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { 8084 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; 8085 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * 8086 ILT_PAGE_CIDS); 8087 init_params->cxts[cos] = 8088 &bp->context[cxt_index].vcxt[cxt_offset].eth; 8089 } 8090} 8091 8092static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8093 struct bnx2x_queue_state_params *q_params, 8094 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 8095 int tx_index, bool leading) 8096{ 8097 memset(tx_only_params, 0, sizeof(*tx_only_params)); 8098 8099 /* Set the command */ 8100 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 8101 8102 /* Set tx-only QUEUE flags: don't zero statistics */ 8103 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 8104 8105 /* choose the index of the cid to send the slow path on */ 8106 tx_only_params->cid_index = tx_index; 8107 8108 /* Set general TX_ONLY_SETUP parameters */ 8109 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 8110 8111 /* Set Tx TX_ONLY_SETUP parameters */ 8112 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 8113 8114 DP(NETIF_MSG_IFUP, 8115 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", 8116 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 8117 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 8118 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 8119 8120 /* send the ramrod */ 8121 return bnx2x_queue_state_change(bp, q_params); 8122} 8123 8124 8125/** 8126 * bnx2x_setup_queue - setup queue 8127 * 8128 * @bp: driver handle 8129 * @fp: pointer to fastpath 8130 * @leading: is leading 8131 * 8132 * This function performs 2 steps in a Queue state machine 8133 * actually: 1) RESET->INIT 2) INIT->SETUP 8134 */ 8135 8136int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8137 bool leading) 8138{ 8139 struct bnx2x_queue_state_params q_params = {NULL}; 8140 struct bnx2x_queue_setup_params *setup_params = 8141 &q_params.params.setup; 8142 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 8143 &q_params.params.tx_only; 8144 int rc; 8145 u8 tx_index; 8146 8147 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); 8148 8149 /* reset IGU state skip FCoE L2 queue */ 8150 if (!IS_FCOE_FP(fp)) 8151 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 8152 IGU_INT_ENABLE, 0); 8153 8154 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8155 /* We want to wait for completion in this context */ 8156 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8157 8158 /* Prepare the INIT parameters */ 8159 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 8160 8161 /* Set the command */ 8162 q_params.cmd = BNX2X_Q_CMD_INIT; 8163 8164 /* Change the state to INIT */ 8165 rc = bnx2x_queue_state_change(bp, &q_params); 8166 if (rc) { 8167 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 8168 return rc; 8169 } 8170 8171 DP(NETIF_MSG_IFUP, "init complete\n"); 8172 8173 8174 /* Now move the Queue to the SETUP state... */ 8175 memset(setup_params, 0, sizeof(*setup_params)); 8176 8177 /* Set QUEUE flags */ 8178 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 8179 8180 /* Set general SETUP parameters */ 8181 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 8182 FIRST_TX_COS_INDEX); 8183 8184 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 8185 &setup_params->rxq_params); 8186 8187 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 8188 FIRST_TX_COS_INDEX); 8189 8190 /* Set the command */ 8191 q_params.cmd = BNX2X_Q_CMD_SETUP; 8192 8193 if (IS_FCOE_FP(fp)) 8194 bp->fcoe_init = true; 8195 8196 /* Change the state to SETUP */ 8197 rc = bnx2x_queue_state_change(bp, &q_params); 8198 if (rc) { 8199 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 8200 return rc; 8201 } 8202 8203 /* loop through the relevant tx-only indices */ 8204 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8205 tx_index < fp->max_cos; 8206 tx_index++) { 8207 8208 /* prepare and send tx-only ramrod*/ 8209 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 8210 tx_only_params, tx_index, leading); 8211 if (rc) { 8212 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 8213 fp->index, tx_index); 8214 return rc; 8215 } 8216 } 8217 8218 return rc; 8219} 8220 8221static int bnx2x_stop_queue(struct bnx2x *bp, int index) 8222{ 8223 struct bnx2x_fastpath *fp = &bp->fp[index]; 8224 struct bnx2x_fp_txdata *txdata; 8225 struct bnx2x_queue_state_params q_params = {NULL}; 8226 int rc, tx_index; 8227 8228 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); 8229 8230 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8231 /* We want to wait for completion in this context */ 8232 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8233 8234 8235 /* close tx-only connections */ 8236 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8237 tx_index < fp->max_cos; 8238 tx_index++){ 8239 8240 /* ascertain this is a normal queue*/ 8241 txdata = fp->txdata_ptr[tx_index]; 8242 8243 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", 8244 txdata->txq_index); 8245 8246 /* send halt terminate on tx-only connection */ 8247 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8248 memset(&q_params.params.terminate, 0, 8249 sizeof(q_params.params.terminate)); 8250 q_params.params.terminate.cid_index = tx_index; 8251 8252 rc = bnx2x_queue_state_change(bp, &q_params); 8253 if (rc) 8254 return rc; 8255 8256 /* send halt terminate on tx-only connection */ 8257 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8258 memset(&q_params.params.cfc_del, 0, 8259 sizeof(q_params.params.cfc_del)); 8260 q_params.params.cfc_del.cid_index = tx_index; 8261 rc = bnx2x_queue_state_change(bp, &q_params); 8262 if (rc) 8263 return rc; 8264 } 8265 /* Stop the primary connection: */ 8266 /* ...halt the connection */ 8267 q_params.cmd = BNX2X_Q_CMD_HALT; 8268 rc = bnx2x_queue_state_change(bp, &q_params); 8269 if (rc) 8270 return rc; 8271 8272 /* ...terminate the connection */ 8273 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8274 memset(&q_params.params.terminate, 0, 8275 sizeof(q_params.params.terminate)); 8276 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 8277 rc = bnx2x_queue_state_change(bp, &q_params); 8278 if (rc) 8279 return rc; 8280 /* ...delete cfc entry */ 8281 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8282 memset(&q_params.params.cfc_del, 0, 8283 sizeof(q_params.params.cfc_del)); 8284 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 8285 return bnx2x_queue_state_change(bp, &q_params); 8286} 8287 8288 8289static void bnx2x_reset_func(struct bnx2x *bp) 8290{ 8291 int port = BP_PORT(bp); 8292 int func = BP_FUNC(bp); 8293 int i; 8294 8295 /* Disable the function in the FW */ 8296 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 8297 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 8298 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 8299 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 8300 8301 /* FP SBs */ 8302 for_each_eth_queue(bp, i) { 8303 struct bnx2x_fastpath *fp = &bp->fp[i]; 8304 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8305 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 8306 SB_DISABLED); 8307 } 8308 8309 if (CNIC_LOADED(bp)) 8310 /* CNIC SB */ 8311 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8312 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET 8313 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); 8314 8315 /* SP SB */ 8316 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8317 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 8318 SB_DISABLED); 8319 8320 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 8321 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 8322 0); 8323 8324 /* Configure IGU */ 8325 if (bp->common.int_block == INT_BLOCK_HC) { 8326 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 8327 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 8328 } else { 8329 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 8330 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 8331 } 8332 8333 if (CNIC_LOADED(bp)) { 8334 /* Disable Timer scan */ 8335 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 8336 /* 8337 * Wait for at least 10ms and up to 2 second for the timers 8338 * scan to complete 8339 */ 8340 for (i = 0; i < 200; i++) { 8341 msleep(10); 8342 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 8343 break; 8344 } 8345 } 8346 /* Clear ILT */ 8347 bnx2x_clear_func_ilt(bp, func); 8348 8349 /* Timers workaround bug for E2: if this is vnic-3, 8350 * we need to set the entire ilt range for this timers. 8351 */ 8352 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 8353 struct ilt_client_info ilt_cli; 8354 /* use dummy TM client */ 8355 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 8356 ilt_cli.start = 0; 8357 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 8358 ilt_cli.client_num = ILT_CLIENT_TM; 8359 8360 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 8361 } 8362 8363 /* this assumes that reset_port() called before reset_func()*/ 8364 if (!CHIP_IS_E1x(bp)) 8365 bnx2x_pf_disable(bp); 8366 8367 bp->dmae_ready = 0; 8368} 8369 8370static void bnx2x_reset_port(struct bnx2x *bp) 8371{ 8372 int port = BP_PORT(bp); 8373 u32 val; 8374 8375 /* Reset physical Link */ 8376 bnx2x__link_reset(bp); 8377 8378 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 8379 8380 /* Do not rcv packets to BRB */ 8381 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 8382 /* Do not direct rcv packets that are not for MCP to the BRB */ 8383 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8384 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8385 8386 /* Configure AEU */ 8387 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 8388 8389 msleep(100); 8390 /* Check for BRB port occupancy */ 8391 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 8392 if (val) 8393 DP(NETIF_MSG_IFDOWN, 8394 "BRB1 is not empty %d blocks are occupied\n", val); 8395 8396 /* TODO: Close Doorbell port? */ 8397} 8398 8399static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 8400{ 8401 struct bnx2x_func_state_params func_params = {NULL}; 8402 8403 /* Prepare parameters for function state transitions */ 8404 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 8405 8406 func_params.f_obj = &bp->func_obj; 8407 func_params.cmd = BNX2X_F_CMD_HW_RESET; 8408 8409 func_params.params.hw_init.load_phase = load_code; 8410 8411 return bnx2x_func_state_change(bp, &func_params); 8412} 8413 8414static int bnx2x_func_stop(struct bnx2x *bp) 8415{ 8416 struct bnx2x_func_state_params func_params = {NULL}; 8417 int rc; 8418 8419 /* Prepare parameters for function state transitions */ 8420 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 8421 func_params.f_obj = &bp->func_obj; 8422 func_params.cmd = BNX2X_F_CMD_STOP; 8423 8424 /* 8425 * Try to stop the function the 'good way'. If fails (in case 8426 * of a parity error during bnx2x_chip_cleanup()) and we are 8427 * not in a debug mode, perform a state transaction in order to 8428 * enable further HW_RESET transaction. 8429 */ 8430 rc = bnx2x_func_state_change(bp, &func_params); 8431 if (rc) { 8432#ifdef BNX2X_STOP_ON_ERROR 8433 return rc; 8434#else 8435 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); 8436 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 8437 return bnx2x_func_state_change(bp, &func_params); 8438#endif 8439 } 8440 8441 return 0; 8442} 8443 8444/** 8445 * bnx2x_send_unload_req - request unload mode from the MCP. 8446 * 8447 * @bp: driver handle 8448 * @unload_mode: requested function's unload mode 8449 * 8450 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 8451 */ 8452u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 8453{ 8454 u32 reset_code = 0; 8455 int port = BP_PORT(bp); 8456 8457 /* Select the UNLOAD request mode */ 8458 if (unload_mode == UNLOAD_NORMAL) 8459 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8460 8461 else if (bp->flags & NO_WOL_FLAG) 8462 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 8463 8464 else if (bp->wol) { 8465 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 8466 u8 *mac_addr = bp->dev->dev_addr; 8467 u32 val; 8468 u16 pmc; 8469 8470 /* The mac address is written to entries 1-4 to 8471 * preserve entry 0 which is used by the PMF 8472 */ 8473 u8 entry = (BP_VN(bp) + 1)*8; 8474 8475 val = (mac_addr[0] << 8) | mac_addr[1]; 8476 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 8477 8478 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 8479 (mac_addr[4] << 8) | mac_addr[5]; 8480 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 8481 8482 /* Enable the PME and clear the status */ 8483 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 8484 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 8485 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 8486 8487 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 8488 8489 } else 8490 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8491 8492 /* Send the request to the MCP */ 8493 if (!BP_NOMCP(bp)) 8494 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8495 else { 8496 int path = BP_PATH(bp); 8497 8498 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", 8499 path, load_count[path][0], load_count[path][1], 8500 load_count[path][2]); 8501 load_count[path][0]--; 8502 load_count[path][1 + port]--; 8503 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", 8504 path, load_count[path][0], load_count[path][1], 8505 load_count[path][2]); 8506 if (load_count[path][0] == 0) 8507 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 8508 else if (load_count[path][1 + port] == 0) 8509 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 8510 else 8511 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 8512 } 8513 8514 return reset_code; 8515} 8516 8517/** 8518 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 8519 * 8520 * @bp: driver handle 8521 * @keep_link: true iff link should be kept up 8522 */ 8523void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) 8524{ 8525 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; 8526 8527 /* Report UNLOAD_DONE to MCP */ 8528 if (!BP_NOMCP(bp)) 8529 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); 8530} 8531 8532static int bnx2x_func_wait_started(struct bnx2x *bp) 8533{ 8534 int tout = 50; 8535 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 8536 8537 if (!bp->port.pmf) 8538 return 0; 8539 8540 /* 8541 * (assumption: No Attention from MCP at this stage) 8542 * PMF probably in the middle of TXdisable/enable transaction 8543 * 1. Sync IRS for default SB 8544 * 2. Sync SP queue - this guarantes us that attention handling started 8545 * 3. Wait, that TXdisable/enable transaction completes 8546 * 8547 * 1+2 guranty that if DCBx attention was scheduled it already changed 8548 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 8549 * received complettion for the transaction the state is TX_STOPPED. 8550 * State will return to STARTED after completion of TX_STOPPED-->STARTED 8551 * transaction. 8552 */ 8553 8554 /* make sure default SB ISR is done */ 8555 if (msix) 8556 synchronize_irq(bp->msix_table[0].vector); 8557 else 8558 synchronize_irq(bp->pdev->irq); 8559 8560 flush_workqueue(bnx2x_wq); 8561 8562 while (bnx2x_func_get_state(bp, &bp->func_obj) != 8563 BNX2X_F_STATE_STARTED && tout--) 8564 msleep(20); 8565 8566 if (bnx2x_func_get_state(bp, &bp->func_obj) != 8567 BNX2X_F_STATE_STARTED) { 8568#ifdef BNX2X_STOP_ON_ERROR 8569 BNX2X_ERR("Wrong function state\n"); 8570 return -EBUSY; 8571#else 8572 /* 8573 * Failed to complete the transaction in a "good way" 8574 * Force both transactions with CLR bit 8575 */ 8576 struct bnx2x_func_state_params func_params = {NULL}; 8577 8578 DP(NETIF_MSG_IFDOWN, 8579 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 8580 8581 func_params.f_obj = &bp->func_obj; 8582 __set_bit(RAMROD_DRV_CLR_ONLY, 8583 &func_params.ramrod_flags); 8584 8585 /* STARTED-->TX_ST0PPED */ 8586 func_params.cmd = BNX2X_F_CMD_TX_STOP; 8587 bnx2x_func_state_change(bp, &func_params); 8588 8589 /* TX_ST0PPED-->STARTED */ 8590 func_params.cmd = BNX2X_F_CMD_TX_START; 8591 return bnx2x_func_state_change(bp, &func_params); 8592#endif 8593 } 8594 8595 return 0; 8596} 8597 8598void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) 8599{ 8600 int port = BP_PORT(bp); 8601 int i, rc = 0; 8602 u8 cos; 8603 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 8604 u32 reset_code; 8605 8606 /* Wait until tx fastpath tasks complete */ 8607 for_each_tx_queue(bp, i) { 8608 struct bnx2x_fastpath *fp = &bp->fp[i]; 8609 8610 for_each_cos_in_tx_queue(fp, cos) 8611 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); 8612#ifdef BNX2X_STOP_ON_ERROR 8613 if (rc) 8614 return; 8615#endif 8616 } 8617 8618 /* Give HW time to discard old tx messages */ 8619 usleep_range(1000, 1000); 8620 8621 /* Clean all ETH MACs */ 8622 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, 8623 false); 8624 if (rc < 0) 8625 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 8626 8627 /* Clean up UC list */ 8628 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, 8629 true); 8630 if (rc < 0) 8631 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", 8632 rc); 8633 8634 /* Disable LLH */ 8635 if (!CHIP_IS_E1(bp)) 8636 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 8637 8638 /* Set "drop all" (stop Rx). 8639 * We need to take a netif_addr_lock() here in order to prevent 8640 * a race between the completion code and this code. 8641 */ 8642 netif_addr_lock_bh(bp->dev); 8643 /* Schedule the rx_mode command */ 8644 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 8645 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 8646 else 8647 bnx2x_set_storm_rx_mode(bp); 8648 8649 /* Cleanup multicast configuration */ 8650 rparam.mcast_obj = &bp->mcast_obj; 8651 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 8652 if (rc < 0) 8653 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 8654 8655 netif_addr_unlock_bh(bp->dev); 8656 8657 bnx2x_iov_chip_cleanup(bp); 8658 8659 8660 /* 8661 * Send the UNLOAD_REQUEST to the MCP. This will return if 8662 * this function should perform FUNC, PORT or COMMON HW 8663 * reset. 8664 */ 8665 reset_code = bnx2x_send_unload_req(bp, unload_mode); 8666 8667 /* 8668 * (assumption: No Attention from MCP at this stage) 8669 * PMF probably in the middle of TXdisable/enable transaction 8670 */ 8671 rc = bnx2x_func_wait_started(bp); 8672 if (rc) { 8673 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 8674#ifdef BNX2X_STOP_ON_ERROR 8675 return; 8676#endif 8677 } 8678 8679 /* Close multi and leading connections 8680 * Completions for ramrods are collected in a synchronous way 8681 */ 8682 for_each_eth_queue(bp, i) 8683 if (bnx2x_stop_queue(bp, i)) 8684#ifdef BNX2X_STOP_ON_ERROR 8685 return; 8686#else 8687 goto unload_error; 8688#endif 8689 8690 if (CNIC_LOADED(bp)) { 8691 for_each_cnic_queue(bp, i) 8692 if (bnx2x_stop_queue(bp, i)) 8693#ifdef BNX2X_STOP_ON_ERROR 8694 return; 8695#else 8696 goto unload_error; 8697#endif 8698 } 8699 8700 /* If SP settings didn't get completed so far - something 8701 * very wrong has happen. 8702 */ 8703 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8704 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8705 8706#ifndef BNX2X_STOP_ON_ERROR 8707unload_error: 8708#endif 8709 rc = bnx2x_func_stop(bp); 8710 if (rc) { 8711 BNX2X_ERR("Function stop failed!\n"); 8712#ifdef BNX2X_STOP_ON_ERROR 8713 return; 8714#endif 8715 } 8716 8717 /* Disable HW interrupts, NAPI */ 8718 bnx2x_netif_stop(bp, 1); 8719 /* Delete all NAPI objects */ 8720 bnx2x_del_all_napi(bp); 8721 if (CNIC_LOADED(bp)) 8722 bnx2x_del_all_napi_cnic(bp); 8723 8724 /* Release IRQs */ 8725 bnx2x_free_irq(bp); 8726 8727 /* Reset the chip */ 8728 rc = bnx2x_reset_hw(bp, reset_code); 8729 if (rc) 8730 BNX2X_ERR("HW_RESET failed\n"); 8731 8732 8733 /* Report UNLOAD_DONE to MCP */ 8734 bnx2x_send_unload_done(bp, keep_link); 8735} 8736 8737void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8738{ 8739 u32 val; 8740 8741 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); 8742 8743 if (CHIP_IS_E1(bp)) { 8744 int port = BP_PORT(bp); 8745 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8746 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8747 8748 val = REG_RD(bp, addr); 8749 val &= ~(0x300); 8750 REG_WR(bp, addr, val); 8751 } else { 8752 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8753 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8754 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8755 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8756 } 8757} 8758 8759/* Close gates #2, #3 and #4: */ 8760static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8761{ 8762 u32 val; 8763 8764 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8765 if (!CHIP_IS_E1(bp)) { 8766 /* #4 */ 8767 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8768 /* #2 */ 8769 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8770 } 8771 8772 /* #3 */ 8773 if (CHIP_IS_E1x(bp)) { 8774 /* Prevent interrupts from HC on both ports */ 8775 val = REG_RD(bp, HC_REG_CONFIG_1); 8776 REG_WR(bp, HC_REG_CONFIG_1, 8777 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8778 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8779 8780 val = REG_RD(bp, HC_REG_CONFIG_0); 8781 REG_WR(bp, HC_REG_CONFIG_0, 8782 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8783 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8784 } else { 8785 /* Prevent incomming interrupts in IGU */ 8786 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8787 8788 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8789 (!close) ? 8790 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8791 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8792 } 8793 8794 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", 8795 close ? "closing" : "opening"); 8796 mmiowb(); 8797} 8798 8799#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8800 8801static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8802{ 8803 /* Do some magic... */ 8804 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8805 *magic_val = val & SHARED_MF_CLP_MAGIC; 8806 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8807} 8808 8809/** 8810 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8811 * 8812 * @bp: driver handle 8813 * @magic_val: old value of the `magic' bit. 8814 */ 8815static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8816{ 8817 /* Restore the `magic' bit value... */ 8818 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8819 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8820 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8821} 8822 8823/** 8824 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8825 * 8826 * @bp: driver handle 8827 * @magic_val: old value of 'magic' bit. 8828 * 8829 * Takes care of CLP configurations. 8830 */ 8831static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8832{ 8833 u32 shmem; 8834 u32 validity_offset; 8835 8836 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); 8837 8838 /* Set `magic' bit in order to save MF config */ 8839 if (!CHIP_IS_E1(bp)) 8840 bnx2x_clp_reset_prep(bp, magic_val); 8841 8842 /* Get shmem offset */ 8843 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8844 validity_offset = 8845 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); 8846 8847 /* Clear validity map flags */ 8848 if (shmem > 0) 8849 REG_WR(bp, shmem + validity_offset, 0); 8850} 8851 8852#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8853#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8854 8855/** 8856 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8857 * 8858 * @bp: driver handle 8859 */ 8860static void bnx2x_mcp_wait_one(struct bnx2x *bp) 8861{ 8862 /* special handling for emulation and FPGA, 8863 wait 10 times longer */ 8864 if (CHIP_REV_IS_SLOW(bp)) 8865 msleep(MCP_ONE_TIMEOUT*10); 8866 else 8867 msleep(MCP_ONE_TIMEOUT); 8868} 8869 8870/* 8871 * initializes bp->common.shmem_base and waits for validity signature to appear 8872 */ 8873static int bnx2x_init_shmem(struct bnx2x *bp) 8874{ 8875 int cnt = 0; 8876 u32 val = 0; 8877 8878 do { 8879 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8880 if (bp->common.shmem_base) { 8881 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8882 if (val & SHR_MEM_VALIDITY_MB) 8883 return 0; 8884 } 8885 8886 bnx2x_mcp_wait_one(bp); 8887 8888 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8889 8890 BNX2X_ERR("BAD MCP validity signature\n"); 8891 8892 return -ENODEV; 8893} 8894 8895static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8896{ 8897 int rc = bnx2x_init_shmem(bp); 8898 8899 /* Restore the `magic' bit value */ 8900 if (!CHIP_IS_E1(bp)) 8901 bnx2x_clp_reset_done(bp, magic_val); 8902 8903 return rc; 8904} 8905 8906static void bnx2x_pxp_prep(struct bnx2x *bp) 8907{ 8908 if (!CHIP_IS_E1(bp)) { 8909 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8910 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8911 mmiowb(); 8912 } 8913} 8914 8915/* 8916 * Reset the whole chip except for: 8917 * - PCIE core 8918 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8919 * one reset bit) 8920 * - IGU 8921 * - MISC (including AEU) 8922 * - GRC 8923 * - RBCN, RBCP 8924 */ 8925static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8926{ 8927 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8928 u32 global_bits2, stay_reset2; 8929 8930 /* 8931 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8932 * (per chip) blocks. 8933 */ 8934 global_bits2 = 8935 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8936 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8937 8938 /* Don't reset the following blocks. 8939 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be 8940 * reset, as in 4 port device they might still be owned 8941 * by the MCP (there is only one leader per path). 8942 */ 8943 not_reset_mask1 = 8944 MISC_REGISTERS_RESET_REG_1_RST_HC | 8945 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8946 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8947 8948 not_reset_mask2 = 8949 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8950 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8951 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8952 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8953 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8954 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8955 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8956 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8957 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8958 MISC_REGISTERS_RESET_REG_2_PGLC | 8959 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8960 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8961 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8962 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8963 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8964 MISC_REGISTERS_RESET_REG_2_UMAC1; 8965 8966 /* 8967 * Keep the following blocks in reset: 8968 * - all xxMACs are handled by the bnx2x_link code. 8969 */ 8970 stay_reset2 = 8971 MISC_REGISTERS_RESET_REG_2_XMAC | 8972 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8973 8974 /* Full reset masks according to the chip */ 8975 reset_mask1 = 0xffffffff; 8976 8977 if (CHIP_IS_E1(bp)) 8978 reset_mask2 = 0xffff; 8979 else if (CHIP_IS_E1H(bp)) 8980 reset_mask2 = 0x1ffff; 8981 else if (CHIP_IS_E2(bp)) 8982 reset_mask2 = 0xfffff; 8983 else /* CHIP_IS_E3 */ 8984 reset_mask2 = 0x3ffffff; 8985 8986 /* Don't reset global blocks unless we need to */ 8987 if (!global) 8988 reset_mask2 &= ~global_bits2; 8989 8990 /* 8991 * In case of attention in the QM, we need to reset PXP 8992 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8993 * because otherwise QM reset would release 'close the gates' shortly 8994 * before resetting the PXP, then the PSWRQ would send a write 8995 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8996 * read the payload data from PSWWR, but PSWWR would not 8997 * respond. The write queue in PGLUE would stuck, dmae commands 8998 * would not return. Therefore it's important to reset the second 8999 * reset register (containing the 9000 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 9001 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 9002 * bit). 9003 */ 9004 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 9005 reset_mask2 & (~not_reset_mask2)); 9006 9007 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 9008 reset_mask1 & (~not_reset_mask1)); 9009 9010 barrier(); 9011 mmiowb(); 9012 9013 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 9014 reset_mask2 & (~stay_reset2)); 9015 9016 barrier(); 9017 mmiowb(); 9018 9019 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 9020 mmiowb(); 9021} 9022 9023/** 9024 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 9025 * It should get cleared in no more than 1s. 9026 * 9027 * @bp: driver handle 9028 * 9029 * It should get cleared in no more than 1s. Returns 0 if 9030 * pending writes bit gets cleared. 9031 */ 9032static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 9033{ 9034 u32 cnt = 1000; 9035 u32 pend_bits = 0; 9036 9037 do { 9038 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 9039 9040 if (pend_bits == 0) 9041 break; 9042 9043 usleep_range(1000, 1000); 9044 } while (cnt-- > 0); 9045 9046 if (cnt <= 0) { 9047 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 9048 pend_bits); 9049 return -EBUSY; 9050 } 9051 9052 return 0; 9053} 9054 9055static int bnx2x_process_kill(struct bnx2x *bp, bool global) 9056{ 9057 int cnt = 1000; 9058 u32 val = 0; 9059 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 9060 u32 tags_63_32 = 0; 9061 9062 9063 /* Empty the Tetris buffer, wait for 1s */ 9064 do { 9065 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 9066 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 9067 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 9068 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 9069 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 9070 if (CHIP_IS_E3(bp)) 9071 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); 9072 9073 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 9074 ((port_is_idle_0 & 0x1) == 0x1) && 9075 ((port_is_idle_1 & 0x1) == 0x1) && 9076 (pgl_exp_rom2 == 0xffffffff) && 9077 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) 9078 break; 9079 usleep_range(1000, 1000); 9080 } while (cnt-- > 0); 9081 9082 if (cnt <= 0) { 9083 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); 9084 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 9085 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 9086 pgl_exp_rom2); 9087 return -EAGAIN; 9088 } 9089 9090 barrier(); 9091 9092 /* Close gates #2, #3 and #4 */ 9093 bnx2x_set_234_gates(bp, true); 9094 9095 /* Poll for IGU VQs for 57712 and newer chips */ 9096 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 9097 return -EAGAIN; 9098 9099 9100 /* TBD: Indicate that "process kill" is in progress to MCP */ 9101 9102 /* Clear "unprepared" bit */ 9103 REG_WR(bp, MISC_REG_UNPREPARED, 0); 9104 barrier(); 9105 9106 /* Make sure all is written to the chip before the reset */ 9107 mmiowb(); 9108 9109 /* Wait for 1ms to empty GLUE and PCI-E core queues, 9110 * PSWHST, GRC and PSWRD Tetris buffer. 9111 */ 9112 usleep_range(1000, 1000); 9113 9114 /* Prepare to chip reset: */ 9115 /* MCP */ 9116 if (global) 9117 bnx2x_reset_mcp_prep(bp, &val); 9118 9119 /* PXP */ 9120 bnx2x_pxp_prep(bp); 9121 barrier(); 9122 9123 /* reset the chip */ 9124 bnx2x_process_kill_chip_reset(bp, global); 9125 barrier(); 9126 9127 /* Recover after reset: */ 9128 /* MCP */ 9129 if (global && bnx2x_reset_mcp_comp(bp, val)) 9130 return -EAGAIN; 9131 9132 /* TBD: Add resetting the NO_MCP mode DB here */ 9133 9134 /* Open the gates #2, #3 and #4 */ 9135 bnx2x_set_234_gates(bp, false); 9136 9137 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 9138 * reset state, re-enable attentions. */ 9139 9140 return 0; 9141} 9142 9143static int bnx2x_leader_reset(struct bnx2x *bp) 9144{ 9145 int rc = 0; 9146 bool global = bnx2x_reset_is_global(bp); 9147 u32 load_code; 9148 9149 /* if not going to reset MCP - load "fake" driver to reset HW while 9150 * driver is owner of the HW 9151 */ 9152 if (!global && !BP_NOMCP(bp)) { 9153 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 9154 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 9155 if (!load_code) { 9156 BNX2X_ERR("MCP response failure, aborting\n"); 9157 rc = -EAGAIN; 9158 goto exit_leader_reset; 9159 } 9160 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 9161 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 9162 BNX2X_ERR("MCP unexpected resp, aborting\n"); 9163 rc = -EAGAIN; 9164 goto exit_leader_reset2; 9165 } 9166 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 9167 if (!load_code) { 9168 BNX2X_ERR("MCP response failure, aborting\n"); 9169 rc = -EAGAIN; 9170 goto exit_leader_reset2; 9171 } 9172 } 9173 9174 /* Try to recover after the failure */ 9175 if (bnx2x_process_kill(bp, global)) { 9176 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", 9177 BP_PATH(bp)); 9178 rc = -EAGAIN; 9179 goto exit_leader_reset2; 9180 } 9181 9182 /* 9183 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 9184 * state. 9185 */ 9186 bnx2x_set_reset_done(bp); 9187 if (global) 9188 bnx2x_clear_reset_global(bp); 9189 9190exit_leader_reset2: 9191 /* unload "fake driver" if it was loaded */ 9192 if (!global && !BP_NOMCP(bp)) { 9193 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 9194 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 9195 } 9196exit_leader_reset: 9197 bp->is_leader = 0; 9198 bnx2x_release_leader_lock(bp); 9199 smp_mb(); 9200 return rc; 9201} 9202 9203static void bnx2x_recovery_failed(struct bnx2x *bp) 9204{ 9205 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 9206 9207 /* Disconnect this device */ 9208 netif_device_detach(bp->dev); 9209 9210 /* 9211 * Block ifup for all function on this engine until "process kill" 9212 * or power cycle. 9213 */ 9214 bnx2x_set_reset_in_progress(bp); 9215 9216 /* Shut down the power */ 9217 bnx2x_set_power_state(bp, PCI_D3hot); 9218 9219 bp->recovery_state = BNX2X_RECOVERY_FAILED; 9220 9221 smp_mb(); 9222} 9223 9224/* 9225 * Assumption: runs under rtnl lock. This together with the fact 9226 * that it's called only from bnx2x_sp_rtnl() ensure that it 9227 * will never be called when netif_running(bp->dev) is false. 9228 */ 9229static void bnx2x_parity_recover(struct bnx2x *bp) 9230{ 9231 bool global = false; 9232 u32 error_recovered, error_unrecovered; 9233 bool is_parity; 9234 9235 DP(NETIF_MSG_HW, "Handling parity\n"); 9236 while (1) { 9237 switch (bp->recovery_state) { 9238 case BNX2X_RECOVERY_INIT: 9239 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 9240 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 9241 WARN_ON(!is_parity); 9242 9243 /* Try to get a LEADER_LOCK HW lock */ 9244 if (bnx2x_trylock_leader_lock(bp)) { 9245 bnx2x_set_reset_in_progress(bp); 9246 /* 9247 * Check if there is a global attention and if 9248 * there was a global attention, set the global 9249 * reset bit. 9250 */ 9251 9252 if (global) 9253 bnx2x_set_reset_global(bp); 9254 9255 bp->is_leader = 1; 9256 } 9257 9258 /* Stop the driver */ 9259 /* If interface has been removed - break */ 9260 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) 9261 return; 9262 9263 bp->recovery_state = BNX2X_RECOVERY_WAIT; 9264 9265 /* Ensure "is_leader", MCP command sequence and 9266 * "recovery_state" update values are seen on other 9267 * CPUs. 9268 */ 9269 smp_mb(); 9270 break; 9271 9272 case BNX2X_RECOVERY_WAIT: 9273 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 9274 if (bp->is_leader) { 9275 int other_engine = BP_PATH(bp) ? 0 : 1; 9276 bool other_load_status = 9277 bnx2x_get_load_status(bp, other_engine); 9278 bool load_status = 9279 bnx2x_get_load_status(bp, BP_PATH(bp)); 9280 global = bnx2x_reset_is_global(bp); 9281 9282 /* 9283 * In case of a parity in a global block, let 9284 * the first leader that performs a 9285 * leader_reset() reset the global blocks in 9286 * order to clear global attentions. Otherwise 9287 * the the gates will remain closed for that 9288 * engine. 9289 */ 9290 if (load_status || 9291 (global && other_load_status)) { 9292 /* Wait until all other functions get 9293 * down. 9294 */ 9295 schedule_delayed_work(&bp->sp_rtnl_task, 9296 HZ/10); 9297 return; 9298 } else { 9299 /* If all other functions got down - 9300 * try to bring the chip back to 9301 * normal. In any case it's an exit 9302 * point for a leader. 9303 */ 9304 if (bnx2x_leader_reset(bp)) { 9305 bnx2x_recovery_failed(bp); 9306 return; 9307 } 9308 9309 /* If we are here, means that the 9310 * leader has succeeded and doesn't 9311 * want to be a leader any more. Try 9312 * to continue as a none-leader. 9313 */ 9314 break; 9315 } 9316 } else { /* non-leader */ 9317 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 9318 /* Try to get a LEADER_LOCK HW lock as 9319 * long as a former leader may have 9320 * been unloaded by the user or 9321 * released a leadership by another 9322 * reason. 9323 */ 9324 if (bnx2x_trylock_leader_lock(bp)) { 9325 /* I'm a leader now! Restart a 9326 * switch case. 9327 */ 9328 bp->is_leader = 1; 9329 break; 9330 } 9331 9332 schedule_delayed_work(&bp->sp_rtnl_task, 9333 HZ/10); 9334 return; 9335 9336 } else { 9337 /* 9338 * If there was a global attention, wait 9339 * for it to be cleared. 9340 */ 9341 if (bnx2x_reset_is_global(bp)) { 9342 schedule_delayed_work( 9343 &bp->sp_rtnl_task, 9344 HZ/10); 9345 return; 9346 } 9347 9348 error_recovered = 9349 bp->eth_stats.recoverable_error; 9350 error_unrecovered = 9351 bp->eth_stats.unrecoverable_error; 9352 bp->recovery_state = 9353 BNX2X_RECOVERY_NIC_LOADING; 9354 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 9355 error_unrecovered++; 9356 netdev_err(bp->dev, 9357 "Recovery failed. Power cycle needed\n"); 9358 /* Disconnect this device */ 9359 netif_device_detach(bp->dev); 9360 /* Shut down the power */ 9361 bnx2x_set_power_state( 9362 bp, PCI_D3hot); 9363 smp_mb(); 9364 } else { 9365 bp->recovery_state = 9366 BNX2X_RECOVERY_DONE; 9367 error_recovered++; 9368 smp_mb(); 9369 } 9370 bp->eth_stats.recoverable_error = 9371 error_recovered; 9372 bp->eth_stats.unrecoverable_error = 9373 error_unrecovered; 9374 9375 return; 9376 } 9377 } 9378 default: 9379 return; 9380 } 9381 } 9382} 9383 9384static int bnx2x_close(struct net_device *dev); 9385 9386/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 9387 * scheduled on a general queue in order to prevent a dead lock. 9388 */ 9389static void bnx2x_sp_rtnl_task(struct work_struct *work) 9390{ 9391 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 9392 9393 rtnl_lock(); 9394 9395 if (!netif_running(bp->dev)) { 9396 rtnl_unlock(); 9397 return; 9398 } 9399 9400 /* if stop on error is defined no recovery flows should be executed */ 9401#ifdef BNX2X_STOP_ON_ERROR 9402 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 9403 "you will need to reboot when done\n"); 9404 goto sp_rtnl_not_reset; 9405#endif 9406 9407 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 9408 /* 9409 * Clear all pending SP commands as we are going to reset the 9410 * function anyway. 9411 */ 9412 bp->sp_rtnl_state = 0; 9413 smp_mb(); 9414 9415 bnx2x_parity_recover(bp); 9416 9417 rtnl_unlock(); 9418 return; 9419 } 9420 9421 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 9422 /* 9423 * Clear all pending SP commands as we are going to reset the 9424 * function anyway. 9425 */ 9426 bp->sp_rtnl_state = 0; 9427 smp_mb(); 9428 9429 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 9430 bnx2x_nic_load(bp, LOAD_NORMAL); 9431 9432 rtnl_unlock(); 9433 return; 9434 } 9435#ifdef BNX2X_STOP_ON_ERROR 9436sp_rtnl_not_reset: 9437#endif 9438 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 9439 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 9440 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) 9441 bnx2x_after_function_update(bp); 9442 /* 9443 * in case of fan failure we need to reset id if the "stop on error" 9444 * debug flag is set, since we trying to prevent permanent overheating 9445 * damage 9446 */ 9447 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 9448 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); 9449 netif_device_detach(bp->dev); 9450 bnx2x_close(bp->dev); 9451 rtnl_unlock(); 9452 return; 9453 } 9454 9455 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { 9456 DP(BNX2X_MSG_SP, 9457 "sending set mcast vf pf channel message from rtnl sp-task\n"); 9458 bnx2x_vfpf_set_mcast(bp->dev); 9459 } 9460 9461 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, 9462 &bp->sp_rtnl_state)) { 9463 DP(BNX2X_MSG_SP, 9464 "sending set storm rx mode vf pf channel message from rtnl sp-task\n"); 9465 bnx2x_vfpf_storm_rx_mode(bp); 9466 } 9467 9468 /* work which needs rtnl lock not-taken (as it takes the lock itself and 9469 * can be called from other contexts as well) 9470 */ 9471 rtnl_unlock(); 9472 9473 /* enable SR-IOV if applicable */ 9474 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, 9475 &bp->sp_rtnl_state)) 9476 bnx2x_enable_sriov(bp); 9477} 9478 9479static void bnx2x_period_task(struct work_struct *work) 9480{ 9481 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 9482 9483 if (!netif_running(bp->dev)) 9484 goto period_task_exit; 9485 9486 if (CHIP_REV_IS_SLOW(bp)) { 9487 BNX2X_ERR("period task called on emulation, ignoring\n"); 9488 goto period_task_exit; 9489 } 9490 9491 bnx2x_acquire_phy_lock(bp); 9492 /* 9493 * The barrier is needed to ensure the ordering between the writing to 9494 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 9495 * the reading here. 9496 */ 9497 smp_mb(); 9498 if (bp->port.pmf) { 9499 bnx2x_period_func(&bp->link_params, &bp->link_vars); 9500 9501 /* Re-queue task in 1 sec */ 9502 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 9503 } 9504 9505 bnx2x_release_phy_lock(bp); 9506period_task_exit: 9507 return; 9508} 9509 9510/* 9511 * Init service functions 9512 */ 9513 9514u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 9515{ 9516 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 9517 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 9518 return base + (BP_ABS_FUNC(bp)) * stride; 9519} 9520 9521static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 9522{ 9523 u32 reg = bnx2x_get_pretend_reg(bp); 9524 9525 /* Flush all outstanding writes */ 9526 mmiowb(); 9527 9528 /* Pretend to be function 0 */ 9529 REG_WR(bp, reg, 0); 9530 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 9531 9532 /* From now we are in the "like-E1" mode */ 9533 bnx2x_int_disable(bp); 9534 9535 /* Flush all outstanding writes */ 9536 mmiowb(); 9537 9538 /* Restore the original function */ 9539 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 9540 REG_RD(bp, reg); 9541} 9542 9543static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 9544{ 9545 if (CHIP_IS_E1(bp)) 9546 bnx2x_int_disable(bp); 9547 else 9548 bnx2x_undi_int_disable_e1h(bp); 9549} 9550 9551static void bnx2x_prev_unload_close_mac(struct bnx2x *bp) 9552{ 9553 u32 val, base_addr, offset, mask, reset_reg; 9554 bool mac_stopped = false; 9555 u8 port = BP_PORT(bp); 9556 9557 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); 9558 9559 if (!CHIP_IS_E3(bp)) { 9560 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 9561 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 9562 if ((mask & reset_reg) && val) { 9563 u32 wb_data[2]; 9564 BNX2X_DEV_INFO("Disable bmac Rx\n"); 9565 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM 9566 : NIG_REG_INGRESS_BMAC0_MEM; 9567 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL 9568 : BIGMAC_REGISTER_BMAC_CONTROL; 9569 9570 /* 9571 * use rd/wr since we cannot use dmae. This is safe 9572 * since MCP won't access the bus due to the request 9573 * to unload, and no function on the path can be 9574 * loaded at this time. 9575 */ 9576 wb_data[0] = REG_RD(bp, base_addr + offset); 9577 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); 9578 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 9579 REG_WR(bp, base_addr + offset, wb_data[0]); 9580 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]); 9581 9582 } 9583 BNX2X_DEV_INFO("Disable emac Rx\n"); 9584 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0); 9585 9586 mac_stopped = true; 9587 } else { 9588 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 9589 BNX2X_DEV_INFO("Disable xmac Rx\n"); 9590 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 9591 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); 9592 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 9593 val & ~(1 << 1)); 9594 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 9595 val | (1 << 1)); 9596 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0); 9597 mac_stopped = true; 9598 } 9599 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 9600 if (mask & reset_reg) { 9601 BNX2X_DEV_INFO("Disable umac Rx\n"); 9602 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 9603 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0); 9604 mac_stopped = true; 9605 } 9606 } 9607 9608 if (mac_stopped) 9609 msleep(20); 9610 9611} 9612 9613#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 9614#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) 9615#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 9616#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 9617 9618static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc) 9619{ 9620 u16 rcq, bd; 9621 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); 9622 9623 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; 9624 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; 9625 9626 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); 9627 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); 9628 9629 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", 9630 port, bd, rcq); 9631} 9632 9633static int bnx2x_prev_mcp_done(struct bnx2x *bp) 9634{ 9635 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 9636 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); 9637 if (!rc) { 9638 BNX2X_ERR("MCP response failure, aborting\n"); 9639 return -EBUSY; 9640 } 9641 9642 return 0; 9643} 9644 9645static struct bnx2x_prev_path_list * 9646 bnx2x_prev_path_get_entry(struct bnx2x *bp) 9647{ 9648 struct bnx2x_prev_path_list *tmp_list; 9649 9650 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) 9651 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && 9652 bp->pdev->bus->number == tmp_list->bus && 9653 BP_PATH(bp) == tmp_list->path) 9654 return tmp_list; 9655 9656 return NULL; 9657} 9658 9659static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) 9660{ 9661 struct bnx2x_prev_path_list *tmp_list; 9662 int rc = false; 9663 9664 if (down_trylock(&bnx2x_prev_sem)) 9665 return false; 9666 9667 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { 9668 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && 9669 bp->pdev->bus->number == tmp_list->bus && 9670 BP_PATH(bp) == tmp_list->path) { 9671 rc = true; 9672 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", 9673 BP_PATH(bp)); 9674 break; 9675 } 9676 } 9677 9678 up(&bnx2x_prev_sem); 9679 9680 return rc; 9681} 9682 9683static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) 9684{ 9685 struct bnx2x_prev_path_list *tmp_list; 9686 int rc; 9687 9688 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); 9689 if (!tmp_list) { 9690 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); 9691 return -ENOMEM; 9692 } 9693 9694 tmp_list->bus = bp->pdev->bus->number; 9695 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); 9696 tmp_list->path = BP_PATH(bp); 9697 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; 9698 9699 rc = down_interruptible(&bnx2x_prev_sem); 9700 if (rc) { 9701 BNX2X_ERR("Received %d when tried to take lock\n", rc); 9702 kfree(tmp_list); 9703 } else { 9704 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", 9705 BP_PATH(bp)); 9706 list_add(&tmp_list->list, &bnx2x_prev_list); 9707 up(&bnx2x_prev_sem); 9708 } 9709 9710 return rc; 9711} 9712 9713static int bnx2x_do_flr(struct bnx2x *bp) 9714{ 9715 int i; 9716 u16 status; 9717 struct pci_dev *dev = bp->pdev; 9718 9719 9720 if (CHIP_IS_E1x(bp)) { 9721 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); 9722 return -EINVAL; 9723 } 9724 9725 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ 9726 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 9727 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", 9728 bp->common.bc_ver); 9729 return -EINVAL; 9730 } 9731 9732 /* Wait for Transaction Pending bit clean */ 9733 for (i = 0; i < 4; i++) { 9734 if (i) 9735 msleep((1 << (i - 1)) * 100); 9736 9737 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 9738 if (!(status & PCI_EXP_DEVSTA_TRPND)) 9739 goto clear; 9740 } 9741 9742 dev_err(&dev->dev, 9743 "transaction is not cleared; proceeding with reset anyway\n"); 9744 9745clear: 9746 9747 BNX2X_DEV_INFO("Initiating FLR\n"); 9748 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); 9749 9750 return 0; 9751} 9752 9753static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) 9754{ 9755 int rc; 9756 9757 BNX2X_DEV_INFO("Uncommon unload Flow\n"); 9758 9759 /* Test if previous unload process was already finished for this path */ 9760 if (bnx2x_prev_is_path_marked(bp)) 9761 return bnx2x_prev_mcp_done(bp); 9762 9763 /* If function has FLR capabilities, and existing FW version matches 9764 * the one required, then FLR will be sufficient to clean any residue 9765 * left by previous driver 9766 */ 9767 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION); 9768 9769 if (!rc) { 9770 /* fw version is good */ 9771 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); 9772 rc = bnx2x_do_flr(bp); 9773 } 9774 9775 if (!rc) { 9776 /* FLR was performed */ 9777 BNX2X_DEV_INFO("FLR successful\n"); 9778 return 0; 9779 } 9780 9781 BNX2X_DEV_INFO("Could not FLR\n"); 9782 9783 /* Close the MCP request, return failure*/ 9784 rc = bnx2x_prev_mcp_done(bp); 9785 if (!rc) 9786 rc = BNX2X_PREV_WAIT_NEEDED; 9787 9788 return rc; 9789} 9790 9791static int bnx2x_prev_unload_common(struct bnx2x *bp) 9792{ 9793 u32 reset_reg, tmp_reg = 0, rc; 9794 bool prev_undi = false; 9795 /* It is possible a previous function received 'common' answer, 9796 * but hasn't loaded yet, therefore creating a scenario of 9797 * multiple functions receiving 'common' on the same path. 9798 */ 9799 BNX2X_DEV_INFO("Common unload Flow\n"); 9800 9801 if (bnx2x_prev_is_path_marked(bp)) 9802 return bnx2x_prev_mcp_done(bp); 9803 9804 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); 9805 9806 /* Reset should be performed after BRB is emptied */ 9807 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 9808 u32 timer_count = 1000; 9809 9810 /* Close the MAC Rx to prevent BRB from filling up */ 9811 bnx2x_prev_unload_close_mac(bp); 9812 9813 /* Check if the UNDI driver was previously loaded 9814 * UNDI driver initializes CID offset for normal bell to 0x7 9815 */ 9816 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); 9817 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 9818 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 9819 if (tmp_reg == 0x7) { 9820 BNX2X_DEV_INFO("UNDI previously loaded\n"); 9821 prev_undi = true; 9822 /* clear the UNDI indication */ 9823 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 9824 } 9825 } 9826 /* wait until BRB is empty */ 9827 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 9828 while (timer_count) { 9829 u32 prev_brb = tmp_reg; 9830 9831 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 9832 if (!tmp_reg) 9833 break; 9834 9835 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); 9836 9837 /* reset timer as long as BRB actually gets emptied */ 9838 if (prev_brb > tmp_reg) 9839 timer_count = 1000; 9840 else 9841 timer_count--; 9842 9843 /* If UNDI resides in memory, manually increment it */ 9844 if (prev_undi) 9845 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); 9846 9847 udelay(10); 9848 } 9849 9850 if (!timer_count) 9851 BNX2X_ERR("Failed to empty BRB, hope for the best\n"); 9852 9853 } 9854 9855 /* No packets are in the pipeline, path is ready for reset */ 9856 bnx2x_reset_common(bp); 9857 9858 rc = bnx2x_prev_mark_path(bp, prev_undi); 9859 if (rc) { 9860 bnx2x_prev_mcp_done(bp); 9861 return rc; 9862 } 9863 9864 return bnx2x_prev_mcp_done(bp); 9865} 9866 9867/* previous driver DMAE transaction may have occurred when pre-boot stage ended 9868 * and boot began, or when kdump kernel was loaded. Either case would invalidate 9869 * the addresses of the transaction, resulting in was-error bit set in the pci 9870 * causing all hw-to-host pcie transactions to timeout. If this happened we want 9871 * to clear the interrupt which detected this from the pglueb and the was done 9872 * bit 9873 */ 9874static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp) 9875{ 9876 if (!CHIP_IS_E1x(bp)) { 9877 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); 9878 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { 9879 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing"); 9880 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 9881 1 << BP_FUNC(bp)); 9882 } 9883 } 9884} 9885 9886static int bnx2x_prev_unload(struct bnx2x *bp) 9887{ 9888 int time_counter = 10; 9889 u32 rc, fw, hw_lock_reg, hw_lock_val; 9890 struct bnx2x_prev_path_list *prev_list; 9891 BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); 9892 9893 /* clear hw from errors which may have resulted from an interrupted 9894 * dmae transaction. 9895 */ 9896 bnx2x_prev_interrupted_dmae(bp); 9897 9898 /* Release previously held locks */ 9899 hw_lock_reg = (BP_FUNC(bp) <= 5) ? 9900 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : 9901 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); 9902 9903 hw_lock_val = (REG_RD(bp, hw_lock_reg)); 9904 if (hw_lock_val) { 9905 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 9906 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); 9907 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 9908 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); 9909 } 9910 9911 BNX2X_DEV_INFO("Release Previously held hw lock\n"); 9912 REG_WR(bp, hw_lock_reg, 0xffffffff); 9913 } else 9914 BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); 9915 9916 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { 9917 BNX2X_DEV_INFO("Release previously held alr\n"); 9918 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); 9919 } 9920 9921 9922 do { 9923 /* Lock MCP using an unload request */ 9924 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 9925 if (!fw) { 9926 BNX2X_ERR("MCP response failure, aborting\n"); 9927 rc = -EBUSY; 9928 break; 9929 } 9930 9931 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { 9932 rc = bnx2x_prev_unload_common(bp); 9933 break; 9934 } 9935 9936 /* non-common reply from MCP night require looping */ 9937 rc = bnx2x_prev_unload_uncommon(bp); 9938 if (rc != BNX2X_PREV_WAIT_NEEDED) 9939 break; 9940 9941 msleep(20); 9942 } while (--time_counter); 9943 9944 if (!time_counter || rc) { 9945 BNX2X_ERR("Failed unloading previous driver, aborting\n"); 9946 rc = -EBUSY; 9947 } 9948 9949 /* Mark function if its port was used to boot from SAN */ 9950 prev_list = bnx2x_prev_path_get_entry(bp); 9951 if (prev_list && (prev_list->undi & (1 << BP_PORT(bp)))) 9952 bp->link_params.feature_config_flags |= 9953 FEATURE_CONFIG_BOOT_FROM_SAN; 9954 9955 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); 9956 9957 return rc; 9958} 9959 9960static void bnx2x_get_common_hwinfo(struct bnx2x *bp) 9961{ 9962 u32 val, val2, val3, val4, id, boot_mode; 9963 u16 pmc; 9964 9965 /* Get the chip revision id and number. */ 9966 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 9967 val = REG_RD(bp, MISC_REG_CHIP_NUM); 9968 id = ((val & 0xffff) << 16); 9969 val = REG_RD(bp, MISC_REG_CHIP_REV); 9970 id |= ((val & 0xf) << 12); 9971 val = REG_RD(bp, MISC_REG_CHIP_METAL); 9972 id |= ((val & 0xff) << 4); 9973 val = REG_RD(bp, MISC_REG_BOND_ID); 9974 id |= (val & 0xf); 9975 bp->common.chip_id = id; 9976 9977 /* force 57811 according to MISC register */ 9978 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { 9979 if (CHIP_IS_57810(bp)) 9980 bp->common.chip_id = (CHIP_NUM_57811 << 16) | 9981 (bp->common.chip_id & 0x0000FFFF); 9982 else if (CHIP_IS_57810_MF(bp)) 9983 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | 9984 (bp->common.chip_id & 0x0000FFFF); 9985 bp->common.chip_id |= 0x1; 9986 } 9987 9988 /* Set doorbell size */ 9989 bp->db_size = (1 << BNX2X_DB_SHIFT); 9990 9991 if (!CHIP_IS_E1x(bp)) { 9992 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 9993 if ((val & 1) == 0) 9994 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 9995 else 9996 val = (val >> 1) & 1; 9997 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 9998 "2_PORT_MODE"); 9999 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 10000 CHIP_2_PORT_MODE; 10001 10002 if (CHIP_MODE_IS_4_PORT(bp)) 10003 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 10004 else 10005 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 10006 } else { 10007 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 10008 bp->pfid = bp->pf_num; /* 0..7 */ 10009 } 10010 10011 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); 10012 10013 bp->link_params.chip_id = bp->common.chip_id; 10014 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 10015 10016 val = (REG_RD(bp, 0x2874) & 0x55); 10017 if ((bp->common.chip_id & 0x1) || 10018 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 10019 bp->flags |= ONE_PORT_FLAG; 10020 BNX2X_DEV_INFO("single port device\n"); 10021 } 10022 10023 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 10024 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 10025 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 10026 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 10027 bp->common.flash_size, bp->common.flash_size); 10028 10029 bnx2x_init_shmem(bp); 10030 10031 10032 10033 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 10034 MISC_REG_GENERIC_CR_1 : 10035 MISC_REG_GENERIC_CR_0)); 10036 10037 bp->link_params.shmem_base = bp->common.shmem_base; 10038 bp->link_params.shmem2_base = bp->common.shmem2_base; 10039 if (SHMEM2_RD(bp, size) > 10040 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 10041 bp->link_params.lfa_base = 10042 REG_RD(bp, bp->common.shmem2_base + 10043 (u32)offsetof(struct shmem2_region, 10044 lfa_host_addr[BP_PORT(bp)])); 10045 else 10046 bp->link_params.lfa_base = 0; 10047 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 10048 bp->common.shmem_base, bp->common.shmem2_base); 10049 10050 if (!bp->common.shmem_base) { 10051 BNX2X_DEV_INFO("MCP not active\n"); 10052 bp->flags |= NO_MCP_FLAG; 10053 return; 10054 } 10055 10056 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 10057 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 10058 10059 bp->link_params.hw_led_mode = ((bp->common.hw_config & 10060 SHARED_HW_CFG_LED_MODE_MASK) >> 10061 SHARED_HW_CFG_LED_MODE_SHIFT); 10062 10063 bp->link_params.feature_config_flags = 0; 10064 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 10065 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 10066 bp->link_params.feature_config_flags |= 10067 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 10068 else 10069 bp->link_params.feature_config_flags &= 10070 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 10071 10072 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 10073 bp->common.bc_ver = val; 10074 BNX2X_DEV_INFO("bc_ver %X\n", val); 10075 if (val < BNX2X_BC_VER) { 10076 /* for now only warn 10077 * later we might need to enforce this */ 10078 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", 10079 BNX2X_BC_VER, val); 10080 } 10081 bp->link_params.feature_config_flags |= 10082 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 10083 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 10084 10085 bp->link_params.feature_config_flags |= 10086 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 10087 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 10088 bp->link_params.feature_config_flags |= 10089 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? 10090 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; 10091 bp->link_params.feature_config_flags |= 10092 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 10093 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 10094 10095 bp->link_params.feature_config_flags |= 10096 (val >= REQ_BC_VER_4_MT_SUPPORTED) ? 10097 FEATURE_CONFIG_MT_SUPPORT : 0; 10098 10099 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 10100 BC_SUPPORTS_PFC_STATS : 0; 10101 10102 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? 10103 BC_SUPPORTS_FCOE_FEATURES : 0; 10104 10105 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? 10106 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; 10107 boot_mode = SHMEM_RD(bp, 10108 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 10109 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 10110 switch (boot_mode) { 10111 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 10112 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 10113 break; 10114 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 10115 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 10116 break; 10117 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 10118 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 10119 break; 10120 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 10121 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 10122 break; 10123 } 10124 10125 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 10126 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 10127 10128 BNX2X_DEV_INFO("%sWoL capable\n", 10129 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 10130 10131 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 10132 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 10133 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 10134 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 10135 10136 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 10137 val, val2, val3, val4); 10138} 10139 10140#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 10141#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 10142 10143static int bnx2x_get_igu_cam_info(struct bnx2x *bp) 10144{ 10145 int pfid = BP_FUNC(bp); 10146 int igu_sb_id; 10147 u32 val; 10148 u8 fid, igu_sb_cnt = 0; 10149 10150 bp->igu_base_sb = 0xff; 10151 if (CHIP_INT_MODE_IS_BC(bp)) { 10152 int vn = BP_VN(bp); 10153 igu_sb_cnt = bp->igu_sb_cnt; 10154 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 10155 FP_SB_MAX_E1x; 10156 10157 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 10158 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 10159 10160 return 0; 10161 } 10162 10163 /* IGU in normal mode - read CAM */ 10164 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 10165 igu_sb_id++) { 10166 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 10167 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 10168 continue; 10169 fid = IGU_FID(val); 10170 if ((fid & IGU_FID_ENCODE_IS_PF)) { 10171 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 10172 continue; 10173 if (IGU_VEC(val) == 0) 10174 /* default status block */ 10175 bp->igu_dsb_id = igu_sb_id; 10176 else { 10177 if (bp->igu_base_sb == 0xff) 10178 bp->igu_base_sb = igu_sb_id; 10179 igu_sb_cnt++; 10180 } 10181 } 10182 } 10183 10184#ifdef CONFIG_PCI_MSI 10185 /* Due to new PF resource allocation by MFW T7.4 and above, it's 10186 * optional that number of CAM entries will not be equal to the value 10187 * advertised in PCI. 10188 * Driver should use the minimal value of both as the actual status 10189 * block count 10190 */ 10191 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); 10192#endif 10193 10194 if (igu_sb_cnt == 0) { 10195 BNX2X_ERR("CAM configuration error\n"); 10196 return -EINVAL; 10197 } 10198 10199 return 0; 10200} 10201 10202static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) 10203{ 10204 int cfg_size = 0, idx, port = BP_PORT(bp); 10205 10206 /* Aggregation of supported attributes of all external phys */ 10207 bp->port.supported[0] = 0; 10208 bp->port.supported[1] = 0; 10209 switch (bp->link_params.num_phys) { 10210 case 1: 10211 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 10212 cfg_size = 1; 10213 break; 10214 case 2: 10215 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 10216 cfg_size = 1; 10217 break; 10218 case 3: 10219 if (bp->link_params.multi_phy_config & 10220 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 10221 bp->port.supported[1] = 10222 bp->link_params.phy[EXT_PHY1].supported; 10223 bp->port.supported[0] = 10224 bp->link_params.phy[EXT_PHY2].supported; 10225 } else { 10226 bp->port.supported[0] = 10227 bp->link_params.phy[EXT_PHY1].supported; 10228 bp->port.supported[1] = 10229 bp->link_params.phy[EXT_PHY2].supported; 10230 } 10231 cfg_size = 2; 10232 break; 10233 } 10234 10235 if (!(bp->port.supported[0] || bp->port.supported[1])) { 10236 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", 10237 SHMEM_RD(bp, 10238 dev_info.port_hw_config[port].external_phy_config), 10239 SHMEM_RD(bp, 10240 dev_info.port_hw_config[port].external_phy_config2)); 10241 return; 10242 } 10243 10244 if (CHIP_IS_E3(bp)) 10245 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 10246 else { 10247 switch (switch_cfg) { 10248 case SWITCH_CFG_1G: 10249 bp->port.phy_addr = REG_RD( 10250 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 10251 break; 10252 case SWITCH_CFG_10G: 10253 bp->port.phy_addr = REG_RD( 10254 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 10255 break; 10256 default: 10257 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 10258 bp->port.link_config[0]); 10259 return; 10260 } 10261 } 10262 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 10263 /* mask what we support according to speed_cap_mask per configuration */ 10264 for (idx = 0; idx < cfg_size; idx++) { 10265 if (!(bp->link_params.speed_cap_mask[idx] & 10266 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 10267 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 10268 10269 if (!(bp->link_params.speed_cap_mask[idx] & 10270 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 10271 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 10272 10273 if (!(bp->link_params.speed_cap_mask[idx] & 10274 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 10275 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 10276 10277 if (!(bp->link_params.speed_cap_mask[idx] & 10278 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 10279 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 10280 10281 if (!(bp->link_params.speed_cap_mask[idx] & 10282 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 10283 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 10284 SUPPORTED_1000baseT_Full); 10285 10286 if (!(bp->link_params.speed_cap_mask[idx] & 10287 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 10288 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 10289 10290 if (!(bp->link_params.speed_cap_mask[idx] & 10291 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 10292 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 10293 10294 } 10295 10296 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 10297 bp->port.supported[1]); 10298} 10299 10300static void bnx2x_link_settings_requested(struct bnx2x *bp) 10301{ 10302 u32 link_config, idx, cfg_size = 0; 10303 bp->port.advertising[0] = 0; 10304 bp->port.advertising[1] = 0; 10305 switch (bp->link_params.num_phys) { 10306 case 1: 10307 case 2: 10308 cfg_size = 1; 10309 break; 10310 case 3: 10311 cfg_size = 2; 10312 break; 10313 } 10314 for (idx = 0; idx < cfg_size; idx++) { 10315 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 10316 link_config = bp->port.link_config[idx]; 10317 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 10318 case PORT_FEATURE_LINK_SPEED_AUTO: 10319 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 10320 bp->link_params.req_line_speed[idx] = 10321 SPEED_AUTO_NEG; 10322 bp->port.advertising[idx] |= 10323 bp->port.supported[idx]; 10324 if (bp->link_params.phy[EXT_PHY1].type == 10325 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 10326 bp->port.advertising[idx] |= 10327 (SUPPORTED_100baseT_Half | 10328 SUPPORTED_100baseT_Full); 10329 } else { 10330 /* force 10G, no AN */ 10331 bp->link_params.req_line_speed[idx] = 10332 SPEED_10000; 10333 bp->port.advertising[idx] |= 10334 (ADVERTISED_10000baseT_Full | 10335 ADVERTISED_FIBRE); 10336 continue; 10337 } 10338 break; 10339 10340 case PORT_FEATURE_LINK_SPEED_10M_FULL: 10341 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 10342 bp->link_params.req_line_speed[idx] = 10343 SPEED_10; 10344 bp->port.advertising[idx] |= 10345 (ADVERTISED_10baseT_Full | 10346 ADVERTISED_TP); 10347 } else { 10348 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10349 link_config, 10350 bp->link_params.speed_cap_mask[idx]); 10351 return; 10352 } 10353 break; 10354 10355 case PORT_FEATURE_LINK_SPEED_10M_HALF: 10356 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 10357 bp->link_params.req_line_speed[idx] = 10358 SPEED_10; 10359 bp->link_params.req_duplex[idx] = 10360 DUPLEX_HALF; 10361 bp->port.advertising[idx] |= 10362 (ADVERTISED_10baseT_Half | 10363 ADVERTISED_TP); 10364 } else { 10365 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10366 link_config, 10367 bp->link_params.speed_cap_mask[idx]); 10368 return; 10369 } 10370 break; 10371 10372 case PORT_FEATURE_LINK_SPEED_100M_FULL: 10373 if (bp->port.supported[idx] & 10374 SUPPORTED_100baseT_Full) { 10375 bp->link_params.req_line_speed[idx] = 10376 SPEED_100; 10377 bp->port.advertising[idx] |= 10378 (ADVERTISED_100baseT_Full | 10379 ADVERTISED_TP); 10380 } else { 10381 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10382 link_config, 10383 bp->link_params.speed_cap_mask[idx]); 10384 return; 10385 } 10386 break; 10387 10388 case PORT_FEATURE_LINK_SPEED_100M_HALF: 10389 if (bp->port.supported[idx] & 10390 SUPPORTED_100baseT_Half) { 10391 bp->link_params.req_line_speed[idx] = 10392 SPEED_100; 10393 bp->link_params.req_duplex[idx] = 10394 DUPLEX_HALF; 10395 bp->port.advertising[idx] |= 10396 (ADVERTISED_100baseT_Half | 10397 ADVERTISED_TP); 10398 } else { 10399 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10400 link_config, 10401 bp->link_params.speed_cap_mask[idx]); 10402 return; 10403 } 10404 break; 10405 10406 case PORT_FEATURE_LINK_SPEED_1G: 10407 if (bp->port.supported[idx] & 10408 SUPPORTED_1000baseT_Full) { 10409 bp->link_params.req_line_speed[idx] = 10410 SPEED_1000; 10411 bp->port.advertising[idx] |= 10412 (ADVERTISED_1000baseT_Full | 10413 ADVERTISED_TP); 10414 } else { 10415 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10416 link_config, 10417 bp->link_params.speed_cap_mask[idx]); 10418 return; 10419 } 10420 break; 10421 10422 case PORT_FEATURE_LINK_SPEED_2_5G: 10423 if (bp->port.supported[idx] & 10424 SUPPORTED_2500baseX_Full) { 10425 bp->link_params.req_line_speed[idx] = 10426 SPEED_2500; 10427 bp->port.advertising[idx] |= 10428 (ADVERTISED_2500baseX_Full | 10429 ADVERTISED_TP); 10430 } else { 10431 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10432 link_config, 10433 bp->link_params.speed_cap_mask[idx]); 10434 return; 10435 } 10436 break; 10437 10438 case PORT_FEATURE_LINK_SPEED_10G_CX4: 10439 if (bp->port.supported[idx] & 10440 SUPPORTED_10000baseT_Full) { 10441 bp->link_params.req_line_speed[idx] = 10442 SPEED_10000; 10443 bp->port.advertising[idx] |= 10444 (ADVERTISED_10000baseT_Full | 10445 ADVERTISED_FIBRE); 10446 } else { 10447 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10448 link_config, 10449 bp->link_params.speed_cap_mask[idx]); 10450 return; 10451 } 10452 break; 10453 case PORT_FEATURE_LINK_SPEED_20G: 10454 bp->link_params.req_line_speed[idx] = SPEED_20000; 10455 10456 break; 10457 default: 10458 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", 10459 link_config); 10460 bp->link_params.req_line_speed[idx] = 10461 SPEED_AUTO_NEG; 10462 bp->port.advertising[idx] = 10463 bp->port.supported[idx]; 10464 break; 10465 } 10466 10467 bp->link_params.req_flow_ctrl[idx] = (link_config & 10468 PORT_FEATURE_FLOW_CONTROL_MASK); 10469 if (bp->link_params.req_flow_ctrl[idx] == 10470 BNX2X_FLOW_CTRL_AUTO) { 10471 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) 10472 bp->link_params.req_flow_ctrl[idx] = 10473 BNX2X_FLOW_CTRL_NONE; 10474 else 10475 bnx2x_set_requested_fc(bp); 10476 } 10477 10478 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", 10479 bp->link_params.req_line_speed[idx], 10480 bp->link_params.req_duplex[idx], 10481 bp->link_params.req_flow_ctrl[idx], 10482 bp->port.advertising[idx]); 10483 } 10484} 10485 10486static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 10487{ 10488 mac_hi = cpu_to_be16(mac_hi); 10489 mac_lo = cpu_to_be32(mac_lo); 10490 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 10491 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 10492} 10493 10494static void bnx2x_get_port_hwinfo(struct bnx2x *bp) 10495{ 10496 int port = BP_PORT(bp); 10497 u32 config; 10498 u32 ext_phy_type, ext_phy_config, eee_mode; 10499 10500 bp->link_params.bp = bp; 10501 bp->link_params.port = port; 10502 10503 bp->link_params.lane_config = 10504 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 10505 10506 bp->link_params.speed_cap_mask[0] = 10507 SHMEM_RD(bp, 10508 dev_info.port_hw_config[port].speed_capability_mask); 10509 bp->link_params.speed_cap_mask[1] = 10510 SHMEM_RD(bp, 10511 dev_info.port_hw_config[port].speed_capability_mask2); 10512 bp->port.link_config[0] = 10513 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 10514 10515 bp->port.link_config[1] = 10516 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 10517 10518 bp->link_params.multi_phy_config = 10519 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 10520 /* If the device is capable of WoL, set the default state according 10521 * to the HW 10522 */ 10523 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 10524 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 10525 (config & PORT_FEATURE_WOL_ENABLED)); 10526 10527 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", 10528 bp->link_params.lane_config, 10529 bp->link_params.speed_cap_mask[0], 10530 bp->port.link_config[0]); 10531 10532 bp->link_params.switch_cfg = (bp->port.link_config[0] & 10533 PORT_FEATURE_CONNECTED_SWITCH_MASK); 10534 bnx2x_phy_probe(&bp->link_params); 10535 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 10536 10537 bnx2x_link_settings_requested(bp); 10538 10539 /* 10540 * If connected directly, work with the internal PHY, otherwise, work 10541 * with the external PHY 10542 */ 10543 ext_phy_config = 10544 SHMEM_RD(bp, 10545 dev_info.port_hw_config[port].external_phy_config); 10546 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 10547 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 10548 bp->mdio.prtad = bp->port.phy_addr; 10549 10550 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 10551 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 10552 bp->mdio.prtad = 10553 XGXS_EXT_PHY_ADDR(ext_phy_config); 10554 10555 /* Configure link feature according to nvram value */ 10556 eee_mode = (((SHMEM_RD(bp, dev_info. 10557 port_feature_config[port].eee_power_mode)) & 10558 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 10559 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 10560 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { 10561 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | 10562 EEE_MODE_ENABLE_LPI | 10563 EEE_MODE_OUTPUT_TIME; 10564 } else { 10565 bp->link_params.eee_mode = 0; 10566 } 10567} 10568 10569void bnx2x_get_iscsi_info(struct bnx2x *bp) 10570{ 10571 u32 no_flags = NO_ISCSI_FLAG; 10572 int port = BP_PORT(bp); 10573 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 10574 drv_lic_key[port].max_iscsi_conn); 10575 10576 if (!CNIC_SUPPORT(bp)) { 10577 bp->flags |= no_flags; 10578 return; 10579 } 10580 10581 /* Get the number of maximum allowed iSCSI connections */ 10582 bp->cnic_eth_dev.max_iscsi_conn = 10583 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 10584 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 10585 10586 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 10587 bp->cnic_eth_dev.max_iscsi_conn); 10588 10589 /* 10590 * If maximum allowed number of connections is zero - 10591 * disable the feature. 10592 */ 10593 if (!bp->cnic_eth_dev.max_iscsi_conn) 10594 bp->flags |= no_flags; 10595 10596} 10597 10598static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) 10599{ 10600 /* Port info */ 10601 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 10602 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); 10603 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 10604 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); 10605 10606 /* Node info */ 10607 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 10608 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); 10609 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 10610 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); 10611} 10612static void bnx2x_get_fcoe_info(struct bnx2x *bp) 10613{ 10614 int port = BP_PORT(bp); 10615 int func = BP_ABS_FUNC(bp); 10616 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 10617 drv_lic_key[port].max_fcoe_conn); 10618 10619 if (!CNIC_SUPPORT(bp)) { 10620 bp->flags |= NO_FCOE_FLAG; 10621 return; 10622 } 10623 10624 /* Get the number of maximum allowed FCoE connections */ 10625 bp->cnic_eth_dev.max_fcoe_conn = 10626 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 10627 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 10628 10629 /* Read the WWN: */ 10630 if (!IS_MF(bp)) { 10631 /* Port info */ 10632 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 10633 SHMEM_RD(bp, 10634 dev_info.port_hw_config[port]. 10635 fcoe_wwn_port_name_upper); 10636 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 10637 SHMEM_RD(bp, 10638 dev_info.port_hw_config[port]. 10639 fcoe_wwn_port_name_lower); 10640 10641 /* Node info */ 10642 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 10643 SHMEM_RD(bp, 10644 dev_info.port_hw_config[port]. 10645 fcoe_wwn_node_name_upper); 10646 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 10647 SHMEM_RD(bp, 10648 dev_info.port_hw_config[port]. 10649 fcoe_wwn_node_name_lower); 10650 } else if (!IS_MF_SD(bp)) { 10651 /* 10652 * Read the WWN info only if the FCoE feature is enabled for 10653 * this function. 10654 */ 10655 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) 10656 bnx2x_get_ext_wwn_info(bp, func); 10657 10658 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) { 10659 bnx2x_get_ext_wwn_info(bp, func); 10660 } 10661 10662 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 10663 10664 /* 10665 * If maximum allowed number of connections is zero - 10666 * disable the feature. 10667 */ 10668 if (!bp->cnic_eth_dev.max_fcoe_conn) 10669 bp->flags |= NO_FCOE_FLAG; 10670} 10671 10672static void bnx2x_get_cnic_info(struct bnx2x *bp) 10673{ 10674 /* 10675 * iSCSI may be dynamically disabled but reading 10676 * info here we will decrease memory usage by driver 10677 * if the feature is disabled for good 10678 */ 10679 bnx2x_get_iscsi_info(bp); 10680 bnx2x_get_fcoe_info(bp); 10681} 10682 10683static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) 10684{ 10685 u32 val, val2; 10686 int func = BP_ABS_FUNC(bp); 10687 int port = BP_PORT(bp); 10688 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 10689 u8 *fip_mac = bp->fip_mac; 10690 10691 if (IS_MF(bp)) { 10692 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 10693 * FCoE MAC then the appropriate feature should be disabled. 10694 * In non SD mode features configuration comes from struct 10695 * func_ext_config. 10696 */ 10697 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) { 10698 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 10699 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 10700 val2 = MF_CFG_RD(bp, func_ext_config[func]. 10701 iscsi_mac_addr_upper); 10702 val = MF_CFG_RD(bp, func_ext_config[func]. 10703 iscsi_mac_addr_lower); 10704 bnx2x_set_mac_buf(iscsi_mac, val, val2); 10705 BNX2X_DEV_INFO 10706 ("Read iSCSI MAC: %pM\n", iscsi_mac); 10707 } else { 10708 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 10709 } 10710 10711 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 10712 val2 = MF_CFG_RD(bp, func_ext_config[func]. 10713 fcoe_mac_addr_upper); 10714 val = MF_CFG_RD(bp, func_ext_config[func]. 10715 fcoe_mac_addr_lower); 10716 bnx2x_set_mac_buf(fip_mac, val, val2); 10717 BNX2X_DEV_INFO 10718 ("Read FCoE L2 MAC: %pM\n", fip_mac); 10719 } else { 10720 bp->flags |= NO_FCOE_FLAG; 10721 } 10722 10723 bp->mf_ext_config = cfg; 10724 10725 } else { /* SD MODE */ 10726 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { 10727 /* use primary mac as iscsi mac */ 10728 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 10729 10730 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 10731 BNX2X_DEV_INFO 10732 ("Read iSCSI MAC: %pM\n", iscsi_mac); 10733 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { 10734 /* use primary mac as fip mac */ 10735 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 10736 BNX2X_DEV_INFO("SD FCoE MODE\n"); 10737 BNX2X_DEV_INFO 10738 ("Read FIP MAC: %pM\n", fip_mac); 10739 } 10740 } 10741 10742 if (IS_MF_STORAGE_SD(bp)) 10743 /* Zero primary MAC configuration */ 10744 memset(bp->dev->dev_addr, 0, ETH_ALEN); 10745 10746 if (IS_MF_FCOE_AFEX(bp)) 10747 /* use FIP MAC as primary MAC */ 10748 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); 10749 10750 } else { 10751 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 10752 iscsi_mac_upper); 10753 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 10754 iscsi_mac_lower); 10755 bnx2x_set_mac_buf(iscsi_mac, val, val2); 10756 10757 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 10758 fcoe_fip_mac_upper); 10759 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 10760 fcoe_fip_mac_lower); 10761 bnx2x_set_mac_buf(fip_mac, val, val2); 10762 } 10763 10764 /* Disable iSCSI OOO if MAC configuration is invalid. */ 10765 if (!is_valid_ether_addr(iscsi_mac)) { 10766 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 10767 memset(iscsi_mac, 0, ETH_ALEN); 10768 } 10769 10770 /* Disable FCoE if MAC configuration is invalid. */ 10771 if (!is_valid_ether_addr(fip_mac)) { 10772 bp->flags |= NO_FCOE_FLAG; 10773 memset(bp->fip_mac, 0, ETH_ALEN); 10774 } 10775} 10776 10777static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) 10778{ 10779 u32 val, val2; 10780 int func = BP_ABS_FUNC(bp); 10781 int port = BP_PORT(bp); 10782 10783 /* Zero primary MAC configuration */ 10784 memset(bp->dev->dev_addr, 0, ETH_ALEN); 10785 10786 if (BP_NOMCP(bp)) { 10787 BNX2X_ERROR("warning: random MAC workaround active\n"); 10788 eth_hw_addr_random(bp->dev); 10789 } else if (IS_MF(bp)) { 10790 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 10791 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 10792 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 10793 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 10794 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 10795 10796 if (CNIC_SUPPORT(bp)) 10797 bnx2x_get_cnic_mac_hwinfo(bp); 10798 } else { 10799 /* in SF read MACs from port configuration */ 10800 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 10801 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 10802 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 10803 10804 if (CNIC_SUPPORT(bp)) 10805 bnx2x_get_cnic_mac_hwinfo(bp); 10806 } 10807 10808 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 10809 10810 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 10811 dev_err(&bp->pdev->dev, 10812 "bad Ethernet MAC address configuration: %pM\n" 10813 "change it manually before bringing up the appropriate network interface\n", 10814 bp->dev->dev_addr); 10815} 10816 10817static bool bnx2x_get_dropless_info(struct bnx2x *bp) 10818{ 10819 int tmp; 10820 u32 cfg; 10821 10822 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { 10823 /* Take function: tmp = func */ 10824 tmp = BP_ABS_FUNC(bp); 10825 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); 10826 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); 10827 } else { 10828 /* Take port: tmp = port */ 10829 tmp = BP_PORT(bp); 10830 cfg = SHMEM_RD(bp, 10831 dev_info.port_hw_config[tmp].generic_features); 10832 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); 10833 } 10834 return cfg; 10835} 10836 10837static int bnx2x_get_hwinfo(struct bnx2x *bp) 10838{ 10839 int /*abs*/func = BP_ABS_FUNC(bp); 10840 int vn; 10841 u32 val = 0; 10842 int rc = 0; 10843 10844 bnx2x_get_common_hwinfo(bp); 10845 10846 /* 10847 * initialize IGU parameters 10848 */ 10849 if (CHIP_IS_E1x(bp)) { 10850 bp->common.int_block = INT_BLOCK_HC; 10851 10852 bp->igu_dsb_id = DEF_SB_IGU_ID; 10853 bp->igu_base_sb = 0; 10854 } else { 10855 bp->common.int_block = INT_BLOCK_IGU; 10856 10857 /* do not allow device reset during IGU info preocessing */ 10858 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 10859 10860 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 10861 10862 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 10863 int tout = 5000; 10864 10865 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 10866 10867 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 10868 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 10869 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 10870 10871 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 10872 tout--; 10873 usleep_range(1000, 1000); 10874 } 10875 10876 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 10877 dev_err(&bp->pdev->dev, 10878 "FORCING Normal Mode failed!!!\n"); 10879 bnx2x_release_hw_lock(bp, 10880 HW_LOCK_RESOURCE_RESET); 10881 return -EPERM; 10882 } 10883 } 10884 10885 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 10886 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 10887 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 10888 } else 10889 BNX2X_DEV_INFO("IGU Normal Mode\n"); 10890 10891 rc = bnx2x_get_igu_cam_info(bp); 10892 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 10893 if (rc) 10894 return rc; 10895 } 10896 10897 /* 10898 * set base FW non-default (fast path) status block id, this value is 10899 * used to initialize the fw_sb_id saved on the fp/queue structure to 10900 * determine the id used by the FW. 10901 */ 10902 if (CHIP_IS_E1x(bp)) 10903 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 10904 else /* 10905 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 10906 * the same queue are indicated on the same IGU SB). So we prefer 10907 * FW and IGU SBs to be the same value. 10908 */ 10909 bp->base_fw_ndsb = bp->igu_base_sb; 10910 10911 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 10912 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 10913 bp->igu_sb_cnt, bp->base_fw_ndsb); 10914 10915 /* 10916 * Initialize MF configuration 10917 */ 10918 10919 bp->mf_ov = 0; 10920 bp->mf_mode = 0; 10921 vn = BP_VN(bp); 10922 10923 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 10924 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 10925 bp->common.shmem2_base, SHMEM2_RD(bp, size), 10926 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 10927 10928 if (SHMEM2_HAS(bp, mf_cfg_addr)) 10929 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 10930 else 10931 bp->common.mf_cfg_base = bp->common.shmem_base + 10932 offsetof(struct shmem_region, func_mb) + 10933 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 10934 /* 10935 * get mf configuration: 10936 * 1. existence of MF configuration 10937 * 2. MAC address must be legal (check only upper bytes) 10938 * for Switch-Independent mode; 10939 * OVLAN must be legal for Switch-Dependent mode 10940 * 3. SF_MODE configures specific MF mode 10941 */ 10942 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 10943 /* get mf configuration */ 10944 val = SHMEM_RD(bp, 10945 dev_info.shared_feature_config.config); 10946 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 10947 10948 switch (val) { 10949 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 10950 val = MF_CFG_RD(bp, func_mf_config[func]. 10951 mac_upper); 10952 /* check for legal mac (upper bytes)*/ 10953 if (val != 0xffff) { 10954 bp->mf_mode = MULTI_FUNCTION_SI; 10955 bp->mf_config[vn] = MF_CFG_RD(bp, 10956 func_mf_config[func].config); 10957 } else 10958 BNX2X_DEV_INFO("illegal MAC address for SI\n"); 10959 break; 10960 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: 10961 if ((!CHIP_IS_E1x(bp)) && 10962 (MF_CFG_RD(bp, func_mf_config[func]. 10963 mac_upper) != 0xffff) && 10964 (SHMEM2_HAS(bp, 10965 afex_driver_support))) { 10966 bp->mf_mode = MULTI_FUNCTION_AFEX; 10967 bp->mf_config[vn] = MF_CFG_RD(bp, 10968 func_mf_config[func].config); 10969 } else { 10970 BNX2X_DEV_INFO("can not configure afex mode\n"); 10971 } 10972 break; 10973 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 10974 /* get OV configuration */ 10975 val = MF_CFG_RD(bp, 10976 func_mf_config[FUNC_0].e1hov_tag); 10977 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 10978 10979 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 10980 bp->mf_mode = MULTI_FUNCTION_SD; 10981 bp->mf_config[vn] = MF_CFG_RD(bp, 10982 func_mf_config[func].config); 10983 } else 10984 BNX2X_DEV_INFO("illegal OV for SD\n"); 10985 break; 10986 default: 10987 /* Unknown configuration: reset mf_config */ 10988 bp->mf_config[vn] = 0; 10989 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); 10990 } 10991 } 10992 10993 BNX2X_DEV_INFO("%s function mode\n", 10994 IS_MF(bp) ? "multi" : "single"); 10995 10996 switch (bp->mf_mode) { 10997 case MULTI_FUNCTION_SD: 10998 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 10999 FUNC_MF_CFG_E1HOV_TAG_MASK; 11000 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 11001 bp->mf_ov = val; 11002 bp->path_has_ovlan = true; 11003 11004 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", 11005 func, bp->mf_ov, bp->mf_ov); 11006 } else { 11007 dev_err(&bp->pdev->dev, 11008 "No valid MF OV for func %d, aborting\n", 11009 func); 11010 return -EPERM; 11011 } 11012 break; 11013 case MULTI_FUNCTION_AFEX: 11014 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); 11015 break; 11016 case MULTI_FUNCTION_SI: 11017 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", 11018 func); 11019 break; 11020 default: 11021 if (vn) { 11022 dev_err(&bp->pdev->dev, 11023 "VN %d is in a single function mode, aborting\n", 11024 vn); 11025 return -EPERM; 11026 } 11027 break; 11028 } 11029 11030 /* check if other port on the path needs ovlan: 11031 * Since MF configuration is shared between ports 11032 * Possible mixed modes are only 11033 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 11034 */ 11035 if (CHIP_MODE_IS_4_PORT(bp) && 11036 !bp->path_has_ovlan && 11037 !IS_MF(bp) && 11038 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 11039 u8 other_port = !BP_PORT(bp); 11040 u8 other_func = BP_PATH(bp) + 2*other_port; 11041 val = MF_CFG_RD(bp, 11042 func_mf_config[other_func].e1hov_tag); 11043 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 11044 bp->path_has_ovlan = true; 11045 } 11046 } 11047 11048 /* adjust igu_sb_cnt to MF for E1x */ 11049 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 11050 bp->igu_sb_cnt /= E1HVN_MAX; 11051 11052 /* port info */ 11053 bnx2x_get_port_hwinfo(bp); 11054 11055 /* Get MAC addresses */ 11056 bnx2x_get_mac_hwinfo(bp); 11057 11058 bnx2x_get_cnic_info(bp); 11059 11060 return rc; 11061} 11062 11063static void bnx2x_read_fwinfo(struct bnx2x *bp) 11064{ 11065 int cnt, i, block_end, rodi; 11066 char vpd_start[BNX2X_VPD_LEN+1]; 11067 char str_id_reg[VENDOR_ID_LEN+1]; 11068 char str_id_cap[VENDOR_ID_LEN+1]; 11069 char *vpd_data; 11070 char *vpd_extended_data = NULL; 11071 u8 len; 11072 11073 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 11074 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 11075 11076 if (cnt < BNX2X_VPD_LEN) 11077 goto out_not_found; 11078 11079 /* VPD RO tag should be first tag after identifier string, hence 11080 * we should be able to find it in first BNX2X_VPD_LEN chars 11081 */ 11082 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 11083 PCI_VPD_LRDT_RO_DATA); 11084 if (i < 0) 11085 goto out_not_found; 11086 11087 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 11088 pci_vpd_lrdt_size(&vpd_start[i]); 11089 11090 i += PCI_VPD_LRDT_TAG_SIZE; 11091 11092 if (block_end > BNX2X_VPD_LEN) { 11093 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 11094 if (vpd_extended_data == NULL) 11095 goto out_not_found; 11096 11097 /* read rest of vpd image into vpd_extended_data */ 11098 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 11099 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 11100 block_end - BNX2X_VPD_LEN, 11101 vpd_extended_data + BNX2X_VPD_LEN); 11102 if (cnt < (block_end - BNX2X_VPD_LEN)) 11103 goto out_not_found; 11104 vpd_data = vpd_extended_data; 11105 } else 11106 vpd_data = vpd_start; 11107 11108 /* now vpd_data holds full vpd content in both cases */ 11109 11110 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 11111 PCI_VPD_RO_KEYWORD_MFR_ID); 11112 if (rodi < 0) 11113 goto out_not_found; 11114 11115 len = pci_vpd_info_field_size(&vpd_data[rodi]); 11116 11117 if (len != VENDOR_ID_LEN) 11118 goto out_not_found; 11119 11120 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 11121 11122 /* vendor specific info */ 11123 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 11124 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 11125 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 11126 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 11127 11128 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 11129 PCI_VPD_RO_KEYWORD_VENDOR0); 11130 if (rodi >= 0) { 11131 len = pci_vpd_info_field_size(&vpd_data[rodi]); 11132 11133 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 11134 11135 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 11136 memcpy(bp->fw_ver, &vpd_data[rodi], len); 11137 bp->fw_ver[len] = ' '; 11138 } 11139 } 11140 kfree(vpd_extended_data); 11141 return; 11142 } 11143out_not_found: 11144 kfree(vpd_extended_data); 11145 return; 11146} 11147 11148static void bnx2x_set_modes_bitmap(struct bnx2x *bp) 11149{ 11150 u32 flags = 0; 11151 11152 if (CHIP_REV_IS_FPGA(bp)) 11153 SET_FLAGS(flags, MODE_FPGA); 11154 else if (CHIP_REV_IS_EMUL(bp)) 11155 SET_FLAGS(flags, MODE_EMUL); 11156 else 11157 SET_FLAGS(flags, MODE_ASIC); 11158 11159 if (CHIP_MODE_IS_4_PORT(bp)) 11160 SET_FLAGS(flags, MODE_PORT4); 11161 else 11162 SET_FLAGS(flags, MODE_PORT2); 11163 11164 if (CHIP_IS_E2(bp)) 11165 SET_FLAGS(flags, MODE_E2); 11166 else if (CHIP_IS_E3(bp)) { 11167 SET_FLAGS(flags, MODE_E3); 11168 if (CHIP_REV(bp) == CHIP_REV_Ax) 11169 SET_FLAGS(flags, MODE_E3_A0); 11170 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 11171 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 11172 } 11173 11174 if (IS_MF(bp)) { 11175 SET_FLAGS(flags, MODE_MF); 11176 switch (bp->mf_mode) { 11177 case MULTI_FUNCTION_SD: 11178 SET_FLAGS(flags, MODE_MF_SD); 11179 break; 11180 case MULTI_FUNCTION_SI: 11181 SET_FLAGS(flags, MODE_MF_SI); 11182 break; 11183 case MULTI_FUNCTION_AFEX: 11184 SET_FLAGS(flags, MODE_MF_AFEX); 11185 break; 11186 } 11187 } else 11188 SET_FLAGS(flags, MODE_SF); 11189 11190#if defined(__LITTLE_ENDIAN) 11191 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 11192#else /*(__BIG_ENDIAN)*/ 11193 SET_FLAGS(flags, MODE_BIG_ENDIAN); 11194#endif 11195 INIT_MODE_FLAGS(bp) = flags; 11196} 11197 11198static int bnx2x_init_bp(struct bnx2x *bp) 11199{ 11200 int func; 11201 int rc; 11202 11203 mutex_init(&bp->port.phy_mutex); 11204 mutex_init(&bp->fw_mb_mutex); 11205 spin_lock_init(&bp->stats_lock); 11206 11207 11208 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 11209 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 11210 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 11211 if (IS_PF(bp)) { 11212 rc = bnx2x_get_hwinfo(bp); 11213 if (rc) 11214 return rc; 11215 } else { 11216 random_ether_addr(bp->dev->dev_addr); 11217 } 11218 11219 bnx2x_set_modes_bitmap(bp); 11220 11221 rc = bnx2x_alloc_mem_bp(bp); 11222 if (rc) 11223 return rc; 11224 11225 bnx2x_read_fwinfo(bp); 11226 11227 func = BP_FUNC(bp); 11228 11229 /* need to reset chip if undi was active */ 11230 if (IS_PF(bp) && !BP_NOMCP(bp)) { 11231 /* init fw_seq */ 11232 bp->fw_seq = 11233 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 11234 DRV_MSG_SEQ_NUMBER_MASK; 11235 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 11236 11237 bnx2x_prev_unload(bp); 11238 } 11239 11240 11241 if (CHIP_REV_IS_FPGA(bp)) 11242 dev_err(&bp->pdev->dev, "FPGA detected\n"); 11243 11244 if (BP_NOMCP(bp) && (func == 0)) 11245 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); 11246 11247 bp->disable_tpa = disable_tpa; 11248 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); 11249 11250 /* Set TPA flags */ 11251 if (bp->disable_tpa) { 11252 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 11253 bp->dev->features &= ~NETIF_F_LRO; 11254 } else { 11255 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 11256 bp->dev->features |= NETIF_F_LRO; 11257 } 11258 11259 if (CHIP_IS_E1(bp)) 11260 bp->dropless_fc = 0; 11261 else 11262 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); 11263 11264 bp->mrrs = mrrs; 11265 11266 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 11267 if (IS_VF(bp)) 11268 bp->rx_ring_size = MAX_RX_AVAIL; 11269 11270 /* make sure that the numbers are in the right granularity */ 11271 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 11272 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 11273 11274 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 11275 11276 init_timer(&bp->timer); 11277 bp->timer.expires = jiffies + bp->current_interval; 11278 bp->timer.data = (unsigned long) bp; 11279 bp->timer.function = bnx2x_timer; 11280 11281 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && 11282 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && 11283 SHMEM2_RD(bp, dcbx_lldp_params_offset) && 11284 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { 11285 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 11286 bnx2x_dcbx_init_params(bp); 11287 } else { 11288 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); 11289 } 11290 11291 if (CHIP_IS_E1x(bp)) 11292 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 11293 else 11294 bp->cnic_base_cl_id = FP_SB_MAX_E2; 11295 11296 /* multiple tx priority */ 11297 if (IS_VF(bp)) 11298 bp->max_cos = 1; 11299 else if (CHIP_IS_E1x(bp)) 11300 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 11301 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 11302 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 11303 else if (CHIP_IS_E3B0(bp)) 11304 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 11305 else 11306 BNX2X_ERR("unknown chip %x revision %x\n", 11307 CHIP_NUM(bp), CHIP_REV(bp)); 11308 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); 11309 11310 /* We need at least one default status block for slow-path events, 11311 * second status block for the L2 queue, and a third status block for 11312 * CNIC if supproted. 11313 */ 11314 if (CNIC_SUPPORT(bp)) 11315 bp->min_msix_vec_cnt = 3; 11316 else 11317 bp->min_msix_vec_cnt = 2; 11318 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); 11319 11320 return rc; 11321} 11322 11323 11324/**************************************************************************** 11325* General service functions 11326****************************************************************************/ 11327 11328/* 11329 * net_device service functions 11330 */ 11331 11332static int bnx2x_open_epilog(struct bnx2x *bp) 11333{ 11334 /* Enable sriov via delayed work. This must be done via delayed work 11335 * because it causes the probe of the vf devices to be run, which invoke 11336 * register_netdevice which must have rtnl lock taken. As we are holding 11337 * the lock right now, that could only work if the probe would not take 11338 * the lock. However, as the probe of the vf may be called from other 11339 * contexts as well (such as passthrough to vm failes) it can't assume 11340 * the lock is being held for it. Using delayed work here allows the 11341 * probe code to simply take the lock (i.e. wait for it to be released 11342 * if it is being held). 11343 */ 11344 smp_mb__before_clear_bit(); 11345 set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state); 11346 smp_mb__after_clear_bit(); 11347 schedule_delayed_work(&bp->sp_rtnl_task, 0); 11348 11349 return 0; 11350} 11351 11352/* called with rtnl_lock */ 11353static int bnx2x_open(struct net_device *dev) 11354{ 11355 struct bnx2x *bp = netdev_priv(dev); 11356 bool global = false; 11357 int other_engine = BP_PATH(bp) ? 0 : 1; 11358 bool other_load_status, load_status; 11359 int rc; 11360 11361 bp->stats_init = true; 11362 11363 netif_carrier_off(dev); 11364 11365 bnx2x_set_power_state(bp, PCI_D0); 11366 11367 /* If parity had happen during the unload, then attentions 11368 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 11369 * want the first function loaded on the current engine to 11370 * complete the recovery. 11371 * Parity recovery is only relevant for PF driver. 11372 */ 11373 if (IS_PF(bp)) { 11374 other_load_status = bnx2x_get_load_status(bp, other_engine); 11375 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 11376 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 11377 bnx2x_chk_parity_attn(bp, &global, true)) { 11378 do { 11379 /* If there are attentions and they are in a 11380 * global blocks, set the GLOBAL_RESET bit 11381 * regardless whether it will be this function 11382 * that will complete the recovery or not. 11383 */ 11384 if (global) 11385 bnx2x_set_reset_global(bp); 11386 11387 /* Only the first function on the current 11388 * engine should try to recover in open. In case 11389 * of attentions in global blocks only the first 11390 * in the chip should try to recover. 11391 */ 11392 if ((!load_status && 11393 (!global || !other_load_status)) && 11394 bnx2x_trylock_leader_lock(bp) && 11395 !bnx2x_leader_reset(bp)) { 11396 netdev_info(bp->dev, 11397 "Recovered in open\n"); 11398 break; 11399 } 11400 11401 /* recovery has failed... */ 11402 bnx2x_set_power_state(bp, PCI_D3hot); 11403 bp->recovery_state = BNX2X_RECOVERY_FAILED; 11404 11405 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" 11406 "If you still see this message after a few retries then power cycle is required.\n"); 11407 11408 return -EAGAIN; 11409 } while (0); 11410 } 11411 } 11412 11413 bp->recovery_state = BNX2X_RECOVERY_DONE; 11414 rc = bnx2x_nic_load(bp, LOAD_OPEN); 11415 if (rc) 11416 return rc; 11417 return bnx2x_open_epilog(bp); 11418} 11419 11420/* called with rtnl_lock */ 11421static int bnx2x_close(struct net_device *dev) 11422{ 11423 struct bnx2x *bp = netdev_priv(dev); 11424 11425 /* Unload the driver, release IRQs */ 11426 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); 11427 11428 /* Power off */ 11429 bnx2x_set_power_state(bp, PCI_D3hot); 11430 11431 return 0; 11432} 11433 11434static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 11435 struct bnx2x_mcast_ramrod_params *p) 11436{ 11437 int mc_count = netdev_mc_count(bp->dev); 11438 struct bnx2x_mcast_list_elem *mc_mac = 11439 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 11440 struct netdev_hw_addr *ha; 11441 11442 if (!mc_mac) 11443 return -ENOMEM; 11444 11445 INIT_LIST_HEAD(&p->mcast_list); 11446 11447 netdev_for_each_mc_addr(ha, bp->dev) { 11448 mc_mac->mac = bnx2x_mc_addr(ha); 11449 list_add_tail(&mc_mac->link, &p->mcast_list); 11450 mc_mac++; 11451 } 11452 11453 p->mcast_list_len = mc_count; 11454 11455 return 0; 11456} 11457 11458static void bnx2x_free_mcast_macs_list( 11459 struct bnx2x_mcast_ramrod_params *p) 11460{ 11461 struct bnx2x_mcast_list_elem *mc_mac = 11462 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 11463 link); 11464 11465 WARN_ON(!mc_mac); 11466 kfree(mc_mac); 11467} 11468 11469/** 11470 * bnx2x_set_uc_list - configure a new unicast MACs list. 11471 * 11472 * @bp: driver handle 11473 * 11474 * We will use zero (0) as a MAC type for these MACs. 11475 */ 11476static int bnx2x_set_uc_list(struct bnx2x *bp) 11477{ 11478 int rc; 11479 struct net_device *dev = bp->dev; 11480 struct netdev_hw_addr *ha; 11481 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; 11482 unsigned long ramrod_flags = 0; 11483 11484 /* First schedule a cleanup up of old configuration */ 11485 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 11486 if (rc < 0) { 11487 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 11488 return rc; 11489 } 11490 11491 netdev_for_each_uc_addr(ha, dev) { 11492 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 11493 BNX2X_UC_LIST_MAC, &ramrod_flags); 11494 if (rc == -EEXIST) { 11495 DP(BNX2X_MSG_SP, 11496 "Failed to schedule ADD operations: %d\n", rc); 11497 /* do not treat adding same MAC as error */ 11498 rc = 0; 11499 11500 } else if (rc < 0) { 11501 11502 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 11503 rc); 11504 return rc; 11505 } 11506 } 11507 11508 /* Execute the pending commands */ 11509 __set_bit(RAMROD_CONT, &ramrod_flags); 11510 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 11511 BNX2X_UC_LIST_MAC, &ramrod_flags); 11512} 11513 11514static int bnx2x_set_mc_list(struct bnx2x *bp) 11515{ 11516 struct net_device *dev = bp->dev; 11517 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 11518 int rc = 0; 11519 11520 rparam.mcast_obj = &bp->mcast_obj; 11521 11522 /* first, clear all configured multicast MACs */ 11523 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 11524 if (rc < 0) { 11525 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); 11526 return rc; 11527 } 11528 11529 /* then, configure a new MACs list */ 11530 if (netdev_mc_count(dev)) { 11531 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 11532 if (rc) { 11533 BNX2X_ERR("Failed to create multicast MACs list: %d\n", 11534 rc); 11535 return rc; 11536 } 11537 11538 /* Now add the new MACs */ 11539 rc = bnx2x_config_mcast(bp, &rparam, 11540 BNX2X_MCAST_CMD_ADD); 11541 if (rc < 0) 11542 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 11543 rc); 11544 11545 bnx2x_free_mcast_macs_list(&rparam); 11546 } 11547 11548 return rc; 11549} 11550 11551 11552/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 11553void bnx2x_set_rx_mode(struct net_device *dev) 11554{ 11555 struct bnx2x *bp = netdev_priv(dev); 11556 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 11557 11558 if (bp->state != BNX2X_STATE_OPEN) { 11559 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 11560 return; 11561 } 11562 11563 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 11564 11565 if (dev->flags & IFF_PROMISC) 11566 rx_mode = BNX2X_RX_MODE_PROMISC; 11567 else if ((dev->flags & IFF_ALLMULTI) || 11568 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 11569 CHIP_IS_E1(bp))) 11570 rx_mode = BNX2X_RX_MODE_ALLMULTI; 11571 else { 11572 if (IS_PF(bp)) { 11573 /* some multicasts */ 11574 if (bnx2x_set_mc_list(bp) < 0) 11575 rx_mode = BNX2X_RX_MODE_ALLMULTI; 11576 11577 if (bnx2x_set_uc_list(bp) < 0) 11578 rx_mode = BNX2X_RX_MODE_PROMISC; 11579 } else { 11580 /* configuring mcast to a vf involves sleeping (when we 11581 * wait for the pf's response). Since this function is 11582 * called from non sleepable context we must schedule 11583 * a work item for this purpose 11584 */ 11585 smp_mb__before_clear_bit(); 11586 set_bit(BNX2X_SP_RTNL_VFPF_MCAST, 11587 &bp->sp_rtnl_state); 11588 smp_mb__after_clear_bit(); 11589 schedule_delayed_work(&bp->sp_rtnl_task, 0); 11590 } 11591 } 11592 11593 bp->rx_mode = rx_mode; 11594 /* handle ISCSI SD mode */ 11595 if (IS_MF_ISCSI_SD(bp)) 11596 bp->rx_mode = BNX2X_RX_MODE_NONE; 11597 11598 /* Schedule the rx_mode command */ 11599 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 11600 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 11601 return; 11602 } 11603 11604 if (IS_PF(bp)) { 11605 bnx2x_set_storm_rx_mode(bp); 11606 } else { 11607 /* configuring rx mode to storms in a vf involves sleeping (when 11608 * we wait for the pf's response). Since this function is 11609 * called from non sleepable context we must schedule 11610 * a work item for this purpose 11611 */ 11612 smp_mb__before_clear_bit(); 11613 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, 11614 &bp->sp_rtnl_state); 11615 smp_mb__after_clear_bit(); 11616 schedule_delayed_work(&bp->sp_rtnl_task, 0); 11617 } 11618} 11619 11620/* called with rtnl_lock */ 11621static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 11622 int devad, u16 addr) 11623{ 11624 struct bnx2x *bp = netdev_priv(netdev); 11625 u16 value; 11626 int rc; 11627 11628 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 11629 prtad, devad, addr); 11630 11631 /* The HW expects different devad if CL22 is used */ 11632 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 11633 11634 bnx2x_acquire_phy_lock(bp); 11635 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 11636 bnx2x_release_phy_lock(bp); 11637 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 11638 11639 if (!rc) 11640 rc = value; 11641 return rc; 11642} 11643 11644/* called with rtnl_lock */ 11645static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 11646 u16 addr, u16 value) 11647{ 11648 struct bnx2x *bp = netdev_priv(netdev); 11649 int rc; 11650 11651 DP(NETIF_MSG_LINK, 11652 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", 11653 prtad, devad, addr, value); 11654 11655 /* The HW expects different devad if CL22 is used */ 11656 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 11657 11658 bnx2x_acquire_phy_lock(bp); 11659 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 11660 bnx2x_release_phy_lock(bp); 11661 return rc; 11662} 11663 11664/* called with rtnl_lock */ 11665static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 11666{ 11667 struct bnx2x *bp = netdev_priv(dev); 11668 struct mii_ioctl_data *mdio = if_mii(ifr); 11669 11670 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 11671 mdio->phy_id, mdio->reg_num, mdio->val_in); 11672 11673 if (!netif_running(dev)) 11674 return -EAGAIN; 11675 11676 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 11677} 11678 11679#ifdef CONFIG_NET_POLL_CONTROLLER 11680static void poll_bnx2x(struct net_device *dev) 11681{ 11682 struct bnx2x *bp = netdev_priv(dev); 11683 int i; 11684 11685 for_each_eth_queue(bp, i) { 11686 struct bnx2x_fastpath *fp = &bp->fp[i]; 11687 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 11688 } 11689} 11690#endif 11691 11692static int bnx2x_validate_addr(struct net_device *dev) 11693{ 11694 struct bnx2x *bp = netdev_priv(dev); 11695 11696 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { 11697 BNX2X_ERR("Non-valid Ethernet address\n"); 11698 return -EADDRNOTAVAIL; 11699 } 11700 return 0; 11701} 11702 11703static const struct net_device_ops bnx2x_netdev_ops = { 11704 .ndo_open = bnx2x_open, 11705 .ndo_stop = bnx2x_close, 11706 .ndo_start_xmit = bnx2x_start_xmit, 11707 .ndo_select_queue = bnx2x_select_queue, 11708 .ndo_set_rx_mode = bnx2x_set_rx_mode, 11709 .ndo_set_mac_address = bnx2x_change_mac_addr, 11710 .ndo_validate_addr = bnx2x_validate_addr, 11711 .ndo_do_ioctl = bnx2x_ioctl, 11712 .ndo_change_mtu = bnx2x_change_mtu, 11713 .ndo_fix_features = bnx2x_fix_features, 11714 .ndo_set_features = bnx2x_set_features, 11715 .ndo_tx_timeout = bnx2x_tx_timeout, 11716#ifdef CONFIG_NET_POLL_CONTROLLER 11717 .ndo_poll_controller = poll_bnx2x, 11718#endif 11719 .ndo_setup_tc = bnx2x_setup_tc, 11720#ifdef CONFIG_BNX2X_SRIOV 11721 .ndo_set_vf_mac = bnx2x_set_vf_mac, 11722#endif 11723#ifdef NETDEV_FCOE_WWNN 11724 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 11725#endif 11726}; 11727 11728static int bnx2x_set_coherency_mask(struct bnx2x *bp) 11729{ 11730 struct device *dev = &bp->pdev->dev; 11731 11732 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 11733 bp->flags |= USING_DAC_FLAG; 11734 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 11735 dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); 11736 return -EIO; 11737 } 11738 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 11739 dev_err(dev, "System does not support DMA, aborting\n"); 11740 return -EIO; 11741 } 11742 11743 return 0; 11744} 11745 11746static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, 11747 struct net_device *dev, unsigned long board_type) 11748{ 11749 int rc; 11750 u32 pci_cfg_dword; 11751 bool chip_is_e1x = (board_type == BCM57710 || 11752 board_type == BCM57711 || 11753 board_type == BCM57711E); 11754 11755 SET_NETDEV_DEV(dev, &pdev->dev); 11756 11757 bp->dev = dev; 11758 bp->pdev = pdev; 11759 11760 rc = pci_enable_device(pdev); 11761 if (rc) { 11762 dev_err(&bp->pdev->dev, 11763 "Cannot enable PCI device, aborting\n"); 11764 goto err_out; 11765 } 11766 11767 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 11768 dev_err(&bp->pdev->dev, 11769 "Cannot find PCI device base address, aborting\n"); 11770 rc = -ENODEV; 11771 goto err_out_disable; 11772 } 11773 11774 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 11775 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); 11776 rc = -ENODEV; 11777 goto err_out_disable; 11778 } 11779 11780 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); 11781 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == 11782 PCICFG_REVESION_ID_ERROR_VAL) { 11783 pr_err("PCI device error, probably due to fan failure, aborting\n"); 11784 rc = -ENODEV; 11785 goto err_out_disable; 11786 } 11787 11788 if (atomic_read(&pdev->enable_cnt) == 1) { 11789 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 11790 if (rc) { 11791 dev_err(&bp->pdev->dev, 11792 "Cannot obtain PCI resources, aborting\n"); 11793 goto err_out_disable; 11794 } 11795 11796 pci_set_master(pdev); 11797 pci_save_state(pdev); 11798 } 11799 11800 if (IS_PF(bp)) { 11801 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 11802 if (bp->pm_cap == 0) { 11803 dev_err(&bp->pdev->dev, 11804 "Cannot find power management capability, aborting\n"); 11805 rc = -EIO; 11806 goto err_out_release; 11807 } 11808 } 11809 11810 if (!pci_is_pcie(pdev)) { 11811 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 11812 rc = -EIO; 11813 goto err_out_release; 11814 } 11815 11816 rc = bnx2x_set_coherency_mask(bp); 11817 if (rc) 11818 goto err_out_release; 11819 11820 dev->mem_start = pci_resource_start(pdev, 0); 11821 dev->base_addr = dev->mem_start; 11822 dev->mem_end = pci_resource_end(pdev, 0); 11823 11824 dev->irq = pdev->irq; 11825 11826 bp->regview = pci_ioremap_bar(pdev, 0); 11827 if (!bp->regview) { 11828 dev_err(&bp->pdev->dev, 11829 "Cannot map register space, aborting\n"); 11830 rc = -ENOMEM; 11831 goto err_out_release; 11832 } 11833 11834 /* In E1/E1H use pci device function given by kernel. 11835 * In E2/E3 read physical function from ME register since these chips 11836 * support Physical Device Assignment where kernel BDF maybe arbitrary 11837 * (depending on hypervisor). 11838 */ 11839 if (chip_is_e1x) 11840 bp->pf_num = PCI_FUNC(pdev->devfn); 11841 else {/* chip is E2/3*/ 11842 pci_read_config_dword(bp->pdev, 11843 PCICFG_ME_REGISTER, &pci_cfg_dword); 11844 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 11845 ME_REG_ABS_PF_NUM_SHIFT); 11846 } 11847 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); 11848 11849 bnx2x_set_power_state(bp, PCI_D0); 11850 11851 /* clean indirect addresses */ 11852 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 11853 PCICFG_VENDOR_ID_OFFSET); 11854 /* 11855 * Clean the following indirect addresses for all functions since it 11856 * is not used by the driver. 11857 */ 11858 if (IS_PF(bp)) { 11859 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 11860 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 11861 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 11862 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 11863 11864 if (chip_is_e1x) { 11865 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 11866 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 11867 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 11868 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 11869 } 11870 11871 /* Enable internal target-read (in case we are probed after PF 11872 * FLR). Must be done prior to any BAR read access. Only for 11873 * 57712 and up 11874 */ 11875 if (!chip_is_e1x) 11876 REG_WR(bp, 11877 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 11878 } 11879 11880 dev->watchdog_timeo = TX_TIMEOUT; 11881 11882 dev->netdev_ops = &bnx2x_netdev_ops; 11883 bnx2x_set_ethtool_ops(dev); 11884 11885 dev->priv_flags |= IFF_UNICAST_FLT; 11886 11887 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 11888 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 11889 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | 11890 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 11891 11892 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 11893 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 11894 11895 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 11896 if (bp->flags & USING_DAC_FLAG) 11897 dev->features |= NETIF_F_HIGHDMA; 11898 11899 /* Add Loopback capability to the device */ 11900 dev->hw_features |= NETIF_F_LOOPBACK; 11901 11902#ifdef BCM_DCBNL 11903 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 11904#endif 11905 11906 /* get_port_hwinfo() will set prtad and mmds properly */ 11907 bp->mdio.prtad = MDIO_PRTAD_NONE; 11908 bp->mdio.mmds = 0; 11909 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 11910 bp->mdio.dev = dev; 11911 bp->mdio.mdio_read = bnx2x_mdio_read; 11912 bp->mdio.mdio_write = bnx2x_mdio_write; 11913 11914 return 0; 11915 11916err_out_release: 11917 if (atomic_read(&pdev->enable_cnt) == 1) 11918 pci_release_regions(pdev); 11919 11920err_out_disable: 11921 pci_disable_device(pdev); 11922 pci_set_drvdata(pdev, NULL); 11923 11924err_out: 11925 return rc; 11926} 11927 11928static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed) 11929{ 11930 u32 val = 0; 11931 11932 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val); 11933 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 11934 11935 /* return value of 1=2.5GHz 2=5GHz */ 11936 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 11937} 11938 11939static int bnx2x_check_firmware(struct bnx2x *bp) 11940{ 11941 const struct firmware *firmware = bp->firmware; 11942 struct bnx2x_fw_file_hdr *fw_hdr; 11943 struct bnx2x_fw_file_section *sections; 11944 u32 offset, len, num_ops; 11945 u16 *ops_offsets; 11946 int i; 11947 const u8 *fw_ver; 11948 11949 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { 11950 BNX2X_ERR("Wrong FW size\n"); 11951 return -EINVAL; 11952 } 11953 11954 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 11955 sections = (struct bnx2x_fw_file_section *)fw_hdr; 11956 11957 /* Make sure none of the offsets and sizes make us read beyond 11958 * the end of the firmware data */ 11959 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 11960 offset = be32_to_cpu(sections[i].offset); 11961 len = be32_to_cpu(sections[i].len); 11962 if (offset + len > firmware->size) { 11963 BNX2X_ERR("Section %d length is out of bounds\n", i); 11964 return -EINVAL; 11965 } 11966 } 11967 11968 /* Likewise for the init_ops offsets */ 11969 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 11970 ops_offsets = (u16 *)(firmware->data + offset); 11971 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 11972 11973 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 11974 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 11975 BNX2X_ERR("Section offset %d is out of bounds\n", i); 11976 return -EINVAL; 11977 } 11978 } 11979 11980 /* Check FW version */ 11981 offset = be32_to_cpu(fw_hdr->fw_version.offset); 11982 fw_ver = firmware->data + offset; 11983 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 11984 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 11985 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 11986 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 11987 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 11988 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], 11989 BCM_5710_FW_MAJOR_VERSION, 11990 BCM_5710_FW_MINOR_VERSION, 11991 BCM_5710_FW_REVISION_VERSION, 11992 BCM_5710_FW_ENGINEERING_VERSION); 11993 return -EINVAL; 11994 } 11995 11996 return 0; 11997} 11998 11999static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 12000{ 12001 const __be32 *source = (const __be32 *)_source; 12002 u32 *target = (u32 *)_target; 12003 u32 i; 12004 12005 for (i = 0; i < n/4; i++) 12006 target[i] = be32_to_cpu(source[i]); 12007} 12008 12009/* 12010 Ops array is stored in the following format: 12011 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 12012 */ 12013static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 12014{ 12015 const __be32 *source = (const __be32 *)_source; 12016 struct raw_op *target = (struct raw_op *)_target; 12017 u32 i, j, tmp; 12018 12019 for (i = 0, j = 0; i < n/8; i++, j += 2) { 12020 tmp = be32_to_cpu(source[j]); 12021 target[i].op = (tmp >> 24) & 0xff; 12022 target[i].offset = tmp & 0xffffff; 12023 target[i].raw_data = be32_to_cpu(source[j + 1]); 12024 } 12025} 12026 12027/* IRO array is stored in the following format: 12028 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 12029 */ 12030static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 12031{ 12032 const __be32 *source = (const __be32 *)_source; 12033 struct iro *target = (struct iro *)_target; 12034 u32 i, j, tmp; 12035 12036 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 12037 target[i].base = be32_to_cpu(source[j]); 12038 j++; 12039 tmp = be32_to_cpu(source[j]); 12040 target[i].m1 = (tmp >> 16) & 0xffff; 12041 target[i].m2 = tmp & 0xffff; 12042 j++; 12043 tmp = be32_to_cpu(source[j]); 12044 target[i].m3 = (tmp >> 16) & 0xffff; 12045 target[i].size = tmp & 0xffff; 12046 j++; 12047 } 12048} 12049 12050static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 12051{ 12052 const __be16 *source = (const __be16 *)_source; 12053 u16 *target = (u16 *)_target; 12054 u32 i; 12055 12056 for (i = 0; i < n/2; i++) 12057 target[i] = be16_to_cpu(source[i]); 12058} 12059 12060#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 12061do { \ 12062 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 12063 bp->arr = kmalloc(len, GFP_KERNEL); \ 12064 if (!bp->arr) \ 12065 goto lbl; \ 12066 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 12067 (u8 *)bp->arr, len); \ 12068} while (0) 12069 12070static int bnx2x_init_firmware(struct bnx2x *bp) 12071{ 12072 const char *fw_file_name; 12073 struct bnx2x_fw_file_hdr *fw_hdr; 12074 int rc; 12075 12076 if (bp->firmware) 12077 return 0; 12078 12079 if (CHIP_IS_E1(bp)) 12080 fw_file_name = FW_FILE_NAME_E1; 12081 else if (CHIP_IS_E1H(bp)) 12082 fw_file_name = FW_FILE_NAME_E1H; 12083 else if (!CHIP_IS_E1x(bp)) 12084 fw_file_name = FW_FILE_NAME_E2; 12085 else { 12086 BNX2X_ERR("Unsupported chip revision\n"); 12087 return -EINVAL; 12088 } 12089 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 12090 12091 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 12092 if (rc) { 12093 BNX2X_ERR("Can't load firmware file %s\n", 12094 fw_file_name); 12095 goto request_firmware_exit; 12096 } 12097 12098 rc = bnx2x_check_firmware(bp); 12099 if (rc) { 12100 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 12101 goto request_firmware_exit; 12102 } 12103 12104 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 12105 12106 /* Initialize the pointers to the init arrays */ 12107 /* Blob */ 12108 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 12109 12110 /* Opcodes */ 12111 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 12112 12113 /* Offsets */ 12114 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 12115 be16_to_cpu_n); 12116 12117 /* STORMs firmware */ 12118 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 12119 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 12120 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 12121 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 12122 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 12123 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 12124 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 12125 be32_to_cpu(fw_hdr->usem_pram_data.offset); 12126 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 12127 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 12128 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 12129 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 12130 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 12131 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 12132 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 12133 be32_to_cpu(fw_hdr->csem_pram_data.offset); 12134 /* IRO */ 12135 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 12136 12137 return 0; 12138 12139iro_alloc_err: 12140 kfree(bp->init_ops_offsets); 12141init_offsets_alloc_err: 12142 kfree(bp->init_ops); 12143init_ops_alloc_err: 12144 kfree(bp->init_data); 12145request_firmware_exit: 12146 release_firmware(bp->firmware); 12147 bp->firmware = NULL; 12148 12149 return rc; 12150} 12151 12152static void bnx2x_release_firmware(struct bnx2x *bp) 12153{ 12154 kfree(bp->init_ops_offsets); 12155 kfree(bp->init_ops); 12156 kfree(bp->init_data); 12157 release_firmware(bp->firmware); 12158 bp->firmware = NULL; 12159} 12160 12161 12162static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 12163 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 12164 .init_hw_cmn = bnx2x_init_hw_common, 12165 .init_hw_port = bnx2x_init_hw_port, 12166 .init_hw_func = bnx2x_init_hw_func, 12167 12168 .reset_hw_cmn = bnx2x_reset_common, 12169 .reset_hw_port = bnx2x_reset_port, 12170 .reset_hw_func = bnx2x_reset_func, 12171 12172 .gunzip_init = bnx2x_gunzip_init, 12173 .gunzip_end = bnx2x_gunzip_end, 12174 12175 .init_fw = bnx2x_init_firmware, 12176 .release_fw = bnx2x_release_firmware, 12177}; 12178 12179void bnx2x__init_func_obj(struct bnx2x *bp) 12180{ 12181 /* Prepare DMAE related driver resources */ 12182 bnx2x_setup_dmae(bp); 12183 12184 bnx2x_init_func_obj(bp, &bp->func_obj, 12185 bnx2x_sp(bp, func_rdata), 12186 bnx2x_sp_mapping(bp, func_rdata), 12187 bnx2x_sp(bp, func_afex_rdata), 12188 bnx2x_sp_mapping(bp, func_afex_rdata), 12189 &bnx2x_func_sp_drv); 12190} 12191 12192/* must be called after sriov-enable */ 12193static int bnx2x_set_qm_cid_count(struct bnx2x *bp) 12194{ 12195 int cid_count = BNX2X_L2_MAX_CID(bp); 12196 12197 if (IS_SRIOV(bp)) 12198 cid_count += BNX2X_VF_CIDS; 12199 12200 if (CNIC_SUPPORT(bp)) 12201 cid_count += CNIC_CID_MAX; 12202 12203 return roundup(cid_count, QM_CID_ROUND); 12204} 12205 12206/** 12207 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 12208 * 12209 * @dev: pci device 12210 * 12211 */ 12212static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, 12213 int cnic_cnt, bool is_vf) 12214{ 12215 int pos, index; 12216 u16 control = 0; 12217 12218 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 12219 12220 /* 12221 * If MSI-X is not supported - return number of SBs needed to support 12222 * one fast path queue: one FP queue + SB for CNIC 12223 */ 12224 if (!pos) { 12225 dev_info(&pdev->dev, "no msix capability found\n"); 12226 return 1 + cnic_cnt; 12227 } 12228 dev_info(&pdev->dev, "msix capability found\n"); 12229 12230 /* 12231 * The value in the PCI configuration space is the index of the last 12232 * entry, namely one less than the actual size of the table, which is 12233 * exactly what we want to return from this function: number of all SBs 12234 * without the default SB. 12235 * For VFs there is no default SB, then we return (index+1). 12236 */ 12237 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 12238 12239 index = control & PCI_MSIX_FLAGS_QSIZE; 12240 12241 return is_vf ? index + 1 : index; 12242} 12243 12244static int set_max_cos_est(int chip_id) 12245{ 12246 switch (chip_id) { 12247 case BCM57710: 12248 case BCM57711: 12249 case BCM57711E: 12250 return BNX2X_MULTI_TX_COS_E1X; 12251 case BCM57712: 12252 case BCM57712_MF: 12253 case BCM57712_VF: 12254 return BNX2X_MULTI_TX_COS_E2_E3A0; 12255 case BCM57800: 12256 case BCM57800_MF: 12257 case BCM57800_VF: 12258 case BCM57810: 12259 case BCM57810_MF: 12260 case BCM57840_4_10: 12261 case BCM57840_2_20: 12262 case BCM57840_O: 12263 case BCM57840_MFO: 12264 case BCM57810_VF: 12265 case BCM57840_MF: 12266 case BCM57840_VF: 12267 case BCM57811: 12268 case BCM57811_MF: 12269 case BCM57811_VF: 12270 return BNX2X_MULTI_TX_COS_E3B0; 12271 return 1; 12272 default: 12273 pr_err("Unknown board_type (%d), aborting\n", chip_id); 12274 return -ENODEV; 12275 } 12276} 12277 12278static int set_is_vf(int chip_id) 12279{ 12280 switch (chip_id) { 12281 case BCM57712_VF: 12282 case BCM57800_VF: 12283 case BCM57810_VF: 12284 case BCM57840_VF: 12285 case BCM57811_VF: 12286 return true; 12287 default: 12288 return false; 12289 } 12290} 12291 12292struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); 12293 12294static int bnx2x_init_one(struct pci_dev *pdev, 12295 const struct pci_device_id *ent) 12296{ 12297 struct net_device *dev = NULL; 12298 struct bnx2x *bp; 12299 int pcie_width, pcie_speed; 12300 int rc, max_non_def_sbs; 12301 int rx_count, tx_count, rss_count, doorbell_size; 12302 int max_cos_est; 12303 bool is_vf; 12304 int cnic_cnt; 12305 12306 /* An estimated maximum supported CoS number according to the chip 12307 * version. 12308 * We will try to roughly estimate the maximum number of CoSes this chip 12309 * may support in order to minimize the memory allocated for Tx 12310 * netdev_queue's. This number will be accurately calculated during the 12311 * initialization of bp->max_cos based on the chip versions AND chip 12312 * revision in the bnx2x_init_bp(). 12313 */ 12314 max_cos_est = set_max_cos_est(ent->driver_data); 12315 if (max_cos_est < 0) 12316 return max_cos_est; 12317 is_vf = set_is_vf(ent->driver_data); 12318 cnic_cnt = is_vf ? 0 : 1; 12319 12320 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf); 12321 12322 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 12323 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt; 12324 12325 if (rss_count < 1) 12326 return -EINVAL; 12327 12328 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 12329 rx_count = rss_count + cnic_cnt; 12330 12331 /* Maximum number of netdev Tx queues: 12332 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 12333 */ 12334 tx_count = rss_count * max_cos_est + cnic_cnt; 12335 12336 /* dev zeroed in init_etherdev */ 12337 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 12338 if (!dev) 12339 return -ENOMEM; 12340 12341 bp = netdev_priv(dev); 12342 12343 bp->flags = 0; 12344 if (is_vf) 12345 bp->flags |= IS_VF_FLAG; 12346 12347 bp->igu_sb_cnt = max_non_def_sbs; 12348 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; 12349 bp->msg_enable = debug; 12350 bp->cnic_support = cnic_cnt; 12351 bp->cnic_probe = bnx2x_cnic_probe; 12352 12353 pci_set_drvdata(pdev, dev); 12354 12355 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); 12356 if (rc < 0) { 12357 free_netdev(dev); 12358 return rc; 12359 } 12360 12361 BNX2X_DEV_INFO("This is a %s function\n", 12362 IS_PF(bp) ? "physical" : "virtual"); 12363 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); 12364 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); 12365 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", 12366 tx_count, rx_count); 12367 12368 rc = bnx2x_init_bp(bp); 12369 if (rc) 12370 goto init_one_exit; 12371 12372 /* Map doorbells here as we need the real value of bp->max_cos which 12373 * is initialized in bnx2x_init_bp() to determine the number of 12374 * l2 connections. 12375 */ 12376 if (IS_VF(bp)) { 12377 bnx2x_vf_map_doorbells(bp); 12378 rc = bnx2x_vf_pci_alloc(bp); 12379 if (rc) 12380 goto init_one_exit; 12381 } else { 12382 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); 12383 if (doorbell_size > pci_resource_len(pdev, 2)) { 12384 dev_err(&bp->pdev->dev, 12385 "Cannot map doorbells, bar size too small, aborting\n"); 12386 rc = -ENOMEM; 12387 goto init_one_exit; 12388 } 12389 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 12390 doorbell_size); 12391 } 12392 if (!bp->doorbells) { 12393 dev_err(&bp->pdev->dev, 12394 "Cannot map doorbell space, aborting\n"); 12395 rc = -ENOMEM; 12396 goto init_one_exit; 12397 } 12398 12399 if (IS_VF(bp)) { 12400 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); 12401 if (rc) 12402 goto init_one_exit; 12403 } 12404 12405 /* Enable SRIOV if capability found in configuration space. 12406 * Once the generic SR-IOV framework makes it in from the 12407 * pci tree this will be revised, to allow dynamic control 12408 * over the number of VFs. Right now, change the num of vfs 12409 * param below to enable SR-IOV. 12410 */ 12411 rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/); 12412 if (rc) 12413 goto init_one_exit; 12414 12415 /* calc qm_cid_count */ 12416 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 12417 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); 12418 12419 /* disable FCOE L2 queue for E1x*/ 12420 if (CHIP_IS_E1x(bp)) 12421 bp->flags |= NO_FCOE_FLAG; 12422 12423 /* disable FCOE for 57840 device, until FW supports it */ 12424 switch (ent->driver_data) { 12425 case BCM57840_O: 12426 case BCM57840_4_10: 12427 case BCM57840_2_20: 12428 case BCM57840_MFO: 12429 case BCM57840_MF: 12430 bp->flags |= NO_FCOE_FLAG; 12431 } 12432 12433 /* Set bp->num_queues for MSI-X mode*/ 12434 bnx2x_set_num_queues(bp); 12435 12436 /* Configure interrupt mode: try to enable MSI-X/MSI if 12437 * needed. 12438 */ 12439 rc = bnx2x_set_int_mode(bp); 12440 if (rc) { 12441 dev_err(&pdev->dev, "Cannot set interrupts\n"); 12442 goto init_one_exit; 12443 } 12444 12445 /* register the net device */ 12446 rc = register_netdev(dev); 12447 if (rc) { 12448 dev_err(&pdev->dev, "Cannot register net device\n"); 12449 goto init_one_exit; 12450 } 12451 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); 12452 12453 12454 if (!NO_FCOE(bp)) { 12455 /* Add storage MAC address */ 12456 rtnl_lock(); 12457 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 12458 rtnl_unlock(); 12459 } 12460 12461 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 12462 BNX2X_DEV_INFO("got pcie width %d and speed %d\n", 12463 pcie_width, pcie_speed); 12464 12465 BNX2X_DEV_INFO( 12466 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 12467 board_info[ent->driver_data].name, 12468 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 12469 pcie_width, 12470 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 12471 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 12472 "5GHz (Gen2)" : "2.5GHz", 12473 dev->base_addr, bp->pdev->irq, dev->dev_addr); 12474 12475 return 0; 12476 12477init_one_exit: 12478 if (bp->regview) 12479 iounmap(bp->regview); 12480 12481 if (IS_PF(bp) && bp->doorbells) 12482 iounmap(bp->doorbells); 12483 12484 free_netdev(dev); 12485 12486 if (atomic_read(&pdev->enable_cnt) == 1) 12487 pci_release_regions(pdev); 12488 12489 pci_disable_device(pdev); 12490 pci_set_drvdata(pdev, NULL); 12491 12492 return rc; 12493} 12494 12495static void bnx2x_remove_one(struct pci_dev *pdev) 12496{ 12497 struct net_device *dev = pci_get_drvdata(pdev); 12498 struct bnx2x *bp; 12499 12500 if (!dev) { 12501 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 12502 return; 12503 } 12504 bp = netdev_priv(dev); 12505 12506 /* Delete storage MAC address */ 12507 if (!NO_FCOE(bp)) { 12508 rtnl_lock(); 12509 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 12510 rtnl_unlock(); 12511 } 12512 12513#ifdef BCM_DCBNL 12514 /* Delete app tlvs from dcbnl */ 12515 bnx2x_dcbnl_update_applist(bp, true); 12516#endif 12517 12518 unregister_netdev(dev); 12519 12520 /* Power on: we can't let PCI layer write to us while we are in D3 */ 12521 if (IS_PF(bp)) 12522 bnx2x_set_power_state(bp, PCI_D0); 12523 12524 /* Disable MSI/MSI-X */ 12525 bnx2x_disable_msi(bp); 12526 12527 /* Power off */ 12528 if (IS_PF(bp)) 12529 bnx2x_set_power_state(bp, PCI_D3hot); 12530 12531 /* Make sure RESET task is not scheduled before continuing */ 12532 cancel_delayed_work_sync(&bp->sp_rtnl_task); 12533 12534 bnx2x_iov_remove_one(bp); 12535 12536 /* send message via vfpf channel to release the resources of this vf */ 12537 if (IS_VF(bp)) 12538 bnx2x_vfpf_release(bp); 12539 12540 if (bp->regview) 12541 iounmap(bp->regview); 12542 12543 /* for vf doorbells are part of the regview and were unmapped along with 12544 * it. FW is only loaded by PF. 12545 */ 12546 if (IS_PF(bp)) { 12547 if (bp->doorbells) 12548 iounmap(bp->doorbells); 12549 12550 bnx2x_release_firmware(bp); 12551 } 12552 bnx2x_free_mem_bp(bp); 12553 12554 free_netdev(dev); 12555 12556 if (atomic_read(&pdev->enable_cnt) == 1) 12557 pci_release_regions(pdev); 12558 12559 pci_disable_device(pdev); 12560 pci_set_drvdata(pdev, NULL); 12561} 12562 12563static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 12564{ 12565 int i; 12566 12567 bp->state = BNX2X_STATE_ERROR; 12568 12569 bp->rx_mode = BNX2X_RX_MODE_NONE; 12570 12571 if (CNIC_LOADED(bp)) 12572 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 12573 12574 /* Stop Tx */ 12575 bnx2x_tx_disable(bp); 12576 12577 bnx2x_netif_stop(bp, 0); 12578 /* Delete all NAPI objects */ 12579 bnx2x_del_all_napi(bp); 12580 if (CNIC_LOADED(bp)) 12581 bnx2x_del_all_napi_cnic(bp); 12582 12583 del_timer_sync(&bp->timer); 12584 12585 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 12586 12587 /* Release IRQs */ 12588 bnx2x_free_irq(bp); 12589 12590 /* Free SKBs, SGEs, TPA pool and driver internals */ 12591 bnx2x_free_skbs(bp); 12592 12593 for_each_rx_queue(bp, i) 12594 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 12595 12596 bnx2x_free_mem(bp); 12597 12598 bp->state = BNX2X_STATE_CLOSED; 12599 12600 netif_carrier_off(bp->dev); 12601 12602 return 0; 12603} 12604 12605static void bnx2x_eeh_recover(struct bnx2x *bp) 12606{ 12607 u32 val; 12608 12609 mutex_init(&bp->port.phy_mutex); 12610 12611 12612 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 12613 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 12614 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 12615 BNX2X_ERR("BAD MCP validity signature\n"); 12616} 12617 12618/** 12619 * bnx2x_io_error_detected - called when PCI error is detected 12620 * @pdev: Pointer to PCI device 12621 * @state: The current pci connection state 12622 * 12623 * This function is called after a PCI bus error affecting 12624 * this device has been detected. 12625 */ 12626static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 12627 pci_channel_state_t state) 12628{ 12629 struct net_device *dev = pci_get_drvdata(pdev); 12630 struct bnx2x *bp = netdev_priv(dev); 12631 12632 rtnl_lock(); 12633 12634 netif_device_detach(dev); 12635 12636 if (state == pci_channel_io_perm_failure) { 12637 rtnl_unlock(); 12638 return PCI_ERS_RESULT_DISCONNECT; 12639 } 12640 12641 if (netif_running(dev)) 12642 bnx2x_eeh_nic_unload(bp); 12643 12644 pci_disable_device(pdev); 12645 12646 rtnl_unlock(); 12647 12648 /* Request a slot reset */ 12649 return PCI_ERS_RESULT_NEED_RESET; 12650} 12651 12652/** 12653 * bnx2x_io_slot_reset - called after the PCI bus has been reset 12654 * @pdev: Pointer to PCI device 12655 * 12656 * Restart the card from scratch, as if from a cold-boot. 12657 */ 12658static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 12659{ 12660 struct net_device *dev = pci_get_drvdata(pdev); 12661 struct bnx2x *bp = netdev_priv(dev); 12662 12663 rtnl_lock(); 12664 12665 if (pci_enable_device(pdev)) { 12666 dev_err(&pdev->dev, 12667 "Cannot re-enable PCI device after reset\n"); 12668 rtnl_unlock(); 12669 return PCI_ERS_RESULT_DISCONNECT; 12670 } 12671 12672 pci_set_master(pdev); 12673 pci_restore_state(pdev); 12674 12675 if (netif_running(dev)) 12676 bnx2x_set_power_state(bp, PCI_D0); 12677 12678 rtnl_unlock(); 12679 12680 return PCI_ERS_RESULT_RECOVERED; 12681} 12682 12683/** 12684 * bnx2x_io_resume - called when traffic can start flowing again 12685 * @pdev: Pointer to PCI device 12686 * 12687 * This callback is called when the error recovery driver tells us that 12688 * its OK to resume normal operation. 12689 */ 12690static void bnx2x_io_resume(struct pci_dev *pdev) 12691{ 12692 struct net_device *dev = pci_get_drvdata(pdev); 12693 struct bnx2x *bp = netdev_priv(dev); 12694 12695 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 12696 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); 12697 return; 12698 } 12699 12700 rtnl_lock(); 12701 12702 bnx2x_eeh_recover(bp); 12703 12704 if (netif_running(dev)) 12705 bnx2x_nic_load(bp, LOAD_NORMAL); 12706 12707 netif_device_attach(dev); 12708 12709 rtnl_unlock(); 12710} 12711 12712static const struct pci_error_handlers bnx2x_err_handler = { 12713 .error_detected = bnx2x_io_error_detected, 12714 .slot_reset = bnx2x_io_slot_reset, 12715 .resume = bnx2x_io_resume, 12716}; 12717 12718static struct pci_driver bnx2x_pci_driver = { 12719 .name = DRV_MODULE_NAME, 12720 .id_table = bnx2x_pci_tbl, 12721 .probe = bnx2x_init_one, 12722 .remove = bnx2x_remove_one, 12723 .suspend = bnx2x_suspend, 12724 .resume = bnx2x_resume, 12725 .err_handler = &bnx2x_err_handler, 12726}; 12727 12728static int __init bnx2x_init(void) 12729{ 12730 int ret; 12731 12732 pr_info("%s", version); 12733 12734 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 12735 if (bnx2x_wq == NULL) { 12736 pr_err("Cannot create workqueue\n"); 12737 return -ENOMEM; 12738 } 12739 12740 ret = pci_register_driver(&bnx2x_pci_driver); 12741 if (ret) { 12742 pr_err("Cannot register driver\n"); 12743 destroy_workqueue(bnx2x_wq); 12744 } 12745 return ret; 12746} 12747 12748static void __exit bnx2x_cleanup(void) 12749{ 12750 struct list_head *pos, *q; 12751 pci_unregister_driver(&bnx2x_pci_driver); 12752 12753 destroy_workqueue(bnx2x_wq); 12754 12755 /* Free globablly allocated resources */ 12756 list_for_each_safe(pos, q, &bnx2x_prev_list) { 12757 struct bnx2x_prev_path_list *tmp = 12758 list_entry(pos, struct bnx2x_prev_path_list, list); 12759 list_del(pos); 12760 kfree(tmp); 12761 } 12762} 12763 12764void bnx2x_notify_link_changed(struct bnx2x *bp) 12765{ 12766 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 12767} 12768 12769module_init(bnx2x_init); 12770module_exit(bnx2x_cleanup); 12771 12772/** 12773 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 12774 * 12775 * @bp: driver handle 12776 * @set: set or clear the CAM entry 12777 * 12778 * This function will wait until the ramdord completion returns. 12779 * Return 0 if success, -ENODEV if ramrod doesn't return. 12780 */ 12781static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 12782{ 12783 unsigned long ramrod_flags = 0; 12784 12785 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 12786 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 12787 &bp->iscsi_l2_mac_obj, true, 12788 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 12789} 12790 12791/* count denotes the number of new completions we have seen */ 12792static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 12793{ 12794 struct eth_spe *spe; 12795 int cxt_index, cxt_offset; 12796 12797#ifdef BNX2X_STOP_ON_ERROR 12798 if (unlikely(bp->panic)) 12799 return; 12800#endif 12801 12802 spin_lock_bh(&bp->spq_lock); 12803 BUG_ON(bp->cnic_spq_pending < count); 12804 bp->cnic_spq_pending -= count; 12805 12806 12807 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 12808 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 12809 & SPE_HDR_CONN_TYPE) >> 12810 SPE_HDR_CONN_TYPE_SHIFT; 12811 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 12812 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 12813 12814 /* Set validation for iSCSI L2 client before sending SETUP 12815 * ramrod 12816 */ 12817 if (type == ETH_CONNECTION_TYPE) { 12818 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { 12819 cxt_index = BNX2X_ISCSI_ETH_CID(bp) / 12820 ILT_PAGE_CIDS; 12821 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - 12822 (cxt_index * ILT_PAGE_CIDS); 12823 bnx2x_set_ctx_validation(bp, 12824 &bp->context[cxt_index]. 12825 vcxt[cxt_offset].eth, 12826 BNX2X_ISCSI_ETH_CID(bp)); 12827 } 12828 } 12829 12830 /* 12831 * There may be not more than 8 L2, not more than 8 L5 SPEs 12832 * and in the air. We also check that number of outstanding 12833 * COMMON ramrods is not more than the EQ and SPQ can 12834 * accommodate. 12835 */ 12836 if (type == ETH_CONNECTION_TYPE) { 12837 if (!atomic_read(&bp->cq_spq_left)) 12838 break; 12839 else 12840 atomic_dec(&bp->cq_spq_left); 12841 } else if (type == NONE_CONNECTION_TYPE) { 12842 if (!atomic_read(&bp->eq_spq_left)) 12843 break; 12844 else 12845 atomic_dec(&bp->eq_spq_left); 12846 } else if ((type == ISCSI_CONNECTION_TYPE) || 12847 (type == FCOE_CONNECTION_TYPE)) { 12848 if (bp->cnic_spq_pending >= 12849 bp->cnic_eth_dev.max_kwqe_pending) 12850 break; 12851 else 12852 bp->cnic_spq_pending++; 12853 } else { 12854 BNX2X_ERR("Unknown SPE type: %d\n", type); 12855 bnx2x_panic(); 12856 break; 12857 } 12858 12859 spe = bnx2x_sp_get_next(bp); 12860 *spe = *bp->cnic_kwq_cons; 12861 12862 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", 12863 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 12864 12865 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 12866 bp->cnic_kwq_cons = bp->cnic_kwq; 12867 else 12868 bp->cnic_kwq_cons++; 12869 } 12870 bnx2x_sp_prod_update(bp); 12871 spin_unlock_bh(&bp->spq_lock); 12872} 12873 12874static int bnx2x_cnic_sp_queue(struct net_device *dev, 12875 struct kwqe_16 *kwqes[], u32 count) 12876{ 12877 struct bnx2x *bp = netdev_priv(dev); 12878 int i; 12879 12880#ifdef BNX2X_STOP_ON_ERROR 12881 if (unlikely(bp->panic)) { 12882 BNX2X_ERR("Can't post to SP queue while panic\n"); 12883 return -EIO; 12884 } 12885#endif 12886 12887 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 12888 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 12889 BNX2X_ERR("Handling parity error recovery. Try again later\n"); 12890 return -EAGAIN; 12891 } 12892 12893 spin_lock_bh(&bp->spq_lock); 12894 12895 for (i = 0; i < count; i++) { 12896 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 12897 12898 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 12899 break; 12900 12901 *bp->cnic_kwq_prod = *spe; 12902 12903 bp->cnic_kwq_pending++; 12904 12905 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", 12906 spe->hdr.conn_and_cmd_data, spe->hdr.type, 12907 spe->data.update_data_addr.hi, 12908 spe->data.update_data_addr.lo, 12909 bp->cnic_kwq_pending); 12910 12911 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 12912 bp->cnic_kwq_prod = bp->cnic_kwq; 12913 else 12914 bp->cnic_kwq_prod++; 12915 } 12916 12917 spin_unlock_bh(&bp->spq_lock); 12918 12919 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 12920 bnx2x_cnic_sp_post(bp, 0); 12921 12922 return i; 12923} 12924 12925static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 12926{ 12927 struct cnic_ops *c_ops; 12928 int rc = 0; 12929 12930 mutex_lock(&bp->cnic_mutex); 12931 c_ops = rcu_dereference_protected(bp->cnic_ops, 12932 lockdep_is_held(&bp->cnic_mutex)); 12933 if (c_ops) 12934 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 12935 mutex_unlock(&bp->cnic_mutex); 12936 12937 return rc; 12938} 12939 12940static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 12941{ 12942 struct cnic_ops *c_ops; 12943 int rc = 0; 12944 12945 rcu_read_lock(); 12946 c_ops = rcu_dereference(bp->cnic_ops); 12947 if (c_ops) 12948 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 12949 rcu_read_unlock(); 12950 12951 return rc; 12952} 12953 12954/* 12955 * for commands that have no data 12956 */ 12957int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 12958{ 12959 struct cnic_ctl_info ctl = {0}; 12960 12961 ctl.cmd = cmd; 12962 12963 return bnx2x_cnic_ctl_send(bp, &ctl); 12964} 12965 12966static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 12967{ 12968 struct cnic_ctl_info ctl = {0}; 12969 12970 /* first we tell CNIC and only then we count this as a completion */ 12971 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 12972 ctl.data.comp.cid = cid; 12973 ctl.data.comp.error = err; 12974 12975 bnx2x_cnic_ctl_send_bh(bp, &ctl); 12976 bnx2x_cnic_sp_post(bp, 0); 12977} 12978 12979 12980/* Called with netif_addr_lock_bh() taken. 12981 * Sets an rx_mode config for an iSCSI ETH client. 12982 * Doesn't block. 12983 * Completion should be checked outside. 12984 */ 12985static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 12986{ 12987 unsigned long accept_flags = 0, ramrod_flags = 0; 12988 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 12989 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 12990 12991 if (start) { 12992 /* Start accepting on iSCSI L2 ring. Accept all multicasts 12993 * because it's the only way for UIO Queue to accept 12994 * multicasts (in non-promiscuous mode only one Queue per 12995 * function will receive multicast packets (leading in our 12996 * case). 12997 */ 12998 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 12999 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 13000 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 13001 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 13002 13003 /* Clear STOP_PENDING bit if START is requested */ 13004 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 13005 13006 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 13007 } else 13008 /* Clear START_PENDING bit if STOP is requested */ 13009 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 13010 13011 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 13012 set_bit(sched_state, &bp->sp_state); 13013 else { 13014 __set_bit(RAMROD_RX, &ramrod_flags); 13015 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 13016 ramrod_flags); 13017 } 13018} 13019 13020 13021static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 13022{ 13023 struct bnx2x *bp = netdev_priv(dev); 13024 int rc = 0; 13025 13026 switch (ctl->cmd) { 13027 case DRV_CTL_CTXTBL_WR_CMD: { 13028 u32 index = ctl->data.io.offset; 13029 dma_addr_t addr = ctl->data.io.dma_addr; 13030 13031 bnx2x_ilt_wr(bp, index, addr); 13032 break; 13033 } 13034 13035 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 13036 int count = ctl->data.credit.credit_count; 13037 13038 bnx2x_cnic_sp_post(bp, count); 13039 break; 13040 } 13041 13042 /* rtnl_lock is held. */ 13043 case DRV_CTL_START_L2_CMD: { 13044 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13045 unsigned long sp_bits = 0; 13046 13047 /* Configure the iSCSI classification object */ 13048 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 13049 cp->iscsi_l2_client_id, 13050 cp->iscsi_l2_cid, BP_FUNC(bp), 13051 bnx2x_sp(bp, mac_rdata), 13052 bnx2x_sp_mapping(bp, mac_rdata), 13053 BNX2X_FILTER_MAC_PENDING, 13054 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 13055 &bp->macs_pool); 13056 13057 /* Set iSCSI MAC address */ 13058 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 13059 if (rc) 13060 break; 13061 13062 mmiowb(); 13063 barrier(); 13064 13065 /* Start accepting on iSCSI L2 ring */ 13066 13067 netif_addr_lock_bh(dev); 13068 bnx2x_set_iscsi_eth_rx_mode(bp, true); 13069 netif_addr_unlock_bh(dev); 13070 13071 /* bits to wait on */ 13072 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 13073 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 13074 13075 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 13076 BNX2X_ERR("rx_mode completion timed out!\n"); 13077 13078 break; 13079 } 13080 13081 /* rtnl_lock is held. */ 13082 case DRV_CTL_STOP_L2_CMD: { 13083 unsigned long sp_bits = 0; 13084 13085 /* Stop accepting on iSCSI L2 ring */ 13086 netif_addr_lock_bh(dev); 13087 bnx2x_set_iscsi_eth_rx_mode(bp, false); 13088 netif_addr_unlock_bh(dev); 13089 13090 /* bits to wait on */ 13091 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 13092 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 13093 13094 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 13095 BNX2X_ERR("rx_mode completion timed out!\n"); 13096 13097 mmiowb(); 13098 barrier(); 13099 13100 /* Unset iSCSI L2 MAC */ 13101 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 13102 BNX2X_ISCSI_ETH_MAC, true); 13103 break; 13104 } 13105 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 13106 int count = ctl->data.credit.credit_count; 13107 13108 smp_mb__before_atomic_inc(); 13109 atomic_add(count, &bp->cq_spq_left); 13110 smp_mb__after_atomic_inc(); 13111 break; 13112 } 13113 case DRV_CTL_ULP_REGISTER_CMD: { 13114 int ulp_type = ctl->data.register_data.ulp_type; 13115 13116 if (CHIP_IS_E3(bp)) { 13117 int idx = BP_FW_MB_IDX(bp); 13118 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 13119 int path = BP_PATH(bp); 13120 int port = BP_PORT(bp); 13121 int i; 13122 u32 scratch_offset; 13123 u32 *host_addr; 13124 13125 /* first write capability to shmem2 */ 13126 if (ulp_type == CNIC_ULP_ISCSI) 13127 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 13128 else if (ulp_type == CNIC_ULP_FCOE) 13129 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 13130 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 13131 13132 if ((ulp_type != CNIC_ULP_FCOE) || 13133 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || 13134 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) 13135 break; 13136 13137 /* if reached here - should write fcoe capabilities */ 13138 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); 13139 if (!scratch_offset) 13140 break; 13141 scratch_offset += offsetof(struct glob_ncsi_oem_data, 13142 fcoe_features[path][port]); 13143 host_addr = (u32 *) &(ctl->data.register_data. 13144 fcoe_features); 13145 for (i = 0; i < sizeof(struct fcoe_capabilities); 13146 i += 4) 13147 REG_WR(bp, scratch_offset + i, 13148 *(host_addr + i/4)); 13149 } 13150 break; 13151 } 13152 13153 case DRV_CTL_ULP_UNREGISTER_CMD: { 13154 int ulp_type = ctl->data.ulp_type; 13155 13156 if (CHIP_IS_E3(bp)) { 13157 int idx = BP_FW_MB_IDX(bp); 13158 u32 cap; 13159 13160 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 13161 if (ulp_type == CNIC_ULP_ISCSI) 13162 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 13163 else if (ulp_type == CNIC_ULP_FCOE) 13164 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 13165 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 13166 } 13167 break; 13168 } 13169 13170 default: 13171 BNX2X_ERR("unknown command %x\n", ctl->cmd); 13172 rc = -EINVAL; 13173 } 13174 13175 return rc; 13176} 13177 13178void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 13179{ 13180 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13181 13182 if (bp->flags & USING_MSIX_FLAG) { 13183 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 13184 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 13185 cp->irq_arr[0].vector = bp->msix_table[1].vector; 13186 } else { 13187 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 13188 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 13189 } 13190 if (!CHIP_IS_E1x(bp)) 13191 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 13192 else 13193 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 13194 13195 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 13196 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 13197 cp->irq_arr[1].status_blk = bp->def_status_blk; 13198 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 13199 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 13200 13201 cp->num_irq = 2; 13202} 13203 13204void bnx2x_setup_cnic_info(struct bnx2x *bp) 13205{ 13206 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13207 13208 13209 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 13210 bnx2x_cid_ilt_lines(bp); 13211 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 13212 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 13213 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 13214 13215 if (NO_ISCSI_OOO(bp)) 13216 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 13217} 13218 13219static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 13220 void *data) 13221{ 13222 struct bnx2x *bp = netdev_priv(dev); 13223 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13224 int rc; 13225 13226 DP(NETIF_MSG_IFUP, "Register_cnic called\n"); 13227 13228 if (ops == NULL) { 13229 BNX2X_ERR("NULL ops received\n"); 13230 return -EINVAL; 13231 } 13232 13233 if (!CNIC_SUPPORT(bp)) { 13234 BNX2X_ERR("Can't register CNIC when not supported\n"); 13235 return -EOPNOTSUPP; 13236 } 13237 13238 if (!CNIC_LOADED(bp)) { 13239 rc = bnx2x_load_cnic(bp); 13240 if (rc) { 13241 BNX2X_ERR("CNIC-related load failed\n"); 13242 return rc; 13243 } 13244 13245 } 13246 13247 bp->cnic_enabled = true; 13248 13249 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 13250 if (!bp->cnic_kwq) 13251 return -ENOMEM; 13252 13253 bp->cnic_kwq_cons = bp->cnic_kwq; 13254 bp->cnic_kwq_prod = bp->cnic_kwq; 13255 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 13256 13257 bp->cnic_spq_pending = 0; 13258 bp->cnic_kwq_pending = 0; 13259 13260 bp->cnic_data = data; 13261 13262 cp->num_irq = 0; 13263 cp->drv_state |= CNIC_DRV_STATE_REGD; 13264 cp->iro_arr = bp->iro_arr; 13265 13266 bnx2x_setup_cnic_irq_info(bp); 13267 13268 rcu_assign_pointer(bp->cnic_ops, ops); 13269 13270 return 0; 13271} 13272 13273static int bnx2x_unregister_cnic(struct net_device *dev) 13274{ 13275 struct bnx2x *bp = netdev_priv(dev); 13276 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13277 13278 mutex_lock(&bp->cnic_mutex); 13279 cp->drv_state = 0; 13280 RCU_INIT_POINTER(bp->cnic_ops, NULL); 13281 mutex_unlock(&bp->cnic_mutex); 13282 synchronize_rcu(); 13283 kfree(bp->cnic_kwq); 13284 bp->cnic_kwq = NULL; 13285 13286 return 0; 13287} 13288 13289struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 13290{ 13291 struct bnx2x *bp = netdev_priv(dev); 13292 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13293 13294 /* If both iSCSI and FCoE are disabled - return NULL in 13295 * order to indicate CNIC that it should not try to work 13296 * with this device. 13297 */ 13298 if (NO_ISCSI(bp) && NO_FCOE(bp)) 13299 return NULL; 13300 13301 cp->drv_owner = THIS_MODULE; 13302 cp->chip_id = CHIP_ID(bp); 13303 cp->pdev = bp->pdev; 13304 cp->io_base = bp->regview; 13305 cp->io_base2 = bp->doorbells; 13306 cp->max_kwqe_pending = 8; 13307 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 13308 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 13309 bnx2x_cid_ilt_lines(bp); 13310 cp->ctx_tbl_len = CNIC_ILT_LINES; 13311 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 13312 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 13313 cp->drv_ctl = bnx2x_drv_ctl; 13314 cp->drv_register_cnic = bnx2x_register_cnic; 13315 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 13316 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 13317 cp->iscsi_l2_client_id = 13318 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 13319 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 13320 13321 if (NO_ISCSI_OOO(bp)) 13322 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 13323 13324 if (NO_ISCSI(bp)) 13325 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 13326 13327 if (NO_FCOE(bp)) 13328 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 13329 13330 BNX2X_DEV_INFO( 13331 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", 13332 cp->ctx_blk_size, 13333 cp->ctx_tbl_offset, 13334 cp->ctx_tbl_len, 13335 cp->starting_cid); 13336 return cp; 13337} 13338 13339u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 13340{ 13341 struct bnx2x *bp = fp->bp; 13342 u32 offset = BAR_USTRORM_INTMEM; 13343 13344 if (IS_VF(bp)) 13345 return bnx2x_vf_ustorm_prods_offset(bp, fp); 13346 else if (!CHIP_IS_E1x(bp)) 13347 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 13348 else 13349 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 13350 13351 return offset; 13352} 13353 13354/* called only on E1H or E2. 13355 * When pretending to be PF, the pretend value is the function number 0...7 13356 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID 13357 * combination 13358 */ 13359int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) 13360{ 13361 u32 pretend_reg; 13362 13363 if (CHIP_IS_E1H(bp) && pretend_func_val > E1H_FUNC_MAX) 13364 return -1; 13365 13366 /* get my own pretend register */ 13367 pretend_reg = bnx2x_get_pretend_reg(bp); 13368 REG_WR(bp, pretend_reg, pretend_func_val); 13369 REG_RD(bp, pretend_reg); 13370 return 0; 13371} 13372